Model 53640 1-Ch. 3.6 GHz or 2-Ch. 1.8 GHz, 12-bit A/D, V-6 FPGA - 3U VPX General Information installed functions and enable the 53640 to ® Model 53640 is a member of the Cobalt operate as a complete turnkey solution, without the need to develop any FPGA IP. family of high performance XMC modules based on the Xilinx Virtex-6 FPGA. A high- Extendable IP Design speed data converter, it is suitable for For applications that require specialized connection to HF or IF ports of a communi- cations or radar system. Its built-in data functions, users can install their own custom ® IP for data processing. Pentek GateFlow capture features offer an ideal turnkey solu- FPGA Design Kits include all of the factory tion as well as a platform for developing and deploying custom FPGA processing IP. installed modules as documented source code. Developers can integrate their own The 53640 includes a 3.6 GHz, 12-bit IP with the Pentek factory-installed functions A/D converter and four banks of memory. It features built-in support for PCI Express or use the GateFlow Design Kit to completely replace the Pentek IP with their own. over the 3U VPX backplane. Xilinx Virtex-6 FPGA The Cobalt Architecture The Pentek Cobalt architecture features The Virtex-6 FPGA can be populated with a variety of different FPGAs to match a Virtex-6 FPGA. All of the board’s data and control paths are accessible by the FPGA, the specific requirements of the processing task. Supported FPGAs include: LX130T, enabling factory-installed functions includ- LX240T, LX365T, SX315T, or SX475T. The ing data multiplexing, channel selection, data packing, gating, triggering and memory SXT parts feature up to 2016 DSP48E1 slices and are ideal for modulation/demodulation, control. The Cobalt architecture organizes encoding/decoding, encryption/decryption, the FPGA as a container for data processing applications where each function exists as and channelization of the signals between transmission and reception. For applications an intellectual property (IP) module. not requiring large DSP resources, one of Each member of the Cobalt family is delivered with factory-installed applications the lower-cost LXT FPGAs can be installed. Option -104 provides 20 pairs of LVDS ideally matched to the board’s analog inter- connections between the FPGA and the faces. The 53640 factory-installed functions include an A/D acquisition IP module. In VPX P2 connector for custom I/O. Option -105 provides dual 4X gigabit addition, IP modules for DDR3 memories, a links between the FPGA and the VPX P1 controller for all data clocking and synchro- Features nization functions, a test signal generator connector to support serial protocols. ➤ ■ Ideal radar and software and a PCIe interface complete the factory- radio interface solution ■ Supports Xilinx Virtex-6 LXT and SXT FPGAs RF In RF In ■ One-channel mode with 3.6 GHz, 12-bit A/D RF RF ■ Two-channel mode with XFORMR XFORMR Sample Clk 1.8 GHz, 12-bit A/Ds TTL TIMING BUS PPS/Gate/Sync ■ 2 GB of DDR3 SDRAM GENERATOR 3.6 GHz (1 Channel) A/D Clock/Sync Bus or ■ Sync bus for multiboard Gate In Clock / Sync / 1.8 GHz (2 Channel) Reset In Gate / PPS 12-Bit A/D synchronization Ref Clk In Ref Clk Out 12 12 ■ LVDS connections to the Sync Bus Virtex-6 FPGA for custom I/O ■ 3U VPX form factor provides VIRTEX-6 FPGA LX130T, LX240T, LX365T, SX315T or SX475T a compact, rugged platform Option -105 Gigabit Serial I/O GTX GTX GTX ■ Compatible with several VITA standards including: 32 32 32 32 16 40 VITA-46, VITA-48 and 8X 4X 4X DDR3 DDR3 DDR3 DDR3 Option -104 Config TM SDRAM SDRAM SDRAM SDRAM VITA-65 (OpenVPX FLASH FPGA x8 512 MB 512 MB 512 MB 512 MB 64 MB PCIe I/O System Specification) Memory Banks1&2 Memory Banks3&4 CROSSBAR ■ Ruggedized and conduction- SWITCH cooled versions available 4X 4X 4X 4X Gbit Gbit Gbit Gbit Serial Serial Serial Serial VPX-P2 VPX-P1 VPX BACKPLANE One Park Way ◆ Upper Saddle River ◆ New Jersey 07458 Pentek, Inc. www.pentek.com . . . . Tel: 201 818 5900 ◆ Fax: 201 818 5904 ◆ Email: info pentek.com @ New! New! New! New! New! Model 53640 1-Ch. 3.6 GHz or 2-Ch. 1.8 GHz, 12-bit A/D, V-6 FPGA - 3U VPX ➤ ➤ A/D Converter Stage ➤ ➤ ➤ synchronized, ideal for larger multichanel The front end accepts analog HF or IF systems. The sync bus includes gate, reset and in and out reference clock signals. inputs on a pair of front panel SSMC con- nectors with transformer coupling into a Multiple 53640s can be synchronized using the Cobalt high speed sync board to drive National Semiconductor ADC12D1800 12-bit the sync bus. A/D. The converter operates in single- channel interleaved mode with a sampling Memory Resources rate of 3.6 GHz and an input bandwidth of The 53640 architecture supports four 1.75 GHz; or, in dual-channel mode with a sampling rate of 1.8 GHz and input band- independent memory banks of DDR3 SDRAM. Each bank is 512 MB deep and is width of 2.8 GHz. an integral part of the board’s DMA and The ADC12D1800 provides a program- mable 15-bit gain adjustment allowing the data capture capabilities. Built-in memory functions include an A/D data transient 53640 to have a full scale input range of capture mode for taking snapshots of data +2 dBm to +4 dBm. A built-in AutoSync fea- ture supports A/D synchronization across for transfer to a host computer. A/D Acquisition IP Module In addition to the factory-installed multiple boards. functions, custom user-installed IP within The 53640 features an A/D The A/D digital outputs are delivered into the Virtex-6 FPGA for signal process- the FPGA can take advantage of the memo- Acquisition IP Module for easy ries for many other purposes. capture and data moving. The IP ing, data capture or for routing to other module can receive data from module resources. PCI Express Interface the A/D, or a test signal generator. Clocking and Synchronization The Model 53640 includes an industry The IP module has associated standard interface fully compliant with PCI memory banks for buffering data The 53640 accepts a 1.8 GHz dual-edge sample clock via a front panel SSMC con- Express Gen. 1 & 2 bus specifications. in FIFO mode or for storing data Supporting PCIe links of x4 or x8, the inter- in transient capture mode. In nector. A second front panel SSMC accepts face includes multiple DMA controllers for single-channel mode, all four a TTL signal that can function as Gate, PPS or Sync. efficient transfers to and from the board. banks are used to store the ➤ single-channel of input data. In A front panel multi-pin sync bus dual-channel mode, memory connector allows multiple boards to be banks 1 and 2 store data from input channel 1 and memory banks 3 and 4 store data from input channel 2. In both modes, continuous, full-rate transient capture of 12-bit data is supported. from from The memory banks are sup- A/D A/D ported with a DMA engine for TEST moving A/D data through the VIRTEX-6 VIRTEX-6 FPGA FPGA D DA AT TAFLOW AFLOW D DET ETAIL AIL SIGNAL (Two channel mode shown) GENERATOR PCIe interface. This powerful INPUT MULTIPLEXER linked-list DMA engine is capable of a unique Acquisition Gate Driven mode. In this mode, the DATA DATA PACKING PACKING length of a transfer performed & FLOW & FLOW CONTROL CONTROL by a link definition need not be to known prior to data acquisition; MUX MUX MEM CONTROL rather, it is governed by the METADATA METADATA length of the acquisition gate. GENERATOR GENERATOR This is extremely useful in appli- LINKED-LIST LINKED-LIST cations where an external gate DMA ENGINE DMA ENGINE drives acquisition and the exact A/D A/D ACQUISITION ACQUISITION length of that gate is not known IP MODULE IP MODULE or is likely to vary. For each transfer, the DMA MEMORY MEMORY CONTROLLER CONTROLLER engine can automatically construct metadata packets containing a PCIe INTERFACE sample-accurate time stamp, and (supports user installed IP) data length information. These actions simplify the host to to to to 8X 4X 4X 40 Mem Mem Mem Mem FPGA Gigabit processor’s job of identifying Bank 1 Bank 2 Bank 3 Bank 4 PCIe GPIO Serial I/O and executing on the data. One Park Way ◆ Upper Saddle River ◆ New Jersey 07458 Pentek, Inc. www.pentek.com . . . . Tel: 201 818 5900 ◆ Fax: 201 818 5904 ◆ Email: info pentek.com @ Model 53640 1-Ch. 3.6 GHz or 2-Ch. 1.8 GHz, 12-bit A/D, V-6 FPGA - 3U VPX ➤ ➤ Fabric-Transparent Crossbar Switch ➤ ➤ ➤ External Trigger Input The 53640 features a unique high-speed Type: Front panel female SSMC connec- tor, TTL switching configuration. A fabric-transparent crossbar switch bridges numerous interfaces Function: Programmable functions include: trigger, gate, sync and PPS and components on the board using gigabit Field Programmable Gate Array serial data paths with no latency. Programmable signal input equalization Standard: Xilinx Virtex-6 XC6VLX130T-2 Optional: Xilinx Virtex-6 XC6VLX240T-2, and output pre-emphasis settings enable XC6VLX365T-2, XC6VSX315T-2, or optimization. Data paths can be selected as single (1X) lanes, or groups of four lanes (4X). XC6VSX475T-2 Custom I/O Specifications Option -104: Provides 20 pairs of LVDS Front Panel Analog Signal Inputs connections between the FPGA and the VPX P2 connector for custom I/O Input Type: Transformer-coupled, front Option -105: Provides one 8X or two panel female SSMC connectors A/D Converter 4X gigabit links between the FPGA and the VPX P1 connector to support serial Type: National Semiconductor protocols ADC12D1800 Sampling Rate: Single-channel mode: Memory: Four 512 MB DDR3 SDRAM memory banks, 400 MHz DDR 500 MHz to 3.6 GHz; dual-channel PCI-Express Interface mode: 150 MHz to 1.8 GHz Resolution: 12 bits PCI Express Bus: Gen. 1or Gen. 2: x4 or x8 Input Bandwidth: single-channel mode: Environmental 1.75 GHz; dual-channel mode: 2.8 GHz Full Scale Input: +2 dBm to +4 dBm, Operating Temp: 0° to 50° C Storage Temp: –20° to 90° C programmable Relative Humidity: 0 to 95%, non-cond. Sample Clock Sources: Front panel SSMC connector Size: 3.937 in. x 6.717 in. (100 mm x 170.6 mm). Sync Bus: Multi-pin connectors, bus includes gate, reset and in and out ref clock Ordering Information Model Description 53640 1-Ch. 3.6 GHz or 2-Ch. 1.8 GHz, 12-bit A/D, Virtex-6 FPGA - 3U VPX Options: -002* -2 FPGA speed grade -062 XC6VLX240T -063 XC6VLX365T -064 XC6VSX315T -065 XC6VSX475T -104 LVDS FPGA I/O to VPX P2 -105 Gigabit serial FPGA I/O to VPX P1 -155* Two 512 MB DDR3 SDRAM Memory Banks (Banks 1 and 2) -165* Two 512 MB DDR3 SDRAM Memory Banks (Banks 3 and 4) * these options always included Contact Pentek for availability of rugged and conduction-cooled versions One Park Way ◆ Upper Saddle River ◆ New Jersey 07458 Pentek, Inc. www.pentek.com . . . . Tel: 201 818 5900 ◆ Fax: 201 818 5904 ◆ Email: info pentek.com @