PENTEK 5341-430
Specifications
A/D Converters
Type: Linear Technology LTC2255. Sampling Rate: 1 MHz to 125 MHz. Internal Clock: Crystal oscillator A or B. External Clock: 1 to 125 MHz. Resolution: 14 bits
Analog Signal Inputs
Input Type: Transformer-coupled, front. panel female MMCX connectors. Transformer Type: Coil Craft WBC1-1TLB. Full Scale Input: +10 dBm into 50 ohms. 3 dB Passband: 250 kHz to 300 MHz
Digital Downconverter
Type: TI/Graychip GC4016 Decimation: 32 to 16,384; with channel. combining mode: 8 or 16. Data Source: A/D, FPGA, or PCI interface. Control Source: FPGA or PCI interface. Output: Parallel complex data
Field Programmable Gate Array
Type: Xilinx Virtex-II Pro XC2VP50
Memory
DDR SDRAM: 512 MB in three banks
Features
- 256 programmable NCOs with 32-bit frequency tuning resolution
- 3U VPX form factor
- Complete software radio interface solution
- GateFlow Core 430 with 256 channels of narrowband digital downconverters factory-installed
- LVDS clock/sync bus for multiboard synchronization
- Programmable decimation settings from 1024 to 9984 in steps of 256
Datasheet
Extracted Text
Model 5341-430 GateFlow T ransceiver , 256-Channel Narrowband DDC - 3U VPX Installed Core General Information coefficients for the DDCs. Default DDC Model 5341-420 is a software radio trans- filter coefficient sets are included with the core for all possible decimation settings. ceiver suitable for connection to HF or IF ports of a communications system. It features Core 430 utilizes a unique method of channelization. It differs from others in that two A/D and two D/A converters with the channel center frequencies need not be built-in support for PCI Express (PCIe) Gen. 2 over the 3U VPX backplane. A unique at fixed intervals, and are independently programmable to any value. fabric-transparent crossbar switch bridges Model 7841 numerous interfaces and components on the Performance board with no latency. Parameter Value The receiver section features two LTC2255 125 MHz 14-bit A/D converters and one TI Input Data Resolution 16-bit GC4016 quad multiband digital down- Output Data Resolution 16-bit Complex converter. The digital outputs of the A/Ds 32 Tuning Resolution Clock Freq / 2 are delivered to the Virtex-II Pro FPGA and to Decimation 1024 – 9984 other board resources including the GC4016 in steps of 256 which supports a decimation range from 32 Passband Ripple <0.4 dB with default to 16,384. For an A/D sample clock frequency filter coefficients of 100 MHz, the output bandwidth for Usable Bandwidth 80% with default each of the four channels ranges from 2.5 MHz filter coefficients down to 5 kHz. By combining two or four Stopband Attenuation >75 dB channels, decimations of 16 or 8 can be NCO SFDR >110 dB achieved for an output bandwidth of up to 5 or 10 MHz, respectively. Features Flexible Architecture For applications that require many Core 430 DDC comes factory-installed ■ Complete software radio channels of narrowband downconverters, in this Model. A multiplexer in front of the interface solution Pentek offers the GateFlow IP Core 430 256-Channel Digital Downconverter bank. core allows data to be sourced from either ■ 3U VPX form factor A/D converter, A or B. At the output, a Factory installed in the 5341-430 FPGA, ■ GateFlow Core 430 with 256 multiplexer allows for routing either the Core 430 creates a flexible, very high channel channels of narrowband count receiver system in a small footprint. output of the GC4016 or the Core 430 DDC digital downconverters factory- to the PCI Bus. installed Core 430: 256-Channel DDC Bank In addition to the DDC outputs, data from ■ 256 programmable NCOs Unlike legacy channelizer methods, the both A/D channels are presented to the PCI with 32-bit frequency tuning Bus at a rate equal to the A/D clock rate Pentek 430 core allows for independent pro- resolution divided by any interger value between 1 and grammable tuning of each channel with 32-bit ■ Programmable decimation resolution. Filter characteristics are compa- 4096. A Texas Instruments DAC5686 digital settings from 1024 to 9984 upconverter and dual D/A accepts baseband rable to many conventional ASIC DDCs. in steps of 256 real or complex data streams from the PCI Bus Added flexibility comes from program- ■ LVDS clock/sync bus for mable global decimation settings ranging with signal bandwidths up to 50 MHz. The multiboard synchronization analog outputs are transformer-coupled to from 1024 to 9984 in steps of 256, and 18-bit front panel MMCX connectors. user programmable FIR decimating filter ➤ LTC2255 CH A A/D A RF 125 MHz RF In XFORMR FIFO 14-bit A/D A/D B FIFO CHAN 1 FIR 1 DDC OUTPUT LTC2255 COMPENSATION CH B RF CHAN 2 1 GAIN 125 MHz C FILTER RF In OUT A XFORMR 14-bit A/D H CHAN 3 DDC A DDC A PCI 2.2 A FIFO FIR 2 DDC OUTPUT N INTERFACE COMPENSATION 2 GAIN OUT B A/D A N FILTER DDC B E MUX DDC B PCI-BUS FIFO M M L CHANNEL 64 Bits/66 MHz A/D B U I SWITCH U XTAL OUT C X Z MATRIX X DDC C OSC A PCI TO Sample FIR DDC C A DDC FIFO 255 OUTPUT Clock A In A B C D PCIe BRIDGE T COMPENSATION 255 GAIN I CHAN 1022 FILTER OUT D MUX CLOCK & DDC D O x4 PCIe Clock/Sync DDC D CHAN 1023 SYNC FIFO GC4016 DIGITAL N FIR Bus 256 DDC OUTPUT GENERATOR DOWNCONVERTER CHAN 1024 COMPENSATION PCI EXPRESS SWITCH 256 GAIN FILTER PEX 8648 Sample A B C D Clock B In COARSE TUNING XTAL 24 lanes / 6 ports OSC B 24 each configurable FINE TUNING TUNING as x1/x4/x8/x16 CONTROL CROSSBAR 16-BIT CH A SWITCH RF 500 MHz RF Out XFORMR D/A D/A A DAC5686 4X 4X 4X 4X DIGITAL FIFO Gbit Gbit Gbit Gbit 16-BIT UPCONVERTER Serial Serial Serial Serial CH B RF D/A B 500 MHz RF Out XFORMR FIFO VPX-P1 D/A XILINX XC2VP50 FPGA WITH GATEFLOW FACTORY INSTALLED CORE 430 VPX BACKPLANE One Park Way ◆ Upper Saddle River ◆ New Jersey 07458 Pentek, Inc. www.pentek.com . . . . Tel: 201 818 5900 ◆ Fax: 201 818 5904 ◆ Email: info pentek.com @ New! New! New! New! New! Model 5341-430 GateFlow T ransceiver , 256-Channel Narrowband DDC - 3U VPX Installed Core ➤ ➤ ➤ ➤ ➤ Clocking and Synchronization A/D Converters Two independent internal timing buses Type: Linear Technology LTC2255 Sampling Rate: 1 MHz to 125 MHz can provide either a single clock or two different clock rates for the input and Internal Clock: Crystal oscillator A or B External Clock: 1 to 125 MHz output signals. Resolution: 14 bits Each timing bus includes a clock, a sync, and a gate or trigger signal. Signals from Digital Downconverter Fabric-Transparent Crossbar Type: TI/Graychip GC4016 either Timing Bus A or B can be selected as Decimation: 32 to 16,384; with channel the timing source for the A/Ds, the downcon- Switch verters, the upconverters and the D/As. combining mode: 8 or 16 The 5341-430 features a unique Data Source: A/D, FPGA, or PCI interface Two external reference clocks are accepted, high-speed switching configura- Control Source: FPGA or PCI interface one for each timing bus and two internal tion. A fabric-transparent crossbar clocks may be used for each timing bus. Output: Parallel complex data switch connects the PCI Express Receiver Bypass Mode: Data from the A/Ds Front panel 26-pin LVDS Clock/Sync switch with the VPX-P1 connec- can be written directly into the FPGAs at connectors allow multiple boards to be syn- tor using gigabit serial data paths chronized. In the slave mode, they accept a rate equal to the A/D clock decimated by with no latency. This allows the any integer between 1 and 4096 differential LVDS inputs that drive the clock, user to select the desired port on Front Panel Analog Signal Outputs sync and gate signals for the two internal VPX-P1. Programmable signal timing buses. Output Type: Transformer-coupled, input equalization and output front panel female MMCX connectors In the master mode, the LVDS bus can pre-emphasis settings on the Full Scale Output: +4 dBm into 50 ohms drive one or both sets of timing signals Crossbar Switch enable optimi- from the two internal timing buses for 3 dB Passband: 60 kHz to 300 MHz zation. Digital Upconverter synchronizing multiple modules. Type: TI DAC5686 Up to seven slave 5341-430’s can be driven from the LVDS bus master, supporting Input Bandwidth: 40 MHz, max. Output IF: DC to 160 MHz synchronous sampling and sync functions Output Signal: Analog, real or quadrature across all connected boards. Sampling Rate: 320 MHz, max; 500 MHz Memory Resources max. with upconversion disabled Resolution: 16 bits Three independent banks of SDRAM are available. Built-in memory functions in- Clock Sources: Selectable from onboard A or B crystal oscillators, external or LVDS clocks clude an A/D data transient capture mode External Clocks with pre- and post-triggering; a D/A wave- form generator mode; and an A/D data Type: Front panel female MMCX connec- tor, sine wave, 0 to +10 dBm, AC- coupled, delay mode for applications like tracking 50 ohms receivers. User-installed functions within the FPGA can take advantage of the Sync/Gate Bus: 26-pin connector, dual clock/sync/gate input/output LVDS SDRAM for many other purposes. buses; one sync/gate input TTL signal PCI Express Switch Field Programmable Gate Array Model 5341-430 includes a PCIe Gen. 2 Type: Xilinx Virtex-II Pro XC2VP50 Memory switch. The switch provides a total of 24 PCIe lanes to the Fabric-Transparent Cross- DDR SDRAM: 512 MB in three banks PCI to PCIe Interface bar Switch on 6 ports. Dynamic lane width PCI Bus: 64-bit, 66 MHz negotiation within the PCIe switch allows for x1, x4, x8 or x16 widths. These can be DMA: 9 channel demand-mode and chaining controller selected in any combination. Gigabit Serial I/O Specifications VPX-P1: Four 4X ports to Fabric-Trans- Analog Signal Inputs parent Crossbar Switch PCI Express: Six ports to Fabric-Trans- Input Type: Transformer-coupled, front panel female MMCX connectors parent Switch, each configurable as x1, x4, x8 or x16 lanes, 24 lanes total Transformer Type: Coil Craft Ordering Information Environmental (Commercial version) WBC1-1TLB Model Description Full Scale Input: +10 dBm into 50 ohms Operating Temp: 0° to 50° C 5341-430 GateFlow Transceiver Storage Temp: –20° to 90° C 3 dB Passband: 250 kHz to 300 MHz with 256-Channel Relative Humidity: 0 to 95%, non-cond. Narrowband DDC Size: 3.937 in. x 6.717 in. (100 mm x 170.6 mm) factory-installed - 3U VPX Contact Pentek for available options One Park Way ◆ Upper Saddle River ◆ New Jersey 07458 Pentek, Inc. www.pentek.com . . . . Tel: 201 818 5900 ◆ Fax: 201 818 5904 ◆ Email: info pentek.com @ Model 5341-430 GateFlow T ransceiver , 256-Channel Narrowband DDC - 3U VPX Installed Core A/D Performance Spurious Free Dynamic Range Spurious Pick-up Model 7841 f = 70 MHz, f = 100 MHz f = 100 MHz, 32k point FFT, 8 averages in s s Input Frequency Response Two-Tone SFDR f = 100 MHz f = 29.5 MHz, f = 30.5 MHz, f = 100 MHz s 1 2 s Crosstalk Phase Noise f = 69 MHz, f = 100 MHz, Ch 1 shown f = 69 MHz, f = 100 MHz in Ch2 s in s Phase Noise @ 100 kHz = -102 - 10*log(610) = -129.8 dB/Hz One Park Way ◆ Upper Saddle River ◆ New Jersey 07458 Pentek, Inc. www.pentek.com . . . . Tel: 201 818 5900 ◆ Fax: 201 818 5904 ◆ Email: info pentek.com @ Model 5341-430 GateFlow T ransceiver , 256-Channel Narrowband DDC - 3U VPX Installed Core D/A Performance Two-Tone Intermodulation Distortion f = 69.5 MHz, f = 70.5 MHz, f = 100 MHz 1 2 s One Park Way ◆ Upper Saddle River ◆ New Jersey 07458 Pentek, Inc. www.pentek.com . . . . Tel: 201 818 5900 ◆ Fax: 201 818 5904 ◆ Email: info pentek.com @
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