Model 5341 Dual Multiband Transceiver with FPGA - 3U VPX General Information processing engine, SDRAM delay memory Model 5341 is a software radio transceiver and data sources on the VPX backplane. Each GC4016 channel may be set for inde- suitable for connection to HF or IF ports of a communications system. It features two pendent tuning frequency and bandwidth. For an A/D sample clock frequency of A/D and two D/A converters, and is capable 100 MHz, the output bandwidth for each of bandwidths to 50 MHz and above. The 5341 features built-in support for channel ranges from 5 kHz up to 2.5 MHz. By combining channels, output bandwidth of up PCI Express (PCIe) Gen. 2 over the 3U VPX to 5 or 10 MHz can be achieved. backplane. A unique fabric-transparent crossbar switch configuration adds gigabit Digital Upconverter Stage serial data paths for Xilinx Aurora or Serial A TI DAC5686 digital upconverter and RapidIO applications. dual D/A is attached to the FPGA, accepting A/D Converter Stage baseband real or complex data streams with signal bandwidths up to 40 MHz. The front end accepts two full scale ana- log HF or IF inputs on front panel MMCX When operating as an upconverter, it connectors at +10 dBm into 50 ohms with interpolates and translates real or complex baseband input signals to any IF center transformer coupling into LTC2255 14-bit 125 MHz A/Ds. frequency between DC and 160 MHz. It delivers real or quadrature (I+Q) analog The digital outputs are delivered into the outputs through two 320 MHz 16-bit D/A Virtex-II Pro FPGA for signal processing or for routing to other module resources. converters to two front panel MMCX con- nectors at +4 dBm into 50 ohms. Digital Downconverter Stage If translation is disabled, the DAC5686 The 5341 features a TI/Graychip GC4016 acts as a two channel interpolating 16-bit D/A with output sampling rates up to 500 MHz. quad digital downconverter, accepting Features either four 14-bit inputs or three 16-bit digital ■ Complete software radio Virtex-II Pro FPGAs inputs from the FPGA, which determines interface solution for 3U VPX A Xilinx XC2VP50 Virtex-II Pro FPGA the source of GC4016 input data. These systems serves as a control and status engine with sources include the A/Ds, FPGA signal ➤ ■ Supports Gigabit Serial Fabrics including PCI Sample Express, Serial RapidIO Clock A In and Xilinx Aurora RF In RF In RF Out RF Out LVDS TIMING BUS XTL Clock A GENERATOR A ■ Two 125 MHz 14-bit A/Ds OSC. A RF XFORMR RF XFORMR RF XFORMR RF XFORMR LVDS ■ Four digital downconverters Sync A Clock/Sync/ LVDS Gate RF XFORMR 16-BIT D/A 16-BIT D/A ■ One digital upconverter Gate A SYNC Bus A 125 MHz 125 MHz DAC5686 INTERRUPTS TTL Gate/ ■ Two 500 MHz 16-bit D/As 14-BIT A/D 14-BIT A/D DIGITAL UPCONVERTER Trigger & CONTROL Bus B TTL Sync ■ 512 MB of DDR SDRAM 32 14 14 LVDS ■ Xilinx Virtex-II Pro FPGA Gate B GC4016 4-CHANNEL FLASH LVDS 16 DDC ■ Up to 1.28 seconds of delay 16 MB Sync B 16 16 LVDS or data capture at 100 MHz 14 24 TIMING BUS XTL 32 Clock B GENERATOR B OSC. B ■ Dual timing buses for XC2VP50 VIRTEX-II PRO FPGA DSP - DDC - DUC - Digital Delay - Demodulation - Decoding - Control independent input and Sample GTP LVDS Control/ Clock B In output clock rates Status 32 32 32 64 To All Sections DDR DDR DDR ■ LVDS clock/sync bus for SDRAM SDRAM SDRAM 128 MB 128 MB 256 MB PCI 2.2 INTERFACE 32 4X multiboard synchronization (64 bits/66 MHz) ■ 32 pairs of LVDS connections 64 to the Virtex-II Pro FPGA for PCI TO XMC - P15 PMC - P14 PCIe BRIDGE custom I/O x4 PCIe ■ Compatible with several 4X PCI EXPRESS SWITCH VITA standards including: PEX 8648 24 lanes / 6 ports VITA-46 (VPX Baseline 24 each configurable as x1/x4/x8/x16 Standard) 32 CROSSBAR VITA-48 (VPX REDI) SWITCH TM VITA-65 (OpenVPX 4X 4X 4X 4X Gbit Gbit Gbit Gbit System Specification) Serial Serial Serial Serial VPX-P1 VPX-P2 VPX BACKPLANE One Park Way ◆ Upper Saddle River ◆ New Jersey 07458 Pentek, Inc. www.pentek.com . . . . Tel: 201 818 5900 ◆ Fax: 201 818 5904 ◆ Email: info pentek.com @ New! New! New! New! New! Model 5341 Dual Multiband Transceiver with FPGA - 3U VPX data and programming interfaces to each A/D Converters ➤ of the on-board resources including the A/D Type: Linear Technology LTC2255 converters, digital downconverter, digital Sampling Rate: 1 MHz to 125 MHz upconverter and D/A converters. Factory Internal Clock: Crystal osc. (2 per A/D) Fabric-Transparent Crossbar installed FPGA functions include data multi- External Clock: 1 to 125 MHz Switch plexing, channel selection, data packing, gating, Resolution: 14 bits The 5341 features a unique triggering and SDRAM memory control. Digital Downconverter high-speed switching configura- Option -104 provides general purpose Type: TI/Graychip GC4016 tion. A fabric-transparent crossbar I/O to VPX-P2 with 16 pairs of LVDS con- Decimation: 32 to 16,384; with channel adds switch connects the PCI Express nections to the FPGA. Option -5xx combining mode: 8 or 16 switch with the VPX-P1 connec- four full duplex 4X gigabit serial paths to Data Source: A/D, FPGA, or PCI interface tor using gigabit serial data paths VPX-P1 connector. Control Source: FPGA or PCI interface with no latency. This allows the Output: Parallel complex data Clocking and Synchronization user to select the desired output Receiver Bypass Mode: Data from the A/Ds port on VPX-P1. Programmable Two independent internal timing buses can be written directly into the FPGAs at signal input equalization and can provide either a single clock or two a rate equal to the A/D clock decimated by output pre-emphasis settings on different clock rates for the correspond- any integer between 1 and 4096 the Crossbar Switch enable opti- ing input and output signals. Front Panel Analog Signal Outputs mization. Each timing bus includes a clock, sync, Output Type: Transformer-coupled, and gate or trigger signal. Signals from front panel female MMCX connectors PCI Express Switch either Timing Bus can be selected as the timing Full Scale Output: +4 dBm into 50 ohms Model 5341 includes a PCIe source for the A/Ds, downconverter, upcon- Option -002: –2 dBm into 50 ohms Gen. 2 switch. The switch pro- verter and D/As. Two external reference 3 dB Passband: 60 kHz to 300 MHz vides a total of 24 PCIe lanes to clocks or two internal clocks may be used Option -002: 400 kHz to 800 MHz the Fabric-Transparent Crossbar for each timing bus. Digital Upconverter Switch on 6 ports. Dynamic lane A front panel 26-pin LVDS Clock/Sync Type: TI DAC5686 width negotiation within the connector allows multiple boards to be Input Bandwidth: 40 MHz, max. PCIe switch allows for x1, x4, synchronized. In the slave mode, each Output IF: DC to 160 MHz x8 or x16 widths. These can be accepts differential LVDS inputs that drive Output Signal: Analog, real or quadrature selected in any combination. the clock, sync and gate signals for the Sampling Rate: 320 MHz, max; 500 MHz two internal timing buses. max. with upconversion disabled In the master mode, the LVDS bus can Resolution: 16 bits drive one or both sets of timing signals Clock Sources: Selectable from onboard crystal Ordering Information from the two internal timing buses for oscillators, external or LVDS clocks Model Description synchronizing multiple boards. External Clocks Up to seven slave 5341 boards can be Type: Female MMCX connector, sine 5341 Dual Multiband Transceiver with FPGA - 3U VPX driven from the LVDS bus master, supporting wave, 0 to +10 dBm, AC- coupled, 50 ohm synchronous sampling and sync functions Sync/Gate Bus: 26-pin connector, dual Options: across all connected boards. clock/sync/gate input/output LVDS -002 Full-scale output: –2 dBm buses; one sync/gate input TTL signal into 50 ohms; Memory Resources Field Programmable Gate Array 3 dB passband: 400 kHz Three independent banks of SDRAM Type: Xilinx Virtex-II Pro to 800 MHz are available to the FPGA (to 1 GB max.). Option -050: XC2VP50 -050 XC2VP50 Virtex-II Pro FPGA Built-in memory functions include an A/D Option -104: 64 lines (32 pairs) data transient capture mode with pre- and Memory -100 100 MHz Bus A and Bus B oscillators post-triggering; a D/A waveform generator DDR SDRAM: 512 MB in three banks mode; and an A/D data delay mode for FLASH: One bank of 16 MB -101 TI DAC5687 replaces the applications such as tracking receivers. PCI to PCIe Interface TI DAC5686 The SDRAMs are also available as a PCI Bus: 64-bit, 66 MHz -104 FPGA I/O to VPX-P2 resource for the two PowerPC processor DMA: 9-channel demand-mode and -125 125 MHz Bus A and cores within the FPGA. A 16 MB FLASH chaining controller per PCI bus 100 MHz Bus B internal oscillators memory supports booting and program Gigabit Serial I/O: store for these processors. FPGA: One 4X port to Crossbar Switch -420 Dual wideband DDC and VPX-P1: Four 4X ports to Crossbar Switch digital interpolation filter Specifications cores, factory-installed in PCI Express: Six ports to Crossbar FPGA Analog Signal Inputs Switch, each configurable as x1, x4, x8 or -430 256-channel narrowband Input Type: Transformer-coupled, front x16 lanes, 24 lanes total DDC core, factory-installed panel female MMCX connectors Environmental (Commercial version) in FPGA Transformer Type: Coil Craft WBC1-1TLB Operating Temp: 0° to 50° C -5xx Gigabit Serial I/O to VPX- Full Scale Input: +10 dBm into 50 ohms Storage Temp: –20° to 90° C P1 - four full-duplex 4X 3 dB Passband: 250 kHz to 300 MHz Relative Humidity: 0 to 95%, non-cond. paths Size: 3.937 in. x 6.717 in. (100 mm x 170.6 mm) One Park Way ◆ Upper Saddle River ◆ New Jersey 07458 Pentek, Inc. www.pentek.com . . . . Tel: 201 818 5900 ◆ Fax: 201 818 5904 ◆ Email: info pentek.com @ Model 5341 Dual Multiband Transceiver with FPGA - 3U VPX A/D Performance Spurious Free Dynamic Range Spurious Pick-up f = 70 MHz, f = 100 MHz f = 100 MHz, 32k point FFT, 8 averages in s s Input Frequency Response Two-Tone SFDR f = 100 MHz f = 29.5 MHz, f = 30.5 MHz, f = 100 MHz s 1 2 s Crosstalk Phase Noise f = 69 MHz, f = 100 MHz, Ch 1 shown f = 69 MHz, f = 100 MHz in Ch2 s in s Phase Noise @ 100 kHz = -102 - 10*log(610) = -129.8 dB/Hz One Park Way ◆ Upper Saddle River ◆ New Jersey 07458 Pentek, Inc. www.pentek.com . . . . Tel: 201 818 5900 ◆ Fax: 201 818 5904 ◆ Email: info pentek.com @ Model 5341 Dual Multiband Transceiver with FPGA - 3U VPX D/A Performance Two-Tone Intermodulation Distortion f = 69.5 MHz, f = 70.5 MHz, f = 100 MHz 1 2 s One Park Way ◆ Upper Saddle River ◆ New Jersey 07458 Pentek, Inc. www.pentek.com . . . . Tel: 201 818 5900 ◆ Fax: 201 818 5904 ◆ Email: info pentek.com @