Model 5331 16-Channel Multiband Receiver with A/Ds and FPGA - 3U VPX General Information channels capable of center frequency tuning Model 5331 is a general-purpose from DC to ƒ /2, where ƒ is the sample S S clock frequency. 16-channel multiband digital receiver 3U VPX board. It includes both a Virtex-II Each GC4016 accepts two 14-bit parallel inputs from the two A/D converters. A cross- FPGA and two 14-bit A/Ds for signal pro- bar switch in each GC4016 allows all 16 cessing. The 5331 features built-in support for PCI Express (PCIe) Gen. 2 over the 3U channels on the board to select either of the two A/D inputs for flexible switching. VPX backplane. Output Bandwidth Front End The Model 5331 accepts two analog RF With a 100 MHz sample clock, the useable output bandwidth of each of the inputs at +4 dBm full scale into 50 ohms on front panel SMA connectors. downconverter channels is 2.5 MHz. How- ever, since the Model 5331 delivers parallel The two inputs are transformer coupled digital outputs from the GC4016 into the and digitized by AD6645 14-bit A/D con- verters. The AD6645 operates at a maximum FPGA, users can take advantage of the GC4016 channel combining mode to join sampling rate of 80 MHz in the standard unit two or four channels into a single channel and up to 105 MHz for option -100. The sampling clock can be driven from with a resulting bandwidth of 5 or 10 MHz, respectively. This supports many of the an internal 80 MHz or 100 MHz crystal new wideband wireless standards. oscillator, or from an external sample clock supplied through a front panel SMA con- Since both A/D converters connect directly to the FPGAs, signals with even nector or the front panel sync bus. wider bandwidths can be accommodated. Digital Downconverters Features FPGA The 5331 includes four TI/Graychip ■ Complete software radio The downconverter outputs are deliv- GC4016 quad multiband digital downcon- interface solution for 3U VPX verter chips. The maximum input sampling ered to a Xilinx Virtex-II XC2V1000 FPGA systems (XC2V3000 with option -300) which is factory rate for the GC4016 is 100 MHz. Each configured to perform various modes of data device includes four independently tunable ■ Supports Gigabit Serial packing, formatting and channel selection. ➤ Fabrics including PCI Express, Serial RapidIO Sample and Xilinx Aurora Clock In RF In RF In ■ Two 80 or 105 MHz, 14-bit CLOCK XTL RF RF GENERATOR A/D converters LVDS Clock OSC. TRANSFORMER TRANSFORMER ■ 16 channels of multiband LVDS Sync digital downconverters A/D Clock AD6645 AD6645 LVDS Gate 14-BIT A/D 14-BIT A/D ■ 5 kHz to 10 MHz output LVDS Trigger 14 14 bandwidth for ƒ = 100 MHz S TTL Gate/ Trigger SYNCHRONIZATION ■ 250 MHz input bandwidth INTERRUPTS GC4016 GC4016 GC4016 GC4016 TTL Sync 4-CHANNEL 4-CHANNEL 4-CHANNEL AND CONTROL 4-CHANNEL ■ Ideal for IF sampling DDC DDC DDC DDC ■ User-configurable Xilinx I&Q I&Q I&Q I&Q Control/ Virtex-II FPGA Status Virtex-II FPGA LVDS ■ Custom FPGA I/O through the VPX P-2 64 ■ Bypass path allows direct PCI INTERFACE 32 capture of A/D data (64 bits/66 MHz) ■ LVDS clock/sync bus for 64 multiboard synchronization PCI TO PMC - P14 PCIe BRIDGE ■ Compatible with several x4 PCIe VITA standards including: PCI EXPRESS SWITCH VITA-46 (VPX Baseline PEX 8648 Standard) 24 lanes / 6 ports 24 each configurable as x1/x4/x8/x16 VITA-48 (VPX REDI) 32 TM CROSSBAR VITA-65 (OpenVPX SWITCH System Specification) 4X 4X 4X 4X Gbit Gbit Gbit Gbit Serial Serial Serial Serial VPX-P1 VPX-P2 VPX BACKPLANE One Park Way ◆ Upper Saddle River ◆ New Jersey 07458 Pentek, Inc. www.pentek.com . . . . Tel: 201 818 5900 ◆ Fax: 201 818 5904 ◆ Email: info pentek.com @ Model 5331 16-Channel Multiband Receiver with A/Ds and FPGA - 3U VPX Dual-port memories in the FPGA Full Scale Input: +4 dBm into 50 ohms ➤ provide efficient transfers by buffering 3 dB Passband: 60 kHz to 270 MHz receiver and A/D data. The A/D outputs A/D Converters, Standard are also connected directly to the FPGA so Type: Analog Devices AD6645-80 that wideband A/D data can be delivered Sampling Rate: 30 MHz to 80 MHz directly to the baseboard bypassing the Internal Clock: 80 MHz crystal osc. downconverters. An A/D decimation mode External Clock: 30 to 80 MHz allows one of every N samples to be written Resolution: 14 bits Fabric-Transparent Crossbar into the FPGA memory, where N is any integer A/D Converters, Option -100 Switch between 1 and 4096. This overcomes the Type: Analog Devices AD6645-105 The 5331 features a unique lower frequency limit on the A/D sample clock. Sampling Rate: 30 MHz to 105 MHz high-speed switching configura- Option -104 provides general purpose Internal Clock: 100 MHz crystal osc. tion. A fabric-transparent crossbar I/O to VPX-P2 with 16 pairs of LVDS con- External Clock: 30 to 105 MHz switch bridges numerous inter- nections to the FPGA. Option -5xx adds Resolution: 14 bits faces and components on the four full duplex 4X gigabit serial paths to Clock Source: Onboard crystal oscillator, VPX-P1 connector. board using gigabit serial data front panel ext clock, or LVDS clock paths with no latency. Program- External Clock Synchronization mable signal input equalization Type: Front panel female SMA connec- The front panel clock and sync bus allow and output pre-emphasis set- tor, sine wave, 0 to +10 dBm, AC- coupled, tings enable optimization. Data one 5331 to act as a master, driving the 50 ohms impedance paths can be selected as single (x1) sample clock out to a front panel cable bus Sync/Gate Bus lanes, or groups of four lanes (x4). using LVDS differential signaling. Type: 26-pin connector, with one clock, Additional sync lines on the bus allow one sync, and two gate input/output synchronization of the local oscillator phase, LVDS signals; two trigger LVDS inputs; frequency switching, decimating filter phase, and one sync and one gate input TTL and data collection on multiple boards. signals Up to eight slave 5331’s can be driven from Digital Downconverters the LVDS bus master, supporting synchronous Type: TI/Graychip GC4016 sampling and sync functions across all con- Decimation: 32 to 16,384; with channel nected boards. In addition to the LVDS timing combining mode: 8 or 16 bus, the Model 5331 can receive front panel Data Source: A/D outputs are connected TTL input signals for gate or trigger functions. to all GC4016’s Output: Parallel complex data Interrupt Sources Bypass Mode: Data from the A/D convert- The Model 5331 has several maskable ers can be written directly into the interrupt sources. PCI interrupts may be FPGAs at a sample rate equal to the A/D generated by A/D converter overload out- clock decimated by any integer between put codes, transitions on the gate signals, 1 and 4096 clock loss, buffer swapping, or a program- Field Programmable Gate Array mable over-temperature condition or faulty Type: Xilinx Virtex-II XC2V1000 standard power supply voltage. The ADM1024 Volt- Option -300: Virtex-II XC2V3000 age/Temperature Monitor provides constant Option -104: Installs the P4 connector monitoring of critical voltages and tempera- with 37 lines to the XC2V1000 or 64 tures and generates an interrupt if values lines to the XC2V3000 FPGA exceed threshold limits which are user pro- Dual Port RAM Data Buffers grammable over the VPX backplane. Size: 4k x 32 DPRAM expandable to 8k x 32 with option -300 FPGA PCI Express Switch PCI to PCIe Interface Model 5331 includes a PCIe Gen. 2 Type: PLX Technology PCI 9656 Ordering Information switch. The switch provides a total of 24 PCI Bus: 64-bit, 66 MHz (also supports Model Description PCIe lanes to the Fabric-Transparent Cross- 32-bit and/or 33 MHz) 5331 16-Channel Multiband bar Switch on 6 ports. Dynamic lane width Gigabit Serial I/O: Receiver with A/Ds and negotiation within the PCIe switch allows VPX-P1: Four 4X ports to Crossbar Switch FPGA - PMC for x1, x4, x8 or x16 widths. These can be PCI Express: Six ports to Crossbar Options: selected in any combination. Switch, each configurable as x1, x4, x8 or -100 105 MHz A/D with x16 lanes, 24 lanes total 100 MHz crystal oscillator Specifications Environmental -104 FPGA I/O to VPX-P2 Front Panel Analog Signal Inputs Operating Temp: 0° to 50° C -300 XC2V3000 FPGA Input Type: Transformer-coupled, front Storage Temp: –20° to 90° C -5xx Gigabit Serial I/O to VPX- panel female SMA connectors Relative Humidity: 0 to 95%, non-cond. P1 - four full-duplex 4X Size: 3.937 in. x 6.717 in. (100 mm x 170.6 mm) Transformer Type: Mini-Circuits ADT4-6T paths One Park Way ◆ Upper Saddle River ◆ New Jersey 07458 Pentek, Inc. www.pentek.com . . . . Tel: 201 818 5900 ◆ Fax: 201 818 5904 ◆ Email: info pentek.com @