Model 5341-420 GateFlow T ransceiver with Dual Wideband DDCs and Installed Core Interpolation Filter - 3U VPX General Information formatter deliver output data in either real Model 5341-420 is a software radio trans- or complex representation. An input gain ceiver suitable for connection to HF or IF block scales both I and Q data streams by a ports of a communications system. It features 16-bit gain term. The NCO provides over two A/D and two D/A converters with 118 dB spurious-free dynamic range (SFDR). built-in support for PCI Express (PCIe) Gen. 2 The mixer utilizes four 18x18-bit multi- over the 3U VPX backplane. A unique pliers to handle the complex inputs from the fabric-transparent crossbar switch bridges NCO and the complex data input samples. Model 7841 numerous interfaces and components on the The FIR filter is capable of storing and utiliz- board with no latency. ing up to four independent sets of 18-bit The receiver section features two LTC2255 coefficients for each decimation value. 125 MHz 14-bit A/D converters and one TI These coefficients are user-programmable GC4016 quad multiband digital down- using RAM structures within the FPGA. converter. Two identical Core 420 DDCs are factory The digital outputs of the A/Ds are deliv- installed in the FPGA. The decimation settings ered to the Virtex-II Pro FPGA and to other of 2, 4, 8, 16, 32, and 64 provide output band- board resources including the GC4016 which widths from 40 MHz down to 1.25 MHz for supports a decimation range from 32 to an A/D sampling rate of 100 MHz. It also 16,384. For an A/D sample clock frequency of delivers better stopband rejection than the 100 MHz, the output bandwidth for each of GC4016 in combined channel modes. Features the four channels ranges from 2.5 MHz down A multiplexer in front of the Core 420 ■ Complete software radio to 5 kHz. By combining two or four channels, DDCs allows data to be sourced from either interface solution decimations of 16 or 8 can be achieved for the A/D converters or from the output of ■ 3U VPX form factor an output bandwidth of up to 5 or 10 MHz, the GC4016, extending the maximum respectively. cascaded decimation factor to 1,048,576. ■ GateFlow Core 420, two For applications that require even wider high-performance wideband Core 420 Interpolation Filter bandwidths, this board includes Pentek’s DDCs and interpolation filter, GateFlow installed Core 420 high-performance The interpolation filter included in the factory-installed wideband DDC, similar in functionality to the 420 Core, expands the interpolation factor ■ Extended DDC decimation GC1012 but with enhanced performance, from 2 to 32,768 programmable in steps of range of 2 to 1,048,576 and an interpolation filter that extends the 2, and relieves the host processor from per- ■ Extended DDC bandwidth range of the DAC5686 D/A converter. forming upsampling tasks. Including the range of 40 MHz to 76.3 Hz DUC, the maximum interpolation factor is ■ Extended DUC interpolation Core 420 Wideband Downconverter 32,768 which is comparable to the maximum range of 2 to 32,768 Like the GC4016, the Core 420 down- decimation of the GC4016 narrowband DDC. ■ Extended DUC bandwidth converter translates any frequency band In addition to the Core 420, all the range of 40 MHz to 2.44 kHz within the input bandwidth range down to standard features of the Model 5341 are zero frequency. A complex FIR low pass retained including D/A waveform generator ■ LVDS clock/sync bus for filter then removes any out of band frequency mode, all data routing and formatting, and multiboard synchronization components. An output decimator and delay and transient capture memory. ➤ LTC2255 CH A RF DDC C 128 MB 125 MHz RF In DDR SDRAM XFORMR DDC D 14-bit A/D MEMORY D/A A CONTROL 128 MB D/A B & DDR SDRAM A/D A DATA ROUTING LTC2255 CH B RF A/D B 125 MHz 256 MB RF In XFORMR 14-bit A/D DDR SDRAM A/D A A/D B WIDEBAND M MEM W DIGITAL U DDC A DDC A FIFO DOWNCONVTER A PCI 2.2 X DDC B DDC B DECIMATION: 2 - 64 MEM R INTERFACE MEMORY XTAL FIFO MEMORY OSC A PCI-BUS Sample A/D A Clock A In A B C D A/D A 64 Bits/66 MHz FIFO A/D B A/D B WIDEBAND MUX M CLOCK & PCI TO A/D B DIGITAL Clock/Sync U DDC A DDC A SYNC GC4016 DIGITAL FIFO PCIe BRIDGE DOWNCONVTER B Bus X GENERATOR DDC B DDC B WB DDC A DOWNCONVERTER DECIMATION: 2 - 64 DDC A MUX DDC A x4 PCIe A B C D FIFO Sample Clock B In WB DDC B XTAL DDC B PCI EXPRESS SWITCH MUX OSC B DDC B FIFO PEX 8648 DDC C 24 lanes / 6 ports FIFO 24 each configurable 16-BIT DDC D as x1/x4/x8/x16 CH A RF 500 MHz FIFO RF Out XFORMR MEMORY D/A CROSSBAR DAC5686 MUX D/A A D/A A FIFO SWITCH DIGITAL CIC CFIR FIFO 16-BIT FILTER FILTER MEMORY UPCONVERTER CH B RF D/A B 4X 4X 4X 4X 500 MHz MUX D/A B FIFO RF Out XFORMR D/A FIFO Gbit Gbit Gbit Gbit INTERPOLATION: 16–2048 Serial Serial Serial Serial VPX-P1 XILINX XC2VP50 FPGA WITH GATEFLOW FACTORY INSTALLED CORE 420 VPX BACKPLANE One Park Way ◆ Upper Saddle River ◆ New Jersey 07458 Pentek, Inc. www.pentek.com . . . . Tel: 201 818 5900 ◆ Fax: 201 818 5904 ◆ Email: info pentek.com @ New! New! New! New! New! Model 5341-420 GateFlow T ransceiver with Dual Wideband DDCs and Installed Core Interpolation Filter - 3U VPX ➤ ➤ ➤ ➤ ➤ Clocking and Synchronization A/D Converters Two independent internal timing buses Type: Linear Technology LTC2255 Sampling Rate: 1 MHz to 125 MHz can provide either a single clock or two different clock rates for the input and Internal Clock: Crystal oscillator A or B External Clock: 1 to 125 MHz output signals. Resolution: 14 bits Each timing bus includes a clock, a sync, and a gate or trigger signal. Signals from Digital Downconverter Fabric-Transparent Crossbar Type: TI/Graychip GC4016 either Timing Bus A or B can be selected as Decimation: 32 to 16,384; with channel the timing source for the A/Ds, the downcon- Switch verters, the upconverters and the D/As. combining mode: 8 or 16 The 5341-420 features a unique Data Source: A/D, FPGA, or PCI interface Two external reference clocks are accepted, high-speed switching configura- Control Source: FPGA or PCI interface one for each timing bus and two internal tion. A fabric-transparent crossbar clocks may be used for each timing bus. Output: Parallel complex data switch connects the PCI Express Receiver Bypass Mode: Data from the A/Ds Front panel 26-pin LVDS Clock/Sync switch with the VPX-P1 connec- can be written directly into the FPGAs at connectors allow multiple boards to be syn- tor using gigabit serial data paths chronized. In the slave mode, they accept a rate equal to the A/D clock decimated by with no latency. This allows the any integer between 1 and 4096 differential LVDS inputs that drive the clock, user to select the desired output Front Panel Analog Signal Outputs sync and gate signals for the two internal port on VPX-P1. Programmable timing buses. Output Type: Transformer-coupled, signal input equalization and front panel female MMCX connectors In the master mode, the LVDS bus can output pre-emphasis settings on Full Scale Output: +4 dBm into 50 ohms drive one or both sets of timing signals the Crossbar Switch enable opti- from the two internal timing buses for 3 dB Passband: 60 kHz to 300 MHz mization. Digital Upconverter synchronizing multiple modules. Type: TI DAC5686 Up to seven slave 5341-420’s can be driven from the LVDS bus master, supporting Input Bandwidth: 40 MHz, max. Output IF: DC to 160 MHz synchronous sampling and sync functions Output Signal: Analog, real or quadrature across all connected boards. Sampling Rate: 320 MHz, max; 500 MHz Memory Resources max. with upconversion disabled Resolution: 16 bits Three independent banks of SDRAM are available. Built-in memory functions in- Clock Sources: Selectable from onboard A or B crystal oscillators, external or LVDS clocks clude an A/D data transient capture mode External Clocks with pre- and post-triggering; a D/A wave- form generator mode; and an A/D data Type: Front panel female MMCX connec- tor, sine wave, 0 to +10 dBm, AC- coupled, delay mode for applications like tracking 50 ohms receivers. User-installed functions within the FPGA can take advantage of the Sync/Gate Bus: 26-pin connector, dual clock/sync/gate input/output LVDS SDRAM for many other purposes. buses; one sync/gate input TTL signal PCI Express Switch Field Programmable Gate Array Model 5341-420 includes a PCIe Gen. 2 Type: Xilinx Virtex-II Pro XC2VP50 Memory switch. The switch provides a total of 24 PCIe lanes to the Fabric-Transparent Cross- DDR SDRAM: 512 MB in three banks FLASH: One bank of 16 MB bar Switch on 6 ports. Dynamic lane width PCI to PCIe Interface negotiation within the PCIe switch allows for x1, x4, x8 or x16 widths. These can be PCI Bus: 64-bit, 66 MHz DMA: 9 channel demand-mode and selected in any combination. chaining controller Specifications Gigabit Serial I/O Analog Signal Inputs VPX-P1: Four 4X ports to Fabric-Trans- parent Crossbar Switch Input Type: Transformer-coupled, front panel female MMCX connectors PCI Express: Six ports to Fabric-Trans- parent Switch, each configurable as x1, Transformer Type: Coil Craft WBC1-1TLB Ordering Information x4, x8 or x16 lanes, 24 lanes total Full Scale Input: +10 dBm into 50 ohms Model Description 3 dB Passband: 250 kHz to 300 MHz Environmental (Commercial version) 5341-420 GateFlow Transceiver Operating Temp: 0° to 50° C with two Wideband DDCs Storage Temp: –20° to 90° C and Interpolation Filter Relative Humidity: 0 to 95%, non-cond. factory-installed - 3U VPX Size: 3.937 in. x 6.717 in. (100 mm x 170.6 mm) Contact Pentek for available options One Park Way ◆ Upper Saddle River ◆ New Jersey 07458 Pentek, Inc. www.pentek.com . . . . Tel: 201 818 5900 ◆ Fax: 201 818 5904 ◆ Email: info pentek.com @ Model 5341-420 GateFlow T ransceiver with Dual Wideband DDCs and Installed Core Interpolation Filter - 3U VPX A/D Performance Spurious Free Dynamic Range Spurious Pick-up Model 7841 f = 70 MHz, f = 100 MHz f = 100 MHz, 32k point FFT, 8 averages in s s Input Frequency Response Two-Tone SFDR f = 100 MHz f = 29.5 MHz, f = 30.5 MHz, f = 100 MHz s 1 2 s Crosstalk Phase Noise f = 69 MHz, f = 100 MHz, Ch 1 shown f = 69 MHz, f = 100 MHz in Ch2 s in s Phase Noise @ 100 kHz = -102 - 10*log(610) = -129.8 dB/Hz One Park Way ◆ Upper Saddle River ◆ New Jersey 07458 Pentek, Inc. www.pentek.com . . . . Tel: 201 818 5900 ◆ Fax: 201 818 5904 ◆ Email: info pentek.com @ Model 5341-420 GateFlow T ransceiver with Dual Wideband DDCs and Installed Core Interpolation Filter - 3U VPX D/A Performance Two-Tone Intermodulation Distortion f = 69.5 MHz, f = 70.5 MHz, f = 100 MHz 1 2 s One Park Way ◆ Upper Saddle River ◆ New Jersey 07458 Pentek, Inc. www.pentek.com . . . . Tel: 201 818 5900 ◆ Fax: 201 818 5904 ◆ Email: info pentek.com @