Model 5342 Multichannel Transceiver with Virtex-4 FPGAs - 3U VPX General Information MHz. It delivers real or quadrature (I+Q) Model 5342 is a multichannel, high-speed analog outputs up to 320 MHz to the 16-bit D/A converter. If translation is disabled, the data converter suitable for connection to HF or IF ports of a communications system. It DAC5686 acts as an interpolating 16-bit D/A with output sampling rates up to 500 MHz. includes four A/Ds with one upconverter and D/A converter. Virtex-4 FPGAs The 5342 features built-in support for The 5342 architecture includes two PCI Express (PCIe) Gen. 2 over the 3U VPX Virtex-4 FPGAs. All of the board’s data and backplane. A unique fabric-transparent crossbar switch configuration adds gigabit control paths are accessible by the FPGAs, enabling factory installed functions including serial data paths for Xilinx Aurora or Serial data multiplexing, channel selection, data RapidIO applications. packing, gating, triggering and SDRAM A/D Converter Stage memory control. In addition, users can include their own custom IP, and integrate The front end accepts four full scale analog HF or IF inputs on front panel MMCX it with factory-shipped functions using a connectors at +10 dBm into 50 ohms with Pentek GateFlow FPGA Design Kit. The Xilinx XC4VSX55 FPGA serves as a transformer coupling into Linear Technology LTC2255 14-bit 125 MHz A/Ds. control and status engine with data and programming interfaces to each of the The digital outputs are delivered into a on-board resources including the A/D Virtex-4 FPGA for signal processing or for routing to other module resources. converters, DDR2 SDRAM memory, digital upconverter and D/A converter. Digital Upconverter and D/A Stage The XC4VSX55 features 512 DSP slices The 5342 features a TI DAC5686 digital and is ideal for implementing functions such as demodulation/modulation, digital upconverter (DUC) and D/A. It accepts a base- Features delay and channelization. For applications band real or complex data stream from its FPGA with signal bandwidths up to 40 MHz. requiring more FPGA logic cells, the Model ■ Complete software radio 5342 can be optionally configured with When operating as an upconverter, the interface solution for 3U VPX XC4VLX100 for up to 221,184 logic cells. DAC5686 interpolates and translates real systems or complex baseband input signals to any A Virtex-4 XC4VFX60 Interface FPGA ■ Supports Gigabit Serial provides board interfaces including PCI IF center frequency between DC and 160 ➤ Fabrics including PCI Express, Serial RapidIO Sample and Xilinx Aurora Clock In RF In RF In RF In RF In RF Out ■ Four 125 MHz 14-bit A/Ds TIMING BUS XTL LVDS GENERATOR A OSC. A RF RF RF RF RF Clock A ■ One digital upconverter XFORMR XFORMR XFORMR XFORMR XFORMR LVDS Clock/Sync/ Sync A ■ One 500 MHz 16-bit D/A Gate LVDS Bus A Gate A 16-BIT D/A SYNC LTC2255 LTC2255 LTC2255 LTC2255 ■ Two Xilinx Virtex-4 FPGAs INTERRUPTS TTL Gate/ 125 MHz 125 MHz 125 MHz 125 MHz DAC5686 & CONTROL Bus B Trigger 14-BIT A/D 14-BIT A/D 14-BIT A/D 14-BIT A/D DIGITAL UPCONVERTER ■ Up to 768 MB of DDR2 TTL Sync 14 14 14 14 32 SDRAM Control/ LVDS Gate B Status ■ LVDS clock/sync bus for LVDS To All VIRTEX-4 XC4VSX55 or XC4VLX100 FPGA Sync B Sections DSP - Channelizer - Digital Delay - Demodulation - Decoding - Control multiboard synchronization LVDS TIMING BUS XTL GTP GTP GTP LVDS Clock B GENERATOR B OSC. B ■ Optional factory-installed IP 32 32 32 4X 4X 4X 64 Cores available DDR2 DDR2 DDR2 SDRAM SDRAM SDRAM 256 MB 256 MB 256 MB GTP ■ Up to 32 pairs of LVDS INTERFACE FPGA VIRTEX-4 XC4VFX60 or FX100 connections to the Virtex-5 GTP PCI 2.2 LVDS FPGAs for custom I/O 32 PCI 2.2 BUS 1 4X 64 (64 Bits, ■ 3U VPX form factor provides 66 MHz) 32 a compact, rugged platform XMC - P15 PCI TO PMC - P14 PCIe BRIDGE ■ Compatible with several 4X 4X x4 PCIe VITA standards including: PCI EXPRESS SWITCH PEX 8648 VITA-46 (VPX Baseline 24 lanes / 6 ports Standard) 24 each configurable as x1/x4/x8/x16 64 VITA-48 (VPX REDI) CROSSBAR TM SWITCH VITA-65 (OpenVPX 4X 4X 4X 4X System Specification) Gbit Gbit Gbit Gbit Serial Serial Serial Serial VPX-P1 VPX-P2 VPX BACKPLANE One Park Way ◆ Upper Saddle River ◆ New Jersey 07458 Pentek, Inc. www.pentek.com . . . . Tel: 201 818 5900 ◆ Fax: 201 818 5904 ◆ Email: info pentek.com @ New! New! New! New! New! Model 5342 Multichannel Transceiver with Virtex-4 FPGAs - 3U VPX and serial I/O. External Clock: 1 to 125 MHz ➤ The interface FPGA also includes two Resolution: 14 bits PowerPC cores which can be used as local A/D Data Reduction Mode: Data from microcontrollers to create complete applica- the A/Ds can be written directly into the Fabric-Transparent Crossbar tion engines. The Model 5342 can be optionally FPGAs at a rate equal to A/D clock deci- configured with XC4VFX100 in place of mated by any value between 1 and 4096 Switch each FX60. Front Panel Analog Signal Output The 5342 features a unique Option -104 provides general purpose Output Type: Transformer-coupled, high-speed switching configura- I/O to VPX-P2 with 16 pairs of LVDS con- front panel female MMCX connector tion. A fabric-transparent crossbar nections to the processing FPGA, and 16 Full Scale Output: +4 dBm into 50 ohms switch bridges numerous inter- pairs of LVDS connections to the interface (other options available) faces and components on the FPGA for custom I/O. 3 dB Passband: 60 kHz to 300 MHz board using gigabit serial data (other options available) paths with no latency. Program- Clocking and Synchronization Digital Upconverter mable signal input equalization Two independent internal timing buses Type: TI DAC5686 and output pre-emphasis set- can provide either a single clock or two Input Bandwidth: 40 MHz, max. tings enable optimization. Data different clock rates for the input and Output IF: DC to 160 MHz paths can be selected as single (x1) output signal paths. Output Signal: Analog, real or quadrature lanes, or groups of four lanes (x4). Each timing bus includes a clock, a sync, Sampling Rate: 320 MHz max; 500 MHz and a gate or trigger signal. Signals from max. with upconversion disabled PCI Express Switch either Timing Bus can be selected as the tim- Resolution: 16 bits Model 5342 includes a PCIe ing source for the A/Ds, upconverter and Clock Sources: Selectable from onboard Gen. 2 switch. The switch pro- D/A. Internal crystal oscillators and a front crystal oscillators, external or LVDS clocks vides a total of 24 PCIe lanes to panel reference input or LVDS bus can drive External Clock the Fabric-Transparent Crossbar the timing buses. Type: Front panel female MMCX connec- Switch on 6 ports. Dynamic lane A front panel 26-pin LVDS Clock/Sync tor, sine wave, 0 to +10 dBm, AC- coupled, width negotiation within the connector allows multiple modules to be 50 ohms PCIe switch allows for x1, x4, x8 synchronized. In the slave mode, each Sync/Gate Bus: 26-pin connector, dual or x16 widths. These can be accepts differential LVDS inputs that drive clock/sync/gate input/output LVDS selected in any combination. the clock, sync and gate signals for the buses; one sync/gate input TTL signal two internal timing buses. Field Programmable Gate Array In the master mode, each LVDS bus can Type: Xilinx Virtex-4 XC4VSX55 & drive one or both sets of timing signals Xilinx Virtex-4 XC4VFX60 from the two internal timing buses for Option -100: XC4VFX100 replaces synchronizing multiple modules. XC4VFX60 Up to seven slave 5342s can be driven Option -110: XC4VLX100 replaces from the LVDS bus master, supporting XC4VSX55 synchronous sampling and sync functions Custom I/O across all connected modules. Option -104: Adds GPIO connector with 32 lines to the XC4VFX60/100 FPGA Memory Resources Memory Three independent 256 MB banks of DDR2 SDRAM: 768 MB in three banks DDR2 SDRAM are available to the SX55 or to SX55/LX100 FPGA Ordering Information LX100 FPGA. Built-in memory functions PCI to PCIe Interface Model Description include an A/D data transient capture mode PCI Bus: 64-bit, 66 MHz 5342 Multichannel Transceiver with pre- and post-triggering and a D/A DMA: 9 channel demand-mode and with four A/Ds, one D/A waveform generator mode. All memory banks chaining controller per PCI bus and Virtex-4 FPGAs - 3U can be easily accessed through the PCI inter- Gigabit Serial I/O: VPX Processing FPGA: Two 4X ports to face using the on-board DMA controllers. Options: Fabric-Transparent Switch; one can be Specifications -100 XC4VFX100 replaces alternately routed to interface FPGA XC4VFX60 Front Panel Analog Signal Inputs VPX-P1: Four 4X ports to Fabric-Trans- -104 FPGA I/O to VPX-P2 Input Type: Transformer-coupled, front parent Crossbar Switch panel female MMCX connectors PCI Express: Six ports to Fabric-Trans- -110 XC4VLX100 replaces XC4VSX55 Transformer Type: Coil Craft parent Switch, each configurable as x1, -428 Four multiband DDCs and WBC1-1TLB x4, x8 or x16 lanes, 24 lanes total interpolation filter, factory- Full Scale Input: +10 dBm into 50 ohms Environmental installed core in the 3 dB Passband: 250 kHz to 300 MHz Operating Temp: 0° to 50° C processing FPGA A/D Converters Storage Temp: –20° to 90° C -5xx Gigabit Serial I/O to VPX- Type: Linear Technology LTC2255 Relative Humidity: 0 to 95%, non-cond. P1- four full-duplex 4X Sampling Rate: 1 MHz to 125 MHz Size: 3.937 in. x 6.717 in. (100 mm x 170.6 mm) paths Internal Clock: 125 MHz crystal osc. One Park Way ◆ Upper Saddle River ◆ New Jersey 07458 Pentek, Inc. www.pentek.com . . . . Tel: 201 818 5900 ◆ Fax: 201 818 5904 ◆ Email: info pentek.com @