Model 53620 3-Ch. 200 MHz A/D, 2-Ch. 800 MHz D/A, Virtex-6 FPGA - 3U VPX General Information and a PCIe interface complete the factory- ® Model 53620 is a member of the Cobalt installed functions and enable the 53620 to operate as a complete turnkey solution, family of high performance 3U VPX boards based on the Xilinx Virtex-6 FPGA. A multi- without the need to develop any FPGA IP. channel, high-speed data converter, it is Extendable IP Design suitable for connection to HF or IF ports of a communications or radar system. Its built- For applications that require specialized functions, users can install their own custom in data capture and playback features offer IP for data processing. Pentek GateFlow an ideal turnkey solution. The 53620 includes three A/Ds, one FPGA Design Kits include all of the factory- installed modules as documented source upconverter, two D/As and four banks of code. Developers can integrate their own memory. It features built-in support for PCI Express over the 3U VPX backplane. IP with the Pentek factory-installed func- tions or use the GateFlow kit to completely The Cobalt Architecture replace the Pentek IP with their own. The Pentek Cobalt Architecture features Xilinx Virtex-6 FPGA a Virtex-6 FPGA. All of the board’s data and The Virtex-6 FPGA can be populated control paths are accessible by the FPGA, Model 53620 COTS (left) enabling factory-installed functions including with a variety of different FPGAs to match and rugged version the specific requirements of the processing data multiplexing, channel selection, data task. Supported FPGAs include: LX130T, packing, gating, triggering and memory control. The Cobalt Architecture organizes LX240T, LX365T, SX315T, or SX475T. The SXT parts feature up to 2016 DSP48E slices the FPGA as a container for data processing and are ideal for modulation/demodulation, applications where each function exists as an intellectual property (IP) module. encoding/decoding, encryption/decryption, and channelization of the signals between Each member of the Cobalt family is deliv- transmission and reception. For applications ered with factory-installed applications ideally matched to the board’s analog interfaces. not requiring large DSP resources, one of the lower-cost LXT FPGAs can be installed. The 53620 factory-installed functions include Option -104 provides 20 pairs of LVDS three A/D acquisition and a D/A waveform playback IP modules, ideally matched to connections between the FPGA and the Features VPX P2 connector for custom I/O. the board’s analog interfaces. IP modules ■ Complete radar and software Option -105 provides one 8X or two 4X for either DDR3 or QDRII+ memories, a radio interface solution controller for all data clocking and synchro- gigabit links between the FPGA and the VPX P1 connector to support serial protocols. nization functions, a test signal generator, ➤ ■ Supports Xilinx Virtex-6 LXT and SXT FPGAs ■ Supports gigabit serial fabrics including PCI Express, Serial RF In RF In RF Out RF In RF Out RapidIO and Xilinx Aurora ■ Three 200 MHz 16-bit A/Ds RF RF RF RF RF RF RF XFORMR XFORMR XFORMR XFORMR XFORMR XFORMR XFORMR ■ One digital upconverter Sample Clk / A/D Reference Clk In ■ Two 800 MHz 16-bit D/As Clock/Sync TIMING BUS Bus GENERATOR ■ Up to 2 GB of DDR3 SDRAM 200 MHz 200 MHz 200 MHz 800 MHz 800 MHz 16-BIT A/D 16-BIT A/D 16-BIT A/D 16-BIT D/A 16-BIT D/A Clock / Sync / or 32 MB of QDRII+ SRAM TTL Gate / Trig DIGITAL Gate / PPS TTL Sync / PPS UPCONVERTER D/A ■ Sample clock synchronization to Sample Clk Clock/Sync 16 16 16 an external system reference Reset Bus 32 Gate A/D ■ LVPECL clock/sync bus for Gate D/A Sync / PPS A/D VIRTEX-6 FPGA multiboard synchronization Sync / PPS D/A VCXO LX130T, LX240T, LX365T, SX315T or SX475T Timing Bus Option -105 ■ LVDS connections to the Gigabit Serial I/O LVDS GTX GTX GTX Virtex-6 FPGA for custom I/O ■ 3U VPX form factor provides 16 16 16 16 16 16 16 16 16 40 8X 4X 4X a compact, rugged platform QDRII+ QDRII+ QDRII+ QDRII+ Config Option -104 SRAM SRAM SRAM SRAM FLASH x8 FPGA ■ Compatible with several VITA 8MB 8MB 8MB 8MB 64 MB PCIe I/O standards including: QDRII+ option 150 QDRII+ option 160 CROSSBAR VITA-46, VITA-48 and DDR3 option 155 DDR3 option 165 SWITCH TM VITA-65 (OpenVPX DDR3 DDR3 DDR3 DDR3 SDRAM SDRAM SDRAM SDRAM 4X 4X 4X 4X 512 MB 512 MB 512 MB 512 MB System Specification) Gbit Gbit Gbit Gbit Serial Serial Serial Serial ■ Ruggedized and conduction- Memory Banks1&2 Memory Banks3&4 VPX-P2 VPX-P1 cooled versions available VPX BACKPLANE One Park Way ◆ Upper Saddle River ◆ New Jersey 07458 Pentek, Inc. www.pentek.com . . . . Tel: 201 818 5900 ◆ Fax: 201 818 5904 ◆ Email: info pentek.com @ New! New! New! New! New! Model 53620 3-Ch. 200 MHz A/D, 2-Ch. 800 MHz D/A, Virtex-6 FPGA - 3U VPX A/D Acquisition IP Modules ➤ ➤ A/D Converter Stage ➤ ➤ ➤ Each timing bus includes a clock, sync The 53620 features three A/D The front end accepts three full-scale and a gate or trigger signal. An on-board Acquisition IP Modules for eas- clock generator receives an external sample analog HF or IF inputs on front panel SSMC ily capturing and moving data. connectors at +8 dBm into 50 ohms with clock from the front panel SSMC connector. Each module can receive data This clock can be used directly for either transformer coupling into three Texas from any of the three A/Ds, a the A/D or D/A sections or can be divided Instruments ADS5485 200 MHz, 16-bit test signal generator or from A/D converters. by a built-in clock synthesizer circuit to pro- the D/A Waveform Playback IP vide different A/D and D/A clocks. In an The digital outputs are delivered into the Module in loopback mode. alternate mode, the sample clock can be Virtex-6 FPGA for signal processing, data cap- Each IP module has an associ- ture or for routing to other board resources. sourced from an onboard programmable ated memory bank for buffering VCXO (Voltage-Controlled Crystal Oscilla- Digital Upconverter and D/A Stage data in FIFO mode or for storing tor). In this mode, the front panel SSMC data in transient capture mode. A TI DAC5688 DUC (digital upconverter) connector can be used to provide a 10 MHz All memory banks are supported reference clock for synchronizing the inter- and D/A accepts a baseband real or complex with DMA engines for easily nal oscillator. data stream from the FPGA and provides moving A/D data through the that input to the upconvert, interpolate and A front panel 26-pin LVPECL Clock/Sync PCIe interface. connector allows multiple boards to be dual D/A stages. These powerful linked-list synchronized. In the slave mode, it accepts When operating as a DUC, it interpolates DMA engines are capable of a and translates real or complex baseband LVPECL inputs that drive the clock, sync unique Acquisition Gate Driven and gate signals. In the master mode, the input signals to any IF center frequency up mode. In this mode, the length of LVPECL bus can drive the timing signals to 360 MHz. It delivers real or quadrature a transfer performed by a link (I+Q) analog outputs to the dual 16-bit D/A for synchronizing multiple boards. definition need not be known Multiple 53620’s can be driven from the converter. Analog output is through a pair prior to data acquisition; rather, LVPECL bus master, supporting synchronous of front panel SSMC connectors. it is governed by the length of If translation is disabled, the DAC5688 sampling and sync functions across all the acquisition gate. This is connected boards. acts as a dual interpolating 16-bit D/A with extremely useful in applications output sampling rates up to 800 MHz. In Memory Resources where an external gate drives both modes the DAC5688 provides interpo- acquisition and the exact length The 53620 architecture supports up to lation factors of 2x, 4x and 8x. of that gate is not known or is four independent memory banks which Clocking and Synchronization likely to vary. can be configured with all QDRII+ SRAM, For each transfer, the DMA Two internal timing buses provide either DDR3 SDRAM, or as combination of two engine can automatically construct banks of each type of memory. a single clock or two different clock rates to metadata packets containing the A/D and D/A signal paths. Each QDRII+ SRAM bank can be up to A/D channel ID, a sample-accu- 8 MB deep and is an integral part of the ➤ rate time stamp and data length information. These actions sim- from from from to A/D Ch 1 A/D Ch 2 A/D Ch 3 D/A plify the host processor’s job of D/A loopback identifying and executing on the data. TEST SIGNAL INPUT MULTIPLEXER GENERATOR D/A Waveform Playback IP Module DATA DATA DATA DATA PACKING PACKING PACKING UNPACKING The Model 53620 factory- & FLOW & FLOW & FLOW & FLOW CONTROL CONTROL CONTROL CONTROL installed functions include a sophisticated D/A Waveform MEMORY MEMORY MEMORY MUX MUX MUX MUX CONTROL CONTROL CONTROL Playback IP module. A linked- to METADATA to METADATA to METADATA list controller allows users to GENERATOR GENERATOR GENERATOR Mem Mem Mem MEMORY CONTROL Bank 1 Bank 2 Bank 3 easily play back to the dual D/As LINKED-LIST LINKED-LIST LINKED-LIST LINKED-LIST to waveforms stored in either on- DMA ENGINE DMA ENGINE DMA ENGINE DMA ENGINE Mem board memory or off-board host Bank 4 D/A A/D A/D A/D WAVEFORM memory. ACQUISITION ACQUISITION ACQUISITION PLAYBACK IP MODULE 1 IP MODULE 2 IP MODULE 3 IP MODULE Parameters including length of waveform, delay from play- back trigger, waveform repetition, etc. can be programmed for each PCIE INTERFACE waveform. VIRTEX-6 VIRTEX-6 FPGA FPGA D DA AT TAFLOW AFLOW D DET ETAIL AIL (supports user installed IP) Up to 64 individual link en- tries can be chained together to x4 x4 4X 4X 40 create complex waveforms with Memory Memory Memory Memory Gigabit FPGA Bank 1 Bank 2 Bank 3 Bank 4 PCIe a minimum of programming. Serial I/O GPIO One Park Way ◆ Upper Saddle River ◆ New Jersey 07458 Pentek, Inc. www.pentek.com . . . . Tel: 201 818 5900 ◆ Fax: 201 818 5904 ◆ Email: info pentek.com @ Model 53620 3-Ch. 200 MHz A/D, 2-Ch. 800 MHz D/A, Virtex-6 FPGA - 3U VPX board’s DMA capabilities, providing Sample Clock Sources: On-board clock ➤ FIFO memory space for creating DMA synthesizer generates two clocks: one packets. For applications requiring deep A/D clock and one D/A clock memory resources, DDR3 SDRAM banks Clock Synthesizer can each be up to 512 MB deep. Built-in Clock Source: Selectable from on-board memory functions include an A/D data programmable VCXO (10 to 810 MHz), transient capture mode and D/A waveform front panel external clock or LVPECL playback mode. timing bus In addition to the factory-installed Synchronization: VCXO can be locked functions, custom user-installed IP within to an external 4 to 180 MHz PLL system the FPGA can take advantage of the memo- reference, typically 10 MHz ries for many other purposes. Clock Dividers: External clock or VCXO can be divided by 1, 2, 4, 8, or 16 for the PCI Express Interface A/D clock The Model 53620 includes an industry- External Clock standard interface fully compliant with PCI Type: Front panel female SSMC connector, Express Gen. 1 & 2 bus specifications. sine wave, 0 to +10 dBm, AC-coupled, Supporting PCIe links up to x8, the inter- 50 ohms, accepts 10 to 800 MHz sample face includes multiple DMA controllers clock or PLL system reference for efficient transfers to and from the board. Timing Bus: 26-pin connector LVPECL bus includes, clock/sync/gate/PPS Fabric-Transparent Crossbar Switch inputs and outputs; TTL signal for gate/ The 53620 features a unique high-speed trigger and sync/PPS inputs switching configuration. A fabric-transpar- Field Programmable Gate Array ent crossbar switch bridges numerous Standard: Xilinx Virtex-6 XC6VLX130T interfaces and components on the board Optional: Xilinx Virtex-6 XC6VLX240T, using gigabit serial data paths with no latency. XC6VLX365T, XC6VSX315T, or Programmable signal input equalization XC6VSX475T and output pre-emphasis settings enable Custom I/O optimization. Data paths can be selected as Option -104: Provides 20 pairs of LVDS single (1X) lanes, or groups of four lanes (4X). connections between the FPGA and the Ordering Information VPX P2 connector for custom I/O. Model Description Specifications Option -105: Provides one 8X or two 4X 53620 3-Channel 200 MHz A/D Front Panel Analog Signal Inputs gigabit links between the FPGA and and 2-Channel 800 MHz Input Type: Transformer-coupled, front the VPX P1 connector to support serial D/A with Virtex-6 FPGA - panel female SSMC connectors protocols. 3U VPX Transformer Type: Coil Craft Memory Options: WBC4-6TLB Option 150 or 160: Two 8 MB QDRII+ -062 XC6VLX240T FPGA Full Scale Input: +8 dBm into 50 ohms SRAM memory banks, 400 MHz DDR -063 XC6VLX365T FPGA 3 dB Passband: 300 kHz to 700 MHz Option 155 or 165: Two 512 MB DDR3 -064 XC6VSX315T FPGA A/D Converters SDRAM memory banks, 400 MHz DDR -065 XC6VSX475T FPGA Type: Texas Instruments ADS5485 PCI-Express Interface -104 LVDS FPGA I/O to VPX Sampling Rate: 10 MHz to 200 MHz PCI Express Bus: Gen. 1 x4 or x8; P2 Resolution: 16 bits Gen. 2: x4 -105 Gigabit serial FPGA I/O D/A Converters Environmental to VPX P1 Type: Texas Instruments DAC5688 Operating Temp: 0° to 50° C -150 Two 8 MB QDRII+ SRAM Input Data Rate: 250 MHz max. Storage Temp: –20° to 90° C Memory Banks Output IF: DC to 400 MHz max. Relative Humidity: 0 to 95%, non-cond. (Banks 1 and 2) Output Signal: 2-channel real or 1-channel Size: 3.937 in. x 6.717 in. (100 mm x 170.6 mm) -160 Two 8 MB QDRII+ SRAM with frequency translation Memory Banks Output Sampling Rate: 800 MHz max. (Banks 3 and 4) with interpolation -155 Two 512 MB DDR3 Resolution: 16 bits SDRAM Memory Banks Front Panel Analog Signal Outputs (Banks 1 and 2) Output Type: Transformer-coupled, -165 Two 512 MB DDR3 front panel female SSMC connectors SDRAM Memory Banks Transformer Type: Coil Craft (Banks 3 and 4) WBC4-6TLB Full Scale Output: +4 dBm into 50 ohms Contact Pentek for availability 3 dB Passband: 300 kHz to 700 MHz of rugged and conduction-cooled versions One Park Way ◆ Upper Saddle River ◆ New Jersey 07458 Pentek, Inc. www.pentek.com . . . . Tel: 201 818 5900 ◆ Fax: 201 818 5904 ◆ Email: info pentek.com @ Model 53620 3-Ch. 200 MHz A/D, 2-Ch. 800 MHz D/A, Virtex-6 FPGA - 3U VPX A/D Performance Spurious Free Dynamic Range Spurious Pick-up f = 200 MHz, Internal Clock f = 70 MHz, f = 200 MHz, Internal Clock s in s Two-Tone SFDR Two-Tone SFDR f = 30 MHz, f = 70 MHz, f = 200 MHz f = 69 MHz, f = 71 MHz, f = 200 MHz 1 2 s 1 2 s Adjacent Channel Crosstalk Crosstalk Input Frequency Response f = 70 MHz, f = 200 MHz, Ch 1 shown f = 200 MHz, Internal Clock in Ch2 s s D/A Performance Spurious Free Dynamic Range Spurious Free Dynamic Range f = 70 MHz, f = 200 MHz, Internal Clock f = 140 MHz, f = 400 MHz, External Clock out s out s One Park Way ◆ Upper Saddle River ◆ New Jersey 07458 Pentek, Inc. www.pentek.com . . . . Tel: 201 818 5900 ◆ Fax: 201 818 5904 ◆ Email: info pentek.com @