PENTEK 5391
Specifications
Environmental
Operating Temp: 0° to 50° C. Storage Temp: –20° to 90° C. Relative Humidity: 0 to 95%, non-cond. Size: 3.937 in. x 6.717 in. (100 mm x 170.6 mm)
Front Panel Clock Outputs (Quantity: Eight)
Connector Type: SMC. Output Impedance: 50 ohms. Output Level: +3 dBm @ 700 MHz. Typ. Phase Noise: –105 dBc/Hz @ 1 kHz. (dependent on reference source stability)
Front Panel Reference Input
Connector Type: SMC. Input Impedance: 50 ohms. Reference Frequency: 5 to 100 MHz. Input Level: –6 dBm to +10 dBm
PLL Clock Synthesizers & Jitter Cleaners
Quantity: Four. Type: Texas Instruments CDC7005. Frequency Dividers: 1, 2, 4, 8 and 16
Programmable VCXOs (Quantity: Four)
Frequency Range: 50 to 700 MHz. Tuning Resolution: 32 bits. Unlocked Accuracy: +20 ppm
Features
- All clocks are phase-locked to input reference signal
- Control and status over the VPX backplane
- Eight SMC clock outputs
- Four progammable VCXOs with 32-bit tuning resolution
- Ideal for A/D and D/A converter clock sources
- Input reference frequency of 5 to100 MHz
- Output clock frequencies between 50 and 700 MHz
- Output clocks of 1, 2, 4, 8, or 16 sub multiples of VCXO base frequencies
- Simultaneous synthesis of up to five different clocks
- Typical phase noise: –105 dBc/Hz @ 1 kHz offset
Datasheet
Extracted Text
Model 5391 Programmable Multifrequency Clock Synthesizer - 3U VPX General Information ing up to five different submultiple clocks, a Model 5391 generates up to eight synthe- wide range of clock configurations is possible. In systems where more than five different sized clock signals suitable for driving A/D and D/A converters in high-performance clock outputs are required simultaneously, multiple 5391’s can be used and phase-locked real-time data acquisition and software radio with a 5 to 100 MHz system reference. systems. The clocks offer exceptionally low phase noise and jitter to preserve the signal PCI Express Interface quality of the data converters. These clocks are Model 5390 includes a PCIe Gen. 2 switch. synthesized from on-board programmable VCXOs (voltage controlled oscillators) and can The switch provides a total of 24 PCIe lanes to the Fabric-Transparent Crossbar Switch be phase-locked to an external reference signal. on 6 ports. Dynamic lane width negotiation Clock Synthesizer Circuits within the PCIe switch allows for x1, x4, x8 The 5391 uses four Texas Instruments or x16 widths. These can be selected in any combination. CDC7005 clock synthesizer and jitter cleaner devices. Each CDC7005 is paired with a dedi- Specifications cated VCXO to provide the base frequency for Front Panel Reference Input the clock synthesizer. Each of the four VCXOs can be independently programmed to a Connector Type: SMC Input Impedance: 50 ohms desired frequency between 50 and 700 MHz Reference Frequency: 5 to 100 MHz with 32-bit tuning resolution. The CDC7005 can output the programmed Input Level: –6 dBm to +10 dBm PLL Clock Synthesizers & Jitter Cleaners Features frequency of its associated VCXO, or gener- Quantity: Four ate submultiples using divisors of 2, 4, 8 or ■ Simultaneous synthesis of 16. The four CDC7005’s can output up to five Type: Texas Instruments CDC7005 up to five different clocks Frequency Dividers: 1, 2, 4, 8 and 16 frequencies each. The 5391 can be programmed ■ Eight SMC clock outputs Programmable VCXOs (Quantity: Four) to route any of these 20 frequencies to the ■ Ideal for A/D and D/A board’s five output drivers. Frequency Range: 50 to 700 MHz converter clock sources Tuning Resolution: 32 bits The CDC7005 includes phase-locking ■ Typical phase noise: Unlocked Accuracy: +20 ppm circuitry that locks the frequency of its asso- –105 dBc/Hz @ 1 kHz offset ciated VCXO to an input reference clock. This Front Panel Clock Outputs (Quantity: Eight) Connector Type: SMC ■ All clocks are phase-locked reference is a 5 to 100 MHz signal supplied to Output Impedance: 50 ohms to input reference signal a front panel SMC connector. Eight front panel SMC connectors supply Output Level: +3 dBm @ 700 MHz ■ Input reference frequency Typ. Phase Noise: –105 dBc/Hz @ 1 kHz synthesized clock outputs driven from the of 5 to100 MHz (dependent on reference source stability) five clock output drivers, as shown in the ■ Four progammable VCXOs block diagram. This supports a single iden- Environmental with 32-bit tuning resolution Operating Temp: 0° to 50° C tical clock to all eight outputs or up to five ■ Output clocks of 1, 2, 4, 8, or Storage Temp: –20° to 90° C different clocks to various outputs. 16 submultiples of VCXO With four independently programmable Relative Humidity: 0 to 95%, non-cond. base frequencies Size: 3.937 in. x 6.717 in. (100 mm x 170.6 mm) VCXOs and each CDC7005 capable of provid- ■ Output clock frequencies between 50 and 700 MHz Clock Out CLOCK ÷1 Out 1 Reference SYNTHESIZER ÷ 2 ■ Control and status over the In AND JITTER ÷ 4 PROGRAM In C Clock Out CLEANER ÷ 8 VCXO R VPX backplane 2 A ÷16 A O S Clock Out S Out 3 CLOCK ÷1 B SYNTHESIZER ÷ 2 A Clock Out AND JITTER PROGRAM ÷ 4 In R 4 CLEANER VCXO ÷ 8 B B ÷16 S Clock Out Out W 5 I CLOCK ÷1 T SYNTHESIZER Clock Out ÷ 2 C AND JITTER ÷ 4 6 In PROGRAM H CLEANER ÷ 8 VCXO C ÷16 C Clock Out Out 7 Supports: any In to any Out, CLOCK ÷1 any In to multiple SYNTHESIZER ÷ 2 AND JITTER Outs ÷ 4 PROGRAM In CLEANER ÷ 8 VCXO Clock Out Out D ÷16 D 8 Control Ordering Information x4 PCIe 24 32 PCI TO PCIe PCI EXPRESS SWITCH CROSSBAR PCI INTERFACE BRIDGE PEX 8648 SWITCH Model Description 24 lanes / 6 ports 4X 4X 4X 4X Gbit Gbit Gbit Gbit each configurable 5391 Programmable as x1/x4/x8/x16 Serial Serial Serial Serial Multifrequency Clock VPX-P1 Synthesizer - 3U VPX VPX BACKPLANE One Park Way ◆ Upper Saddle River ◆ New Jersey 07458 Pentek, Inc. www.pentek.com . . . . Tel: 201 818 5900 ◆ Fax: 201 818 5904 ◆ Email: info pentek.com @ New! New! New! New! New!
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