PENTEK 5390
Specifications
Environmental
Operating Temp: 0° to 50° C. Storage Temp: –20° to 90° C. Relative Humidity: 0 to 95%, non-cond.
Frequency Range
50 to 700 MHz. Unlocked Accuracy: +20 ppm
Front Panel Clock Outputs (Quantity: Eight)
Connector Type: SMC.Output Impedance: 50 ohms. Output Level: +3 dBm @ 700 MHz. Typ. Phase Noise: –105 dBc/Hz @ 1 kHz (dependent on reference source stability)
Front Panel Reference Input
Connector Type: SMC.Input Impedance: 50 ohms. Reference Frequency: 5 to 100 MHz. Input Level: –6 dBm to +10 dBm
PLL Clock Synthesizers & Jitter Cleaners
Quantity: Four. Type: Texas Instruments CDC7005. Frequency Dividers: 1, 2, 4, 8 and 16
Quad VCXOs
(Quantity: Four) Frequencies per VCXO: 4*, softwareprogrammable
Size
3.937 in. x 6.717 in. (100 mm x 170.6 mm)
Features
- All clocks are phase-locked to input reference signal
- Control and status via the VPX backplane
- Eight SMC clock outputs
- Four quad VCXOs allow selection from 16 different base frequencies
- Ideal for A/D and D/A converter clock sources
- Input reference frequency of 5 or 10 MHz
- Output clock frequencies between 50 and 500 MHz
- Output clocks of 1, 2, 4, 8, or 16 submultiples of VCXO base frequencies
- Simultaneous synthesis of up to five different clocks
- Typical phase noise: -125 dBc/Hz @ 1 kHz offset
Datasheet
Extracted Text
Model 5390 Multifrequency Clock Synthesizer - 3U VPX General Information five different submultiple clocks, a wide Model 5390 generates up to eight synthe- range of clock configurations is possible. In systems where more than five different clock sized clock signals suitable for driving A/D and D/A converters in high-performance outputs are required simultaneously, multiple 5390’s can be used and phase-locked with a real-time data acquisition and software radio 5 to 100 MHz system reference. systems. The clocks offer exceptionally low phase noise and jitter to preserve the signal PCI Express Switch quality of the data converters. These clocks are Model 5390 includes a PCIe Gen. 2 switch. synthesized from on-board quad VCXOs (voltage controlled oscillators) and can be The switch provides a total of 24 PCIe lanes to the Fabric-Transparent Crossbar Switch phase-locked to an external reference signal. on 6 ports. Dynamic lane width negotiation Clock Synthesizer Circuits within the PCIe switch allows for x1, x4, x8 The 5390 uses four Texas Instruments or x16 widths. CDC7005 clock synthesizer and jitter cleaner Specifications devices. Each CDC7005 is paired with a dedi- Front Panel Reference Input cated VCXO to provide the base frequency for Connector Type: SMC the clock synthesizer. Each of the four VCXOs can be independently programmed Input Impedance: 50 ohms Features Reference Frequency: 5 to 100 MHz to generate one of four frequencies between Input Level: –6 dBm to +10 dBm ■ Simultaneous synthesis of 50 and 700 MHz. up to five different clocks The CDC7005 can output the selected PLL Clock Synthesizers & Jitter Cleaners Quantity: Four frequency of its associated VCXO, or gener- ■ Eight SMC clock outputs Type: Texas Instruments CDC7005 ate submultiples using divisors of 2, 4, 8 or ■ Ideal for A/D and D/A 16. The four CDC7005’s can output up to five Frequency Dividers: 1, 2, 4, 8 and 16 converter clock sources Quad VCXOs (Quantity: Four) frequencies each. The 5390 can be programmed ■ Typical phase noise: Frequencies per VCXO: 4*, software- to route any of these 20 frequencies to the –105 dBc/Hz @ 1 kHz offset board’s five output drivers. programmable ■ All clocks are phase-locked Frequency Range: 50 to 700 MHz The CDC7005 includes phase-locking to input reference signal Unlocked Accuracy: +20 ppm circuitry that locks the frequency of its asso- ■ Input reference frequency ciated VCXO to an input reference clock. This Front Panel Clock Outputs (Quantity: Eight) of 5 to 100 MHz Connector Type: SMC reference is a 5 to 100 MHz signal supplied to Output Impedance: 50 ohms ■ Four quad VCXOs allow a front panel SMC connector. Eight front panel SMC connectors supply Output Level: +3 dBm @ 700 MHz selection from 16 different Typ. Phase Noise: –105 dBc/Hz @ 1 kHz base frequencies synthesized clock outputs driven from the (dependent on reference source stability) five clock output drivers, as shown in the ■ Output clocks of 1, 2, 4, 8, or block diagram. This supports a single iden- Environmental 16 submultiples of VCXO Operating Temp: 0° to 50° C tical clock to all eight outputs or up to five base frequencies Storage Temp: –20° to 90° C different clocks to various outputs. ■ Output clock frequencies With four independent quadVCXOs and Relative Humidity: 0 to 95%, non-cond. between 50 and 700 MHz Size: 3.937 in. x 6.717 in. (100 mm x 170.6 mm) each CDC7005 capable of providing up to ■ Control and status over the VPX backplane Clock Out CLOCK ÷1 Out 1 Reference SYNTHESIZER ÷ 2 In QUAD AND JITTER ÷ 4 In C Clock Out VCXO CLEANER ÷ 8 R 2 A A ÷16 O S Clock Out Out S 3 CLOCK ÷1 B SYNTHESIZER ÷ 2 A Clock Out AND JITTER QUAD ÷ 4 In R 4 CLEANER VCXO ÷ 8 B B ÷16 S Clock Out Out W 5 Ordering Information I CLOCK ÷1 T Clock Out SYNTHESIZER ÷ 2 C 6 Model Description AND JITTER ÷ 4 QUAD In H CLEANER ÷ 8 VCXO C ÷16 C Clock Out 5390 Multifrequency Clock Out 7 Supports: Synthesizer - 3U VPX any In to any Out, CLOCK ÷1 any In to multiple SYNTHESIZER ÷ 2 Options Outs AND JITTER ÷ 4 In QUAD CLEANER ÷ 8 VCXO Clock Out Specify frequencies of D ÷16 Out D 8 four factory-installed quad Control 32 PCI TO PCIe x4 PCIe 24 VCXOs between 50 and PCI EXPRESS SWITCH CROSSBAR PCI INTERFACE BRIDGE PEX 8648 SWITCH 700 MHz 24 lanes / 6 ports 4X 4X 4X 4X each configurable Gbit Gbit Gbit Gbit as x1/x4/x8/x16 Serial Serial Serial Serial Contact Pentek to order specific * VPX-P1 frequencies VPX BACKPLANE One Park Way ◆ Upper Saddle River ◆ New Jersey 07458 Pentek, Inc. www.pentek.com . . . . Tel: 201 818 5900 ◆ Fax: 201 818 5904 ◆ Email: info pentek.com @ New! New! New! New! New!
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