L-Band RF Tuner, 2-Channel 200 MHz A/D, Virtex-6 FPGA - 3U VPX Model 53690 General Information factory-installed functions and enable the ® Model 53690 is a member of the Cobalt 53690 to operate as a complete turnkey solution without the need to develop any family of high performance 3U VPX boards based on the Xilinx Virtex-6 FPGA. A 2-Chan- FPGA IP. nel high-speed data converter, it is suitable Extendable IP Design for connection directly to the RF port of a communications or radar system. Its built-in For applications that require specialized functions, users can install their own custom data capture features offer an ideal turnkey IP for data processing. Pentek GateFlow solution as well as a platform for developing and deploying custom FPGA processing IP. FPGA Design Kits include all of the factory- installed modules as documented source The Model 53690 includes an L-Band code. Developers can integrate their own IP RF tuner, two A/Ds and four banks of memory. It features built-in support for PCI with the Pentek factory-installed functions or use the GateFlow kit to completely replace Express over the 3U VPX backplane. the Pentek IP with their own. The Cobalt Architecture Xilinx Virtex-6 FPGA The Pentek Cobalt Architecture features The Virtex-6 FPGA can be populated a Virtex-6 FPGA. All of the board’s data and Model 53690 COTS (left) control paths are accessible by the FPGA, with a variety of different FPGAs to match and rugged version the specific requirements of the processing enabling factory-installed functions including task. Supported FPGAs include: LX130T data multiplexing, channel selection, data packing, gating, triggering and memory LX240T, LX365T, SX315T, or SX475T. The SXT parts feature up to 2016 DSP48E slices control. The Cobalt Architecture organizes and are ideal for modulation/demodulation, the FPGA as a container for data processing applications where each function exists as an encoding/decoding, encryption/decryption, and channelization of the signals between intellectual property (IP) module. transmission and reception. For applications Each member of the Cobalt family is deliv- ered with factory-installed applications ideally not requiring large DSP resources, one of the lower-cost LXT FPGAs can be installed. matched to the board’s analog interfaces. Option -104 provides 20 pairs of LVDS Features The 53690 factory-installed functions include two A/D acquisition IP modules. connections between the FPGA and the ■ Accepts RF signals from VPX P2 connector for custom I/O. IP modules for either DDR3 or QDRII+ 925 MHz to 2175 MHz Option -105 provides dual 4X gigabit memories, a controller for all data clocking ■ Programmable LNA boosts and synchronization functions, a test signal links between the FPGA and the VPX P1 LNB (low-noise block) connector to support serial protocols. generator, and a PCIe interface complete the ➤ antenna signal levels with up to 60 dB gain ■ Programmable analog Ref RF Ref downconverter provides In In Out I + Q baseband signals with GC 12-BIT bandwidths ranging from MAX2112 D/A 4 to 40 MHz Sample Clk / Control Reference Clk In ■ Two 200 MHz 16-bit A/Ds Ref I Q Trigger 1 TIMING ■ Supports Xilinx Virtex-6 LXT GENERATOR Trigger 2 A/D Clock/Sync 200 MHz 200 MHz and SXT FPGAs 16-BIT A/D 16-BIT A/D Clock / Sync / TTL Gate / Trig Gate / PPS ■ 2 GB of DDR3 SDRAM or TTL Sync / PPS 32 MB of QDRII+ SRAM Sample Clk 16 16 2 Ref In ■ Sample clock synchronization Gate A 2 IC Gate B to an external system reference Sync / PPS A VIRTEX-6 FPGA Sync / PPS B VCXO ■ Clock/sync bus for multiboard LX130T, LX240T, LX365T, SX315T or SX475T Timing Bus Option -105 Gigabit Serial I/O synchronization LVDS GTX GTX GTX ■ 3U VPX form factor provides 16 16 16 16 16 16 16 16 16 40 a compact, rugged platform 8X 4X 4X QDRII+ QDRII+ QDRII+ QDRII+ Config Option -104 SRAM SRAM SRAM SRAM FLASH FPGA x8 ■ Compatible with several VITA 8MB 8MB 8MB 8MB 64 MB PCIe I/O standards including: QDRII+ option 150 QDRII+ option 160 CROSSBAR VITA-46, VITA-48 and DDR3 option 155 DDR3 option 165 SWITCH TM VITA-65 (OpenVPX DDR3 DDR3 DDR3 DDR3 SDRAM SDRAM SDRAM SDRAM 4X 4X 4X 4X System Specification) 512 MB 512 MB 512 MB 512 MB Gbit Gbit Gbit Gbit Serial Serial Serial Serial ■ Ruggedized and conduction- Memory Banks1&2 Memory Banks3&4 VPX-P2 VPX-P1 cooled versions available VPX BACKPLANE One Park Way ◆ Upper Saddle River ◆ New Jersey 07458 Pentek, Inc. www.pentek.com . . . . Tel: 201 818 5900 ◆ Fax: 201 818 5904 ◆ Email: info pentek.com @ New! New! New! New! New! L-Band RF Tuner, 2-Channel 200 MHz A/D, Virtex-6 FPGA - 3U VPX Model 53690 ➤ ➤ RF Tuner Stage A/D Clocking and Synchronization ➤ ➤ ➤ A front panel SSMC connector accepts An internal timing generator provides L-Band signals between 925 MHz and all timing, gating, triggering and synchro- 2175 MHz from an antenna LNB (low noise nization functions required by the A/D block). A Maxim MAX2112 tuner directly converters. It also serves as an optional converts these L-Band signals to baseband source for the L-Band tuner reference. using a broadband I/Q downconverter. The front panel SSMC clock input can The device includes an RF variable-gain be used directly as the A/D sample clock. LNA (low noise amplifier), a PLL (phase- In an alternate mode, the sample clock locked loop) synthesized local oscillator, can be sourced from an on-board program- quadrature (I + Q) downconverting mixers, mable VCXO (voltage-controlled crystal baseband lowpass filters with program- oscillator). In this mode, the front panel SSMC mable cutoff frequency, and variable-gain clock input connector accepts a 10 MHz ref- baseband amplifiers. erence signal for synchronizing the VCXO The fractional-N PLL synthesizer locks using a PLL. its VCO to the timing generator output, or The timing generator uses a front panel to an external reference input between 12 LVPECL 26-pin clock/sync connector for and 30 MHz. Together, the baseband amplifi- one clock, two sync, and two gate/trigger ers and the RF LNA offer a programmable signals. In the slave mode, it accepts LVPECL linear gain range of 60 dB. inputs that drive the clock, sync and gate/ An integrated lowpass filter with vari- trigger signals within the board. In the able bandwidth provides bandwidths master mode, the LVPECL bus drives out- ranging from 4 to 40 MHz, programmable put timing signals to synchronize multiple with 8 bits of resolution. slave boards, supporting synchronous A/D Acquisition IP Modules sampling and sync functions across all A/D Converter Stage The 53690 features two A/D connected boards. Acquisition IP Modules for eas- The analog baseband I and Q analog Memory Resources ily capturing and moving data. tuner outputs are then applied to two Each IP module can receive data The 53690 architecture supports up to Texas Instruments ADS5485 200 MHz, from either of the two A/Ds or 16-bit A/D converters. The digital outputs four independent memory banks which a test signal generator are delivered into the Virtex-6 FPGA for can be configured with all QDRII+ SRAM, Each IP module has an asso- signal processing, data capture or for rout- all DDR3 SDRAM, or as combination of ciated memory bank for buffering ing to other board resources. two banks of each type of memory. ➤ data in FIFO mode or for storing data in transient capture mode. All memory banks are supported with DMA engines for easily from from moving A/D data through the A/D (I) A/D (Q) PCIe interface. These powerful linked-list DMA engines are TEST capable of a unique Acquisition INPUT MULTIPLEXER SIGNAL GENERATOR Gate Driven mode. In this mode, the length of a transfer performed DATA DATA by a link definition need not be PACKING PACKING & FLOW & FLOW known prior to data acquisition; CONTROL CONTROL rather, it is governed by the length MEMORY MEMORY MUX MUX CONTROL CONTROL of the acquisition gate. This is extremely useful in applications to to METADATA METADATA Mem GENERATOR Mem GENERATOR where an external gate drives Bank 1 Bank 2 acquisition and the exact length LINKED-LIST LINKED-LIST DMA ENGINE DMA ENGINE of that gate is not known or is A/D A/D likely to vary. ACQUISITION ACQUISITION IP MODULE 1 For each transfer, the DMA IP MODULE 2 engine can automatically construct metadata packets containing A/D channel ID, a sample-accu- PCIe INTERFACE rate time stamp and data length VIRTEX-6 VIRTEX-6 FPGA FPGA D DA AT TAFLOW AFLOW D DET ETAIL AIL (supports user installed IP) information. These actions sim- plify the host processor’s job of identifying and executing on the 8X 4X 4X 40 Memory Memory Memory Memory Gigabit FPGA PCIe data. Bank 1 Bank 2 Bank 3 Bank 4 Serial I/O GPIO One Park Way ◆ Upper Saddle River ◆ New Jersey 07458 Pentek, Inc. www.pentek.com . . . . Tel: 201 818 5900 ◆ Fax: 201 818 5904 ◆ Email: info pentek.com @ L-Band RF Tuner, 2-Channel 200 MHz A/D, Virtex-6 FPGA - 3U VPX Model 53690 Each QDRII+ SRAM bank can be up to A/D Converters ➤ 8 MB deep and is an integral part of the Type: Texas Instruments ADS5485 module’s DMA capabilities, providing Sampling Rate: 10 MHz to 200 MHz FIFO memory space for creating DMA Resolution: 16 bits packets. For applications requiring deeper Sample Clock Sources: On-board timing memory resources, DDR3 SDRAM banks generator/synthesizer can each be up to 512 MB deep. Built-in A/D Clock Synthesizer memory functions include multichannel Clock Source: Selectable from on-board A/D data capture, tagging and streaming. programmable VCXO (10 to 810 MHz), The factory-installed A/D Acquisition front panel external clock or LVPECL Modules use memory banks 1 & 2. Banks 3 timing bus & 4 can be optionally installed to support Synchronization: VCXO can be locked custom user-installed IP within the FPGA . to an external 4 to 180 MHz PLL system reference, typically 10 MHz PCI Express Interface Clock Dividers: External clock or VCXO The Model 53690 includes an industry can be divided by 1, 2, 4, 8, or 16, for the standard interface fully compliant with PCI A/D clock Express Gen. 1 & 2 bus specifications. Timing Generator External Clock Input Supporting PCIe links up to x8, the inter- Type: Front panel female SSMC connec- face includes multiple DMA controllers for tor, sine wave, 0 to +10 dBm, AC-coupled, efficient transfers to and from the module. 50 ohms, accepts 10 to 200 MHz (up to 800 MHz when Timing Generator divider Fabric-Transparent Crossbar Switch is enabled) or PLL system reference The 53690 features a unique high-speed Timing Generator Bus: 26-pin front panel connector LVPECL bus includes, clock/ switching configuration. A fabric-transparent sync/gate/PPS inputs and outputs; crossbar switch bridges numerous interfaces and components on the board using gigabit TTL signal for gate/trigger and sync/ PPS inputs serial data paths with no latency. External Trigger Input Programmable signal input equalization and output pre-emphasis settings enable Quantity: 2 Type: Front panel female SSMC connec- optimization. Data paths can be selected as Ordering Information tor, LVTTL single (1X) lanes, or groups of four lanes (4X). Model Description Function: Programmable functions 53690 L-Band RF Tuner with Specifications include: trigger, gate, sync and PPS 2-Channel 200 MHz A/D Field Programmable Gate Array Front Panel Analog Signal Input and Virtex-6 FPGA - 3U Connector: Front panel female SSMC Standard: Xilinx Virtex-6 XC6VLX130T VPX Impedance: 50 ohms Optional: Xilinx Virtex-6 XC6VLX240T, Options: XC6VLX365T, XC6VSX315T, or L-Band Tuner -062 XC6VLX240T FPGA Type: Maxim MAX2112 XC6VSX475T -063 XC6VLX365T FPGA Custom I/O Input Frequency Range: 925 MHz to -064 XC6VSX315T FPGA Option -104: Provides 20 pairs of LVDS 2175 MHz -065 XC6VSX475T FPGA Monolithic VCO Phase Noise: connections between the FPGA and the -104 LVDS FPGA I/O to VPX VPX P2 connector for custom I/O -97 dBc/Hz at 10 kHz P2 Option -105: Provides one 8X or two Fractional-N PLL Synthesizer: -105 Gigabit serial FPGA I/O freq = (N.F) x freq 4X gigabit links between the FPGA and VCO REF to VPX P1 where integer N = 19 to 251 and the VPX P1 connector to support serial -150 Two 8 MB QDRII+ protocols fractional F is a 20-bit binary value SRAM Memory Banks PLL Reference (freq ): Front panel Memory REF (Banks 1 and 2) Option 150 or 160: Two 8 MB QDRII+ SSMC connector or on-board 27 MHz -160 Two 8 MB QDRII+ SRAM memory banks, 400 MHz DDR crystal (Option -100), 12 to 30 MHz SRAM Memory Banks LNA Gain: 0 to 65 dB, controlled by a Option 155 or 165: Two 512 MB DDR3 (Banks 3 and 4) SDRAM memory banks, 400 MHz DDR programmable 12-bit D/A converter* -155 Two 512 MB DDR3 PCI-Express Interface Baseband Amplifier Gain: 0 to 15 dB, SDRAM Memory Banks in 1 dB steps* PCI Express Bus: Gen. 1 x4 or x8; (Banks 1 and 2) Gen. 2 x4 *Usable Full-Scale Input Range: –50 dBm -165 Two 512 MB DDR3 Environmental to +10 dBm SDRAM Memory Banks Baseband Low Pass Filter: Cutoff fre- Operating Temp: 0° to 50° C (Banks 3 and 4) Storage Temp: –20° to 90° C quency programmable from 4 to 40 MHz Relative Humidity: 0 to 95%, non-cond. with 8-bit resolution Contact Pentek for availability Size: 3.937 in. x 6.717 in. (100 mm x 170.6 mm). of rugged and conduction-cooled versions One Park Way ◆ Upper Saddle River ◆ New Jersey 07458 Pentek, Inc. www.pentek.com . . . . Tel: 201 818 5900 ◆ Fax: 201 818 5904 ◆ Email: info pentek.com @