Model 53662 4-Ch 200 MHz A/D with 32-Ch DDC and Virtex-6 FPGA - 3U VPX General Information SDRAM memory controllers, and a PCIe ® Model 53662 is a member of the Cobalt interface complete the factory-installed func- tions and enable the 53662 to operate as a family of high performance 3U VPX boards based on the Xilinx Virtex-6 FPGA. This four- complete turnkey solution without the need channel, high-speed data converter with to develop any FPGA IP. programmable DDCs (digital downconverters) Extendable IP Design is suitable for connection to HF or IF ports of For applications that require specialized a communications or radar system. Its built-in function, users can install their own custom data capture feature offers an ideal turnkey solution. IP for data processing. Pentek GateFlow FPGA Design Kits include all of the factory The 53662 includes four A/Ds and four installed modules as documented source banks of memory. It features built-in support for PCI Express over the 3U VPX backplane. code. Developers can integrate their own IP with the Pentek factory-installed functions The Cobalt Architecture or use the GateFlow kit to completely The Pentek Cobalt architecture features replace the Pentek IP with their own. a Virtex-6 FPGA. All of the board’s data and Xilinx Virtex-6 FPGA control paths are accessible by the FPGA, Model 53662 COTS (left) enabling factory-installed functions includ- The Virtex-6 FPGA can be populated and rugged version with a variety of different FPGAs to match ing data multiplexing, channel selection, the specific requirements of the processing data packing, gating, and triggering. The Cobalt architecture organizes the FPGA as task. Supported FPGAs include: LX240T, LX365T, SX315T, or SX475T. The SXT parts a container for data processing applications feature up to 2016 DSP48E slices and are where each function exists as an intellectual property (IP) module. ideal for modulation/demodulation, encod- ing/decoding, encryption/decryption, and Each member of the Cobalt family is deliv- channelization of the signals between ered with factory-installed applications ideally matched to the board’s analog interfaces. transmission and reception. For applications not requiring large DSP resources, one of The 53662 factory-installed functions include the lower-cost LXT FPGAs can be installed. four A/D acquisition IP modules. Each of the four acquisition IP modules Option -104 provides 20 pairs of LVDS connections between the FPGA and the contains a powerful, programmable 8-chan- VPX P2 connector for custom I/O. nel DDC IP core. IP modules for control of all data clocking, synchronization, gate and Option -105 provides one 8X or two 4X gigabit links between the FPGA and the VPX trigger functions, a test signal generator, Features P1 connector to support serial protocols. voltage and temperature monitoring, DDR3 ➤ ■ Complete radar and software radio interface solution RF In RF In RF In RF In ■ Supports Xilinx Virtex-6 LXT and SXT FPGAs ■ Four 200 MHz 16-bit A/Ds RF RF RF RF XFORMR XFORMR XFORMR XFORMR Sample Clk / ■ Four multiband DDCs Reference Clk In ■ Up to 2 GB of DDR3 SDRAM Gate / Trigger / TIMING BUS A/D Clock/Sync Bus Sync / PPS GENERATOR 200 MHz 200 MHz 200 MHz 200 MHz ■ Sample clock synchronization 16-BIT A/D 16-BIT A/D 16-BIT A/D 16-BIT A/D Clock / Sync / TTL Gate / Trig to an external system Gate / PPS TTL Sync / PPS reference Sample Clk 16 16 16 16 Reset ■ LVPECL clock/sync bus for Gate A Gate B multiboard synchronization Sync / PPS A VIRTEX-6 FPGA Sync / PPS B VCXO ■ 3U VPX form factor provides LX240T, LX365T, SX315T or SX475T Timing Bus Option -105 a compact, rugged platform Gigabit Serial I/O LVDS GTX GTX GTX ■ Compatible with several VITA 16 32 32 32 32 standards including: 40 8X 4X 4X DDR3 DDR3 DDR3 DDR3 Config VITA-46, VITA-48 and Option -104 SDRAM SDRAM SDRAM SDRAM FLASH FPGA x8 TM 512 MB 512 MB 512 MB 512 MB 64 MB VITA-65 (OpenVPX PCIe I/O System Specification) Memory Banks1&2 Memory Banks3&4 CROSSBAR DDR3 option 155 DDR3 option 165 ■ Ruggedized and conduction- SWITCH cooled versions available 4X 4X 4X 4X Gbit Gbit Gbit Gbit Serial Serial Serial Serial VPX-P2 VPX-P1 VPX BACKPLANE One Park Way ◆ Upper Saddle River ◆ New Jersey 07458 Pentek, Inc. www.pentek.com . . . . Tel: 201 818 5900 ◆ Fax: 201 818 5904 ◆ Email: info pentek.com @ New! New! New! New! New! Model 53662 4-Ch 200 MHz A/D with 32-Ch DDC and Virtex-6 FPGA - 3U VPX A/D Acquisition IP Modules Clocking and Synchronization available output bandwidths range from The 53662 features four A/D An internal timing bus provides all tim- 19.53 kHz to 10.0 MHz. Each 8-channel Acquisition IP Modules for eas- bank can have its own unique decimation ing and synchronization required by the ily capturing and moving data. setting supporting a different bandwidth A/D converters. It includes a clock, two Each IP module can receive data associated with each of the four acquisition sync and two gate or trigger signals. An from any of the four A/Ds or a modules. on-board clock generator receives an exter- test signal generator The decimating filter for each DDC nal sample clock from the front panel Each IP module has an associ- bank accepts a unique set of user-supplied SSMC connector. This clock can be used ated memory bank for buffering 18-bit coefficients. The 80% default filters directly by the A/D or divided by a built- data in FIFO mode or for storing deliver an output bandwidth of 0.8 ƒ /N, in clock synthesizer circuit. In an alternate * s data in transient capture mode. where N is the decimation setting. The mode, the sample clock can be sourced All memory banks are supported rejection of adjacent-band components from an on-board programmable voltage- with DMA engines for easily within the 80% output bandwidth is better controlled crystal oscillator. In this mode, moving A/D data through the than 100 dB. the front panel SSMC connector can be PCIe interface. These powerful Each DDC delivers a complex output used to provide a reference clock, typically linked-list DMA engines are stream consisting of 24-bit I + 24-bit Q 10 MHz, for synchronizing the internal capable of a unique Acquisition /N. Any number of samples at a rate of ƒ oscillator. s Gate Driven mode. In this mode, channels can be enabled within each bank, A front panel 26-pin LVPECL Clock/Sync the length of a transfer performed selectable from 0 to 8. Each bank includes connector allows multiple boards to be by a link definition need not be an output sample interleaver that delivers synchronized. In the slave mode, it accepts known prior to data acquisition; a channel-multiplexed stream for all enabled LVPECL inputs that drive the clock, sync rather, it is governed by the length channels within a bank. and gate signals. In the master mode, the of the acquisition gate. This is LVPECL bus can drive the timing signals A/D Converter Stage ➤ ➤ extremely useful in applications ➤ ➤ ➤ for synchronizing multiple boards. where an external gate drives The front end accepts four analog HF Multiple 53662’s can be driven from the acquisition and the exact length or IF inputs on front panel SSMC connectors LVPECL bus master, supporting synchronous of that gate is not known or is with transformer coupling into four Texas sampling and sync functions across all con- likely to vary. Instruments ADS5485 200 MHz, 16-bit nected boards. For each transfer, the DMA A/D converters. Memory Resources engine can automatically construct The digital outputs are delivered into metadata packets containing the Virtex-6 FPGA for signal processing, The 53662 architecture supports up to A/D channel ID, a sample-accu- data capture and for routing to other mod- four independent memory banks which rate time stamp and data length ule resources. can be configured with DDR3 SDRAM. ➤ information. These actions sim- plify the host processor’s job of identifying and executing on the from from from from data. A/D Ch 1 A/D Ch 3 A/D Ch 4 A/D Ch 2 TEST DDC IP Cores SIGNAL INPUT MULTIPLEXER GENERATOR Within each A/D Acquisition IP Module is a powerful 8-chan- DIGITAL DIGITAL DIGITAL DIGITAL nel DDC bank. Because of the DOWN- DOWN- DOWN- DOWN- CONVERTER CONVERTER CONVERTER CONVERTER . . . . flexible input routing of the BANK 1: CH 1-8 BANK 2: CH 9-16 BANK 3: CH 17-24 BANK 4: CH 18-32 DEC: 16 TO 8192 DEC: 16 TO 8192 DEC: 16 TO 8192 DEC: 16 TO 8192 A/D Acquisition IP Modules, DDC DDC DDC DDC many different configurations CORE CORE CORE CORE can be achieved including one DATA PACKING & DATA PACKING & DA DAT TA A P PACKING ACKING & & DA DAT TA A P PACKING ACKING & & FLOW CONTROL FLOW CONTROL FLOW FLOW C CONTROL ONTROL FLOW FLOW C CONTROL ONTROL A/D driving all 32 DDC channels MEMORY MEMORY MEMORY MEMORY or each of the four A/Ds driving its CONTROL CONTROL CONTROL CONTROL METADATA METADATA METADATA METADATA MUX MUX MUX MUX own DDC bank. GENERATOR GENERATOR GENERATOR GENERATOR to to to to Mem Mem Mem Mem Each of the 32 channels has LINKED-LIST LINKED-LIST LINKED-LIST LINKED-LIST Bank 1 Bank 2 Bank 3 Bank 4 DMA ENGINE DMA ENGINE DMA ENGINE DMA ENGINE an independent 32-bit tuning A/D A/D A/D A/D frequency setting that ranges ACQUISITION ACQUISITION ACQUISITION ACQUISITION IP MODULE 1 IP MODULE 2 IP MODULE 3 IP MODULE 4 from DC to ƒ , where ƒ is the s s A/D sampling frequency. All of the 8 channels within a bank share a common decimation VIRTEX-6 VIRTEX-6 FPGA FPGA DA DAT TA AFLOW FLOW DET DETAIL AIL (supports user installed IP) PCIe INTERFACE setting that can range from 16 to 8192, programmable in steps of 8. For example, with a sam- 32 32 32 32 4X 4X 40 8X Memory Memory Memory Memory Gigabit FPGA PCIe pling rate of 200 MHz, the GPIO Bank 1 Bank 2 Bank 3 Bank 4 Serial I/O One Park Way ◆ Upper Saddle River ◆ New Jersey 07458 Pentek, Inc. www.pentek.com . . . . Tel: 201 818 5900 ◆ Fax: 201 818 5904 ◆ Email: info pentek.com @ Model 53662 4-Ch 200 MHz A/D with 32-Ch DDC and Virtex-6 FPGA - 3U VPX Each DDR3 SDRAM bank can be up to Sample Clock Sources: On-board clock ➤ 512 MB deep and is an integral part of the synthesizer board’s DMA capabilities, providing FIFO Clock Synthesizer memory and capture space for creating Clock Source: Selectable from on-board DMA packets. Built-in memory functions programmable VCXO (10 to 810 MHz), include multichannel A/D data capture, front panel external clock or LVPECL tagging and streaming. timing bus In addition to the factory installed func- Synchronization: VCXO can be locked tions, custom user-installed IP within the to an external 4 to 180 MHz PLL system FPGA can take advantage of the memories reference, typically 10 MHz for many other purposes. Clock Dividers: External clock or VCXO can be divided by 1, 2, 4, 8, or 16 for the PCI Express Interface A/D clock The Model 53662 includes an industry External Clock standard interface fully compliant with PCI Type: Front panel female SSMC Express Gen. 1 & 2 bus specifications. connector, sine wave, 0 to +10 dBm, AC-coupled, 50 ohms, accepts 10 to Supporting PCIe links up to x8, the inter- face includes multiple DMA controllers for 800 MHz divider input clock, or PLL system reference efficient transfers to and from the module. Timing Bus: 26-pin connector LVPECL bus Fabric-Transparent Crossbar Switch includes, clock/sync/gate/PPS inputs and The 53662 features a unique high-speed outputs; TTL signal for gate/trigger and sync/PPS inputs switching configuration. A fabric-transpar- ent crossbar switch bridges numerous External Trigger Input Type: Front panel female SSMC connec- interfaces and components on the board tor, LVTTL using gigabit serial data paths with no latency. Programmable signal input equalization Function: Programmable functions include: trigger, gate, sync and PPS and output pre-emphasis settings enable Field Programmable Gate Array optimization. Data paths can be selected as single (1X) lanes, or groups of four lanes (4X). Standard: Xilinx Virtex-6 XC6VLX240T Optional: Xilinx Virtex-6 XC6VLX365T, Specifications XC6VSX315T, or XC6VSX475T Front Panel Analog Signal Inputs Custom I/O Option -104: Provides 20 pairs of LVDS Input Type: Transformer-coupled, front connections between the FPGA and the panel female SSMC connectors Transformer Type: Coil Craft VPX P2 connector for custom I/O Option -105: Provides one 8X or two WBC4-6TLB Ordering Information 4X gigabit links between the FPGA and Full Scale Input: +8 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz the VPX P1 connector to support serial Model Description protocols A/D Converters 53662 4-Ch 200 MHz A/D with Memory Type: Texas Instruments ADS5485 32-Ch DDC and Virtex-6 Sampling Rate: 10 MHz to 200 MHz Option 155 or 165: Two 512 MB DDR3 FPGA - 3U VPX SDRAM memory banks, 400 MHz DDR Resolution: 16 bits Options: PCI-Express Interface Digital Downconverters -062 XC6VLX240T Quantity: Four 8-channel banks, one PCI Express Bus: Gen. 1: x4 or x8; -063 XC6VLX365T Gen. 2: x4 per acquisition module -064 XC6VSX315T Environmental Decimation Range: 16x to 8192x in -065 XC6VSX475T steps of 8x Operating Temp: 0° to 50° C -104 LVDS FPGA I/O through Storage Temp: –20° to 90° C LO Tuning Freq. Resolution: 32 bits, VPX P2 Relative Humidity: 0 to 95%, non-cond. 0 to ƒ s -105 Gigabit serial FPGA I/O Phase Offset Resolution: 32 bits, 0 to Size: 3.937 in. x 6.717 in. (100 mm x 170.6 mm). through VPX P1 360 degrees -155 Two 512 MB DDR3 FIR Filter: 18-bit coefficients, 24-bit output, SDRAM Memory Banks with user-programmable coefficients (Banks 1 and 2) Default Filter Set: 80% bandwidth, -165 Two 512 MB DDR3 >100 dB stopband attenuation SDRAM Memory Banks (Banks 3 and 4) Contact Pentek for availability of rugged and conduction-cooled versions One Park Way ◆ Upper Saddle River ◆ New Jersey 07458 Pentek, Inc. www.pentek.com . . . . Tel: 201 818 5900 ◆ Fax: 201 818 5904 ◆ Email: info pentek.com @ Model 53662 4-Ch 200 MHz A/D with 32-Ch DDC and Virtex-6 FPGA - 3U VPX A/D Performance Spurious Free Dynamic Range Spurious Pick-up f = 70 MHz, f = 200 MHz, Internal Clock f = 200 MHz, Internal Clock in s s Two-Tone SFDR Two-Tone SFDR f = 30 MHz, f = 70 MHz, f = 200 MHz f = 69 MHz, f = 71 MHz, f = 200 MHz 1 2 s 1 2 s Adjacent Channel Crosstalk Crosstalk Input Frequency Response f = 200 MHz, Internal Clock f = 70 MHz, f = 200 MHz, Ch 1 shown s in Ch2 s One Park Way ◆ Upper Saddle River ◆ New Jersey 07458 Pentek, Inc. www.pentek.com . . . . Tel: 201 818 5900 ◆ Fax: 201 818 5904 ◆ Email: info pentek.com @