Model 53661 4-Channel 200 MHz A/D with DDCs and Virtex-6 FPGA - 3U VPX General Information nization functions, a test signal generator, ® Model 53661 is a member of the Cobalt an Aurora gigabit serial interface, and a PCIe interface complete the factory-installed family of high performance 3U VPX boards based on the Xilinx Virtex-6 FPGA. A multi- functions and enable the 53661 to operate channel, high-speed data converter with a as a complete turnkey solution without the need to develop any FPGA IP. programmable DDC, it is suitable for connec- tion to HF or IF ports of a communications Extendable IP Design or radar system. Its built-in data capture and For applications that require specialized playback features offer an ideal turnkey solution. function, users can install their own custom IP for data processing. Pentek GateFlow The 53661 includes four A/Ds and four FPGA Design Kits include all of the factory banks of memory. It features built-in support for PCI Express over the 3U VPX backplane. installed modules as documented source code. Developers can integrate their own The Cobalt Architecture IP with the Pentek factory-installed functions The Pentek Cobalt Architecture features or use the GateFlow kit to completely replace the Pentek IP with their own. a Virtex-6 FPGA. All of the board’s data and control paths are accessible by the FPGA, Xilinx Virtex-6 FPGA Model 53661 COTS (left) enabling factory-installed functions including and rugged version The Virtex-6 FPGA can be populated data multiplexing, channel selection, data with a variety of different FPGAs to match packing, gating, triggering and memory control. The Cobalt Architecture organizes the specific requirements of the processing task. Supported FPGAs include: LX240T, the FPGA as a container for data processing LX365T, SX315T, or SX475T. applications where each function exists as an intellectual property (IP) module. The SXT parts feature up to 2016 DSP48E slices and are ideal for modula- Each member of the Cobalt family is deliv- tion/demodulation, encoding/decoding, ered with factory-installed applications ideally matched to the board’s analog interfaces. encryption/decryption, and channelization of the signals between transmission and The 53661 factory-installed functions include reception. For applications not requiring four A/D acquisition IP modules. Each of the four acquisition IP modules large DSP resources, one of the lower-cost LXT FPGAs can be installed. contains a powerful, programmable DDC Option -104 provides 20 pairs of LVDS (digital downconverter) IP core. IP modules for either DDR3 or QDRII+ memories, a connections between the FPGA and the VPX P2 connector for custom I/O. Features controller for all data clocking and synchro- ➤ ■ Complete radar and software radio interface solution ■ Supports Xilinx Virtex-6 RF In RF In RF In RF In LXT and SXT FPGAs ■ Four 200 MHz 16-bit A/Ds RF RF RF RF XFORMR XFORMR XFORMR XFORMR ■ Four multiband DDCs Sample Clk / Reference Clk In (digital downconverters) Gate / Trigger / TIMING BUS A/D Clock/Sync Bus Sync / PPS GENERATOR 200 MHz 200 MHz 200 MHz 200 MHz ■ Multiboard programmable 16-BIT A/D 16-BIT A/D 16-BIT A/D 16-BIT A/D TTL Gate / Trig Clock / Sync / beamformer TTL Sync / PPS Gate / PPS ■ Up to 2 GB of DDR3 SDRAM Sample Clk 16 16 16 16 or 32 MB of QDRII+ SRAM Reset Gate A Gate B ■ Sample clock synchronization to Sync / PPS A VIRTEX-6 FPGA an external system reference Sync / PPS B VCXO LX240T, LX365T, SX315T or SX475T Timing Bus Aurora ■ LVPECL clock/sync bus for Gigabit Serial I/O LVDS GTX GTX GTX multiboard synchronization ■ 3U VPX form factor provides 16 16 16 16 16 16 16 16 16 40 8X 4X 4X a compact, rugged platform QDRII+ QDRII+ QDRII+ QDRII+ Config Option -104 Sum Sum SRAM SRAM SRAM SRAM FLASH to FPGA x8 from 8MB 8MB 8MB 8MB 64 MB ■ Compatible with several VITA PCIe next I/O prior board board standards including: QDRII+ option 150 QDRII+ option 160 CROSSBAR VITA-46, VITA-48 and DDR3 option 155 DDR3 option 165 SWITCH TM DDR3 DDR3 DDR3 DDR3 VITA-65 (OpenVPX SDRAM SDRAM SDRAM SDRAM 4X 4X 4X 4X 512 MB 512 MB 512 MB 512 MB System Specification) Gbit Gbit Gbit Gbit Serial Serial Serial Serial ■ Ruggedized and conduction- Memory Banks1&2 Memory Banks3&4 VPX-P2 VPX-P1 cooled versions available VPX BACKPLANE One Park Way ◆ Upper Saddle River ◆ New Jersey 07458 Pentek, Inc. www.pentek.com . . . . Tel: 201 818 5900 ◆ Fax: 201 818 5904 ◆ Email: info pentek.com @ New! New! New! New! New! Model 53661 4-Channel 200 MHz A/D with DDCs and Virtex-6 FPGA - 3U VPX A/D Acquisition IP Modules providing a wide range to satisfy most change bit growth. A power meter and The 53661 features four A/D applications. threshold detect block is provided for the Acquisition IP Modules for eas- The decimating filter for each DDC summed output. The output is then directed ily capturing and moving data. accepts a unique set of user-supplied 18-bit back into the A/D Acquisition IP Module 1 Each IP module can receive data coefficients. The 80% default filters deliver FIFO for reading over the PCIe. For larger from any of the four A/Ds or a an output bandwidth of 0.8 ƒ /N, where systems, multiple 53661’s can be chained * s test signal generator N is the decimation setting. The rejection of together via a built-in Xilinx Aurora giga- adjacent-band components within the Each IP module has an asso- bit serial interface through the VPX P1 ciated memory bank for buffering 80% output bandwidth is better than 100 dB. connector. This allows summation across data in FIFO mode or for storing Each DDC delivers a complex output stream channels on multiple boards. data in transient capture mode. consisting of 24-bit I + 24-bit Q or16-bit I + A/D Converter Stage ➤ ➤ ➤ ➤ ➤ All memory banks are supported 16-bit Q samples at a rate of ƒ /N. s with DMA engines for easily The front end accepts three analog HF Beamformer IP Core moving A/D data through the or IF inputs on front panel SSMC connec- PCIe interface. These powerful In addition to the DDCs, the 53661 fea- tors with transformer coupling into three linked-list DMA engines are tures a complete beamforming subsystem. Texas Instruments ADS5485 200 MHz, Each DDC core contains programable I & Q capable of a unique Acquisition 16-bit A/D converters. Gate Driven mode. In this mode, phase and gain adjustments followed by a The digital outputs are delivered into the length of a transfer performed power meter that continuously measures the the Virtex-6 FPGA for signal processing, by a link definition need not be individual average power output. The time data capture and for routing to other known prior to data acquisition; constant of the averaging interval for each board resources. rather, it is governed by the length meter is programmable up to 8K samples. Clocking and Synchronization of the acquisition gate. This is The power meters present average power extremely useful in applications measurements for each DDC core output in An internal timing bus provides all where an external gate drives easy-to-read registers. timing and synchronization required by acquisition and the exact length In addition, each DDC core includes a the A/D converters. It includes a clock, of that gate is not known or is threshold detector to automatically send two sync and two gate or trigger signals. likely to vary. an interrupt to the processor if the average An on-board clock generator receives an For each transfer, the DMA power level of any DDC core falls below external sample clock from the front panel engine can automatically construct or exceeds a programmable threshold. SSMC connector. This clock can be used metadata packets containing A programmable summation block directly by the A/D or divided by a built- A/D channel ID, a sample-accu- provides summing of any of the four DDC in clock synthesizer circuit. In an alternate rate time stamp and data length core outputs. An additional programmable mode, the sample clock can be sourced information. These actions sim- gain stage compensates for summation from an on-board programmable voltage ➤ plify the host processor’s job of identifying and executing on the data. from from from from A/D Ch 1 A/D Ch 2 A/D Ch 3 A/D Ch 4 DDC IP Cores TEST SIGNAL INPUT MULTIPLEXER GENERATOR Within each A/D Acquisition IP Module is a powerful DDC IP DDC DDC DDC DDC core. Because of the flexible DEC: 2 TO 65536 DEC: 2 TO 65536 DEC: 2 TO 65536 DEC: 2 TO 65536 input routing of the A/D POWER POWER POWER POWER METER & METER & METER & METER & Acquistion IP Modules, many THRESHOLD THRESHOLD THRESHOLD THRESHOLD DETECT DETECT DETECT DETECT MUX different configurations can be DDC CORE DDC CORE DDC CORE DDC CORE DATA PACKING & DATA PACKING & DA DAT TA A P PACKING ACKING & & DA DAT TA A P PACKING ACKING & & achieved including one A/D FLOW CONTROL FLOW CONTROL FLOW FLOW C CONTROL ONTROL FLOW FLOW C CONTROL ONTROL driving all four DDCs or each of the MEMORY MEMORY MEMORY MEMORY CONTROL CONTROL CONTROL CONTROL METADATA METADATA METADATA METADATA four A/Ds driving its own DDC. MUX MUX MUX MUX GENERATOR GENERATOR GENERATOR GENERATOR to to to to Each DDC has an indepen- Mem Mem Mem Mem LINKED-LIST LINKED-LIST LINKED-LIST LINKED-LIST Bank 1 Bank 2 Bank 3 Bank 4 dent 32-bit tuning frequency DMA ENGINE DMA ENGINE DMA ENGINE DMA ENGINE A/D A/D A/D A/D setting that ranges from DC to ACQUISITION ACQUISITION ACQUISITION ACQUISITION IP MODULE 1 IP MODULE 2 IP MODULE 3 IP MODULE 4 ƒ , where ƒ is the A/D sam- s s pling frequency. Each DDC can have its own unique decimation AURORA setting, supporting as many as sum out GIGABIT � VIRTEX-6 VIRTEX-6 FPGA FPGA DA DAT TAFLOW AFLOW DET DETAIL AIL PCIe INTERFACE four different output bandwidths SERIAL SUMMER INTERFACE sum in for the board. Decimations can be BEAMFORMER CORE programmed from 2 to 65,536 4X 4X 8X 8X to next from previous PCIe board board One Park Way ◆ Upper Saddle River ◆ New Jersey 07458 Pentek, Inc. www.pentek.com . . . . Tel: 201 818 5900 ◆ Fax: 201 818 5904 ◆ Email: info pentek.com @ Model 53661 4-Channel 200 MHz A/D with DDCs and Virtex-6 FPGA - 3U VPX controlled crystal oscillator. In this mode, Beamformer ➤ the front panel SSMC connector can be Summation: Four channels on-board; used to provide a 10 MHz reference clock multiple boards can be summed via for synchronizing the internal oscillator. Summation Expansion Chain PCI Express Interface A front panel 26-pin LVPECL Clock/Sync Summation Expansion Chain: One The Model 53661 includes an connector allows multiple boards to be syn- chain in and one chain out link via industry-standard interface fully chronized. In the slave mode, it accepts XMC connector using Aurora protocol compliant with PCI Express LVPECL inputs that drive the clock, sync Phase Shift Coefficients: I & Q with Gen. 1 & 2 bus specifications. and gate signals. In the master mode, the 16-bit resolution Supporting PCIe links up to x8, LVPECL bus can drive the timing signals Gain Coefficients: 16-bit resolution the interface includes multiple for synchronizing multiple boards. Channel Summation: 24-bit DMA controllers for efficient Multiple 53661’s can be driven from the Multiboard Summation Expansion: transfers to and from the board. LVPECL bus master, supporting synchro- 32-bit nous sampling and sync functions across Sample Clock Sources: On-board clock Fabric-Transparent Crossbar all connected boards. synthesizer Switch Clock Synthesizer Memory Resources The 53661 features a unique Clock Source: Selectable from on-board high-speed switching configura- The 53661 architecture supports up to programmable VCXO (10 to 810 MHz), tion. A fabric-transparent crossbar four independent memory banks which front panel external clock or LVPECL switch bridges numerous inter- can be configured with all QDRII+ SRAM, timing bus faces and components on the DDR3 SDRAM, or as combination of two Synchronization: VCXO can be locked board using gigabit serial data banks of each type of memory. to an external 4 to 180 MHz PLL system paths with no latency. Each QDRII+ SRAM bank can be up to reference, typically 10 MHz Programmable signal input 8 MB deep and is an integral part of the Clock Dividers: External clock or VCXO equalization and output pre- module’s DMA capabilities, providing can be divided by 1, 2, 4, 8, or 16 for the emphasis settings enable FIFO memory space for creating DMA A/D clock optimization. Data paths can be packets. For applications requiring deeper External Clock selected as single (1X) lanes, or memory resources, DDR3 SDRAM banks Type: Front panel female SSMC connector, groups of four lanes (4X). can each be up to 512 MB deep. Built-in sine wave, 0 to +10 dBm, AC-coupled, memory functions include multichannel 50 ohms, accepts 10 to 800 MHz divider A/D data capture, tagging and streaming. input clock or PLL system reference In addition to the factory-installed func- Timing Bus: 26-pin connector LVPECL tions, custom user-installed IP within the bus includes, clock/sync/gate/PPS in- FPGA can take advantage of the memories puts and outputs; TTL signal for gate/ Ordering Information for many other purposes. trigger and sync/PPS inputs Model Description External Trigger Input 53661 4-Channel 200 MHz A/D Specifications Type: Front panel female SSMC connector, with DDCs and Virtex-6 Front Panel Analog Signal Inputs LVTTL FPGA - 3U VPX Input Type: Transformer-coupled, Function: Programmable functions Options: front panel female SSMC connectors include: trigger, gate, sync and PPS -062 XC6VLX240T Transformer Type: Coil Craft WBC4-6TLB Field Programmable Gate Array -063 XC6VLX365T Full Scale Input: +8 dBm into 50 ohms Standard: Xilinx Virtex-6 XC6VLX240T -064 XC6VSX315T 3 dB Passband: 300 kHz to 700 MHz Optional: Xilinx Virtex-6 XC6VLX365T, -065 XC6VSX475T A/D Converters XC6VSX315T, or XC6VSX475T -104 LVDS FPGA I/O to VPX Type: Texas Instruments ADS5485 Custom I/O P2 Sampling Rate: 10 MHz to 200 MHz Option -104: Provides 20 pairs of LVDS -150 Two 8 MB QDRII+ SRAM Resolution: 16 bits connections between the FPGA and the Memory Banks Digital Downconverters VPX P2 connector for custom I/O. (Banks 1 and 2) Quantity: Four channels Memory -160 Two 8 MB QDRII+ SRAM Decimation Range: 2x to 65,536x in Option 150 or 160: Two 8 MB QDRII+ Memory Banks two stages of 2x to 256x SRAM memory banks, 400 MHz DDR (Banks 3 and 4) LO Tuning Freq. Resolution: 32 bits, Option 155 or 165: Two 512 MB DDR3 -155 Two 512 MB DDR3 0 to ƒ SDRAM memory banks, 400 MHz DDR s SDRAM Memory Banks LO SFDR: >120 dB PCI-Express Interface (Banks 1 and 2) Phase Offset Resolution: 32 bits, 0 to PCI Express Bus: Gen. 1: x4 or x8; -165 Two 512 MB DDR3 360 degrees Gen. 2: x4 SDRAM Memory Banks FIR Filter: 18-bit coefficients, 24-bit Environmental (Banks 3 and 4) output, with user programmable Operating Temp: 0° to 50° C coefficients Storage Temp: –20° to 90° C Contact Pentek for availability Default Filter Set: 80% bandwidth, Relative Humidity: 0 to 95%, non-cond. of rugged and conduction-cooled <0.3 dB passband ripple, >100 dB Size: 3.937 in. x 6.717 in. (100 mm x 170.6 mm) versions stopband attenuation One Park Way ◆ Upper Saddle River ◆ New Jersey 07458 Pentek, Inc. www.pentek.com . . . . Tel: 201 818 5900 ◆ Fax: 201 818 5904 ◆ Email: info pentek.com @ Model 53661 4-Channel 200 MHz A/D with DDCs and Virtex-6 FPGA - 3U VPX A/D Performance Spurious Free Dynamic Range Spurious Pick-up f = 70 MHz, f = 200 MHz, Internal Clock f = 200 MHz, Internal Clock in s s Two-Tone SFDR Two-Tone SFDR f = 30 MHz, f = 70 MHz, f = 200 MHz f = 69 MHz, f = 71 MHz, f = 200 MHz 1 2 s 1 2 s Adjacent Channel Crosstalk Crosstalk Input Frequency Response f = 200 MHz, Internal Clock f = 70 MHz, f = 200 MHz, Ch 1 shown s in Ch2 s One Park Way ◆ Upper Saddle River ◆ New Jersey 07458 Pentek, Inc. www.pentek.com . . . . Tel: 201 818 5900 ◆ Fax: 201 818 5904 ◆ Email: info pentek.com @