Model 53660 4-Channel 200 MHz, 16-bit A/D with Virtex-6 FPGA - 3U VPX General Information the 53660 to operate as a complete turnkey ® Model 53660 is a member of the Cobalt solution, without the need to develop any FPGA IP. family of high performance 3U VPX boards based on the Xilinx Virtex-6 FPGA. A multi- Extendable IP Design channel, high-speed data converter, it is For applications that require specialized suitable for connection to HF or IF ports of a communications or radar system. Its built- functions, users can install their own custom IP for data processing. Pentek GateFlow in data capture features offer an ideal turnkey FPGA Design Kits include all of the factory- solution. The 53660 includes four A/Ds and four installed modules as documented source code. Developers can integrate their own banks of memory. It features built-in support for IP with the Pentek factory-installed func- PCI Express over the 3U VPX backplane. tions or use the GateFlow kit to completely The Cobalt Architecture replace the Pentek IP with their own. The Pentek Cobalt Architecture features Xilinx Virtex-6 FPGA a Virtex-6 FPGA. All of the board’s data and control paths are accessible by the FPGA, The Virtex-6 FPGA can be populated with a variety of different FPGAs to match enabling factory-installed functions including Model 53660 COTS (left) data multiplexing, channel selection, data the specific requirements of the processing and rugged version task. Supported FPGAs include: LX130T, packing, gating, triggering and memory LX240T, LX365T, SX315T, or SX475T. The control. The Cobalt Architecture organizes the FPGA as a container for data processing SXT parts feature up to 2016 DSP48E slices and are ideal for modulation/demodulation, applications where each function exists as encoding/decoding, encryption/decryption, an intellectual property (IP) module. Each member of the Cobalt family is deliv- and channelization of the signals between transmission and reception. For applications ered with factory-installed applications ideally not requiring large DSP resources, one of matched to the board’s analog interfaces. The 53660 factory-installed functions include the lower-cost LXT FPGAs can be installed. Option -104 provides 20 pairs of LVDS four A/D acquisition IP modules. connections between the FPGA and the IP modules for either DDR3 or QDRII+ memories, a controller for all data clocking VPX P2 connector for custom I/O. Features Option -105 provides one 8X or two 4X and synchronization functions, a test signal gigabit links between the FPGA and the VPX ■ Complete radar and software generator, and a PCIe interface complete the factory-installed functions and enable P1 connector to support serial protocols. ➤ radio interface solution ■ Supports Xilinx Virtex-6 LXT and SXT FPGAs ■ Supports gigabit serial fabrics including PCI Express, Serial RF In RF In RF In RF In RapidIO and Xilinx Aurora ■ Four 200 MHz 16-bit A/Ds RF RF RF RF XFORMR XFORMR XFORMR XFORMR ■ Up to 2 GB of DDR3 SDRAM Sample Clk / Reference Clk In or 32 MB of QDRII+ SRAM Gate / Trigger / TIMING BUS A/D Clock/Sync Bus Sync / PPS GENERATOR 200 MHz 200 MHz 200 MHz 200 MHz ■ Sample clock synchronization to 16-BIT A/D 16-BIT A/D 16-BIT A/D 16-BIT A/D TTL Gate / Trig Clock / Sync / an external system reference Gate / PPS TTL Sync / PPS ■ LVPECL clock/sync bus for Sample Clk 16 16 16 16 multiboard synchronization Reset Gate A ■ LVDS connections to the Gate B Sync / PPS A VIRTEX-6 FPGA Virtex-6 FPGA for custom I/O Sync / PPS B VCXO LX130T, LX240T, LX365T, SX315T or SX475T Timing Bus Option -105 ■ 3U VPX form factor provides Gigabit Serial I/O LVDS GTX GTX GTX a compact, rugged platform ■ Compatible with several VITA 16 16 16 16 16 16 16 16 16 40 8X 4X 4X standards including: QDRII+ QDRII+ QDRII+ QDRII+ Config Option -104 SRAM SRAM SRAM SRAM FLASH FPGA x8 VITA-46, VITA-48 and 8MB 8MB 8MB 8MB 64 MB PCIe I/O TM VITA-65 (OpenVPX QDRII+ option 150 QDRII+ option 160 CROSSBAR System Specification) DDR3 option 155 DDR3 option 165 SWITCH ■ Ruggedized and conduction- DDR3 DDR3 DDR3 DDR3 SDRAM SDRAM SDRAM SDRAM 4X 4X 4X 4X 512 MB 512 MB 512 MB 512 MB cooled versions available Gbit Gbit Gbit Gbit Serial Serial Serial Serial Memory Banks1&2 Memory Banks3&4 VPX-P2 VPX-P1 VPX BACKPLANE One Park Way ◆ Upper Saddle River ◆ New Jersey 07458 Pentek, Inc. www.pentek.com . . . . Tel: 201 818 5900 ◆ Fax: 201 818 5904 ◆ Email: info pentek.com @ New! New! New! New! New! Model 53660 4-Channel 200 MHz, 16-bit A/D with Virtex-6 FPGA - 3U VPX ➤ ➤ A/D Converter Stage ➤ ➤ ➤ LVPECL bus can drive the timing signals The front end accepts four full-scale for synchronizing multiple boards. analog HF or IF inputs on front panel SSMC Multiple 53660’s can be driven from the connectors at +8 dBm into 50 ohms with LVPECL bus master, supporting synchro- transformer coupling into four Texas nous sampling and sync functions across Instruments ADS5485 200 MHz, 16-bit all connected boards. A/D converters. Memory Resources The digital outputs are delivered into the Virtex-6 FPGA for signal processing, The 53660 architecture supports up to data capture or for routing to other module four independent memory banks which resources. can be configured with all QDRII+ SRAM, DDR3 SDRAM, or as combination of two Clocking and Synchronization banks of each type of memory. An internal timing bus provides all Each QDRII+ SRAM bank can be up to timing and synchronization required by 8 MB deep and is an integral part of the the A/D converters. It includes a clock, two board’s DMA capabilities, providing FIFO sync and two gate or trigger signals. An on- memory space for creating DMA packets. board clock generator receives an external For applications requiring deeper memory sample clock from the front panel SSMC resources, DDR3 SDRAM banks can each connector. This clock can be used directly be up to 512 MB deep. Built-in memory by the A/D or divided by a built-in clock functions include multichannel A/D data synthesizer circuit. In an alternate mode, capture, tagging and streaming. the sample clock can be sourced from an In addition to the factory-installed func- on-board programmable voltage-controlled tions, custom user-installed IP within the A/D Acquisition IP Modules crystal oscillator. In this mode, the front FPGA can take advantage of the memories The 53660 features four A/D panel SSMC connector can be used to for many other purposes. Acquisition IP Modules for eas- provide a 10 MHz reference clock for synchro- PCI Express Interface ily capturing and moving data. nizing the internal oscillator. Each IP module can receive data A front panel 26-pin LVPECL Clock/Sync The Model 53660 includes an industry- from any of the four A/Ds or a connector allows multiple boards to be syn- standard interface fully compliant with PCI test signal generator chronized. In the slave mode, it accepts Express Gen. 1 & 2 bus specifications. Each IP module has an asso- LVPECL inputs that drive the clock, sync Supporting PCIe links up to x8, the inter- ciated memory bank for buffering and gate signals. In the master mode, the face includes multiple DMA controllers for data in FIFO mode or for storing efficient transfers to and from the board. ➤ data in transient capture mode. All memory banks are supported with DMA engines for easily from from from from moving A/D data through the A/D Ch 1 A/D Ch 2 A/D Ch 3 A/D Ch 4 PCIe interface. These powerful linked-list DMA engines are TEST capable of a unique Acquisition SIGNAL INPUT MULTIPLEXER GENERATOR Gate Driven mode. In this mode, the length of a transfer performed DATA DATA DATA DATA by a link definition need not be PACKING PACKING PACKING PACKING & FLOW & FLOW & FLOW & FLOW known prior to data acquisition; CONTROL CONTROL CONTROL CONTROL rather, it is governed by the length MEMORY MEMORY MEMORY MEMORY MUX MUX MUX MUX of the acquisition gate. This is CONTROL CONTROL CONTROL CONTROL extremely useful in applications to to METADATA METADATA to METADATA to METADATA Mem GENERATOR Mem GENERATOR Mem GENERATOR Mem GENERATOR where an external gate drives Bank 1 Bank 2 Bank 3 Bank 4 acquisition and the exact length LINKED-LIST LINKED-LIST LINKED-LIST LINKED-LIST DMA ENGINE DMA ENGINE DMA ENGINE DMA ENGINE of that gate is not known or is A/D A/D A/D likely to vary. A/D ACQUISITION ACQUISITION ACQUISITION ACQUISITION IP MODULE 1 For each transfer, the DMA IP MODULE 2 IP MODULE 3 IP MODULE 4 engine can automatically construct metadata packets containing A/D channel ID, a sample-accu- PCIe INTERFACE rate time stamp and data length VIRTEX-6 VIRTEX-6 FPGA FPGA D DA AT TAFLOW AFLOW D DET ETAIL AIL (supports user installed IP) information. These actions sim- plify the host processor’s job of identifying and executing on the 8X 4X 4X 40 Memory Memory Memory Memory Gigabit FPGA PCIe data. Bank 1 Bank 2 Bank 3 Bank 4 Serial I/O GPIO One Park Way ◆ Upper Saddle River ◆ New Jersey 07458 Pentek, Inc. www.pentek.com . . . . Tel: 201 818 5900 ◆ Fax: 201 818 5904 ◆ Email: info pentek.com @ Model 53660 4-Channel 200 MHz, 16-bit A/D with Virtex-6 FPGA - 3U VPX External Clock ➤ ➤ Fabric-Transparent Crossbar Switch ➤ ➤ ➤ Type: Front panel female SSMC connec- The 53660 features a unique high-speed tor, sine wave, 0 to +10 dBm, AC-coupled, switching configuration. A fabric-transpar- 50 ohms, accepts 10 to 800 MHz divider ent crossbar switch bridges numerous input clock or PLL system reference interfaces and components on the board using Timing Bus: 26-pin front panel connector gigabit serial data paths with no latency. LVPECL bus includes, clock/sync/ Programmable signal input equalization gate/PPS inputs and outputs; TTL and output pre-emphasis settings enable signal for gate/trigger and sync/PPS optimization. Data paths can be selected as inputs single (1X) lanes, or groups of four lanes (4X). External Trigger Input Type: Front panel female SSMC connec- Specifications tor, LVTTL Front Panel Analog Signal Inputs Function: Programmable functions Input Type: Transformer-coupled, include: trigger, gate, sync and PPS front panel female SSMC connectors Field Programmable Gate Array Transformer Type: Coil Craft Standard: Xilinx Virtex-6 XC6VLX130T WBC4-6TLB Optional: Xilinx Virtex-6 XC6VLX240T, Full Scale Input: +8 dBm into 50 ohms XC6VLX365T, XC6VSX315T, or 3 dB Passband: 300 kHz to 700 MHz XC6VSX475T A/D Converters Custom I/O Type: Texas Instruments ADS5485 Option -104: Provides 20 pairs of LVDS Sampling Rate: 10 MHz to 200 MHz connections between the FPGA and the Resolution: 16 bits VPX P2 connector for custom I/O Sample Clock Sources: On-board clock Option -105: Provides one 8X or two synthesizer 4X gigabit links between the FPGA and Clock Synthesizer the VPX P1 connector to support serial Clock Source: Selectable from on-board protocols programmable VCXO (10 to 810 MHz), Memory front panel external clock or LVPECL Option 150 or 160: Two 8 MB QDRII+ timing bus SRAM memory banks, 400 MHz DDR Synchronization: VCXO can be locked Option 155 or 165: Two 512 MB DDR3 Ordering Information to an external 4 to 180 MHz PLL system SDRAM memory banks, 400 MHz DDR Model Description reference, typically 10 MHz PCI-Express Interface Clock Dividers: External clock or VCXO 53660 4-Channel 200 MHz, PCI Express Bus: Gen. 1: x4 or x8; 16-bit A/D with Virtex-6 can be divided by 1, 2, 4, 8, or 16 for the Gen. 2: x4 FPGA - 3U VPX A/D clock Environmental Options: Operating Temp: 0° to 50° C -062 XC6VLX240T FPGA Storage Temp: –20° to 90° C -063 XC6VLX365T FPGA Relative Humidity: 0 to 95%, non-cond. -064 XC6VSX315T FPGA Size: 3.937 in. x 6.717 in. (100 mm x 170.6 mm). -065 XC6VSX475T FPGA -104 LVDS FPGA I/O to VPX P2 -105 Gigabit serial FPGA I/O to VPX P1 -150 Two 8 MB QDRII+ SRAM Memory Banks (Banks 1 and 2) -160 Two 8 MB QDRII+ SRAM Memory Banks (Banks 3 and 4) -155 Two 512 MB DDR3 SDRAM Memory Banks (Banks 1 and 2) -165 Two 512 MB DDR3 SDRAM Memory Banks (Banks 3 and 4) Contact Pentek for availability of rugged and conduction-cooled versions One Park Way ◆ Upper Saddle River ◆ New Jersey 07458 Pentek, Inc. www.pentek.com . . . . Tel: 201 818 5900 ◆ Fax: 201 818 5904 ◆ Email: info pentek.com @ Model 53660 4-Channel 200 MHz, 16-bit A/D with Virtex-6 FPGA - 3U VPX A/D Performance Spurious Free Dynamic Range Spurious Pick-up f = 70 MHz, f = 200 MHz, Internal Clock f = 200 MHz, Internal Clock in s s Two-Tone SFDR Two-Tone SFDR f = 30 MHz, f = 70 MHz, f = 200 MHz f = 69 MHz, f = 71 MHz, f = 200 MHz 1 2 s 1 2 s Adjacent Channel Crosstalk Crosstalk Input Frequency Response f = 200 MHz, Internal Clock f = 70 MHz, f = 200 MHz, Ch 1 shown s in Ch2 s One Park Way ◆ Upper Saddle River ◆ New Jersey 07458 Pentek, Inc. www.pentek.com . . . . Tel: 201 818 5900 ◆ Fax: 201 818 5904 ◆ Email: info pentek.com @