Two 500 MHz A/Ds, DUC, 800 MHz D/As, Virtex-6 FPGA - 3U VPX Model 53650 General Information the factory-installed functions and enable ® Model 53650 is a member of the Cobalt the 53650 to operate as a complete turnkey family of high performance 3U VPX boards solution, without the need to develop any based on the Xilinx Virtex-6 FPGA. A two- FPGA IP. channel, high-speed data converter, it is Extendable IP Design suitable for connection to HF or IF ports of a communications or radar system. Its built- For applications that require specialized in data capture and playback features offer functions, users can install their own custom an ideal turnkey solution. IP for data processing. Pentek GateFlow The 53650 includes two A/Ds, one DUC FPGA Design Kits include all of the factory (digital upconverter), two D/As and four installed modules as documented source code. banks of memory. It features built-in support Developers can integrate their own IP with for PCI Express over the 3U VPX backplane. the Pentek factory-installed functions or use the GateFlow Design Kit to completely replace The Cobalt Architecture the Pentek IP with their own. The Pentek Cobalt architecture features Xilinx Virtex-6 FPGA a Virtex-6 FPGA. All of the board’s data and control paths are accessible by the FPGA, The Virtex-6 FPGA can be populated Model 53650 COTS (left) enabling factory-installed functions includ- with a variety of different FPGAs to match and rugged version ing data multiplexing, channel selection, the specific requirements of the processing data packing, gating, triggering and memory task. Supported FPGAs include: LX130T, control. The Cobalt architecture organizes LX240T, LX365T, SX315T, or SX475T. The the FPGA as a container for data processing SXT parts feature up to 2016 DSP48E slices applications where each function exists as and are ideal for modulation/demodulation, an intellectual property (IP) module. encoding/decoding, encryption/decryption, Each member of the Cobalt family is and channelization of the signals between delivered with factory-installed applications transmission and reception. For applications ideally matched to the board’s analog inter- not requiring large DSP resources, one of faces. The 53650 factory-installed functions the lower-cost LXT FPGAs can be installed. include two A/D acquisition and one D/A Option -104 provides 20 pairs of LVDS waveform playback IP modules. In addition, connections between the FPGA and the Features IP modules for either DDR3 or QDRII+ VPX P2 connector for custom I/O. ■ Complete radar and software memories, a controller for all data clocking Option -105 provides one 8X or two 4X radio interface solution and synchronization functions, a test signal gigabit links between the FPGA and the VPX generator and a PCIe interface complete P1 connector to support serial protocols. ■ Supports Xilinx Virtex-6 ➤ LXT and SXT FPGAs ■ Supports gigabit serial fabrics RF In RF Out RF Out RF In including PCI Express, Serial RapidIO and Xilinx Aurora ■ Two 500 MHz 12-bit A/Ds RF RF RF RF RF RF Sample Clk / XFORMR XFORMR XFORMR XFORMR XFORMR XFORMR ■ One digital upconverter Reference Clk In A/D TIMING BUS Clock/Sync TTL ■ Two 800 MHz 16-bit D/As PPS/Gate/Sync GENERATOR Bus 500 MHz 500 MHz 800 MHz 800 MHz 12-BIT A/D 12-BIT A/D 16-BIT D/A 16-BIT D/A ■ Up to 2 GB of DDR3 SDRAM TTL Gate / Trig Clock / Sync / DIGITAL Gate / PPS TTL Sync / PPS or 32 MB of QDRII+ SRAM UPCONVERTER D/A Clock/Sync Sample Clk ■ Sample clock synchronization to 16 16 Bus 32 Reset an external system reference Gate A/D Gate D/A ■ LVPECL clock/sync bus for VIRTEX-6 FPGA Sync / PPS A/D VCXO multiboard synchronization LX130T, LX240T, LX365T, SX315T or SX475T Sync / PPS D/A Option -105 Gigabit Serial I/O Timing Bus ■ LVDS connections to the LVDS GTX GTX GTX Virtex-6 FPGA for custom I/O 16 16 16 16 16 16 16 16 16 ■ 3U VPX form factor provides 40 8X 4X 4X QDRII+ QDRII+ QDRII+ QDRII+ Config Option -104 a compact, rugged platform SRAM SRAM SRAM SRAM FLASH FPGA x8 8MB 8MB 8MB 8MB 64 MB PCIe I/O ■ Compatible with several VITA standards including: QDRII+ option 150 QDRII+ option 160 CROSSBAR DDR3 option 155 DDR3 option 165 VITA-46, VITA-48 and SWITCH TM DDR3 DDR3 DDR3 DDR3 VITA-65 (OpenVPX SDRAM SDRAM SDRAM SDRAM 4X 4X 4X 4X 512 MB 512 MB 512 MB 512 MB System Specification) Gbit Gbit Gbit Gbit Serial Serial Serial Serial Memory Banks1&2 Memory Banks3&4 ■ Ruggedized and conduction- VPX-P2 VPX-P1 cooled versions available VPX BACKPLANE One Park Way ◆ Upper Saddle River ◆ New Jersey 07458 Pentek, Inc. www.pentek.com . . . . Tel: 201 818 5900 ◆ Fax: 201 818 5904 ◆ Email: info pentek.com @ New! New! New! New! New! Two 500 MHz A/Ds, DUC, 800 MHz D/As, Virtex-6 FPGA - 3U VPX Model 53650 ➤ ➤ A/D Converter Stage ➤ ➤ ➤ Each timing bus includes a clock, sync The front end accepts two full scale and a gate or trigger signal. An on-board analog HF or IF inputs on front panel SSMC clock generator receives an external sample A/D Acquisition IP Modules connectors at +5 dBm into 50 ohms with clock from the front panel SSMC connector. The 53650 features two A/D transformer coupling into two Texas Instru- This clock can be used directly for either Acquisition IP Modules for easy ments ADS5463 500 MHz, 12-bit A/D the A/D or D/A sections or can be divided capture and data moving. Each converters. by a built-in clock synthesizer circuit to pro- IP module can receive data from The digital outputs are delivered into vide different A/D and D/A clocks. In an either of the two A/Ds, a test the Virtex-6 FPGA for signal processing, alternate mode, the sample clock can be signal generator or from the D/A data capture or for routing to other board sourced from an onboard programmable Waveform Playback IP Module resources. voltage-controlled crystal oscillator. In this in loopback mode. Each IP mod- mode, the front panel SSMC connector can Digital Upconverter and D/A Stage ule has an associated memory be used to provide a 10 MHz reference clock bank for buffering data in FIFO A TI DAC5688 DUC and D/A accepts a for synchronizing the internal oscillator. mode or for storing data in tran- baseband real or complex data stream from A front panel 26-pin LVPECL Clock/Sync sient capture mode. All memory the FPGA and provides that input to the connector allows multiple boards to be syn- banks are supported with DMA upconvert, interpolate and dual D/A stages. chronized. In the slave mode, it accepts engines for moving A/D data When operating as a DUC, it interpolates LVPECL inputs that drive the clock, sync through the PCIe interface. and translates real or complex baseband and gate signals. In the master mode, the These powerful linked-list input signals to any IF center frequency up LVPECL bus can drive the timing signals DMA engines are capable of a to 360 MHz. It delivers real or quadrature for synchronizing multiple boards. unique Acquisition Gate Driven (I+Q) analog outputs to the dual 16-bit D/A Multiple 53650’s can be driven from the mode. In this mode, the length of converter. Analog output is through a pair LVPECL bus master, supporting synchronous a transfer performed by a link of front panel SSMC connectors. sampling and sync functions across all definition need not be known If translation is disabled, the DAC5688 connected boards. prior to data acquisition; rather, acts as a dual interpolating 16-bit D/A with Memory Resources it is governed by the length of output sampling rates up to 800 MHz. In the acquisition gate. This is both modes the DAC5688 provides interpo- The 53650 architecture supports up to extremely useful in applications lation factors of 2x, 4x and 8x. four independent memory banks which where an external gate drives can be configured with all QDRII+ SRAM, Clocking and Synchronization acquisition and the exact length DDR3 SDRAM, or as combination of two of that gate is not known or is Two internal timing buses provide either banks of each type of memory. likely to vary. a single clock or two different clock rates to Each QDRII+ SRAM bank can be up to For each transfers, the DMA the A/D and D/A signal paths. 8 MB deep and is an integral part of the ➤ engine can automatically construct metadata packets containing A/D channel ID, a sample-accurate from from to A/D Ch 1 A/D Ch 2 D/A time stamp, and data length infor- D/A loopback mation. These actions simplify the host processor’s job of identi- TEST SIGNAL fying and executing on the data. INPUT MULTIPLEXER GENERATOR D/A Waveform Playback IP DATA DATA DATA PACKING PACKING Module UNPACKING & FLOW & FLOW & FLOW CONTROL CONTROL CONTROL The Model 53650 factory- installed functions include a MEMORY MEMORY MUX MUX MUX CONTROL CONTROL sophisticated D/A Waveform to METADATA to METADATA Playback IP module. A linked- GENERATOR GENERATOR MEMORY Mem Mem CONTROL Bank 1 Bank 2 list controller allows users to LINKED-LIST LINKED-LIST LINKED-LIST to easily play back waveforms stored DMA ENGINE DMA ENGINE DMA ENGINE Mem in either on-board memory or Bank 3 D/A A/D A/D WAVEFORM off- board host memory to the ACQUISITION ACQUISITION PLAYBACK IP MODULE 1 IP MODULE 2 IP MODULE dual D/As. Parameters including length of waveform, delay from playback trigger, waveform repetition, PCIe INTERFACE etc. can be programmed for each VIRTEX-6 VIRTEX-6 FPGA FPGA D DA AT TAFLOW AFLOW D DET ETAIL AIL (supports user installed IP) waveform. Up to 64 individual link entries can be chained together 8X 4X 4X 40 to create complex waveforms Memory Memory Memory Memory Gigabit FPGA Bank 1 Bank 2 Bank 3 Bank 4 PCIe with a minimum of programming. Serial I/O GPIO One Park Way ◆ Upper Saddle River ◆ New Jersey 07458 Pentek, Inc. www.pentek.com . . . . Tel: 201 818 5900 ◆ Fax: 201 818 5904 ◆ Email: info pentek.com @ Two 500 MHz A/Ds, DUC, 800 MHz D/As, Virtex-6 FPGA - 3U VPX Model 53650 board’s DMA capabilities, providing Transformer Type: Coil Craft ➤ FIFO memory space for creating DMA WBC4-6TLB packets. For applications requiring deep Full Scale Output: +4 dBm into 50 ohms memory resources, DDR3 SDRAM banks 3 dB Passband: 300 kHz to 700 MHz can each be up to 512 MB deep. Built-in Sample Clock Sources: On-board clock memory functions include an A/D data synthesizer generates two clocks: one transient capture mode and D/A waveform A/D clock and one D/A clock playback mode. Clock Synthesizer In addition to the factory-installed Clock Source: Selectable from on-board functions, custom user-installed IP within programmable VCXO (10 to 810 MHz), the FPGA can take advantage of the memo- front panel external clock or LVPECL ries for many other purposes. timing bus Synchronization: VCXO can be locked PCI Express Interface to an external 4 to 180 MHz PLL system The Model 78650 includes an industry- reference, typically 10 MHz standard interface fully compliant with PCI Clock Dividers: External clock or VCXO Express Gen. 1 & 2 bus specifications. can be divided by 1, 2, 4, 8, or 16, indepen- Supporting PCIe links up to x8, the inter- dently for the A/D clock and D/A clock face includes multiple DMA controllers for External Clock efficient transfers to and from the board. Type: Front panel female SSMC connec- tor, sine wave, 0 to +10 dBm, Fabric-Transparent Crossbar Switch AC-coupled, 50 ohms, accepts 10 to The 53620 features a unique high-speed 800 MHz divider input clock or PLL switching configuration. A fabric-transpar- system reference ent crossbar switch bridges numerous Timing Bus: 26-pin front panel connector interfaces and components on the board LVPECL bus includes, clock/sync/gate/ using gigabit serial data paths with no latency. PPS inputs and outputs; TTL signal for Programmable signal input equalization gate/trigger and sync/PPS inputs and output pre-emphasis settings enable External Trigger Input optimization. Data paths can be selected as Type: Front panel female SSMC connec- Ordering Information single (1X) lanes, or groups of four lanes (4X). tor, LVTTL Model Description Function: Programmable functions 53650 Two 500 MHz A/Ds, one Specifications include: trigger, gate, sync and PPS DUC, Two 800 MHz D/As Front Panel Analog Signal Inputs Field Programmable Gate Array with Virtex-6 FPGA - 3U Input Type: Transformer-coupled, front Standard: Xilinx Virtex-6 XC6VLX130T VPX panel female SSMC connectors Optional: Xilinx Virtex-6 XC6VLX240T, Options: Transformer Type: Coil Craft XC6VLX365T, XC6VSX315T, or -014 400 MHz, 14-bit A/Ds WBC4-6TLB XC6VSX475T -062 XC6VLX240T Full Scale Input: +5 dBm into 50 ohms Custom I/O -063 XC6VLX365T 3 dB Passband: 300 kHz to 700 MHz Option -104: Provides 20 pairs of LVDS -064 XC6VSX315T A/D Converters (standard) connections between the FPGA and the -065 XC6VSX475T Type: Texas Instruments ADS5463 VPX P2 connector for custom I/O -104 LVDS FPGA I/O to VPX Sampling Rate: 20 MHz to 500 MHz Option -105: Provides one 8X or two P2 Resolution: 12 bits 4X gigabit links between the FPGA and -105 Gigabit serial FPGA I/O A/D Converters (option 014) the VPX P1 connector to support serial to VPX P1 Type: Texas Instruments ADS5474 protocols -150 Two 8 MB QDRII+ SRAM Sampling Rate: 20 MHz to 400 MHz Memory Memory Banks Resolution: 14 bits Option 150 or 160: Two 8 MB QDRII+ (Banks 1 and 2) D/A Converters SRAM memory banks, 400 MHz DDR -160 Two 8 MB QDRII+ SRAM Type: Texas Instruments DAC5688 Option 155 or 165: Two 512 MB DDR3 Memory Banks Input Data Rate: 250 MHz, max. SDRAM memory banks, 400 MHz DDR (Banks 3 and 4) Output IF: DC to 400 MHz, max. PCI-Express Interface -155 Two 512 MB DDR3 Output Signal: 2-channel real or PCI Express Bus: Gen.1: x4 or x8; SDRAM Memory Banks 1-channel with frequency translation Gen. 2: x4 (Banks 1 and 2) Output Sampling Rate: 800 MHz, max. Environmental -165 Two 512 MB DDR3 with interpolation Operating Temp: 0° to 50° C SDRAM Memory Banks Resolution: 16 bits Storage Temp: –20° to 90° C (Banks 3 and 4) Front Panel Analog Signal Outputs Relative Humidity: 0 to 95%, non-cond. Output Type: Transformer-coupled, Size: 3.937 in. x 6.717 in. (100 mm x 170.6 mm) Contact Pentek for availability front panel female SSMC connectors of rugged and conduction-cooled versions One Park Way ◆ Upper Saddle River ◆ New Jersey 07458 Pentek, Inc. www.pentek.com . . . . Tel: 201 818 5900 ◆ Fax: 201 818 5904 ◆ Email: info pentek.com @