Model 53630 1 GHz A/D and D/A, Virtex-6 FPGA - 3U VPX General Information factory-installed functions and enable the ® Model 53630 is a member of the Cobalt 53630 to operate as a complete turnkey solu- tion, without the need to develop any FPGA IP . family of high performance 3U VPX boards based on the Xilinx Virtex-6 FPGA. A high- Extendable IP Design speed data converter, it is suitable for For applications that require specialized connection to HF or IF ports of a communica- tions or radar system. Its built-in data capture functions, users can install their own custom IP for data processing. Pentek GateFlow and playback features offer an ideal turnkey FPGA Design Kits include all of the factory solution. It includes 1 GHz A/D and D/A convert- installed modules as documented source code. Developers can integrate their own IP with ers and four banks of memory. It features the Pentek factory-installed functions or use built-in support for PCI Express over the 3U VPX backplane. the GateFlow Design Kit to completely replace the Pentek IP with their own. The Cobalt Architecture Xilinx Virtex-6 FPGA The Pentek Cobalt architecture features The Virtex-6 FPGA can be populated a Virtex-6 FPGA. All of the board’s data and with a variety of different FPGAs to match control paths are accessible by the FPGA, Model 53630 COTS (left) enabling factory-installed functions includ- the specific requirements of the processing and rugged version task. Supported FPGAs include: LX130T, ing data multiplexing, channel selection, LX240T, LX365T, SX315T, or SX475T. The data packing, gating, triggering and memory control. The Cobalt architecture organizes SXT parts feature up to 2016 DSP48E slices and are ideal for modulation/demodulation, the FPGA as a container for data processing encoding/decoding, encryption/decryption, applications where each function exists as an intellectual property (IP) module. and channelization of the signals between transmission and reception. For applications Each member of the Cobalt family is not requiring large DSP resources, one of delivered with factory-installed applications ideally matched to the board’s analog inter- the lower-cost LXT FPGAs can be installed. Option -104 provides 20 pairs of LVDS faces. The 53630 factory-installed functions connections between the FPGA and the include an A/D acquisition and a D/A wave- form playback IP module. In addition, IP VPX P2 connector for custom I/O. Features Option -105 provides one 8X or two 4X modules for either DDR3 or QDRII+ ■ Complete radar and software gigabit links between the FPGA and the VPX memories, a controller for all data clocking radio interface solution and synchronization functions, a test signal P1 connector to support serial protocols. ➤ ■ Supports Xilinx Virtex-6 generator and a PCIe interface complete the LXT and SXT FPGAs ■ Supports gigabit serial fabrics including PCI Express, Serial RF In RF Out RapidIO and Xilinx Aurora ■ One 1 GHz 12-bit A/D RF RF RF ■ One 1 GHz 16-bit D/A XFORMR XFORMR XFORMR Sample Clk / Reference Clk In ■ Up to 2 GB of DDR3 SDRAM TTL or 16 MB of QDRII+ SRAM TIMING BUS PPS/Gate/Sync A/D Clock/Sync Bus 1 GHz GENERATOR 12-BIT A/D Gate In ■ Sample clock synchronization to 1 GHz Sync In Clock / Sync / 16-BIT D/A an external system reference Gate / PPS D/A Clock/Sync Bus A/D Sync Bus 12 ■ LVPECL clock/sync bus for Gate In 16 Sync In multiboard synchronization D/A Sync Bus ■ LVDS connections to the VIRTEX-6 FPGA LX130T, LX240T, LX365T, SX315T or SX475T Virtex-6 FPGA for custom I/O Option -105 VCXO Gigabit Serial I/O ■ 3U VPX form factor provides LVDS GTX GTX GTX a compact, rugged platform 16 16 16 16 16 16 16 16 16 40 ■ Compatible with several VITA 8X 4X 4X DDR3 DDR3 DDR3 DDR3 Option -104 Config SDRAM SDRAM SDRAM SDRAM standards including: FLASH FPGA x8 512 MB 512 MB 512 MB 512 MB 64 MB PCIe I/O VITA-46, VITA-48 and Memory Banks 1 & 2 Memory Banks 3 & 4 TM VITA-65 (OpenVPX DDR3 option 155 DDR3 option 165 CROSSBAR SWITCH System Specification) QDRII+ QDRII+ SRAM SRAM 4X 4X 4X 4X ■ Ruggedized and conduction- 8MB 8MB Gbit Gbit Gbit Gbit Serial Serial Serial Serial cooled versions available QDRII+ option 150 VPX-P2 VPX-P1 VPX BACKPLANE One Park Way ◆ Upper Saddle River ◆ New Jersey 07458 Pentek, Inc. www.pentek.com . . . . Tel: 201 818 5900 ◆ Fax: 201 818 5904 ◆ Email: info pentek.com @ New! New! New! New! New! Model 53630 1 GHz A/D and D/A, Virtex-6 FPGA - 3U VPX ➤ ➤ A/D Converter Stage ➤ ➤ ➤ vide different A/D and D/A clocks. In an The front end accepts an analog HF or alternate mode, the sample clock can be A/D Acquisition IP Module sourced from an onboard programmable IF input on a front panel SSMC connector The 53630 features an A/D with transformer coupling into a Texas voltage-controlled crystal oscillator. In this Acquisition IP Module for easy mode, the front panel SSMC connector can Instruments ADS5400 1 GHz, 12-bit A/D capture and data moving. The IP be used to provide a 10 MHz reference clock converter. module can receive data from The digital outputs are delivered into for synchronizing the internal oscillator. the A/D, a test signal generator, Two front panel 7-pin LVPECL Sync the Virtex-6 FPGA for signal processing, or from the D/A Waveform Play- connectors allow multiple boards to be syn- data capture or for routing to other module back IP Module in loopback resources. chronized. One connector for the A/D and mode. The IP module has associ- one for the D/A each provide sync and ated memory banks for buffering D/A Converter Stage gate signals. data in FIFO mode or for storing The 53630 features a TI DAC5681Z 1 GHz, data in transient capture mode. Memory Resources 16-bit D/A. The converter has an input The memory banks are supported The 53630 architecture supports up to sample rate of 1 GSPS, allowing it to acept with a DMA engine for moving full rate data from the FPGA. Additionally, four independent memory banks which A/D data through the PCIe can be configured with all QDRII+ SRAM, the D/A includes a 2x or 4x interpolation interface. DDR3 SDRAM, or as combination of two filter for applications that provide 1/2 or 1/4 This powerful linked-list DMA rate input data. Analog output is through banks of each type of memory. Each QDRII+ engine is capable of a unique SRAM bank can be up to 8 MB deep and is a front panel SSMC connector. Acquisition Gate Driven mode. an integral part of the board’s DMA capa- In this mode, the length of a Clocking and Synchronization bilities, providing FIFO memory space for transfer performed by a link Two internal timing buses provide either creating DMA packets. For applications definition need not be known requiring deep memory resources, DDR3 a single clock or two different clock rates to prior to data acquisition; rather, the A/D and D/A signal paths. SDRAM banks can each be up to 512 MB it is governed by the length of deep. Built-in memory functions include an Each timing bus includes a clock, sync the acquisition gate. This is A/D data transient capture mode and D/A and a gate or trigger signal. An on-board extremely useful in applications clock generator receives an external sample waveform playback mode. where an external gate drives In addition to the factory-installed func- clock from the front panel SSMC connector. acquisition and the exact length tions, custom user-installed IP within the This clock can be used directly for either of that gate is not known or is the A/D or D/A sections or can be divided FPGA can take advantage of the memories likely to vary. for many other purposes. by a built-in clock synthesizer circuit to pro- ➤ For each transfer, the DMA engine can automatically construct metadata packets containing a sample-accurate time stamp, and data length information. These from to actions simplify the host A/D D/A processor’s job of identifying D/A loopback and executing on the data. TEST SIGNAL INPUT MULTIPLEXER GENERATOR D/A Waveform Playback IP Module DATA DATA The Model 53630 factory- PACKING UNPACKING & FLOW & FLOW installed functions include a CONTROL CONTROL sophisticated D/A Waveform MEMORY MUX MUX CONTROLLER Playback IP module. A linked- list controller allows users to to to METADATA MEMORY GENERATOR Mem Mem CONTROLLER easily play back waveforms Bank 1 Bank 2 stored in either on-board to to LINKED-LIST LINKED-LIST DMA ENGINE DMA ENGINE Mem Mem memory or off- board host Bank 3 Bank 4 D/A A/D memory to the D/A. WAVEFORM ACQUISITION PLAYBACK IP MODULE Parameters including length of IP MODULE waveform, delay from playback trigger, waveform repetition, etc. can be programmed for each PCIe INTERFACE waveform. VIRTEX-6 VIRTEX-6 FPGA FPGA D DA AT TAFLOW AFLOW D DET ETAIL AIL (supports user installed IP) Up to 64 individual link entries can be chained together to 8X 4X 4X 40 create complex waveforms with Memory Memory Memory Memory Gigabit FPGA Bank 1 Bank 2 Bank 3 Bank 4 a minimum of programming. PCIe GPIO Serial I/O One Park Way ◆ Upper Saddle River ◆ New Jersey 07458 Pentek, Inc. www.pentek.com . . . . Tel: 201 818 5900 ◆ Fax: 201 818 5904 ◆ Email: info pentek.com @ Model 53630 1 GHz A/D and D/A, Virtex-6 FPGA - 3U VPX ➤ ➤ PCI Express Interface ➤ ➤ ➤ Clock Synthesizer The Model 53630 includes an industry- Clock Source: Selectable from on-board programmable VCXO or front panel ex- standard interface fully compliant with PCI Express Gen. 1 & 2 bus specifications. ternal clock VCXO Frequency Ranges: 10 to 945 Supporting PCIe links up to x8, the inter- MHz, 970 to 1134 MHz, and 1213 to face includes multiple DMA controllers for efficient transfers to and from the board. 1417 MHz Synchronization: VCXO can be locked Fabric-Transparent Crossbar Switch to an external 4 to 200 MHz PLL system The 53630 features a unique high-speed reference, typically 10 MHz Clock Dividers: External clock or VCXO switching configuration. A fabric-transpar- can be divided by 1, 2, 4, 8, or 16, inde- ent crossbar switch bridges numerous interfaces and components on the board pendently for the A/D clock and D/A clock using gigabit serial data paths with no latency. External Clock Programmable signal input equalization and output pre-emphasis settings enable Type: Front panel female SSMC connector, sine wave, 0 to +10 dBm, AC-coupled, optimization. Data paths can be selected as 50 ohms, accepts 100 MHz to 1 GHz single (1X) lanes, or groups of four lanes (4X). divider input clock, or PLL system Specifications reference Timing Bus: 7-pin connectors, LVPECL Front Panel Analog Signal Inputs Input Type: Transformer-coupled, front bus for sync and gate, one A/D connec- tor and one D/A connector panel female SSMC connectors External Trigger Input A/D Converter Type: Texas Instruments ADS5400 Type: Front panel female SSMC connec- tor, LVTTL Sampling Rate: 100 MHz to 1 GHz Function: Programmable functions Resolution: 12 bits D/A Converter include: trigger, gate, sync and PPS Field Programmable Gate Array Type: Texas Instruments DAC5681Z Standard: Xilinx Virtex-6 XC6VLX130T-2 Input Data Rate: 1 GHz max. Interpolation Filter: bypass, 2x or 4x Optional: Xilinx Virtex-6 XC6VLX240T-2, XC6VLX365T-2, XC6VSX315T-2, or Output Sampling Rate: 1 GHz max. XC6VSX475T-2 Resolution: 16 bits Front Panel Analog Signal Outputs Custom I/O Option -104: Provides 20 pairs of LVDS Output Type: Transformer-coupled, Ordering Information connections between the FPGA and the front panel female SSMC connectors Model Description Sample Clock Sources: On-board clock VPX P2 connector for custom I/O 53630 1 GHz A/D and D/A, Option -105: Provides one 8X or two synthesizer generates two clocks: one Virtex-6 FPGA - 3U VPX 4X gigabit links between the FPGA and A/D clock and one D/A clock the VPX P1 connector to support serial Options: protocols -062 XC6VLX240T Memory -063 XC6VLX365T Option 150: Two 8 MB QDRII+ SRAM -064 XC6VSX315T memory banks, 400 MHz DDR -065 XC6VSX475T Option 155 or 165: Two 512 MB DDR3 -104 LVDS FPGA I/O to VPX SDRAM memory banks, 400 MHz DDR P2 PCI-Express Interface -105 Gigabit serial FPGA I/O PCI Express Bus: Gen.1: x4 or x8; to VPX P1 Gen 2: x4 -150 Two 8 MB QDRII+ SRAM Environmental Memory Banks Operating Temp: 0° to 50° C (Banks 1 and 2) Storage Temp: –20° to 90° C -155 Two 512 MB DDR3 Relative Humidity: 0 to 95%, non-cond. SDRAM Memory Banks Size: 3.937 in. x 6.717 in. (100 mm x 170.6 mm) (Banks 1 and 2) -165 Two 512 MB DDR3 SDRAM Memory Banks (Banks 3 and 4) Contact Pentek for availability of rugged and conduction-cooled versions One Park Way ◆ Upper Saddle River ◆ New Jersey 07458 Pentek, Inc. www.pentek.com . . . . Tel: 201 818 5900 ◆ Fax: 201 818 5904 ◆ Email: info pentek.com @