3-Channel 200 MHz A/D with DDC, DUC with 2-Channel Model 53621 800 MHz D/A, and a Virtex-6 FPGA - 3U VPX General Information sition modules. IP modules for either DDR3 ® Model 53621 is a member of the Cobalt or QDRII+ memories, a controller for all data clocking and synchronization functions, family of high performance 3U VPX boards based on the Xilinx Virtex-6 FPGA. A multi- a test signal generator, an Aurora gigabit channel, high-speed data converter with a serial interface, and a PCIe interface com- plete the factory-installed functions and programmable DDC, it is suitable for connec- tion to HF or IF ports of a communications enable the 53621 to operate as a complete turnkey solution, without the need to develop or radar system. Its built-in data capture and any FPGA IP. playback features offer an ideal turnkey solution. Extendable IP Design The 53621 includes three A/Ds, one For applications that require specialized upconverter, two D/As and four banks of memory. It features built-in support for function, users can install their own custom IP for data processing. Pentek GateFlow PCI Express over the 3U VPX backplane. FPGA Design Kits include all of the factory- The Cobalt Architecture installed modules as documented source The Pentek Cobalt Architecture features code. Developers can integrate their own IP with the Pentek factory-installed func- a Virtex-6 FPGA. All of the board’s data and Model 53621 COTS (left) control paths are accessible by the FPGA, tions or use the GateFlow kit to completely and rugged version replace the Pentek IP with their own. enabling factory-installed functions including data multiplexing, channel selection, data Xilinx Virtex-6 FPGA packing, gating, triggering and memory The Virtex-6 FPGA can be populated control. The Cobalt Architecture organizes with a variety of different FPGAs to match the FPGA as a container for data processing applications where each function exists as the specific requirements of the processing task. Supported FPGAs include: LX240T, an intellectual property (IP) module. LX365T, SX315T, or SX475T. The SXT parts Each member of the Cobalt family is deliv- ered with factory-installed applications ideally feature up to 2016 DSP48E slices and are ideal for modulation/demodulation, encod- matched to the board’s analog interfaces. ing/decoding, encryption/decryption, and The 53621 factory-installed functions include three A/D acquisition and a D/A waveform channelization of the signals between transmission and reception. For applications playback IP modules. Each of the three Features not requiring large DSP resources, one of acquisition IP modules contains a powerful, ■ Complete radar and software programmable DDC IP core. The waveform the lower-cost LXT FPGAs can be installed. radio interface solution Option -104 provides 20 pairs of LVDS playback IP module contains an intrepolation connections between the FPGA and the IP core, ideal for matching playback rates to ■ Supports Xilinx Virtex-6 the data and decimation rates of the acqui- VPX P2 connector for custom I/O. ➤ LXT and SXT FPGAs ■ Three 200 MHz 16-bit A/Ds RF In RF In RF In RF Out RF Out ■ Three multiband DDCs (digital downconverters) RF RF RF RF RF RF RF XFORMR XFORMR XFORMR XFORMR XFORMR XFORMR XFORMR ■ One DUC (digital upconverter) Sample Clk / A/D Reference Clk In ■ Two 800 MHz 16-bit D/As Clock/Sync TIMING BUS Bus GENERATOR 200 MHz 200 MHz 200 MHz 800 MHz 800 MHz ■ Multiboard programmable 16-BIT A/D 16-BIT A/D 16-BIT A/D 16-BIT D/A 16-BIT D/A Clock / Sync / beamformer TTL Gate / Trig DIGITAL Gate / PPS TTL Sync / PPS UPCONVERTER D/A ■ Up to 2 GB of DDR3 SDRAM Clock/Sync Sample Clk 16 16 16 or 32 MB of QDRII+ SRAM Reset Bus 32 Gate A/D Gate D/A ■ Sample clock synchronization to Sync / PPS A/D VIRTEX-6 FPGA an external system reference Sync / PPS D/A VCXO LX240T, LX365T, SX315T or SX475T Timing Bus Aurora ■ LVPECL clock/sync bus for Gigabit Serial I/O LVDS GTX GTX GTX multiboard synchronization ■ 3U VPX form factor provides 16 16 16 16 16 16 16 16 16 40 8X 4X 4X a compact, rugged platform QDRII+ QDRII+ QDRII+ QDRII+ Sum Config Option -104 Sum SRAM SRAM SRAM SRAM FLASH x8 to FPGA from 8MB 8MB 8MB 8MB ■ Compatible with several VITA 64 MB PCIe next prior I/O board board standards including: QDRII+ option 150 QDRII+ option 160 CROSSBAR VITA-46, VITA-48 and DDR3 option 155 DDR3 option 165 SWITCH TM DDR3 DDR3 DDR3 DDR3 VITA-65 (OpenVPX SDRAM SDRAM SDRAM SDRAM 4X 4X 4X 4X 512 MB 512 MB 512 MB 512 MB System Specification) Gbit Gbit Gbit Gbit Serial Serial Serial Serial Memory Banks1&2 Memory Banks3&4 ■ Ruggedized and conduction- VPX-P2 VPX-P1 cooled versions available VPX BACKPLANE One Park Way ◆ Upper Saddle River ◆ New Jersey 07458 Pentek, Inc. www.pentek.com . . . . Tel: 201 818 5900 ◆ Fax: 201 818 5904 ◆ Email: info pentek.com @ New! New! New! New! New! 3-Channel 200 MHz A/D with DDC, DUC with 2-Channel Model 53621 800 MHz D/A, and a Virtex-6 FPGA - 3U VPX power level of any DDC core falls below setting that ranges from DC to ƒ , where ƒ s s or exceeds a programmable threshold. is the A/D sampling frequency. Each A/D Acquisition IP Modules A programmable summation block DDC can have its own unique decimation provides summing of any of the three DDC The 53621 features three A/D setting, supporting as many as three differ- core outputs. An additional programmable Acquisition IP Modules for eas- ent output bandwidths for the board. gain stage compensates for summation ily capturing and moving data. Decimations can be program-med from 2 to change bit growth. A power meter and Each module can receive data 65,536 providing a wide range to satisfy threshold detect block is provided for the from any of the three A/Ds, a most applications. summed output. The output is then directed test signal generator or from The decimating filter for each DDC back into the A/D Acquisition IP Module 1 the D/A Waveform Playback IP accepts a unique set of user-supplied 18-bit FIFO for reading over the PCIe. For larger Module in loopback mode. coefficients. The 80% default filters deliver systems, multiple 53621’s can be chained Each IP module has an associ- an output bandwidth of 0.8 ƒ /N, where * s together via a built-in Xilinx Aurora giga- ated memory bank for buffering N is the decimation setting. The rejection of bit serial interface through the VPX P1 data in FIFO mode or for storing adjacent-band components within the connector. This allows summation across data in transient capture mode. 80% output bandwidth is better than 100 dB. channels on multiple boards. All memory banks are supported Each DDC delivers a complex output stream with DMA engines for easily consisting of 24-bit I + 24-bit Q or16-bit I + moving A/D data through the 16-bit Q samples at a rate of ƒ /N. s PCIe interface. D/A Waveform Playback IP Module Beamformer IP Core These powerful linked-list The Model 53621 factory-installed DMA engines are capable of a In addition to the DDCs, the 53621 fea- functions include a sophisticated D/A unique Acquisition Gate Driven tures a complete beamforming subsystem. Waveform Playback IP module. A linked- mode. In this mode, the length of Each DDC core contains programable I & Q list controller allows users to easily play a transfer performed by a link phase and gain adjustments followed by a back to the dual D/As waveforms stored definition need not be known power meter that continuously measures the in either on-board memory or off-board prior to data acquisition; rather, individual average power output. The time host memory . it is governed by the length of constant of the averaging interval for each Parameters including length of waveform, the acquisition gate. This is meter is programmable up to 8K samples. delay from playback trigger, waveform extremely useful in applications The power meters present average power repetition, etc. can be programmed for each where an external gate drives measurements for each DDC core output in waveform. acquisition and the exact length easy-to-read registers. Up to 64 individual link entries can be of that gate is not known or is In addition, each DDC core includes a chained together to create complex wave- likely to vary. threshold detector to automatically send forms with a minimum of programming. For each transfer, the DMA an interrupt to the processor if the average ➤ engine can automatically construct metadata packets containing A/D channel ID, a sample-accu- from from from to rate time stamp and data length D/A A/D Ch 1 A/D Ch 2 A/D Ch 3 information. These actions sim- plify the host processor’s job of D/A loopback TEST SIGNAL identifying and executing on the INPUT MULTIPLEXER GENERATOR data. DDC DDC DDC INTERPOLATOR DEC: 2 TO 65536 DEC: 2 TO 65536 DEC: 2 TO 65536 2 TO 65536 IP CORE POWER POWER POWER METER & METER & METER & DATA UNPACKING THRESHOLD THRESHOLD THRESHOLD DETECT DETECT DETECT & FLOW CONTROL MUX DDC IP Cores DDC CORE DDC CORE DDC CORE MUX DATA PACKING & DATA PACKING & DA DAT TA A P PACKING ACKING & & Within each A/D Acquisition FLOW CONTROL FLOW CONTROL FLOW FLOW C CONTROL ONTROL MEMORY MEMORY MEMORY IP Module is a powerful DDC IP CONTROL CONTROL CONTROL MEMORY METADATA METADATA METADATA core. Because of the flexible CONTROL MUX MUX MUX GENERATOR GENERATOR GENERATOR to to to Mem Mem Mem input routing of the A/D Acqui- to LINKED-LIST Bank 1 LINKED-LIST Bank 2 LINKED-LIST LINKED-LIST DMA ENGINE Bank 3 Mem DMA ENGINE DMA ENGINE DMA ENGINE sition IP Modules, many Bank 4 D/A A/D A/D A/D WAVEFORM different configurations can be ACQUISITION ACQUISITION ACQUISITION PLAYBACK IP MODULE 1 IP MODULE 2 IP MODULE 3 IP MODULE achieved including one A/D driving all three DDCs or each of the three A/Ds driving its own AURORA DDC. sum out GIGABIT � VIRTEX-6 VIRTEX-6 FPGA FPGA DA DAT TAFLOW AFLOW DET DETAIL AIL PCIe INTERFACE SERIAL SUMMER Each DDC has an indepen- INTERFACE sum in BEAMFORMER CORE dent 32-bit tuning frequency 4X 4X 8X 8X to next from previous PCIe board board One Park Way ◆ Upper Saddle River ◆ New Jersey 07458 Pentek, Inc. www.pentek.com . . . . Tel: 201 818 5900 ◆ Fax: 201 818 5904 ◆ Email: info pentek.com @ 3-Channel 200 MHz A/D with DDC, DUC with 2-Channel Model 53621 800 MHz D/A, and a Virtex-6 FPGA - 3U VPX ➤ ➤ A/D Converter Stage ➤ ➤ ➤ A front panel 26-pin LVPECL Clock/Sync The front end accepts three analog HF connector allows multiple boards to be syn- or IF inputs on front panel SSMC connectors chronized. In the slave mode, it accepts with transformer coupling into three Texas LVPECL inputs that drive the clock, sync Instruments ADS5485 200 MHz, 16-bit and gate signals. In the master mode, the A/D converters. LVPECL bus can drive the timing signals The digital outputs are delivered into for synchronizing multiple boards. the Virtex-6 FPGA for signal processing, Multiple 53621’s can be driven from the data capture and for routing to other LVPECL bus master, supporting synchronous board resources. sampling and sync functions across all connected boards. Digital Upconverter and D/A Stage Memory Resources A TI DAC5688 DUC (digital upconverter) and D/A accepts a baseband real or complex The 53621 architecture supports up to data stream from the FPGA and provides four independent memory banks which that input to the upconvert, interpolate and can be configured with all QDRII+ SRAM, dual D/A stages. DDR3 SDRAM, or as combination of two When operating as a DUC, it interpolates banks of each type of memory. and translates real or complex baseband Each QDRII+ SRAM bank can be up to input signals to any IF center frequency up 8 MB deep and is an integral part of the to 360 MHz. It delivers real or quadrature module’s DMA capabilities, providing (I+Q) analog outputs to the dual 16-bit D/A FIFO memory space for creating DMA converter. Analog output is through a pair packets. For applications requiring deep of front panel SSMC connectors. memory resources, DDR3 SDRAM banks If translation is disabled, the DAC5688 can each be up to 512 MB deep. Built-in acts as a dual interpolating 16-bit D/A with memory functions include an A/D data output sampling rates up to 800 MHz. In transient capture mode and D/A waveform both modes the DAC5688 provides interpo- playback mode. lation factors of 2x, 4x and 8x. In addition to In addition to the factory-installed func- the DAC5688, an FPGA-based interpolator tions, custom user-installed IP within the core provides additional interpolation from FPGA can take advantage of the memories 2x to 65,536x. The two interpolators can be for many other purposes. combined to crate a total range from 2x to PCI Express Interface 524,288x. The Model 53621 includes an industry- Clocking and Synchronization standard interface fully compliant with PCI Two internal timing buses provide either Express Gen. 1 & 2 bus specifications. a single clock or two different clock rates to Supporting PCIe links up to x8, the inter- the A/D and D/A signal paths. face includes multiple DMA controllers Each timing bus includes a clock, sync for efficient transfers to and from the board. and a gate or trigger signal. An on-board Fabric-Transparent Crossbar Switch clock generator receives an external sample clock from the front panel SSMC connector. The 53621 features a unique high-speed This clock can be used directly for either the switching configuration. A fabric-transpar- A/D or D/A sections or can be divided by a ent crossbar switch bridges numerous built-in clock synthesizer circuit to provide interfaces and components on the board different A/D and D/A clocks. In an alter- using gigabit serial data paths with no latency. nate mode, the sample clock can be sourced Programmable signal input equalization from an on-board programmable VCXO and output pre-emphasis settings enable (Voltage-Controlled Crystal Oscillator). In optimization. this mode, the front panel SSMC connector Data paths can be selected as single (1X) can be used to provide a 10 MHz reference lanes, or groups of four lanes (4X). ➤ clock for synchronizing the internal oscillator. One Park Way ◆ Upper Saddle River ◆ New Jersey 07458 Pentek, Inc. www.pentek.com . . . . Tel: 201 818 5900 ◆ Fax: 201 818 5904 ◆ Email: info pentek.com @ 3-Channel 200 MHz A/D with DDC, DUC with 2-Channel Model 53621 800 MHz D/A, and a Virtex-6 FPGA - 3U VPX ➤ ➤ Specifications ➤ ➤ ➤ Front Panel Analog Signal Outputs Front Panel Analog Signal Inputs Output: Transformer-coupled, front panel female SSMC connectors Input Type: Transformer-coupled, front panel female SSMC connectors Transformer: Coil Craft WBC4-6TLB Full Scale Output: +4 dBm into 50 ohms Transformer Type: Coil Craft 3 dB Passband: 300 kHz to 700 MHz WBC4-6TLB Full Scale Input: +8 dBm into 50 ohms Sample Clock Sources: On-board clock synthesizer generates two clocks: one 3 dB Passband: 300 kHz to 700 MHz A/D clock and one D/A clock A/D Converters Type: Texas Instruments ADS5485 Clock Synthesizer Clock Source: Selectable from on-board Sampling Rate: 10 MHz to 200 MHz programmable VCXO (10 to 810 MHz), Resolution: 16 bits Digital Downconverters front panel external clock or LVPECL timing bus Quantity: Three channels Synchronization: VCXO can be locked Decimation Range: 2x to 65,536x in two stages of 2x to 256x to an external 4 to 180 MHz PLL system reference, typically 10 MHz LO Tuning Freq. Resolution: 32 bits, Clock Dividers: External clock or VCXO 0 to ƒ s LO SFDR: >120 dB can be divided by 1, 2, 4, 8, or 16, inde- pendently for the A/D clock and D/A Phase Offset Resolution: 32 bits, clock 0 to 360 degrees FIR Filter: 18-bit coefficients, 24-bit output, External Clock Type: Front panel female SSMC connector, with user programmable coefficients sine wave, 0 to +10 dBm, AC-coupled, Default Filter Set: 80% bandwidth, <0.3 dB passband ripple, >100 dB stopband 50 ohms, accepts 10 to 800 MHz divider input clock or PLL system reference attenuation Timing Bus: 26-pin connector LVPECL D/A Converters Type: Texas Instruments DAC5688 bus includes, clock/sync/gate/PPS in- puts and outputs; TTL signal for gate/ Input Data Rate: 250 MHz max. trigger and sync/PPS inputs Output IF: DC to 400 MHz max. Output Signal: 2-channel real or Field Programmable Gate Array Ordering Information Standard: Xilinx Virtex-6 XC6VLX240T 1-channel with frequency translation Optional: Xilinx Virtex-6 XC6VLX365T, Output Sampling Rate: 800 MHz max. Model Description with 2x, 4x or 8x interpolation XC6VSX315T, or XC6VSX475T 53621 3-Channel 200 MHz A/D Custom I/O Resolution: 16 bits with DDC, DUC with Option -104: Provides 20 pairs of LVDS Digital Interpolator 2-Channel 800 MHz D/A, Interpolation Range: 2x to 65,536x in connections between the FPGA and the and a Virtex-6 FPGA - 3U XMC VPX P2 connector for custom I/O two stages of 2x to 256x Memory Beamformer Options: Summation: Three channels on-board; Option 150 or 160: Two 8 MB QDRII+ -062 XC6VLX240T SRAM memory banks, 400 MHz DDR multiple boards can be summed via -063 XC6VLX365T Option 155 or 165: Two 512 MB DDR3 Summation Expansion Chain -064 XC6VSX315T Summation Expansion Chain: One SDRAM memory banks, 400 MHz DDR -065 XC6VSX475T PCI-Express Interface chain in and one chain out link via XMC -104 LVDS FPGA I/O to VPX PCI Express Bus: Gen. 1: x4 or x8; connector using Aurora protocol P2 Phase Shift Coefficients: I & Q with Gen. 2: x4 -150 Two 8 MB QDRII+ SRAM Environmental 16-bit resolution Memory Banks Operating Temp: 0° to 50° C Gain Coefficients: 16-bit resolution (Banks 1 and 2) Channel Summation: 24-bit Storage Temp: –20° to 90° C -160 Two 8 MB QDRII+ SRAM Relative Humidity: 0 to 95%, non-cond. Multiboard Summation Expansion: Memory Banks Size: 3.937 in. x 6.717 in. (100 mm x 170.6 mm) 32-bit (Banks 3 and 4) -155 Two 512 MB DDR3 SDRAM Memory Banks (Banks 1 and 2) -165 Two 512 MB DDR3 SDRAM Memory Banks (Banks 3 and 4) Contact Pentek for availability of rugged and conduction-cooled versions One Park Way ◆ Upper Saddle River ◆ New Jersey 07458 Pentek, Inc. www.pentek.com . . . . Tel: 201 818 5900 ◆ Fax: 201 818 5904 ◆ Email: info pentek.com @ 3-Channel 200 MHz A/D with DDC, DUC with 2-Channel Model 53621 800 MHz D/A, and a Virtex-6 FPGA - 3U VPX A/D Performance Spurious Free Dynamic Range Spurious Pick-up f = 200 MHz, Internal Clock f = 70 MHz, f = 200 MHz, Internal Clock s in s Two-Tone SFDR Two-Tone SFDR f = 30 MHz, f = 70 MHz, f = 200 MHz f = 69 MHz, f = 71 MHz, f = 200 MHz 1 2 s 1 2 s Adjacent Channel Crosstalk Crosstalk Input Frequency Response f = 70 MHz, f = 200 MHz, Ch 1 shown f = 200 MHz, Internal Clock in Ch2 s s D/A Performance Spurious Free Dynamic Range Spurious Free Dynamic Range f = 70 MHz, f = 200 MHz, Internal Clock f = 140 MHz, f = 400 MHz, External Clock out s out s One Park Way ◆ Upper Saddle River ◆ New Jersey 07458 Pentek, Inc. www.pentek.com . . . . Tel: 201 818 5900 ◆ Fax: 201 818 5904 ◆ Email: info pentek.com @