Model 5358 Dual 500 MHz A/D, 800 MHz D/A, Virtex-5 FPGAs - 3U VPX General Information Analog output is through a pair of front Model 5358 is a dual-channel, high-speed panel SMC connectors at +4 dBm into data converter suitable for connection to 50 ohms. If translation is disabled, the HF or IF ports of a communication system. It DAC5688 acts as a dual interpolating 16-bit includes two 500 MHz A/Ds, 800 MHz D/As D/A with output sampling rates up to and Virtex-5 FPGAs. 800 MHz. In both modes the DAC provides The 5358 features built-in support for interpolation factors of 2x, 4x and 8x. PCI Express (PCIe) Gen. 2 over the 3U VPX Virtex-5 FPGAs backplane. A unique fabric-transparent crossbar switch configuration adds gigabit The architecture includes two Virtex-5 serial data paths for Xilinx Aurora or Serial FPGAs. All of the board’s data and control RapidIO applications. paths are accessible by the FPGAs, enabling factory-installed functions including data A/D Converter Stage multiplexing, channel selection, data packing, The front end accepts two full scale gating, triggering and SDRAM memory analog HF or IF inputs on front panel SMC control. In addition to the built-in functions, connectors at +8 dBm into 50 ohms with users can install their own custom IP for transformer coupling into TI ADS5463 12-bit data processing. Pentek GateFlow FPGA 500 MHz A/Ds. Designed with a 750 MHz Design Kits facilitate integration of user-cre- input bandwidth, the A/Ds are excellent ated IP with the factory shipped functions. for undersampling applications. The processing FPGA serves as a control The digital outputs are delivered into the and status engine with data and program- processing FPGA for signal processing, cap- ming interfaces to each of the on-board ture or routing to other board resources. resources including the data converters, DDR2 SDRAM memory, interface FPGA, Digital Upconverter and D/A Stage programmable LVDS I/O and clock, gate Features A TI DAC5688 digital upconverter (DUC) and synchronization circuits. The processing ■ Complete software radio and D/A accepts a baseband real or complex FPGA can be populated with a variety of interface solution for 3U VPX data stream from the FPGA and provides different FPGAs to match the specific require- systems that input to the upconvert, interpolate and ments of the processing task. Supported ■ Supports Gigabit Serial dual D/A stages. FPGAs include: Virtex-5 SX50T, SX95T, Fabrics including PCI When operating as an upconverter, it LX50T, LX155T, and FX100T. Express, Serial RapidIO interpolates and translates real or complex The SXT parts feature between 288 and and Xilinx Aurora baseband input signals to any IF center 640 DSP48E slices and are ideal for demodu- ■ Two 500 MHz 12-bit A/Ds frequency between DC and 300 MHz. It lation/modulation, decoding/encoding, delivers real or quadrature (I+Q) outputs at decryption/encryption, digital delay, and ■ One DUC (Digital Upconverter) up to 500 MHz to the 16-bit D/A converter. channelization of the signals between ➤ ■ Two 800 MHz, 16-bit D/As ■ Up to 1 GB of DDR2 RF In RF In RF Out RF Out SDRAM RF RF RF RF XFORMR XFORMR XFORMR XFORMR ■ Two Xilinx Virtex-5 FPGAs Sample Clk / Reference Clk In TIMING BUS ■ Dual timing buses for A/D Clock Bus PPS In GENERATOR 500 MHz 500 MHz 800 MHz 800 MHz 12-BIT A/D 12-BIT A/D 16-BIT D/A 16-BIT D/A independent A/D and D/A Clock / Sync / D/A Clock Bus TTL Gate / Trig DIGITAL UPCONVERTER Gate / PPS TTL Sync / PPS 14 14 clock rates Sample Clk 32 Sync Clk To All ■ LVPECL clock/sync bus for Gate A Sections PROCESSING FPGA Gate B Sync VIRTEX-5 LX50T, LX155T, SX50T, SX95T or FX100T Control/ multiboard synchronization PPS VCXO Status GTP GTP GTP LVDS Timing Bus ■ 32 pairs of LVDS 32 32 8 4X 4X 4X 64 DDR2 DDR2 FLASH connections to the Virtex-5 SDRAM SDRAM 32 MB 256 MB 256 MB GTP INTERFACE FPGA FPGAs for custom I/O VIRTEX-5 LX30T or SX50T GTP PCI-X LVDS ■ 3U VPX form factor provides 32 PCI-X BUS 1 4X 64 a compact, rugged platform (64 Bits, 100 MHz) 32 ■ Compatible with several PCI-X TO XMC - P15 PMC - P14 PCIe BRIDGE VITA standards including: 4X 4X x4 PCIe VITA-46 (VPX Baseline PCI EXPRESS SWITCH PEX 8648 Standard) 24 lanes / 6 ports 24 each configurable as x1/x4/x8/x16 64 VITA-48 (VPX REDI) CROSSBAR TM SWITCH VITA-65 (OpenVPX 4X 4X 4X 4X System Specification) Gbit Gbit Gbit Gbit Serial Serial Serial Serial ■ Ruggedized and conduction- VPX-P1 VPX-P2 cooled versions available VPX BACKPLANE One Park Way ◆ Upper Saddle River ◆ New Jersey 07458 Pentek, Inc. www.pentek.com . . . . Tel: 201 818 5900 ◆ Fax: 201 818 5904 ◆ Email: info pentek.com @ New! New! New! New! New! Model 5358 Dual 500 MHz A/D, 800 MHz D/A, Virtex-5 FPGAs - 3U VPX reception and transmission. For applications Output Sampling Rate: 800 MHz max. requiring more FPGA logic cells, the board can with intepolation be optionally configured with an LX155T in the Resolution: 16 bits Memory Resources processing FPGA position for 156,648 logic cells. Front Panel Analog Signal Outputs Up to two independent 512 MB A second Virtex-5 FPGA provides the Output Type: Transformer-coupled, banks of DDR2 SDRAM are avail- board’s PCI-X interface. The interface FPGA front panel female SMC connectors able to the processing FPGAs. can be configured as an LXT family or an SXT Full Scale Output: +4 dBm into 50 ohms Built-in memory functions include family part, providing not only interface 3 dB Passband: 250 kHz to 750 MHz an A/D data transient capture functionality, but processing resources up to Sample Clock Sources: On-board clock mode with pre- and post-trigger- an additional 640 DSP48E slices. synthesizer generates two clocks: one ing and D/A waveform playback Option -104 provides general purpose A/D clock and one D/A clock mode. All memory banks are I/O to VPX-P2 with 16 pairs of LVDS con- Clock Synthesizer: supported with DMA engines for nections to the processing FPGA, and 16 Clocks Source: Selectable from on-board easily moving data through the more to the interface FPGA for custom I/O. programmable VCXO, front panel exter- PCI interface. nal clock or LVPECL timing bus Clocking and Synchronization Synchronization: Clocks can be locked to a Fabric-Transparent Crossbar Two internal timing buses can provide front panel 5 or 10 MHz system reference Switch either a single clock or two different clock External Clocks The 5358 features a unique rates to the A/D and D/A signal paths. Type: Front panel female SMC connector, high-speed switching configura- Each timing bus includes a clock, sync sine wave, 0 to +10 dBm, AC- coupled, tion. A fabric-transparent crossbar and a gate or trigger signal. An internal 50 ohms, accepts 20 to 500 MHz sample switch bridges numerous inter- clock generator receives an external sample clock or 10 MHz system reference faces and components on the clock from the front panel SMC connector. Timing Bus: 26-pin connector LVPECL board using gigabit serial data This clock can be used directly for either the bus includes clock/sync/gate/PPS input/ paths with no latency. Program- A/D or D/A sections or can be divided by output; TTL signals for gate/trigger and mable signal input equalization a built-in clock synthesizer circuit to pro- sync/PPS inputs and output pre-emphasis settings vide different A/D and D/A clocks. In an Field Programmable Gate Arrays enable optimization. Data paths alternate mode, the sample clock can be Processing FPGA: Virtex-5 XC5VSX50T; can be selected as single (x1) lanes, sourced from an on-board programmable optional FPGAs include: XC5VLX50T, or groups of four lanes (x4). voltage controlled crystal oscillator. In this XC5VSX95T, XC5VFX100T, or mode, the front panel SMC connector can be XC5VLX155T PCI Express Switch used to provide a 10 MHz system reference Interface FPGA: Virtex-5 XC5VLX30T; Model 5358 includes a PCIe clock for synchronizing the internal oscillator. optional FPGA: XC5VSX50T or XC5VFX70T Gen. 2 switch. The switch pro- A front panel 26-pin LVPECL Clock/Sync Custom I/O vides a total of 24 PCIe lanes to connector allows multiple boards to be syn- Option -104: Provides GPIO to VPX-P2 the Fabric-Transparent Crossbar chronized. In the slave mode, it accepts with 16 LVDS pairs to processing FPGA Switch on 6 ports. Dynamic lane LVPECL inputs that drive the clock, sync and (SX95T, LX155T or FX100T only) and 16 width negotiation within the PCIe gate signals. In the master mode, the LVPECL pairs to interface FPGA switch allows for x1, x4, x8 or bus can drive the timing signals for synchro- Memory x16 widths. These can be selected nizing multiple modules. DDR2 SDRAM: Up to 1.0 GB in two in any combination. Up to three slave 5358’s can be driven banks to processing FPGA from the LVPECL bus master, supporting PCI to PCIe Interface synchronous sampling and sync functions PCI-X Bus: 64-bits, 100 MHz and 64- or across all connected boards. 32-bits at 33 or 66 MHz DMA: 4 channel demand-mode and Ordering Information Specifications chaining controller per PCI bus Model Description Front Panel Analog Signal Inputs Gigabit Serial I/O: 5358 Dual 500 MHz A/D, Input Type: Transformer-coupled, front Processing FPGA: Two 4X ports to Fab- 800 MHz D/A, Virtex-5 panel female SMC connectors ric-Transparent Switch; one can be FPGAs - 3U VPX Full Scale Input: +8 dBm into 50 ohms alternately routed to interface FPGA 3 dB Passband: 250 kHz to 750 MHz VPX-P1: Four 4X ports to Fabric-Trans- Options: A/D Converters parent Crossbar Switch -104 FPGA I/O to VPX-P2 Type: TI ADS5463 PCI Express: Six ports to Fabric-Trans- -140 1 GB DDR2 SDRAM Sampling Rate: 20 MHz to 500 MHz parent Switch, each configurable as x1, -5xx Gigabit Serial I/O to VPX- Resolution: 12 bits x4, x8 or x16 lanes, 24 lanes total P1- four full-duplex 4X D/A Converters Environmental paths Type: TI DAC5688 Operating Temperature: -703 Level L3 Conduction- Input Data Rate: 250 MHz max. Forced-Air Cooled: 0° to 50° C std; Cooled Version Output IF: DC to 300 MHz -20° to 65° C (Level L2) Output Signal: 2-channel real or Conduction-Cooled: -40° to 70° C (Level L3) Contact Pentek for additional Size: 3.937 in. x 6.717 in. (100 mm x 170.6 mm) 1-channel with frequency translation available options. One Park Way ◆ Upper Saddle River ◆ New Jersey 07458 Pentek, Inc. www.pentek.com . . . . Tel: 201 818 5900 ◆ Fax: 201 818 5904 ◆ Email: info pentek.com @