Model 5353 4/2-Ch. DDC, four 200 MHz 16-bit A/Ds, Beamformer - 3U VPX General Information Each of the DDC channels has an inde- Model 5353 is a high-speed software pendent 32-bit tuning frequency setting that radio board designed for processing ranges from DC to ƒ , where ƒ is the A/D s s baseband RF or IF signals from a communi- sampling frequency. cations receiver. It features four 200 MHz Decimation and Filtering 16-bit A/Ds supported by a high-perfor- mance 4-channel installed DDC (digital Each of the four DDC channels can have its downconverter) and a complete set of own unique decimation setting supporting as beamforming functions. With buit-in multi- many as four different output bandwidths for board synchronization, it is ideally matched the board. The DDC core can be configured to the requirements of real-time software in four-channel mode with each channel radio and radar systems. offering decimations between 2 and 256, The 5353 features built-in support for or in two-channel mode with each channel PCI Express (PCIe) Gen. 2 over the 3U VPX having a decimation range of 2 to 65536, for backplane. A unique fabric-transparent applications that require a wider range of crossbar switch configuration adds gigabit decimations. serial data paths for Xilinx Aurora or Serial The decimating filter for each DDC RapidIO applications. channel accepts a unique set of user-supplied Features 18-bit coefficients. The 80% default filters A/D Converter Stage ■ Built-in Beamformer supports /N, deliver an output bandwidth of 0.8 ƒ * s multiboard systems The front end accepts four full-scale where N is the decimation setting. The analog RF or IF inputs on front panel SMC rejection of adjacent-band components ■ Programmable Power Meter connectors at +8 dBm into 50 ohms with and Threshold Detect per within the 80% output bandwidth is better channel transformer coupling into four Texas Instru- than 100 dB. Each DDC delivers a complex ments ADS5485 200 MHz, 16-bit A/D output stream consisting of 24-bit I + 24-bit ■ Four 200 MHz, 16-bit A/Ds /N. converters. Q samples at a rate of ƒ s ■ 2 or 4 Channels of DDC The digital outputs are delivered into a ■ Independent 32-bit DDC Power Meters Xilinx Virtex-5 FPGA for routing, formatting tuning for all channels Each DDC includes a power meter that and DDC signal processing. ■ DDC decimation range from continuously measures the individual average 2 to 256 or from 2 to 65536 DDC Input Selection and Tuning power output. The power meters calculate ■ Independent decimation The Model 5353 employs an advanced and present average power measurements for factors for each channel FPGA-based digital downconverter engine each channel in easy-to-read registers. The consisting of two or four DDC channels. time constant of the averaging interval for ■ Default filters offer 0.2 dB Four independently controllable input mul- each meter is programmable up to 8 kilo- ripple and 100 dB rejection tiplexers select one of the four A/Ds as the samples. Threshold detectors can generate ■ LVPECL clock/sync bus for input source for each DDC channel. In this interrupts when the calculated power levels multiboard synchronization way, many different configurations can be exceed or fall below user-programmable ■ 3U VPX form factor with achieved including one A/D driving all thresholds, ideal for scanning and monitor- ruggedized and conduction- four DDC channels and each of the four A/Ds ing applications. ➤ cooled versions available driving its own DDC bank. SUM IN 4X CH 1 200 MHz AURORA RF CH 1 GIGABIT RF In XFORMR 16-bit A/D CH 2 SUM OUT 4X SERIAL CH 3 INTERFACE XMC - P15 CH 4 CH 2 RF 200 MHz � I+Q F RF In XFORMR 16-bit A/D SUMMER CH 1 I M DIGITAL CH 1 F U CH 2 DOWNCONVERTER M 0 I+Q X U CH 1 CH 3 RF 200 MHz CH 3 DEC: 2 - 65536 X RF In 16-bit A/D 1 XFORMR POWER CH 4 (DEC: 2 - 256)* METER 4X 4X & Gbit Gbit F THRESHOLD CH 2 PCI-X CH 4 Serial Serial RF 200 MHz CH 1 I DETECTORS M DIGITAL 64 bits RF In XFORMR 16-bit A/D F CH 2 DOWNCONVERTER U M 0 PCI-X BUS 100 MHz I+Q X PCI-X TO CH 2 U CH 3 DEC: 2 - 65536 PCIe BRIDGE X 2 CH 4 POWER (DEC: 2 - 256)* METER PCI-X x4 PCIe & INTERFACE F THRESHOLD CH 3 CH 1 I DETECTORS PCI EXPRESS SWITCH M XILINX Sample DIGITAL F CH 2 U PEX 8648 M XC5VLX30T Clock In TIMING BUS DOWNCONVERTER 0 I+Q X U CH 3 CH 3 GENERATOR X 24 lanes / 6 ports 3 PPS In (DEC: 2 - 256)* POWER CH 4 24 each configurable METER Clock / Sync / as x1/x4/x8/x16 & Gate / PPS F THRESHOLD TTL CH 4 CH 1 I CROSSBAR DETECTORS In M F DIGITAL SWITCH CH 2 U M DOWNCONVERTER 0 I+Q X U CH 3 LVDS CH 4 X 4X 4X 4X 4X (DEC: 2 - 256)* 4 Bus CH 4 POWER XTAL Gbit Gbit Gbit Gbit METER OSC Serial Serial Serial Serial & Timing THRESHOLD VPX-P1 Bus DETECTORS *2 Channel Mode: Dec 2-65536, 4 Channel Mode: Dec 2-256 VPX BACKPLANE XILINX XC5VSX95T One Park Way ◆ Upper Saddle River ◆ New Jersey 07458 Pentek, Inc. www.pentek.com . . . . Tel: 201 818 5900 ◆ Fax: 201 818 5904 ◆ Email: info pentek.com @ New! New! New! New! New! Model 5353 4/2-Ch. DDC, four 200 MHz 16-bit A/Ds, Beamformer - 3U VPX Beamformer for the group of four A/D converters that In addition to the A/Ds and DDCs, the allows the A/Ds to be clocked by internal or external clock sources and a multiboard 5353 includes essential resources of a com- plete beamforming subsystem. First, each timing bus. The timing bus includes a clock, a sync, DDC channel provides user-programmable two gate or trigger signals and a PPS signal. I & Q phase and gain adjustments to apply VPX Interface beamforming weights. Then, a summation The timing bus can be driven by an internal For large systems, multiple crystal oscillator, a front panel reference block adds the four DDC output channels. 5353’s can be chained together input or the LVPECL bus. An additional programmable gain stage via a built-in Xilinx Aurora compensates for summation bit growth. A A front panel 26-pin LVPECL Clock/ interface through the VPX-P1 Sync connector allows multiple boards to power meter and threshold detect block is connector. be synchronized. In the slave mode, each provided for the sum output. The sum out- This link creates a board-to- put is then delivered to the Channel 1 FIFO accepts differential LVPECL inputs that board summation expansion drive the clock, sync, gate and PPS signals for delivery through the PCIe interface out chain for creating larger multi- for the internal timing bus. to the VPX backplane. channel beamformer systems. For larger systems, multiple 5353’s can be In the master mode, the LVPECL bus can Xilinx’s Aurora protocol is drive the timing signals for synchronizing chained together using a built-in Xilinx used to provide an efficient x4, multiple boards. Up to three slave 5353’s Aurora engine. It accepts an x4 gigabit sum 1.25 GB/sec point-to-point data input stream from a previous board and can be driven from each LVPECL bus mas- path between boards. ter, supporting synchronous sampling and propagates a x4 sum output stream to the sync functions across all connected boards. next board through the VPX-P1 connector. For larger systems, many more boards can Output Multiplexers and FIFOs be synchronized with an external clock and sync generator. Four output MUXs can be independently switched to deliver either A/D data or DDC Fabric-Transparent Crossbar Switch data into each of the four output FIFOs. The 5353 features a unique high-speed This allows users to view either the wideband A/D data or the narrowband DDC data, switching configuration. A fabric-transpar- ent crossbar switch bridges numerous depending on the application. interfaces and components on the board Each of the output FIFOs operates at its own input and output rates to support dif- using gigabit serial data paths with no latency. Programmable signal input equal- ferent DDC decimation settings between ization and output pre-emphasis settings the banks and efficient block transfers to the PCI-X bus. enable optimization. Data paths can be selected as single (x1) lanes, or groups of Clocking and Synchronization four lanes (x4). The Model 5353 architecture includes a flexible timing and synchronization circuit PHASE SHIFT GAIN I I I I DECIMATION: 2-65536 Q Q Q Q (DECIMATION: 2-256)* From Weight Phase I POWER METER & SUMMATION EXPANSION Previous Board THRESHOLD DETECT AURORA CHAIN IN DIGITAL Weight Phase Q A PORT DOWNCONVERTER A Weight Gain 1.25 GByte/sec x4 Aurora Link P15 PHASE SHIFT GAIN I I I I DECIMATION: 2-65536 Q Q Q Q (DECIMATION: 2-256)* SUMMATION CHAIN BIT GROWTH To FIFO 1 COMPENSATION (Final Result or Weight Phase I POWER METER & THRESHOLD DETECT Intermediate Result DIGITAL Weight Phase Q I I I B DOWNCONVERTER B Weight Gain Q Q Q PHASE SHIFT GAIN SUMMATION POWER METER & I I I I Summation THRESHOLD DETECT (DECIMATION: 2-256)* Chain Q Q Q Q Gain Weight Phase I POWER METER & THRESHOLD DETECT To DIGITAL Weight Phase Q SUMMATION EXPANSION C DOWNCONVERTER C Weight Gain Next Board CHAIN OUT AURORA PORT 1.25 GByte/sec PHASE x4 Aurora Link SHIFT GAIN P15 I I I I (DECIMATION: 2-256)* Q Q Q Q Weight Phase I POWER METER & THRESHOLD DETECT DIGITAL Weight Phase Q D DOWNCONVERTER D Weight Gain BEAMFORMER DATA FLOW DETAIL *2 Channel Mode: Dec 2-65536, 4 Channel Mode: Dec 2-256 One Park Way ◆ Upper Saddle River ◆ New Jersey 07458 Pentek, Inc. www.pentek.com . . . . Tel: 201 818 5900 ◆ Fax: 201 818 5904 ◆ Email: info pentek.com @ Model 5353 4/2-Ch. DDC, four 200 MHz 16-bit A/Ds, Beamformer - 3U VPX PCI Express Switch FIR Filter: Default passband 0.8 ƒ /N * s Model 5353 includes a PCIe Gen. 2 switch. with 0.2 dB passband ripple and 100 dB adjacent channel rejection The switch provides a total of 24 PCIe lanes to the Fabric-Transparent Crossbar Switch FIR Filter Coefficients: 18 bits, user- programmable (default values provided) on 6 ports. Dynamic lane width negotiation Qty FIR Filter Taps: 28 N/8 within the PCIe switch allows for x1, x4, x8 * or x16 widths. These can be selected in any Output Format: 24 bits I + 24 bits Q Output Spectrum Modes: Normal or combination. frequency-reversed Specifications Output Spectrum Offset: No offset or Front Panel Analog Signal Inputs offset by one-half the output bandwidth Beamformer Input Type: Transformer-coupled, front panel female SMC connectors Summation: Four channels on-board; multiple boards can be summed via Transformer Type: Coil Craft WBC4-6TLB Summation Expansion Chain Full Scale Input: +8 dBm into 50 ohms Summation Expansion Chain: One 3 dB Passband: 300 kHz to 700 MHz chain in and one chain out link via XMC A/D Converters connector using Aurora protocol Type: Texas Instruments ADS5485 Phase Shift Coefficients: I & Q with Sampling Rate: 10 MHz to 200 MHz 16-bit resolution Internal Clock: 200 MHz crystal osc. Gain Coefficients: 16-bit resolution External Clock: 10 to 200 MHz Channel Summation: 24-bit Resolution: 16 bits Multiboard Summation Expansion: A/D Data Reduction Mode: Data from the 32-bit A/Ds can be decimated by any value Output Multiplexer and FIFO between 1 and 4096 Qty Output FIFOs: Four Clock Sources: Selectable from onboard FIFO Source Selection: Independent crystal oscillator, external reference or multiplexer selects DDC output or A/D LVPECL clocks PCI to PCIe Interface External Clock PCI-X Bus: 64-bits, 100 MHz and 64- or Type: Front panel female SMC connector, 32-bits at 33 or 66 MHz sine wave, 0 to +10 dBm, AC-coupled 50 DMA: 4 channel demand-mode and ohms chaining controller per PCI bus Sync/Gate Bus: 26-pin connector, clock/ Gigabit Serial I/O: sync/gate/PPS, input/output LVPECL Processing FPGA: Two 4X ports to bus; one gate/trigger and one sync/PPS Aurora Gigabit Serial Interface input TTL signal VPX-P1: Four 4X ports to Fabric-Trans- Digital Downconverter parent Crossbar Switch Type: IP core for Xilinx Virtex-5 PCI Express: Six ports to Fabric-Trans- Qty of DDC Channels: 2 or 4 parent Switch, each configurable as x1, Center Frequency Tuning: 4 tuning x4, x8 or x16 lanes, 24 lanes total words, one for each DDC channel Environmental Center Frequency Tuning Range: DC Operating Temperature: to ƒ with 32 bit resolution Forced-Air Cooled: 0° to 50° C std; s NCO SFDR: –120 dBFS -20° to 65° C (Level L2) Channel Phase Offset Adjustment: Ordering Information Conduction-Cooled: -40° to 70°C (Level 32-bit resolution L3) Model Description Channel Gain Adjustment: 32-bit reso- Storage Temperature: 5353 4/2-Channel DDC with lution Forced-Air Cooled: -20° to 90° C std; four 200 MHz, 16-bit A/Ds Input Selection for DDC Banks: Any -40° to 100° C (Level L1, L2) and Beamformer - 3U channel can select any of the four A/Ds Conduction-Cooled: -50° to 100°C (L3) VPX Decimation Range (N): Relative Humidity: 0 to 95%, non-cond.; Options: 2-Channel Mode: 2 to 65536 0 to 100% with conformal coating -5xx Gigabit Serial I/O to VPX- 4-Channel Mode: 2 to 256 Size: 3.937 in. x 6.717 in. (100 mm x 170.6mm) P1- two full-duplex 4X paths -703 Level L3 Conduction- Cooled Version -730 Two-Slot Heat Sink Contact Pentek for additional available options. One Park Way ◆ Upper Saddle River ◆ New Jersey 07458 Pentek, Inc. www.pentek.com . . . . Tel: 201 818 5900 ◆ Fax: 201 818 5904 ◆ Email: info pentek.com @ Model 5353 4/2-Ch. DDC, four 200 MHz 16-bit A/Ds, Beamformer - 3U VPX A/D Performance Spurious Pickup Spurious-Free Dynamic Range ƒ = 70 MHz, ƒ = 200 MHz, Internal Clock ƒ = 200 MHz, Internal Clock in s s Input Frequency Response Two-Tone SFDR ƒ = 200 MHz, Int. Clock ƒ = 30 MHz, ƒ = 70 MHz, ƒ = 200 MHz, Int. Clock s in1 in2 s Adjacent Channel Crosstalk Phase Noise at 70 MHz ƒ = 70 MHz, Α = 0 dBFS, ƒ = 200 MHz, Int. Clock ƒ = 200 MHz, Int. Clock in in s s One Park Way ◆ Upper Saddle River ◆ New Jersey 07458 Pentek, Inc. www.pentek.com . . . . Tel: 201 818 5900 ◆ Fax: 201 818 5904 ◆ Email: info pentek.com @