Model 5352 32-Channel DDC with Four 200 MHz, 16-bit A/Ds - 3U VPX General Information Decimation and Filtering Model 5352 is a high-speed software radio All of the eight channels within a bank module designed for processing baseband RF share a common decimation setting that or IF signals from a communications receiver. can range from 16 to 8192, programmable It features four 200 MHz 16-bit A/Ds. The in steps of 8. For example, with a sampling A/Ds are supported by a high-performance rate of 200 MHz, the available output band- 32-channel installed DDC (digital downcon- widths range from 19.53 kHz to 10.0 MHz. verter) IP Core, and interfaces ideally matched Each 8-channel bank can have a unique to the requirements of real-time software radio decimation setting supporting up to four and radar systems. different output bandwidths for the board. The 5352 features built-in support for The decimating filter for each DDC PCI Express (PCIe) Gen. 2 over the 3U VPX bank accepts a unique set of user-supplied backplane. 18-bit coefficients. The 80% default filters /N, deliver an output bandwidth of 0.8 ƒ * s A/D Converter Stage where N is the decimation setting. Rejec- The front end accepts four full-scale analog tion of adjacent-band components within RF or IF inputs on front panel SMC connec- the 80% bandwidth is better than 100 dB. tors at +8 dBm into 50 ohms with transformer Each DDC delivers a complex output coupling into four Texas Instruments ADS5485 stream consisting of 24-bit I + 24-bit Q Features /N. Any number of 200 MHz, 16-bit A/D converters. The digi- samples at a rate of ƒ s ■ 32 channels of DDC in tal outputs are delivered into a Xilinx Virtex-5 channels can be enabled with each bank, banks of 8 channels FPGA for routing, formatting and DDC signal selectable from 0 to 8. Each bank includes ■ Independent 32-bit DDC processing. an output sample interleaver that delivers tuning for all channels a channel-multiplexed stream for all enabled ■ DDC decimation from 16 to DDC Input Selection and Tuning channels within the bank. 8192 in steps of 8 The Model 5352 SX95T FPGA employs an Power Meters and Threshold Detectors ■ Bandwidths from 20 kHz to advanced FPGA-based digital down-con- 10 MHz verter engine consisting of four identical The 5352 features 32 power meters that ■ User-programmable 18-bit 8-channel DDC banks. Four independently continuously measure the individual aver- controllable input multiplexers select one of age power output of each DDC channel. FIR filter coefficients the four attached A/Ds as the input source The time constant of the averaging interval ■ Default filters offer 0.2 dB for each DDC bank. In this way, many differ- is programmable up to 16 kilosamples. In ripple and 100 dB rejection ent configurations can be achieved including addition, threshold detectors automatically ■ Power meters and threshold one A/D driving all 32 DDC channels send an interrupt to the processor if the detectors and each of the four A/Ds driving its own average power level of any DDC falls below ■ LVPECL clock/sync bus for DDC bank. or exceeds a programmable threshold. ➤ multiboard synchronization Each of the DDCs has an independent ■ 3U VPX form factor with 32-bit tuning frequency setting ranging ruggedized and conduction- from DC to ƒ (ƒ is the A/D sample rate). s s cooled versions available CH 1 RF 200 MHz RF In XFORMR 16-bit A/D CH 1 8 X 4 M I+Q CHANNEL F U CH 2 RF 200 MHz CH 1 I SUMMATION X F RF In XFORMR 16-bit A/D DDC CH 2 M I+Q 0 PCI-X BANK 1: U CH 3 CH 1-8 64 bits X 1 CH 4 POWER 100 MHz DEC. PCI-X BUS PCI-X TO METER CH 3 16-8192 RF 200 MHz PCIe BRIDGE & RF In XFORMR 16-bit A/D F THRESHOLD CH 2 PCI-X CH 1 I DETECTORS M x4 PCIe INTERFACE F DDC CH 2 U M I+Q 0 BANK 2: X CH 4 U PCI EXPRESS SWITCH RF 200 MHz CH 3 XILINX CH 9-16 X 2 PEX 8648 RF In XFORMR 16-bit A/D POWER XC5VLX30T CH 4 DEC. METER 16-8192 & 24 lanes / 6 ports F 24 THRESHOLD each configurable CH 3 CH 1 Sample I DETECTORS M as x1/x4/x8/x16 F Clk In DDC CH 2 U M TIMING BUS I+Q 0 BANK 3: X CROSSBAR U CH 3 GENERATOR CH 17-24 PPS In X SWITCH 3 CH 4 POWER DEC. METER 16-8192 Clock / Sync / 4X 4X 4X 4X TTL & Gate / PPS F THRESHOLD Gbit Gbit Gbit Gbit In CH 4 CH 1 I DETECTORS M Serial Serial Serial Serial F DDC CH 2 U M I+Q 0 BANK 4: VPX-P1 X U LVPECL CH 3 CH 25-32 X 4 Bus CH 4 POWER DEC. XTAL METER 16-8192 VPX BACKPLANE OSC & THRESHOLD DETECTORS Timing XILINX XC5VSX95T Bus One Park Way ◆ Upper Saddle River ◆ New Jersey 07458 Pentek, Inc. www.pentek.com . . . . Tel: 201 818 5900 ◆ Fax: 201 818 5904 ◆ Email: info pentek.com @ New! New! New! New! New! Model 5352 32-Channel DDC with Four 200 MHz, 16-bit A/Ds - 3U VPX Output Multiplexers and FIFOs Specifications Four output MUXs in the SX95T FPGA Front Panel Analog Signal Inputs can be independently switched to deliver Input Type: Transformer-coupled, front either A/D data or DDC data into each of panel female SMC connectors the four output FIFOs. This allows users to Transformer Type: Coil Craft WBC4-6TLB view either the wideband A/D data or the narrowband DDC data, depending on the Full Scale Input: +8 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz application. Each of the output FIFOs oper- A/D Converters ates at its own input rate and output rate to support different DDC decimation settings Type: Texas Instruments ADS5485 Sampling Rate: 10 MHz to 200 MHz between the banks and efficient block Internal Clock: 200 MHz crystal osc. transfers to the PCI bus. External Clock: 10 to 200 MHz Clocking and Synchronization Resolution: 16 bits A/D Data Reduction Mode: Data from the The Model 5352 architecture includes a flexible timing and synchronization circuit for A/Ds can be decimated by any value be- the group of four A/D converters that tween 1 and 4096 Clock Sources: Selectable from onboard allows the A/Ds to be clocked by internal or external clock sources and a multiboard crystal oscillators, external or LVPECL clocks timing bus. External Clock The timing bus includes a clock, a sync, two gate or trigger signals and a PPS signal. Type: Front panel female SMC connector, sine wave, 0 to +10 dBm, AC- coupled, The timing bus can be driven by an internal 50 ohms crystal oscillator, a front panel reference input or the LVPECL bus. Sync/Gate Bus: 26-pin connector, clock/ sync/gate/PPS input/output LVPECL A front panel 26-pin LVPECL Clock/Sync bus; one gate/trigger and one sync/ connector allows multiple boards to be syn- chronized. In the slave mode, each accepts PPS input TTL signal Field Programmable Gate Array differential LVPECL inputs that drive the Processing FPGA: Xilinx Virtex-5 clock, sync, gate and PPS signals for the internal timing bus. XC5VSX95T dedicated to digital downcoverters and output In the master mode, the LVPECL bus can Interface FPGA: Xilinx Virtex-5 drive the timing signals for synchronizing multiple boards. Up to three slave 5352’s can XC5VLX30T dedicated to the PCI interface be driven from each LVPECL bus master, PCI to PCIe Interface supporting synchronous sampling and sync functions across all connected boards. PCI-X Bus: 64-bits, 100 MHz and 64- or 32-bits at 33 or 66 MHz For larger systems, many more boards can DMA: 4 channel demand-mode and be synchronized with an external clock and sync generator. chaining controller per PCI bus Gigabit Serial I/O Fabric-Transparent Crossbar Switch VPX-P1: Four 4X ports to Fabric-Trans- The 5352 features a unique high-speed parent Crossbar Switch PCI Express: Six ports to Fabric-Trans- switching configuration. A fabric-transparent parent Switch, each configurable as x1, crossbar switch connects the PCI Express switch with the VPX-P1 connector using x4, x8 or x16 lanes, 24 lanes total Environmental gigabit serial data paths with no latency. This Operating Temperature: allows the user to select the desired output port on VPX-P1. Programmable signal Forced-Air Cooled: 0° to 50° C std; Ordering Information -20° to 65° C (Level L2) input equalization and output pre-emphasis Conduction-Cooled: -40° to 70° C (Level L3) Model Description settings on the Crossbar Switch enable optimization. Storage Temperature: 5352 32-Channel DDC with four Forced-Air Cooled: -20° to 90° C std; 200 MHz, 16-bit A/D s - 3U PCI Express Switch VPX -40° to 100° C (Level L1, L2) Model 5352 includes a PCIe Gen. 2 switch. Conduction-Cooled: -50° to 100° C (L3) Options: Relative Humidity: 0 to 95%, non-cond.; The switch provides a total of 24 PCIe lanes -703 Level L3 Conduction- 0 to 100% with conformal coating Cooled Version to the Fabric-Transparent Crossbar Switch on 6 ports. Dynamic lane width negotiation Size: 3.937 in. x 6.717 in. (100 mm x 170.6 mm) -731 Two-slot heat sink within the PCIe switch allows for x1, x4, x8 or x16 widths. These can be selected in any Contact Pentek for additional combination. available options. One Park Way ◆ Upper Saddle River ◆ New Jersey 07458 Pentek, Inc. www.pentek.com . . . . Tel: 201 818 5900 ◆ Fax: 201 818 5904 ◆ Email: info pentek.com @ Model 5352 32-Channel DDC with Four 200 MHz, 16-bit A/Ds - 3U VPX A/D Performance Spurious Pickup Spurious-Free Dynamic Range ƒ = 70 MHz, ƒ = 200 MHz, Internal Clock ƒ = 200 MHz, Internal Clock in s s Input Frequency Response Two-Tone SFDR ƒ = 200 MHz, Int. Clock ƒ = 30 MHz, ƒ = 70 MHz, ƒ = 200 MHz, Int. Clock s in1 in2 s Adjacent Channel Crosstalk Phase Noise at 70 MHz ƒ = 70 MHz, Α = 0 dBFS, ƒ = 200 MHz, Int. Clock ƒ = 200 MHz, Int. Clock in in s s One Park Way ◆ Upper Saddle River ◆ New Jersey 07458 Pentek, Inc. www.pentek.com . . . . Tel: 201 818 5900 ◆ Fax: 201 818 5904 ◆ Email: info pentek.com @