Model 5351 256-Channel DDC with Four 200 MHz, 16-bit A/Ds - 3U VPX General Information Each of the DDCs has an independent Model 5351 is a high-speed software 32-bit tuning frequency setting that ranges from DC to ƒ where ƒ is the A/D sample radio board designed for processing s s baseband RF or IF signals from a communi- rate. cations receiver. It features four 200 MHz Decimation and Filtering 16-bit A/Ds. The A/D converters are sup- ported by a high-performance 256-channel All of the 64 channels within a bank share a common decimation setting that installed DDC (digital downconverter) IP can range from 128 to 1024, programmable in Core and interfaces ideally matched to the requirements of real-time software radio and steps of 64. For example, with a sampling rate of 200 MHz, the available output band- radar systems. widths range from 156.25 kHz to 1.25 MHz. The 5351 features built-in support for PCI Express (PCIe) Gen. 2 over the 3U VPX Each 64-channel bank can have its own unique decimation setting supporting as backplane. many as four different output bandwidths A/D Converter Stage for the board. The front end accepts four full-scale The decimating filter for each DDC bank accepts a unique set of user-supplied 18-bit analog RF or IF inputs on front panel SMC connectors at +8 dBm into 50 ohms with trans- coefficients. The 80% default filters deliver Features an output bandwidth of 0.8 ƒ /N, where N former-coupling into Texas Instruments * s ■ 256 DDC channels is the decimation setting. The rejection of ADS5485 200 MHz, 16-bit A/D converters. ■ Four 200 MHz 16-bit A/Ds The digital outputs are delivered into a Xilinx adjacent-band components within the 80% output bandwidth is better than 100 dB. Virtex-5 FPGA for routing, formatting and ■ Independent tuning for each Each DDC delivers a complex output DDC signal processing. channel and decimation for stream consisting of 24-bit I + 24-bit Q each bank DDC Input Selection and Tuning samples at a rate of ƒ /N. Any number of s ■ DDC decimation from 128 to channels can be enabled with each bank, The Model 5351 SX95T FPGA employs 1024 in steps of 64 an advanced FPGA-based digital down- selectable from 0 to 64. Each bank includes ■ User-programmable 18-bit converter engine consisting of four identical an output sample interleaver that delivers FIR filter coefficients a channel-multiplexed stream for all enabled 64-channel DDC banks. Four independently ■ Default filters offer 0.2 dB controllable input multiplexers select one of channels within the bank. ripple and 100 dB rejection the attached four A/Ds as the input source Output Multiplexers and FIFOs ■ Each bank independently for each DDC bank. In this way, many selects one of four A/Ds different configurations can be achieved Four output MUXs in the SX95T FPGA can be independently switched to deliver ■ LVPECL clock/sync bus for including one A/D driving all 256 DDC either A/D or DDC data into each output multiboard synchronization channels and each of the four A/Ds driving its own DDC bank. FIFO. This allows users to view either ➤ ■ 3U VPX form factor with ruggedized and conduction- cooled versions available CH 1 200 MHz RF RF In 16-bit A/D XFORMR CH 1 CH 2 200 MHz CH 1 RF M RF In XFORMR 16-bit A/D CH 2 DIGITAL U FIFO 1 M I+Q PCI-X DOWNCONVERTER X U CH 3 BANK 1: CH 1-64 64 bits X CH 4 DEC: 128 - 1024 100 MHz PCI-X BUS PCI-X TO CH 3 RF 200 MHz PCIe BRIDGE RF In XFORMR 16-bit A/D CH 2 CH 1 PCI-X M x4 PCIe INTERFACE CH 2 DIGITAL U M FIFO 2 I+Q DOWNCONVERTER X CH 4 U RF 200 MHz CH 3 PCI EXPRESS SWITCH XILINX BANK 2: CH 65-128 X RF In 16-bit A/D XFORMR PEX 8648 A CH 4 DEC: 128 - 1024 XC5VLX30T 24 lanes / 6 ports CH 3 24 each configurable CH 1 M Sample as x1/x4/x8/x16 DIGITAL CH 2 U M FIFO 3 Clock In TIMING BUS I+Q DOWNCONVERTER X U CH 3 CROSSBAR GENERATOR BANK 3: CH 129-192 X SWITCH PPS In CH 4 DEC: 128 - 1024 Clock / Sync / 4X 4X 4X 4X Gate / PPS CH 4 TTL Gbit Gbit Gbit Gbit CH 1 M In Serial Serial Serial Serial CH 2 DIGITAL U FIFO 4 M I+Q DOWNCONVERTER X VPX-P1 U CH 3 LVPECL BANK 4: CH 193-256 X Bus CH 4 DEC: 128 - 1024 XTAL OSC VPX BACKPLANE Timing XILINX XC5VSX95T Bus One Park Way ◆ Upper Saddle River ◆ New Jersey 07458 Pentek, Inc. www.pentek.com . . . . Tel: 201 818 5900 ◆ Fax: 201 818 5904 ◆ Email: info pentek.com @ New! New! New! New! New! Model 5351 256-Channel DDC with Four 200 MHz, 16-bit A/Ds - 3U VPX Specifications wideband A/D data or narrowband DDC Front Panel Analog Signal Inputs data, depending on the application. Each of the output FIFOs operates at its Input Type: Transformer-coupled, front panel female SMC connectors own input and output rate to support differ- ent DDC decimation settings between the Transformer Type: Coil Craft WBC4-6TLB banks and efficient block transfers to the Full Scale Input: +8 dBm into 50 ohms PCI bus. 3 dB Passband: 300 kHz to 700 MHz A/D Converters Clocking and Synchronization Type: Texas Instruments ADS5485 The Model 5351 architecture includes a Sampling Rate: 10 MHz to 200 MHz flexible timing and synchronization circuit Internal Clock: 200 MHz crystal osc. for the bank of four A/D converters, External Clock: 10 to 200 MHz allowing the A/Ds to be clocked by internal Resolution: 16 bits or external clock sources and a multiboard A/D Data Reduction Mode: Data from the timing bus. A/Ds can be decimated by any value The timing bus includes a clock, a sync, between 1 and 4096 two gate or trigger signals and a PPS signal. Clock Sources: Selectable from onboard The timing bus can be driven by an internal crystal oscillators, external or LVPECL crystal oscillator, a front panel reference clocks input or the LVPECL bus. External Clock A front panel 26-pin LVPECL Clock/Sync Type: Front panel female SMC connector, connectors allows multiple boards to be sine wave, 0 to +10 dBm, AC- coupled, synchronized. In the slave mode, each accepts 50 ohms differential LVPECL inputs that drive the Sync/Gate Bus: 26-pin connector, clock/ clock, sync, gate and PPS signals for the sync/gate/PPS input/output LVPECL internal timing bus. bus; one gate/trigger and one sync/ In the master mode, the LVPECL bus can PPS input TTL signal drive the timing signals for synchronizing Field Programmable Gate Array multiple bords. Up to three slave 5351’s Processing FPGA: Xilinx Virtex-5 can be driven from each LVPECL bus mas- XC5VSX95T dedicated to digital ter, supporting synchronous sampling and downcoverters and output sync functions across all connected boards. Interface FPGA: Xilinx Virtex-5 More boards can be synchronized with an XC5VLX30T dedicated to the PCI external clock and sync generator. interface PCI to PCIe Interface Fabric-Transparent Crossbar Switch PCI-X Bus: 64-bits, 100 MHz and 64- or The 5351 features a unique high-speed 32-bits at 33 or 66 MHz switching configuration. A fabric-transparent DMA: 4 channel demand-mode and crossbar switch connects the PCI Express chaining controller per PCI bus switch with the VPX-P1 connector using Gigabit Serial I/O gigabit serial data paths with no latency. This VPX-P1: Four 4X ports to Fabric-Trans- allows the user to select the desired output parent Crossbar Switch port on VPX-P1. Programmable signal PCI Express: Six ports to Fabric-Trans- input equalization and output pre-emphasis parent Switch, each configurable as x1, settings on the Crossbar Switch enable x4, x8 or x16 lanes, 24 lanes total optimization. Environmental Operating Temperature: PCI Express Switch Forced-Air Cooled: 0° to 50° C std; Model 5351 includes a PCIe Gen. 2 switch. -20° to 65° C (Level L2) Ordering Information The switch provides a total of 24 PCIe lanes Conduction-Cooled: -40° to 70°C (Level Model Description to the Fabric-Transparent Crossbar Switch L3) on 6 ports. Dynamic lane width negotiation 5351 256-Channel DDC with Storage Temperature: four 200 MHz, 16-bit A/D within the PCIe switch allows for x1, x4, x8 Forced-Air Cooled: -20° to 90° C std; - 3U VPX or x16 widths. These can be selected in any -40° to 100° C (Level L1, L2) Options: combination. Conduction-Cooled: -50° to 100°C (L3) -703 Level L3 Conduction- Relative Humidity: 0 to 95%, non-cond.; Cooled Version 0 to 100% with conformal coating Size: 3.937 in. x 6.717 in. (100 mm x 170.6mm) -731 Two-slot heat sink Contact Pentek for additional available options. One Park Way ◆ Upper Saddle River ◆ New Jersey 07458 Pentek, Inc. www.pentek.com . . . . Tel: 201 818 5900 ◆ Fax: 201 818 5904 ◆ Email: info pentek.com @ Model 5351 256-Channel DDC with Four 200 MHz, 16-bit A/Ds - 3U VPX A/D Performance Spurious Pickup Spurious-Free Dynamic Range ƒ = 70 MHz, ƒ = 200 MHz, Internal Clock ƒ = 200 MHz, Internal Clock in s s Input Frequency Response Two-Tone SFDR ƒ = 200 MHz, Int. Clock ƒ = 30 MHz, ƒ = 70 MHz, ƒ = 200 MHz, Int. Clock s in1 in2 s Adjacent Channel Crosstalk Phase Noise at 70 MHz ƒ = 70 MHz, Α = 0 dBFS, ƒ = 200 MHz, Int. Clock ƒ = 200 MHz, Int. Clock in in s s One Park Way ◆ Upper Saddle River ◆ New Jersey 07458 Pentek, Inc. www.pentek.com . . . . Tel: 201 818 5900 ◆ Fax: 201 818 5904 ◆ Email: info pentek.com @