Model 5350 Quad 200 MHz, 16-bit A/D with Virtex-5 FPGAs - 3U VPX General Information There are two FPGA types on the 5350: Model 5350 is a high-speed data con- processing and interface. The processing FPGA serves as a control and status engine verter suitable for connection as the HF or IF input of a communications system. It features with data and programming interfaces to each of the onboard resources including the four 200 MHz, 16-bit A/Ds. These are sup- A/D converters, DDR2 SDRAM memory, ported by an array of data processing and transport resources ideally matched to require- interface FPGA, programmable LVPECL I/O and clock, gate and synchronization circuits. ments of high-performance systems. The processing FPGA can be populated with The 5350 features built-in support for PCI Express (PCIe) Gen. 2 over the 3U VPX a variety of different FPGAs to match the specific requirements of the processing task. backplane. A unique fabric-transparent Supported FPGAs include: Virtex-5 SX50T, crossbar switch configuration adds gigabit serial data paths for Xilinx Aurora or Serial SX95T, LX50T, LX155T and FX100T. The SXT parts feature between 288 and RapidIO applications. 640 DSP48E Slices and are ideal for demodu- A/D Converter Stage lation/modulation, decoding/encoding, The front end accepts four full scale decryption/encryption, digital delay and channelization of the signals between recep- analog HF or IF inputs on front panel SMC Model 5350 commercial (left) and connectors at +8 dBm into 50 ohms with tion and transmission. For applications conduction-cooled version requiring more FPGA logic cells, the Model transformer coupling into Texas Instruments 5350 can be optionally configured with an ADS5485 200 MHz, 16-bit A/D converters. The digital outputs are delivered into the LX155T in the processing FPGA position for 155,648 logic cells. Virtex-5 FPGA for signal processing or for The interface FPGA provides board con- routing to other board resources. nections including PCI-X or PCI Express, Virtex-5 FPGAs preserving the processing FPGA resources for signal processing. The interface FPGA The Model 5350 architecture includes Features two Virtex-5 FPGAs. All data and control can be configured as an LXT or an SXT ■ Complete software radio family part, providing not only interface paths are accessible by the FPGAs, enabling interface solution for 3U VPX functionality, but processing resources up factory installed functions including data systems multiplexing, channel selection, data pack- to an additional 640 DSP48E Slices. ■ Supports Gigabit Serial Option -104 provides general purpose ing, gating, triggering and SDRAM memory Fabrics including PCI I/O to VPX-P2 with 16 pairs of LVDS con- control. In addition, users can install their Express, Serial RapidIO own custom IP for data processing. Pentek nections to the processing FPGA, and 16 and Xilinx Aurora pairs of LVDS connections to the interface GateFlow FPGA Design Kits facilitate ■ Four 200 MHz 16-bit A/Ds FPGA for custom I/O. integration of user-created IP. ➤ ■ Up to 1 GB of DDR2 RF In RF In RF In RF In SDRAM ■ Two Xilinx Virtex-5 FPGAs RF RF RF RF XFORMR XFORMR XFORMR XFORMR Sample Clk In ■ Up to 2.56 seconds of data TIMING BUS PPS In GENERATOR Clock/Sync Bus 200 MHz 200 MHz 200 MHz 200 MHz capture at 200 MHz 16-bit A/D 16-bit A/D 16-bit A/D 16-bit A/D Clock / Sync / TTL Gate / PPS ■ LVPECL clock/sync bus for In To All multiboard synchronization Sections PROCESSING FPGA LVPECL VIRTEX-5 LX50T, SX50T, SX95T, LX155T or FX100T Control/ Bus GTP GTP GTP LVDS ■ Up to 32 pairs of LVDS Status XTL 32 32 8 connections to the Virtex-5 OSC 4X 4X 4X 64 Timing DDR2 DDR2 FLASH SDRAM FPGAs for custom I/O Bus SDRAM 32 MB 512 MB 512 MB GTP INTERFACE FPGA ■ 3U VPX form factor provides VIRTEX-5 LX30T or SX50T GTP PCI-X LVDS a compact, rugged platform 32 PCI-X BUS 1 4X 64 ■ Compatible with several (64 Bits, 100 MHz) 32 VITA standards including: PCI-X TO XMC - P15 PMC - P14 PCIe BRIDGE VITA-46 (VPX Baseline 4X 4X x4 PCIe Standard) PCI EXPRESS SWITCH PEX 8648 VITA-48 (VPX REDI) TM 24 lanes / 6 ports VITA-65 (OpenVPX 24 each configurable as x1/x4/x8/x16 64 System Specification) CROSSBAR SWITCH ■ Ruggedized and conduction- 4X 4X 4X 4X cooled versions available Gbit Gbit Gbit Gbit Serial Serial Serial Serial VPX-P1 VPX-P2 VPX BACKPLANE One Park Way ◆ Upper Saddle River ◆ New Jersey 07458 Pentek, Inc. www.pentek.com . . . . Tel: 201 818 5900 ◆ Fax: 201 818 5904 ◆ Email: info pentek.com @ New! New! New! New! New! Model 5350 Quad 200 MHz, 16-bit A/D with Virtex-5 FPGAs - 3U VPX Clocking and Synchronization Specifications The Model 5350 architecture includes a Front Panel Analog Signal Inputs flexible timing and synchronization circuit Input Type: Transformer-coupled, front for each bank of four A/D converters, panel female SMC connectors allowing the A/Ds to be clocked by internal Transformer Type: Coil Craft or external clock sources and a multiboard WBC4-6TLB timing bus. Full Scale Input: +8 dBm into 50 ohms Each timing bus includes a clock, a sync, 3 dB Passband: 300 kHz to 700 MHz two gate or trigger signals and a PPS signal. A/D Converters The timing bus can be driven by an internal Type: Texas Instruments ADS5485 crystal oscillator, a front panel reference Sampling Rate: 10 MHz to 200 MHz input or the LVPECL bus. Internal Clock: 200 MHz crystal osc. A front panel 26-pin LVPECL Clock/Sync External Clock: 10 to 200 MHz connector allows multiple boards to be syn- Resolution: 16 bits chronized. In the slave mode, each accepts A/D Data Reduction Mode: Data from the differential LVPECL inputs that drive the A/Ds can be decimated by any value clock, sync, gate and PPS signals for the between 1 and 4096 internal timing bus. Clock Sources: Selectable from onboard crys- In the master mode, the LVPECL bus can tal oscillators, external or LVPECL clocks drive the timing signals for synchronizing External Clock multiple boards. Up to three slave 5350s can Type: Front panel female SMC connector, be driven from the LVPECL bus master, sine wave, 0 to +10 dBm, AC- coupled, supporting synchronous sampling and 50 ohms sync functions across all connected boards. Sync/Gate Bus: 26-pin connector, clock/ More boards can be synchronized with an sync/gate/PPS input/output LVPECL external clock and sync generator. bus; one gate/trigger and one sync/ PPS input TTL signal Memory Resources Field Programmable Gate Array Up to two independent 512 MB banks Processing FPGA: Xilinx Virtex-5 of DDR2 SDRAM are available to the XC5VSX50T standard; XC5VLX50T, processing FPGA. Built-in memory functions XC5VSX95T, XC5VLX155T or include an A/D data transient capture XC5VFX100T, optional mode with pre- and post-triggering. Each Interface FPGA: Xilinx Virtex-5 memory bank can be easily accessed through XC5VLX30T std.; XC5VSX50T optional the PCI interface using the on-board DMA Custom I/O controllers. Option -104: Provides GPIO to VPX-P2 Custom user-installed functions within with 16 LVDS pairs to processing FPGA the FPGA can take advantage of all three (SX95T, LX155T or FX100T only) and 16 banks to support various applications. pairs to interface FPGA Memory Fabric-Transparent Crossbar Switch DDR2 SDRAM: Up to 1 GB in two banks The 5350 features a unique high-speed PCI to PCIe Interface switching configuration. A fabric-transpar- PCI-X Bus: 64-bits, 100 MHz and 64- or ent crossbar switch bridges numerous 32-bits at 33 or 66 MHz interfaces and components on the board DMA: 4 channel demand-mode and using gigabit serial data paths with no latency. chaining controller per PCI bus Ordering Information Programmable signal input equalization Gigabit Serial I/O: and output pre-emphasis settings enable Processing FPGA: Two 4X ports to Fab- Model Description optimization. Data paths can be selected as ric-Transparent Switch; one can be 5350 Quad 200 MHz, 16-bit A/D single (x1) lanes, or groups of four lanes (x4). alternately routed to interface FPGA with Virtex-5 FPGAs - 3U VPX VPX-P1: Four 4X ports to Fabric-Trans- PCI Express Switch parent Crossbar Switch Options: Model 5350 includes a PCIe Gen. 2 PCI Express: Six ports to Fabric-Trans- -104 FPGA I/O to VPX-P2 switch. The switch provides a total of 24 parent Switch, each configurable as x1, -5xx Gigabit Serial I/O to VPX- PCIe lanes to the Fabric-Transparent Cross- x4, x8 or x16 lanes, 24 lanes total P1- four full duplex 4X bar Switch on 6 ports. Dynamic lane width Environmental paths negotiation within the PCIe switch allows Operating Temperature: -703 Level L3 Conduction- for x1, x4, x8 or x16 widths. These can be Forced-Air Cooled: 0° to 50° C std; Cooled Version selected in any combination. -20° to 65° C (Level L2) Conduction-Cooled: -40° to 70° C (Level L3) Contact Pentek for additional Size: 3.937 in. x 6.717 in. (100 mm x 170.6 mm) available options. One Park Way ◆ Upper Saddle River ◆ New Jersey 07458 Pentek, Inc. www.pentek.com . . . . Tel: 201 818 5900 ◆ Fax: 201 818 5904 ◆ Email: info pentek.com @ Model 5350 Quad 200 MHz, 16-bit A/D with Virtex-5 FPGAs - 3U VPX A/D Performance Spurious Pickup Spurious-Free Dynamic Range ƒ = 70 MHz, ƒ = 200 MHz, Internal Clock ƒ = 200 MHz, Internal Clock in s s Input Frequency Response Two-Tone SFDR ƒ = 200 MHz, Int. Clock ƒ = 30 MHz, ƒ = 70 MHz, ƒ = 200 MHz, Int. Clock s in1 in2 s Adjacent Channel Crosstalk Phase Noise at 70 MHz ƒ = 70 MHz, Α = 0 dBFS, ƒ = 200 MHz, Int. Clock ƒ = 200 MHz, Int. Clock in in s s One Park Way ◆ Upper Saddle River ◆ New Jersey 07458 Pentek, Inc. www.pentek.com . . . . Tel: 201 818 5900 ◆ Fax: 201 818 5904 ◆ Email: info pentek.com @