Model 5342-428 GateFlow Transceiver with Four Multiband DDCs and Installed Core Interpolation Filter - 3U VPX General Information FIR filters. Each filter is capable of any deci- Model 5342-428 is a software radio trans- mation from 2 to 256. The decimations of the first stage filter and the second stage ceiver suitable for connection to HF or IF Model 7140-420 ports of a communications system. It features filter multiply to yield overall decimation Installed Core factors up to 65,536. The second stage FIR two A/D and two D/A converters with may be bypassed for decimations of 256 or built-in support for PCI Express (PCIe) Gen. 2 over the 3U VPX backplane. A unique lower. The decimation of each DDC can be set independently. After each filter stage is fabric-transparent crossbar switch bridges a post filter gain stage. This gain is prima- numerous interfaces and components on the board with no latency. rily used to compensate for bit growth in the filter at different decimations but may A/D and D/A Converter Stages also be used to amplify small signals after The front end accepts four full scale out of band signals have been filtered out. The NCO provides over 108 dB spuri- analog HF or IF inputs on front panel MMCX ous-free dynamic range (SFDR). The FIR connectors at +10 dBm into 50 ohms with transformer coupling into Linear Technology filter is capable of storing and utilizing two independent sets of 18-bit coefficients. LTC2255 14-bit 125 MHz A/D converters. These coefficients are user-programmable The digital outputs are delivered to the Virtex-4 FPGA for signal processing or for using RAM structures within the FPGA. NCO tuning frequency, decimation and routing to other board resources. filter coefficients can be changed dynamically. A TI DAC5686 digital upconverter (DUC) and D/A accepts a baseband real or complex Four identical Core 428 DDCs are factory Features installed in the 5342-428 FPGA. An input data stream from the FPGA with signal band- ■ Complete software radio multiplexer allows any DDC to indepen- widths up to 40 MHz. interface solution When operating as an upconverter, it dently select any of the four A/D sources. The overal decimation range from 2 to ■ 3U VPX form factor interpolates and translates real or complex 65,536, programmable in steps of 1, provides baseband input signals to any IF center fre- ■ GateFlow IP Core 428, with quency between DC and 160 MHz. It delivers output bandwidths from 50 MHz down to four high-performance 1.52 kHz for an A/D sampling rate of real or quadrature (I+Q) analog output multiband DDCs and one 125 MHz and assuming an 80% filter. samples at up to 320 MHz to the 16-bit D/A Interpolation Filter, factory- converter. Output is through a front panel installed Core 428 Interpolation Filter MMCX connector at +4 dBm into 50 ohms. ■ Two sets of 18-bit user- The Core 428 interpolation filter increases If translation is disabled, the DAC5686 programmable FIR filter acts as an interpolating 16-bit D/A with out- the sampling rate of real or complex base- coefficients band signals by a factor of 16 to 2048, put sampling rates up to 500 MHz. ■ Decimation range from 2 to programmable in steps of 4, and relieves 65,536 in steps of 1 Core 428 Multiband DDCs the host processor from performing ■ Interpolation range from 2 to The Core 428 downconverter translates upsampling tasks. The interpolation filter 32,768 in steps of 4 can be used in series with the DUC’s built- any frequency band within the input band- ■ LVDS clock/sync bus for width range down to zero frequency. The in interpolation, creating a maximum multiboard synchronization interpolation factor of 32,768. DDCs consist of two cascaded decimating ➤ LTC2255 CH A RF A/D A 256 MB 125 MHz RF In XFORMR DDR2 SDRAM A/D B 14-bit A/D MEMORY A/D C CONTROL 256 MB A/D D & LTC2255 DDR2 SDRAM CH B RF D/A DATA ROUTING A/D A 125 MHz RF In XFORMR 14-bit A/D A/D B DIGITAL DIGITAL M 256 MB DOWNCONVTER A DOWNCONVTER A U DDR2 SDRAM A/D C STAGE 1 STAGE 2 X LTC2255 A/D D DEC: 2 - 256 DEC: 1 - 256 CH C RF MEM W 125 MHz A/D A RF In XFORMR FIFO PCI 2.2 14-bit A/D A/D B DIGITAL DIGITAL INTERFACE M MEM R DOWNCONVTER B DOWNCONVTER B U A/D C FIFO LTC2255 STAGE 1 STAGE 2 CH D X A/D A RF PCI-BUS A/D D DEC: 2 - 256 DEC: 1 - 256 125 MHz A/D A RF In XFORMR MUX 64 Bits/66 MHz DDC A A 14-bit A/D A/D A FIFO A/D B A/D B DIGITAL DIGITAL PCI TO M A/D B MUX DOWNCONVTER C DOWNCONVTER C DDC B PCIe BRIDGE U A/D C FIFO Sample STAGE 1 STAGE 2 X A/D C A/D D DEC: 2 - 256 DEC: 1 - 256 A/D C Clock In XTAL MUX x4 PCIe DDC C CLOCK & OSC A FIFO A/D A SYNC A/D D Clock/Sync A/D B DIGITAL DIGITAL PCI EXPRESS SWITCH A/D D M GENERATOR XTAL MUX Bus DOWNCONVTER D DOWNCONVTER D DDC D U FIFO PEX 8648 A/D C OSC B STAGE 1 STAGE 2 X A/D D DEC: 2 - 256 DEC: 1 - 256 USER IN 24 lanes / 6 ports FIFO 24 each configurable TOTAL DECIMATION: 2 - 65536 USER OUT as x1/x4/x8/x16 FIFO CROSSBAR 16-BIT DAC5686 MEMORY RF SWITCH RF Out 500 MHz DIGITAL CIC CFIR MUX XFORMR D/A FIFO D/A FILTER FILTER D/A UPCONVERTER FIFO 4X 4X 4X 4X Gbit Gbit Gbit Gbit INTERPOLATION: 16 - 2048 Serial Serial Serial Serial VPX-P1 XILINX XC4VSX55 FPGA WITH GATEFLOW FACTORY INSTALLED CORE 428 VPX BACKPLANE One Park Way ◆ Upper Saddle River ◆ New Jersey 07458 Pentek, Inc. www.pentek.com . . . . Tel: 201 818 5900 ◆ Fax: 201 818 5904 ◆ Email: info pentek.com @ New! New! New! New! New! Model 5342-428 GateFlow Transceiver with Four Multiband DDCs and Installed Core Interpolation Filter - 3U VPX Clocking and Synchronization Specifications Two independent internal timing buses Front Panel Analog Signal Inputs can provide either a single clock or two Input Type: Transformer-coupled, front different clock rates for the input and panel female MMCX connectors output signals. Transformer Type: Coil Craft Each timing bus includes a clock, a sync, WBC1-1TLB and a gate or trigger signal. Signals from Full Scale Input: +10 dBm into 50 ohms either Timing Bus A or B can be selected as 3 dB Passband: 250 kHz to 300 MHz the timing source for the A/Ds, the downcon- A/D Converters verters, the upconverters and the D/As. Type: Linear Technology LTC2255 Two external reference clocks are accepted, Sampling Rate: 1 MHz to 125 MHz one for each timing bus and two internal Internal Clock: 125 MHzcrystal oscillator clocks may be used for each timing bus. External Clock: 1 to 125 MHz Front panel 26-pin LVDS Clock/Sync Resolution: 14 bits connectors allow multiple boards to be syn- A/D Data Reduction Mode: Data from chronized. In the slave mode, they accept the A/Ds can be written directly into the differential LVDS inputs that drive the clock, FPGAs at a rate equal to A/D clock deci- sync and gate signals for the two internal mated by any value between 1 and 4096 timing buses. Front Panel Analog Signal Output In the master mode, the LVDS bus can Output Type: Transformer-coupled, drive one or both sets of timing signals front panel female MMCX connectors from the two internal timing buses for Full Scale Output: +4 dBm into 50 ohms synchronizing multiple boards. 3 dB Passband: 60 kHz to 300 MHz Up to seven slave 5342-428’s can be driven Digital Upconverter from the LVDS bus master, supporting syn- Type: TI DAC5686 chronous sampling and sync functions Input Bandwidth: 40 MHz, max. across all connected boards. Output IF: DC to 160 MHz Output Signal: Analog, real or quadrature Memory Resources Sampling Rate: 320 MHz, max; 500 MHz Three independent banks of SDRAM max. with upconversion disabled are available. Built-in memory functions in- Resolution: 16 bits clude an A/D data transient capture mode Clock Sources: Selectable from onboard A or B with pre- and post-triggering; a D/A wave- crystal oscillators, external or LVDS clocks form generator mode; and an A/D data External Clock delay mode for applications like tracking Type: Front panel female MMCX connec- receivers. User-installed functions within tor, sine wave, 0 to +10 dBm, AC- coupled, the FPGA can take advantage of the 50 ohms SDRAM for many other purposes. Sync/Gate Bus: 26-pin connector, dual clock/sync/gate input/output LVDS Fabric-Transparent Crossbar Switch buses; one sync/gate input TTL signal The 5342-428 features a unique high-speed Field Programmable Gate Arrays switching configuration. A fabric-transparent Type: Xilinx Virtex-4 XC4VSX55 and crossbar switch connects the PCI Express Xilinx Virtex-4 XC4VFX60 switch with the VPX-P1 connector using Memory gigabit serial data paths with no latency. This DDR2 SDRAM: 768 MB in three banks allows the user to select the desired output of 256 MB each port on VPX-P1. Programmable signal PCI to PCIe Interface input equalization and output pre-emphasis PCI Bus: 64-bit, 66 MHz settings on the Crossbar Switch enable DMA: 9 channel demand-mode and optimization. chaining controller Gigabit Serial I/O PCI Express Switch VPX-P1: Four 4X ports to Fabric-Trans- Ordering Information Model 5342-428 includes a PCIe Gen. 2 parent Crossbar Switch Model Description switch. The switch provides a total of 24 PCI Express: Six ports to Fabric-Trans- 5342-428 GateFlow Transceiver PCIe lanes to the Fabric-Transparent Cross- parent Switch, each configurable as x1, with four Multiband DDCs bar Switch on 6 ports. Dynamic lane width x4, x8 or x16 lanes, 24 lanes total and one Interpolation negotiation within the PCIe switch allows Environmental (Commercial version) Filter factory-installed - for x1, x4, x8 or x16 widths. These can be Operating Temp: 0° to 50° C 3U VPX selected in any combination. Storage Temp: –20° to 90° C Relative Humidity: 0 to 95%, non-cond. Contact Pentek for available Size: 3.937 in. x 6.717 in. (100 mm x 170.6 mm) options One Park Way ◆ Upper Saddle River ◆ New Jersey 07458 Pentek, Inc. www.pentek.com . . . . Tel: 201 818 5900 ◆ Fax: 201 818 5904 ◆ Email: info pentek.com @