VMIVME-7487 486 PC/AT VMEbus CPU Dual-Port Memory • 100 percent PC/AT-compatible processor board on VMEbus • High performance — Available in 66 or 100 MHz CPU clock speeds • Single slot 6U size • Coprocessor and 8 Kbyte four-way set associative cache-on-chip (16 Kbyte on DX4 option) • Up to 16 Mbyte dual-ported DRAM • Super VGA 1,024 x 768 noninterlaced resolution with 1 Mbyte video DRAM on-board • One parallel centronics port • Two serial RS-232C ports • PC/AT keyboard interface • Real-time clock with on-board battery • Floppy and IDE controllers on-board • Front panel reset button and small speaker included • Industry-standard gate array technology offers full VMEbus functionality • Interrupt handler, interrupter, and system controller • Access all VMEbus memory in real or protected modes • Three-way byte-swapping hardware for little-endian and big-endian type interfacing in both master and slave modes • Software drivers for DOS and real-time UNIX Resolutions of 800 x 600 256-color and 1,024 x 768 • Diskless operation with optional flash mezzanine board • Ethernet adapter available 16-color in interlaced and noninterlaced modes are supported. MICROPROCESSOR — High performance is achieved by the use of Intel’s industry-standard 80486DX2 FLOPPY AND IDE CONTROLLERS — The 66 MHz 32-bit CPU. For even higher performance, the VMIVME-7487 incorporates both Floppy and IDE VMIVME-7487 can also be ordered with the 80486DX4 Controllers on-board supporting all standard PC/AT drives (100 MHz) CPU. The on-chip cache ensures true and formats. zero-wait-state operation with hit ratios exceeding 90 percent. For intensive mathematical calculations, the The VMIVME-7487 provides industry-standard 80486DX models incorporate a high-performance math interfaces to the VMIVME-7450 which is a dual-slot board coprocessor on-chip. Complete software compatibility is containing one 3.5-in floppy and one 3.5-in hard drive. The ensured with all PC/AT software which supports Intel’s VMIVME-7450 does not contain any electronics and draws family of math chips. power only from P1. MEMORY — The VMIVME-7487 accepts one bank of 32-bit wide DRAMs with a total maximum capacity of 16 Mbyte. Page mode offers nearly zero-wait-state system performance during burst cache refill mode. Ordering Options Jan. 3, 1996 800-007487-000 C ABC – D E F Memory above 640 Kbyte can be configured as VMIVME-7487 – – Extended, Expanded LIM 4.0, and System and Video BIOS A = Memory Size Shadow for improved performance. 0 = 1 Mbyte 1 = 4 Mbyte 2 = 16 Mbyte The on-board DRAM is dual-ported to the VMEbus. A 5 = 1 Mbyte with VME64 set of registers enable the dual-port feature of the board as 6 = 4 Mbyte with VME64 well as the VMEbus base address (A32 or A24), and the size 7 = 16 Mbyte with VME64 B = Mezzanine Options of the memory “window” accessible from the VMEbus, 0 = None (64 Kbyte increments up to 16 Mbyte). 2 = Ethernet 3 = Flash Disk C = CPU Selection EPROM — There is a total of 128 Kbyte of EPROM 0 = Reserved 1 = Reserved space on the board for the BIOS. Nonvolatile memory 2 = 66 MHz 486DX2 expansion is supported by the Flash Mezzanine Option. 3 = Reserved 4 = Reserved 5 = 100 MHz 486DX4 SUPER VGA CONTROLLER — The Video interface For Ordering Information, Call: controller of the VMIVME-7487 is included on the main 1-800-322-3616 or 1-256-880-0444 • FAX (256) 882-0859 board with 1 Mbyte DRAM standard. No additional E-mail: info@vmic.com Web Address: www.vmic.com Copyright © June 1993 by VMIC mezzanine boards or VMEbus slots are required. Specifications subject to change without notice. VMIC • 12090 South Memorial Parkway • Huntsville, Alabama 35803-3308 1 VMIVME-7487 E0000H. VMEbus A31 to A24 are driven from the extended Ethernet CONTROLLER — The Ethernet Adapter is address page register. VMEbus A23 to A16 are driven from a small plug-in board compatible with the Novell NE-2000. the standard address page register which is only activated The 10BASE-T and Thinnet Transceivers are sold separately. when in real mode. FLASH MEZZANINE — The Flash Mezzanine is a VMEbus SLAVE INTERFACE — small plug-in board containing 2 Mbyte of flash memory. The Memory Access user may erase and program the flash disk with MS-DOS® SAD032:SD32:SBLT32:SBLT64 (Option) and embedded software. With the custom BIOS supplied with A32:A24:A16:D32:D16:08 (EO): BLT32) the Flash Mezzanine Option, the VMIVME-7487 may be (BLT64 when VME64 option is ordered) configured for diskless operation. The VMIVME-7487 slave interface provides access to the on-board DRAM as well as to mailbox registers which are SERIAL AND PARALLEL PORTS — Two serial and used for communication between VMEbus and the 80486 one Centronics ports are available and accessible through the microprocessor. front panel. Both serial ports support an asynchronous RS-232C interface. The interface allows access to the on-board DRAM. The amount (window size) of DRAM accessible from the KEYBOARD CONTROLLER AND REAL-TIME VMEbus is programmable in increments of 64 Kbyte up to CLOCK — The VMIVME-7487 has an on-board PS/2 16 Mbyte. Keyboard Controller and a compatible connector accessible from the front panel. The on-board real-time clock is fully MAILBOX ACCESS — Access to mailbox registers is PC/AT compatible. provided using A16/D8(O) VMEbus accesses only. RESET SWITCH AND ANNUNCIATORS — A small MAILBOXES — The VMIVME-7487 provides four push-button switch on the front panel will reset the mailboxes which are accessible from both the 80486 and the VMIVME-7487. If the System Controller is also enabled, a VMEbus providing interprocessor communication. The SYSRESET* will also be generated on the VMEbus. mailboxes have the ability to interrupt the 80486 when accessed by VMEbus. Three LEDs are also visible on the front panel. A green LED is tied to the +5 V power, a red LED indicates the status VMEbus REQUESTER — The VMIVME-7487 of user software, and a yellow LED is illuminated during hard allows the 80486 to request and gain control of the bus using disk accesses. any of the VMEbus request lines, (BR3*-BR0*), under software control. The requester can be programmed to A small speaker is also included on the VMIVME-7487 operate in any of the following modes: to provide compatibility with the PC/AT internal speaker function. Release-On-Request (ROR) VMEbus MASTER INTERFACE — Release-When-Done (RWD) MA32:MBLT32:MBLT64 (Option) Release-On-Clear (ROC) (A32:A24:A16:D32:D16:D8 (EO):BLT32) VMEbus Capture and Hold (BCAP) (BLT64 when VME64 option is ordered) INTERRUPT HANDLER — The VMIVME-7487 When the 80486 microprocessor is in protected mode, incorporates an Interrupt Handler which monitors all the VMEbus is accessed using a 16 Mbyte window. VMEbus VMEbus IRQ* lines. The handler can be programmed to address A31 to A24 are driven from the extended address respond to interrupts on any or all of the IRQ* inputs. 8-bit page register. 80486 address signals A31 to A24 are decoded to provide 16 unique 16 Mbyte regions. Each region All normal-process VMEbus-related interrupts are generates a unique address modifier code for the desired connected to the IRQ11 and IRQ12 PC/AT interrupt. These address width (A32/A24/A16) and access type (supervisory include: or nonprivileged, code or data). The 80486 address decode also allows user-defined address modifier codes to be output Mailbox interrupts when accessing a specific 16 Mbyte region. VMEbus interrupts VMEbus interrupter IACK cycle (acknowledgment of When the 80486 microprocessor is operating in real VMIVME-7487 VMEbus-issued interrupts) . mode, the VMEbus is accessed using a 64 Kbyte window at 2 For Ordering Information, Call: 1-800-322-3616 or 1-256-880-0444 • FAX (256) 882-0859 VMIVME-7487 All error processing VMEbus-related interrupts are The byte swapping hardware provides independent byte connected to the PC/AT NMI interrupt. These include: swapping for both the Master and Slave interface. Both Master and Slave interface byte swapping is programmed ACFAIL* interrupt under 80486 software control. BERR* interrupt SYSFAIL* interrupt SOFTWARE — The VMIVME-7487 is 100 percent PC/AT compatible and in addition to MS-DOS it can run Software NMI Microsoft Windows in Enhanced mode, DR-DOS, OS/2, O/S 9000, SCO Xenix, UNIX, and other operating systems. Each interrupt source can be programmed with a unique vector. This allows both the non-NMI and NMI interrupt VMIC’s VMEaccess™ and IOWorks Access™ service routine to simply read an interrupt acknowledge software are sets of development tools and run-time software register. The returned ID will correspond to the highest which support the management of VMEbus functions in priority interrupt pending. applications containing any of VMIC’s CPU modules. INTERRUPTER — The VMIVME-7487 can issue SPECIFICATIONS interrupts on any or all of the seven VMEbus interrupt lines (IRQ7* to IRQ1*) under program control. An ID Register is associated with each interrupt line. During the interrupt 6U double Eurocard format, single slot acknowledge cycle, the interrupter issues the ID associated Height 9.2 in (233.4 mm) with the IRQ* being acknowledged. Depth 6.3 in (160 mm) Thickness 0.8 in (20.3 mm) The interrupter also provides an interrupt acknowledge ID Register that can be programmed with a unique ID to Power Requirements: allow interrupt processing software to know when a specific +5 VDC (±5 percent), 3.0 A (typical), 4 A maximum interrupt has been acknowledged by the VMEbus interrupt handler. +12 VDC (±5 percent), 25 mA (typical), 50 mA maximum SYSTEM CONTROLLER — The on-board VMEbus System Controller allows the board to work at slot 1, or it may -12 VDC (±5 percent), 25 mA (typical), 50 mA be disabled when another board is acting as the system maximum controller. Note: The currents at +12 and -12 VDC are specified The System Controller can be programmed under with the serial connectors open. software control to provide the following modes of arbitration: Operating Temperature: 0 to 55 °C Forced air cooling required Round Robin (RRS) Single Level (SGL) Relative Humidity: 10 to 90 percent, noncondensing Priority (PRI) VMEbus Interface: The System Controller provides a SYSCLK driver, DTB Master: BLT32 (BLT 64 with VME64 option) IACK* Daisy-Chain Driver, and a VMEbus Access Time-Out A32/D32, A24/D32, A16/D32 Timer. The SYSTEM controller also provides an arbitration DTB Slave: BLT32 (BLT 64 with VME64 option) time-out if BBSY* is not seen within 10 ms after a BGOUT* A32/D32, A24/D32 DRAM signal is issued. access DTB Slave: A16/D8(O) BYTE SWAPPING — The Intel 80x86 family of Interprocessor communication processors use little-endian format. To accommodate other Requester: Programmable, BR(3-0), ROR, VMEbus modules which transfer data in big-endian format, RWD, BCAP, ROC such as the 680x0 processor family, the VMIVME-7487 Interrupt Handler: IH(1 to 7) D8(O) incorporates Byte Swapping hardware. Interrupter: Programmable, IRQ7* to IRQ1* VMIC • 12090 South Memorial Parkway • Huntsville, Alabama 35803-3308 3 VMIVME-7487 Arbiter: SGL, PRI, RRS TRADEMARKS BTO: 10 µs Compliance: Rev. C.1 VMEaccess and IOWorks Access are trademarks and the VMIC logo is a registered trademark of VMIC. MS-DOS is a registered trademark of Microsoft Corporation. Other registered trademarks are the property of their respective owners. 4 For Ordering Information, Call: 1-800-322-3616 or 1-256-880-0444 • FAX (256) 882-0859