W83977EF/CTF WINBOND I/O W83977EF/CTF Data Sheet Revision History Version Pages Dates Version Main Contents on Web 1N.A. 4, 7, 49, 50, 53, 2 Parallel port pin description 3 4Wake-Up and ACPI function. 5 6 7 8 9 Please note that all data and specifications are subject to change without notice. All the trade marks LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Winbond for any damages resulting from such improper use or sales. sheet belong to their respective owners.of products and companies mentioned in this data 10 A1 0.50 11/09/981, 2, 8, 83, 116 Typo correction. 0.4309/07/98119, 120 Explanation of Keyboard/Mouse correction 0.4208/17/9814, 15, 16 55, 90, 91 0.41 06/16/98 Data correction For Beta Site customers only 0.4006/01/98 First published. W83977EF/ CTF PRELIMINARY Table of Contents- GENERAL DESCRIPTION..........................................................................................1 FEATURES.................................................................................................................2 PIN CONFIGURATION ...............................................................................................5 1.0 PIN DESCRIPTION.....................................................................................................................6 1.1 HOST INTERFACE......................................................................................................................6 1.2 GENERAL PURPOSE I/O PORT.................................................................................................8 1.3 SERIAL PORT INTERFACE........................................................................................................9 ............................................................................................................ ............................................................................................... ...................................................................................................................... ...................................................................................................................... 1.8 POWER PINS............................................................................................................................ 1.9 ACPI INTERFACE..................................................................................................................... 2.0 FDC FUNCTIONAL DESCRIPTION ...................................................................19 2.1 W83977EF/CTF FDC................................................................................................................. 2.1.1 AT interface ......................................................................................................................... 19 2.1.2 FIFO (Data) ......................................................................................................................... 19 2.1.3 Data Separator .................................................................................................................... 20 2.1.4 Write Precompensation........................................................................................................ 20 2.1.5 Perpendicular Recording Mode ............................................................................................ 21 2.1.6 FDC Core ............................................................................................................................ 21 2.1.7 FDC Commands.................................................................................................................. 21 2.2 REGISTER DESCRIPTIONS..................................................................................................... 2.2.1 Status Register A (SA Register) (Read base address + 0) ................................................... 33 Publication Release Date: March 1999 -I - Revision A1 33 19 18 18 181.7 KBC INTERFACE 161.6 FDC INTERFACE 111.5 MULTI-MODE PARALLEL PORT 101.4 INFRARED INTERFACE W83977EF/ CTF PRELIMINARY 2.2.2 Status Register B (SB Register) (Read base address + 1) ................................................... 35 2.2.3 Digital Output Register (DO Register) (Write base address + 2) ........................................... 37 2.2.4 Tape Drive Register (TD Register) (Read base address + 3)................................................ 37 2.2.5 Main Status Register (MS Register) (Read base address + 4).............................................. 38 2.2.6 Data Rate Register (DR Register) (Write base address + 4)................................................. 38 2.2.7 FIFO Register (R/W base address + 5)................................................................................ 40 2.2.8 Digital Input Register (DI Register) (Read base address + 7)................................................ 42 2.2.9 Configuration Control Register (CC Register) (Write base address + 7)................................ 43 3.0 UART PORT .......................................................................................................45 .................... ............................................................................................................... 3.2.1 UART Control Register (UCR) (Read/Write)......................................................................... 45 3.2.2 UART Status Register (USR) (Read/Write) .......................................................................... 47 3.2.3 Handshake Control Register (HCR) (Read/Write)................................................................. 48 3.2.4 Handshake Status Register (HSR) (Read/Write) .................................................................. 49 3.2.5 UART FIFO Control Register (UFR) (Write only).................................................................. 50 3.2.6 Interrupt Status Register (ISR) (Read only) .......................................................................... 51 3.2.7 Interrupt Control Register (ICR) (Read/Write)....................................................................... 52 3.2.8 Programmable Baud Generator (BLL/BHL) (Read/Write) ..................................................... 52 3.2.9 User-defined Register (UDR) (Read/Write)........................................................................... 53 4.0 INFRARED (IR) PORTS......................................................................................54 4.1 IR PORT.................................................................................................................................... 4.2 CIR PORT(FOR W83977CTF ONLY)........................................................................................ 4.2.1 Bank0.Reg0 - Receiver Buffer Registers (RBR) (Read)........................................................ 54 4.2.2 Bank0.Reg1 - Interrupt Control Register (ICR) ..................................................................... 54 4.2.3 Bank0.Reg2 - Interrupt Status Register (ISR)....................................................................... 55 4.2.4 Bank0~3.Reg3 - CIR Control Register 0/Bank Select Register (CTR0/BSR) (BANK0~3)...... 56 4.2.5 Bank0.Reg4 - CIR Control Register (CTR) ........................................................................... 57 4.2.6 Bank0.Reg5 - UART Line Status Register (USR) ................................................................ 58 Publication Release Date: March 1999 -II - Revision A1 54 54 453.2 REGISTER ADDRESS 453.1 UNIVERSAL ASYNCHRONOUS RECEIVER/TRANSMITTER (UART A, UART B) W83977EF/ CTF PRELIMINARY 4.2.7 Bank0.Reg6 - Remote Infrared Config Register (RIR_CFG) ................................................. 58 4.2.8 Bank0.Reg7 - User Defined Register (UDR/AUDR).............................................................. 59 4.2.9 Bank1.Reg0~1 - Baud Rate Divisor Latch (BLL/BHL)........................................................... 60 4.2.10 Bank1.Reg2 - Version ID Regiister I (VID).......................................................................... 61 4.2.11 Bank0~3.Reg3 - CIR Control Register 0/Bank Select Register (CTR0/BSR) (BANK0~3).... 61 4.2.12 Bank1.Reg4 - Timer Low Byte Register (TMRL)................................................................. 61 4.2.13 Bank1.Reg5 - Timer High Byte Register (TMRH) ............................................................... 61 ........................................................................................ 5.0 PARALLEL PORT .............................................................................................63 5.1 PRINTER INTERFACE LOGIC.................................................................................................. ....................................................................................... 5.2.1 Data Swapper..................................................................................................................... 65 5.2.2 Printer Status Buffer ............................................................................................................ 65 5.2.3 Printer Control Latch and Printer Control Swapper .............................................................. 66 5.2.4 EPP Address Port................................................................................................................ 66 5.2.5 EPP Data Port 0-3 ............................................................................................................... 67 5.2.6 Bit Map of Parallel Port and EPP Registers.......................................................................... 67 5.2.7 EPP Pin Descriptions.......................................................................................................... 68 5.2.8 EPP Operation..................................................................................................................... 68 .............................................................. 5.3.1 ECP Register and Mode Definitions ..................................................................................... 69 5.3.2 Data and ecpAFifo Port........................................................................................................ 70 5.3.3 Device Status Register (DSR)............................................................................................. 70 5.3.4 Device Control Register (DCR) ............................................................................................ 71 5.3.5 cFifo (Parallel Port Data FIFO) Mode = 010 ....................................................................... 72 5.3.6 ecpDFifo (ECP Data FIFO) Mode = 011............................................................................... 72 5.3.7 tFifo (Test FIFO Mode) Mode = 110.................................................................................... 72 5.3.8 cnfgA (Configuration Register A) Mode = 111 ..................................................................... 72 5.3.9 cnfgB (Configuration Register B) Mode = 111 .................................................................... 72 5.3.10 ecr (Extended Control Register) Mode = all....................................................................... 73 Publication Release Date: March 1999 -III - Revision A1 695.3 EXTENDED CAPABILITIES PARALLEL (ECP) PORT 645.2 ENHANCED PARALLEL PORT (EPP) 63 624.3 DEMODULATION BLOCK DIAGRAM W83977EF/ CTF PRELIMINARY 5.3.11 Bit Map of ECP Port Registers........................................................................................... 74 5.3.12 ECP Pin Descriptions....................................................................................................... 75 5.3.13 ECP Operation................................................................................................................. 76 5.3.14 FIFO Operation................................................................................................................. 76 5.3.15 DMA Transfers................................................................................................................. 77 5.3.16 Programmed I/O (NON-DMA) Mode.................................................................................. 77 ........................................................................................ .................................................................................... 6.0 KEYBOARD CONTROLLER ..............................................................................78 6.1 OUTPUT BUFFER.................................................................................................................... 6.2 INPUT BUFFER........................................................................................................................ 6.3 STATUS REGISTER................................................................................................................. .............................................................................................................................. 6.5 HARDWARE GATEA20/KEYBOARD RESET CONTROL LOGIC............................................ 6.5.1 KB Control Register (Logic Device 5, CR-F0)....................................................................... 82 6.5.2 Port 92 Control Register (Default Value = 0x24)................................................................... 82 6.6 ONNOW / SECURITY KEYBOARD AND MOUSE WAKE-UP.................................................... 6.6.1 Keyboard Wake-Up Function ............................................................................................... 83 6.6.2 Keyboard Password Wake-Up Function.............................................................................. 83 6.6.3 Mouse Wake-Up Function.................................................................................................... 83 7.0 GENERAL PURPOSE I/O...................................................................................84 7.1 BASIC I/O FUNCTIONS............................................................................................................. 7.2 ALTERNATE I/O FUNCTIONS................................................................................................... 7.2.1 Interrupt Steering ................................................................................................................. 88 7.2.2 Watch Dog Timer Output ..................................................................................................... 89 7.2.3 Power LED .......................................................................................................................... 89 7.2.4 General Purpose Address Decoder...................................................................................... 89 8.0 PLUG AND PLAY CONFIGURATION ................................................................90 Publication Release Date: March 1999 -IV - Revision A1 88 86 83 81 806.4 COMMANDS 79 78 78 775.5 EXTENSION 2FDD MODE (EXT2FDD) 775.4 EXTENSION FDD MODE (EXTFDD) W83977EF/ CTF PRELIMINARY 8.1 COMPATIBLE PNP.................................................................................................................... 8.1.1 Extended Function Registers ............................................................................................... 90 8.1.2 Extended Functions Enable Registers (EFERs) ................................................................... 91 8.1.3 Extended Function Index Registers (EFIRs), Extended Function Data Registers(EFDRs) .... 91 8.2 CONFIGURATION SEQUENCE............................................................................................... 8.2.1 Enter the extended function mode........................................................................................ 91 8.2.2 Configurate the configuration registers................................................................................. 92 8.2.3 Exit the extended function mode .......................................................................................... 92 8.2.4 Software programming example........................................................................................... 92 9.0 ACPI REGISTERS FEATURES ..........................................................................93 10.0 CONFIGURATION REGISTER........................................................................94 10.1 CHIP (GLOBAL) CONTROL REGISTER.................................................................................. .................................................................................................... ............................................................................... ¢) ............................................................................................ ............................................................................................... .................................................................................................... ...................................................................................................... 10.8 LOGICAL DEVICE 7 (GP I/O PORT I).................................................................................... 10.9 LOGICAL DEVICE 8 (GP I/O PORT II)................................................................................... 10.10 LOGICAL DEVICE A (ACPI)................................................................................................. 11.0 SPECIFICATIONS...........................................................................................125 ......................................................................................... ....................................................................................................... ........................................................................................................ 11.3.1 FDC: Data rate = 1 MB, 500 KB, 300 KB, 250 KB/sec......................................................129 11.3.2 UART/Parallel Port...........................................................................................................131 11.3.3 Parallel Port Mode Parameters ........................................................................................131 Publication Release Date: March 1999 -V - Revision A1 12911.3 AC CHARACTERISTICS 12511.2 DC CHARACTERISTICS 12511.1 ABSOLUTE MAXIMUM RATINGS 118 113 109 10910.7 LOGICAL DEVICE 6 (CIR) 10810.6 LOGICAL DEVICE 5 (KBC) 10510.5 LOGICAL DEVICE 3 (UART B) 10510.4 LOGICAL DEVICE 2 (UART A) 10410.3 LOGICAL DEVICE 1 (PARALLEL PORT) 10010.2 LOGICAL DEVICE 0 (FDC) 94 91 90 W83977EF/ CTF PRELIMINARY 11.3.4 EPP Data or Address Read Cycle Timing Parameters......................................................132 11.3.5 EPP Data or Address Write Cycle Timing Parameters......................................................133 11.3.6 Parallel Port FIFO Timing Parameters..............................................................................134 11.3.7 ECP Parallel Port Forward Timing Parameters.................................................................134 11.3.8 ECP Parallel Port Reverse Timing Parameters.................................................................134 11.3.9 KBC Timing Parameters ..................................................................................................135 11.3.10 GPIO Timing Parameters...............................................................................................136 11.3.11 Keyboard/Mouse Timing Parameters .............................................................................136 12.0 TIMING WAVEFORMS ..................................................................................137 ....................................................................................................................................... .................................................................................................................. 12.2.1 Modem Control Timing.....................................................................................................139 .................................................................................................................. 12.3.1 Parallel Port Timing..........................................................................................................140 12.3.2 EPP Data or Address Read Cycle (EPP Version 1.9).......................................................141 12.3.3 EPP Data or Address Write Cycle (EPP Version 1.9) .......................................................142 12.3.4 EPP Data or Address Read Cycle (EPP Version 1.7).......................................................143 12.3.5 EPP Data or Address Write Cycle (EPP Version 1.7) .......................................................144 12.3.6 Parallel Port FIFO Timing.................................................................................................144 12.3.7 ECP Parallel Port Forward Timing....................................................................................145 12.3.8 ECP Parallel Port Reverse Timing....................................................................................145 ....................................................................................................................................... 12.4.1 Write Cycle Timing...........................................................................................................146 12.4.2 Read Cycle Timing...........................................................................................................146 12.4.3 Send Data to K/B.............................................................................................................146 12.4.4 Receive Data from K/B.....................................................................................................147 12.4.5 Input Clock.......................................................................................................................147 12.4.6 Send Data to Mouse ........................................................................................................147 12.4.7 Receive Data from Mouse................................................................................................147 12.5 GPIO WRITE TIMING DIAGRAM.......................................................................................... Publication Release Date: March 1999 -VI - Revision A1 148 14612.4 KBC 14012.3 PARALLEL PORT 13812.2 UART/PARALLEL 13712.1 FDC W83977EF/ CTF PRELIMINARY 12.6 MASTER RESET (MR) TIMING............................................................................................. 12.7 KEYBOARD/MOUSE WAKE-UP TIMING.............................................................................. 13.0 APPLICATION CIRCUITS ..............................................................................149 ..................................................................................... ................................................................................... 13.3 FOUR FDD MODE................................................................................................................. 14.0 ORDERING INFORMATION...........................................................................151 15.0 HOW TO READ THE TOP MARKING...........................................................151 16.0 PACKAGE DIMENSIONS ..............................................................................152 Publication Release Date: March 1999 -VII - Revision A1 151 15013.2 PARALLEL PORT EXTENSION 2FDD 14913.1 PARALLEL PORT EXTENSION FDD 148 148 W83977EF/ CTF PRELIMINARY GENERAL DESCRIPTION W83977EF/CTF is an evolving product from Winbond's most popular I/O chip W83877F --- which integrates the disk drive adapter, serial port (UART), IrDA 1.0 SIR, parallel port, and configurable plug-and-play registers for the whole chip --- plus additional powerful features: ACPI, 8042 keyboard controller with PS/2 mouse support, 14 general purpose I/O ports, full 16-bit address and OnNow CIR(W83977CTF only) Wake-Up. The disk drive adapter functions of W83977EF/CTF include a floppy disk drive controller compatible with the industry standard 82077/ 765, data separator, write pre-compensation circuit, decode logic, data rate selection, clock generator, drive interface control logic, and interrupt and DMA logic. The wide range of functions integrated onto the W83977EF/CTF greatly reduces the number of components required for interfacing with floppy disk drives. The W83977EF/CTF supports four 360K, 720K, 1.2M, 1.44M, or 2.88M disk drives and data transfer rates of 250 Kb/s, 300 Kb/s, 500 Kb/s,1 W83977EF/CTF provides two high-speed serial communication ports (UARTs), one of which supports serial Infrared communication. Each UART includes a 16-byte send/receive FIFO, a programmable baud rate generator, complete modem control capability, and a processor interrupt 230k, 460k, or 921k bps W83977EF/CTF supports one PC-compatible printer port (SPP), Bi-directional Printer port (BPP) and also Enhanced Parallel Port (EPP) and Extended Capabilities Port (ECP). Through the printer port interface pins, also available are: Extension FDD Mode and Extension 2FDD Mode, allowing one or two external floppy disk drives to be connected. The configuration registers support mode selection, function enable/disable, and power down function selection. Furthermore, the configurable PnP features are compatible with the plug-and-play feature TM demand of Windows 95, which makes system resource allocation more efficient than ever. W83977EF/CTF provides functions that comply with ACPI ( Advanced Configuration and Power Interface), including support for legacy and ACPI power management through SMI or SCI function W83977EF/CTF The keyboard controller is based on 8042 compatible instruction set, with a 2K Byte programmable TM ROM and a 256-Byte RAM bank. Keyboard BIOS firmware is available with optional AMIKEY- TM Phoenix MultiKey/42 W83977EF/CTF provides the system designer with a set of flexible I/O control functions through a set of General Purpose I/O ports. These GPIO ports may serve as simple I/O, or may be individually configured to provide a predefined alternate function. The W83977EF/CTF also supports Power-loss control, and ensures that the system never fails to TM detect any Wake-Up event provided by a chipset such as INTEL PIIX4 . W83977EF/CTF is made to fully comply with Microsoft PC98 Hardware Design Guide. IRQs, DMAs, and I/O space resource are flexible to adjust to meet ISA PnP requirements. Moreover, W83977EF/CTF is made to meet the specification of PC98's requirements in power management: ACPI DPM Another benifit is that W83977EF/CTF has the same pin assignment as W83977AF, W83977F, W83977TF, W83977ATF. This makes the design very flexible. Publication Release Date: March 1999 -1 - Revision A1 (Device Power Management). and The , or customer code. 2, also has auto power management to reduce power consumption.pins. The which support higher speed modems.with baud rates of system. Both UARTs provide legacy speed with baud rate up to 115.2k bps and also advanced speed The Mb/s, and 2 Mb/s. decoding, OnNow keyboard Wake-Up, OnNow mouse Wake-Up The W83977EF/ CTF PRELIMINARY FEATURES General ·Plug & Play 1.0A compatible · · ·Compliant with Microsoft PC98 ·DPM ACPI · signal issued from any of the 12 IQRs pins or GPIO xx ·Programmable configuration settings ·Single 24/48 Mhz clock input FDC ·Compatible with IBM PC AT disk drive systems · ·Supports vertical recording format · · ·Supports floppy disk drives and tape drives · ·Built-in address mark detection circuit to simplify the read electronics · forced to be inactive) ·Supports up to four 3.5-inch or 5.25-inch floppy disk drives · · ·3-mode FDD, and its Win95 driver UART · ·MIDI compatible ·Fully programmable serial-interface characteristics: --- Even, odd or no parity bit generation/detection Publication Release Date: March 1999 -2 - Revision A1 --- 1, 1.5 or 2 stop bits generation --- 5, 6, 7 or 8-bit characters Two high-speed 16550 compatible UARTs with 16-byte send/receive FIFOs Supports 360K/720K/1.2M/1.44M/2.88M format; 250K, 300K, 500K, 1M, 2M bps data transfer rate Completely compatible with industry standard 82077 FDD anti-virus functions with software write protect and FDD write enable signal (write data signal is Detects all overrun and underrun conditions 16-byte data FIFOs DMA enable logic Variable write pre-compensation with track selectable capability Reports ACPI status interrupt by SCI# (Device Power Management), Supports Hardware Design Guide Capable of ISA Bus IRQ Sharing Supports 12 IRQs, 4 DMA channels, full 16-bit address decoding W83977EF/ CTF PRELIMINARY ·Internal diagnostic capabilities: --- Loop-back controls for communications link fault isolation --- Break, parity, overrun, framing error simulation · ·Maximum baud rate up to 921k bps Infrared ·Supports IrDA version 1.0 SIR protocol with maximum baud rate up to 115.2K bps · · Supports Consumer Infrared (CIR) port. (for W83977CTF only) Parallel Port ·Compatible with IBM parallel port ·Supports PS/2 compatible bi-directional parallel port · - Compatible with IEEE 1284 specification · - Compatible with IEEE 1284 specification · · Keyboard Controller TMTM ·8042 based with optional F/W from AMIKKEY-2, Phoenix MultiKey/42 ·With 2K bytes of programmable ROM, and 256 bytes of RAM · · · · · ·Fast Gate A20 and Hardware Keyboard Reset ·8 Bit Timer/ Counter · · Publication Release Date: March 1999 -3 - Revision A1 6MHz, 8 MHz, 12 MHz, or 16 MHz operating frequency Supports binary and BCD arithmetic Supports both interrupt and polling modes Supports port 92 Supports PS/2 mouse Software compatibility with the 8042 and PC87911 microcontrollers Asynchronous Access to Two Data Registers and One status Register or customer code Enhanced printer port back-drive current protection B through parallel port Extension FDD mode supports disk drive B; and Extension 2FDD mode supports disk drives A and Supports Extended Capabilities Port (ECP) Supports Enhanced Parallel Port (EPP) Supports SHARP ASK-IR protocol with maximum baud rate up to 57,600 bps for 14.769 Mhz and 1.5M bps for 24 Mhz -1)Programmable baud generator allows division of 1.8461 Mhz and 24 Mhz by 1 to (2 16 W83977EF/ CTF PRELIMINARY General Purpose I/O Ports · · OnNow Funtions · · ·CIR(Consumer Infra-Red) Wake-Up by programmable keys (for W83977CTF only) Package · Publication Release Date: March 1999 -4 - Revision A1 128-pin PQFP Mouse Wake-Up by programmable buttons Keyboard Wake-Up by programmable keys pins output, power LED output, infrared I/O pins, general purpose address decoder, KBC control I/O General purpose I/O ports can serve as simple I/O ports, interrupt steering inputs, watch-dog timer 14 programmable general purpose I/O ports: 6 dedicate, 8 optional W83977EF/ CTF PRELIMINARY PIN CONFIGURATION PPPA WAN RNS SSWC MWOT IIUL #NT# III##// RRRIIIIIII//GMK/G/GGQQRRRRRRRAAAAAVCRQAVPPCRVPP 111QQQQQQNQ111111AAAAAAAAAAS22LLISC22I 210134567C95S4321C0987654321032B1KKBA0 11999988888877777777766619999998888766 00098765432109876543210987654321098765 210 10364 10463 10562 VSS 10661 IOW# 10760 AEN 10859 10958 D0KBLOCK/GP13 11057 D1 11156 GA20/GP11 D2 112 55 D3VCC 54 113DCDB# D4 53 114 D5 11552 VCC 11651 D6 11750 D7 11849 MR DSRB# 119 48 DACK0#/GP16 12047 VSS DCDA# 121 46 SOUTA/PENKBC 122 45 DACK1# 12344 DTRA#/PNPCSV# 12443 DACK2#RTSA#/HEFRAS 12542 DSRA# 41 126 DACK3# 12740 39 128 31111111111222222222233333333 12345679489036789238012356712450145687 CDD//////////////SPVB/PPVPPPPPP/////II RRDHRWTWWSDDDMILEUADDDDDDSIEASRRLMCSDD VVDREDTISSONCC7543LNFRSEPOCS6210RTTKSDDAAETYKIDKARABAIDXXIBRB TKEEECPNTNDAXNH0N 10G, G P 1 0, / S C I Publication Release Date: March 1999 -5 - Revision A1 SUSCIN#/GP25 TC CIRRX/GP24DRQ3 CTSA# DRQ2 DRQ1 SINA SCI#/DRQ0/GP17 CTSB# RTSB DTRB# SINB SOUTB/PEN48 KBRST/GP12 KDATA IOCHRDY MDATA XTAL2 IOR# XTAL1IRQ15/GP15 IRQ14/GP14 VBAT W83977EF/ CTF PRELIMINARY 1.0 PIN DESCRIPTION 8 I/OD OUT OUT OD OD IN t IN c IN cu IN cs IN ts IN 1.1 Host Interface SYMBOL PIN I/O FUNCTION -INt INt INt I/O - I/O - INts IOW#INts INts OD INMaster Reset; Active high; MR is low during normal ts Publication Release Date: March 1999 -6 - Revision A1 operations. 118MR extend the host read/write cycle. 24 In EPP Mode, this pin is the IO Channel Ready output to108IOCHRDY System address bus enable107AEN CPU I/O write signal106 CPU I/O read signal105IOR# 12t D7D6 System data bus bits 6-7116-117 12t D5D0 System data bus bits 0-5109-114 System address bus bit 1591A15 System address bus bits 11-1486-89A11-A14 System address bus bits 0-1074-84A10A0 tsu resistor- TTL level Schmitt-triggered input pin with internal pull-up - TTL level Schmitt-triggered input pin - CMOS level Schmitt-triggered input pin - CMOS level input pin with internal pull-up resitor - CMOS level input pin - TTL level input pin 24 - Open-drain output pin with 24 mA sink capability 12 - Open-drain output pin with 12 mA sink capability 12t - TTL level output pin with 12 mA source-sink capability 8t - TTL level output pin with 8 mA source-sink capability 24t - TTL level bi-directional pin with 24 mA source-sink capabilityI/O 16u - CMOS level bi-directional pin open drain output with 16 mA sink capability with internal pull-up resistor 16u - CMOS level bi-directional pin with 16 mA source-sink capability with internal pull-up resistorI/O 12 - CMOS level bi-directional pin with 12 mA source-sink capabilityI/O 12t - TTL level bi-directional pin with 12 mA source-sink capabilityI/O - CMOS level bi-directional pin with 8 mA source-sink capabilityI/O 8t - TTL level bi-directional pin with 8 mA source-sink capabilityI/O 6t - TTL level bi-directional pin with 6 mA source-sink capabilityI/O Note: Please refer to Section 11.2 DC CHARACTERISTICS for details. W83977EF/ CTF PRELIMINARY SYMBOL PIN I/O FUNCTION IN default) I/O (WDTO) Alternate function from GP16: Watch dog timer output I/OKBC P15 I/O port. (CR2C bit 5_4 = 10) OUT I/O Alternate function from GP17: Power LED output. I/OKBC P14 I/O port (CR2C bit 7_6 = 10) OUT INts OUT INts OUT INts OUT TCINTerminal Count. When active, this pin indicates termination of a ts OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT Publication Release Date: March 1999 -7 - Revision A1 12t Interrupt request 12102IRQ12 12t Interrupt request 11101IRQ11 12t Interrupt request 10100IRQ10 12t Interrupt request 992IRQ9 12t Interrupt request 794IRQ7 12t Interrupt request 695IRQ6 12t Interrupt request 596IRQ5 12t Interrupt request 497IRQ4 12t Interrupt request 398IRQ3 12t Interrupt request 199IRQ1 DMA transfer. 128 12t DMA Channel 3 request signal127DRQ3 DMA Channel 3 Acknowledge signal126DACK3# 12t DMA Channel 2 request signal125DRQ2 DMA Channel 2 Acknowledge signal124DACK2# 12t DMA Channel 1 request signal123DRQ1 DMA Channel 1 Acknowledge signal122DACK1# 12t System Control Interrupt (CR2C bit 7_6 = 11)SCI# 12t P14 (PLEDO) 12t General purpose I/O port 1bit 7. (CR2C bit 7_6 = 01)GP17 12t DMA Channel 0 request signal. (CR2C bit 7_6 = 00, default)121DRQ0 12t P15 12t General purpose I/O port 1bit 6. (CR2C bit 5_4 = 01)GP16 tsu DMA Channel 0 Acknowledge signal. (CR2C bit 5_4 = 00,119DACK0# 1.1 Host Interface, continued W83977EF/ CTF PRELIMINARY SYMBOL PIN I/O FUNCTION OUT I/O Alternate Function 2 from GP14: KBC P17 I/O port. OUT OUT I/O Alternate Function 2 from GP15: KBC P12 I/O port. WDTOUTWatch-Dog timer output. (CR2C bit 3_2 = 10) 1INt 1.2 General Purpose I/O Port SYMBOL PIN I/O FUNCTION PWR_CTL#OD I/O (KBRST) SMI #ODSystem Management Interrupt. (CR2B bit 4_3 = 00, default) In the legacy power management mode, SMI# is drive low by the I/O Alternate Function from GP21: KBC P13 I/O port. I/OKBC P16 I/O port. (CR2B bit 4_3 = 10) PANSWOT#ODPanel Switch output. (CR2B bit 5 = 0, default) I/OGeneral purpose I/O port 2 bit 2. (CR2B bit 5 = 1) Alternate Function from GP22: KBC P14 I/O port. Publication Release Date: March 1999 -8 - Revision A1 (P14) 12t GP22 12t 72 12t P16 (P13) 12t General purpose I/O port 2 bit 1. (CR2B bit 4_3 = 01)GP21 power management events. 12t 70 Alternate Function from GP20: Keyboard reset (KBC P20) 16tu General purpose I/O port 2 bit 0.GP20 16u Power supply control69 24 or 48 MHz clock input, selectable through bit 5 of CR24.CLKIN 12t (P12) enable output. Alternate Function 1 from GP15: General purpose address write(GPACS2#) 12t General purpose I/O port 1 bit 5. (CR2C bit 3_2 = 01)GP15 12t Interrupt request 15.(CR2C bit 3_2 = 00, default)104IRQ15 12t Power LED output. (CR2C bit 1_0 = 10)PLEDO (P17) decode output. Alternate Function 1 from GP14: General purpose address(GPACS1#) 12t General purpose I/O port 1 bit 4. (CR2C bit 1_0 = 01)GP14 12t Interrupt request 14. (CR2C bit 1_0 = 00, default)103IRQ14 1.1 Host Interface, continued W83977EF/ CTF PRELIMINARY SYMBOL PIN I/O FUNCTION PANSWIN#INPanel Switch input. (CR2B bit 7_6 = 00, default)t I/OGeneral purpose I/O port 2 bit 3. (CR2B bit 7_6 = 01) Alternate Function from GP23: KBC P15 I/O port INConsumer infrared receiver inputt Alternate Function from GP24: KBC P16 I/O port I/O I/OKBC P13 I/O port. (CR2A bit 5_4 = 10) INts Alternate Function from GP25: GATE A20 (KBC P21) I/O 1.3 Serial Port Interface SYMBOL PIN I/O FUNCTION INClear To Send is the modem control input.t The function of these pins can be tested by reading Bit 4 of the INData Set Ready. An active low signal indicates the modem ort I/OUART A Request To Send. An active low signal informs the During power-on reset, this pin is pulled down internally and is defined as HEFRAS, which provides the power-on value for CR26 bit 6 (HEFRAS). A 4.7 k W is recommended if intending to pull up. (select 370H as configuration I/O port ¢ I/OUART B Request To Send. An active low signal informs the Publication Release Date: March 1999 -9 - Revision A1 modem or data set that the controller is ready to send data. RTSB# 8t 50 s address) HEFRAS modem or data set that the controller is ready to send data. RTSA# 8t 43 data to the UART. DSRB# 49 data set is ready to establish a communication link and transfer DSRA# 42 handshake status register. 48CTSB# 41CTSA# 12 General purpose I/O port 2 bit 5.GP25 (GA20) Suspend C input39 SUSC# 12t P13 12t General purpose I/O port 2 bit 4 (CR2A bit 5_4 = 01)GP24 (P16) 40CIRRX (P15) 12t GP23 73 1.2 General Purpose I/O Port ,continued W83977EF/ CTF PRELIMINARY SYMBOL PIN I/O FUNCTION I/OUART A Data Terminal Ready. An active low signal informs the modem or data set that the controller is ready to communicate. During power-on reset, this pin is pulled down internally and is defined as PNPCSV#, which provides the power-on value for W is recommended if intending to pull up. (clears the default value of FDC, UARTs, and PRT). I/OUART B Data Terminal Ready. An active low signal informs the modem or data set that controller is ready to communicate. INSerial Input. Used to receive serial data through thet communication link. I/OUART A Serial Output. Used to transmit serial data out to the SOUTA communication link. During power-on reset, this pin is pulled down internally and is defined as PENKBC, which provides the power-on value for CR24 bit 2 (ENKBC). A 4.7 k W resistor is recommended if SOUTBI/O power-on value for CR24 bit 6 (EN48). A 4.7 k W recommended if intending to pull up. INData Carrier Detect. An active low signal indicates the modemt INRing Indicator. An active low signal indicates that a ring signal ist being received from the modem or data set. 1.4 Infrared Interface SYMBOL PIN I/O FUNCTION INInfrared Receiver Input. cs OUTInfrared Transmitter Output. Publication Release Date: March 1999 -10 - Revision A1 12t 38IRTX 37IRRX 66RIB# 65RIA# DCDB# 54 or data set has detected a data carrier. 47DCDA# resistor is PEN48 down internally and is defined as PEN48, which provides the 8t UART B Serial Output. During power-on reset, this pin is pulled53 intending to pull up. (enables KBC). PENKBC 8t 46 SINB 45, 52SINA DTRB# 8t 51 CR24 bit 0 (PNPCSV#). A 4.7 k PNPCSV# DTRA# 8t 44 1.3 Serial Port Interface, continued W83977EF/ CTF PRELIMINARY 1.5 Multi-Mode Parallel Port SYMBOL PIN I/O FUNCTION PRINTER MODE: SLCTINt An active high input on this pin indicates that the printer is selected. This pin is pulled high internally. Refer to description of the parallel port for definition of this pin in ECP and EPP mode. OD WE2# This pin is for Extension FDD B; its function is the same as the WE# pin of FDC. EXTENSION 2FDD MODE: WE2#OD This pin is for Extension FDD A and B; its function is the same as the WE# pin of FDC. PRINTER MODE: PEINt An active high input on this pin indicates that the printer has detected the end of the paper. This pin is pulled high internally. Refer to description of the parallel port for definition of this pin in ODEXTENSION FDD MODE: WD2# This pin is for Extension FDD B; its function is the same as the WD# pin of FDC. ODEXTENSION 2FDD MODE: WD2# This pin is for Extension FDD A and B; its function is the same as the WD# pin of FDC. Publication Release Date: March 1999 -11 - Revision A1 12 12 ECP and EPP mode. 19PE 12 12 EXTENSION FDD MODE: 18SLCT The following pins have alternate functions, which are controlled by CR28 and L3-CRF0. W83977EF/ CTF PRELIMINARY SYMBOL PIN I/O FUNCTION INPRINTER MODE: BUSYt An active high input indicates that the printer is not ready to receive data. This pin is pulled high internally. Refer to description of the parallel port for definition of this pin in ECP OD This pin is for Extension FDD B; the function of this pin is the same as the MOB# pin of FDC. OD This pin is for Extension FDD A and B; the function of this pin is the same as the MOB# pin of FDC. INt An active low input on this pin indicates that the printer has received data and is ready to accept more data. This pin is pulled high internally. Refer to description of the parallel port for definition of this pin in ECP and EPP mode. OD This pin is for the Extension FDD B; its function is the same as the DSB# pin of FDC. OD This pin is for Extension FDD A and B; it function is the same as the DSB# pin of FDC. INt An active low input on this pin indicates that the printer has Refer to description of the parallel port for definition of this pin in OD This pin is for Extension FDD B; its function is the same as the HEAD#pin of FDC. OD This pin is for Extension FDD A and B; its function is the same the HEAD# pin of FDC. Publication Release Date: March 1999 -12 - Revision A1 as EXTENSION 2FDD MODE: HEAD2# 12 12 EXTENSION FDD MODE: HEAD2# ECP and EPP mode. encountered an error condition. This pin is pulled high internally. PRINTER MODE: ERR#34ERR# 12 EXTENSION 2FDD MODE: DSB2# 12 EXTENSION FDD MODE: DSB2# PRINTER MODE: ACK#22ACK# EXTENSION 2FDD MODE:MOB2# 12 EXTENSION FDD MODE: MOB2# 12 and EPP mode. 21BUSY 1.5 Multi-Mode Parallel Port, continued W83977EF/ CTF PRELIMINARY SYMBOL PIN I/O FUNCTION OD Output line for detection of printer selection. This pin is pulled high internally. Refer to description of the parallel port for definition of this pin in ECP and EPP mode. OD This pin is for Extension FDD B; its function is the same as the STEP# pin of FDC. OD This pin is for Extension FDD A and B; its function is the same as the STEP# pin of FDC. INIT#ODPRINTER MODE: INIT# Output line for the printer initialization. This pin is pulled high internally. Refer to description of the parallel port for definition of this pin in ECP and EPP mode. OD This pin is for Extension FDD B; its function is the same as the DIR# pin of FDC. OD This pin is for Extension FDD A and B; its function is the same as the DIR# pin of FDC. ODPRINTER MODE: AFD# An active low output from this pin causes the printer to auto feed a line after a line is printed. This pin is pulled high internally. Refer to description of the parallel port for definition of this pin in OD This pin is for Extension FDD B; its function is the same as the DRVDEN0 pin of FDC. OD This pin is for Extension FDD A and B; its function is the same as the DRVDEN0 pin of FDC. Publication Release Date: March 1999 -13 - Revision A1 12 EXTENSION 2FDD MODE: DRVDEN0 12 EXTENSION FDD MODE: DRVDEN0 ECP and EPP mode. 12 35AFD# 12 EXTENSION 2FDD MODE: DIR2# 12 EXTENSION FDD MODE: DIR2# 12 33 12 EXTENSION 2FDD MODE: STEP2# 12 EXTENSION FDD MODE:STEP2# 12 PRINTER MODE: SLIN#32SLIN# 1.5 Multi-Mode Parallel Port, continued W83977EF/ CTF PRELIMINARY SYMBOL PIN I/O FUNCTION ODPRINTER MODE: STB# An active low output is used to latch the parallel data into the printer. This pin is pulled high internally. Refer to description of the parallel port for definition of this pin in ECP and EPP mode. -EXTENSION FDD MODE: This pin is a tri-state output. -EXTENSION 2FDD MODE: This pin is a tri-state output. I/O Parallel port data bus bit 0. Refer to description of the parallel port for definition of this pin in ECP and EPP mode. INt This pin is for Extension FDD B; the function of this pin is the same as the INDEX# pin of FDC. It is pulled high internally. INt This pin is for Extension FDD A and B; the function of this pin is the same as the INDEX# pin of FDC. It is pulled high internally. I/O Parallel port data bus bit 1. Refer to description of the parallel port for definition of this pin in ECP and EPP mode. INt This pin is for Extension FDD B; the function of this pin is the same as the TRAK0# pin of FDC. It is pulled high internally. INt This pin is for Extension FDD A and B; the function of this pin is the same as the TRAK0# pin of FDC. It is pulled high internally. I/O Parallel port data bus bit 2. Refer to description of the parallel port for definition of this pin in ECP and EPP mode. INEXTENSION FDD MODE: WP2#t This pin is for Extension FDD B; the function of this pin is the same as the WP# pin of FDC. It is pulled high internally. EXTENSION. 2FDD MODE: WP2# INt This pin is for Extension FDD A and B; the function of this pin is the same as the WP# pin of FDC. It is pulled high internally. Publication Release Date: March 1999 -14 - Revision A1 12t PD2 PRINTER MODE: PD229 EXTENSION. 2FDD MODE: TRAK02# EXTENSION FDD MODE: TRAK02# 12t PD1 PRINTER MODE: PD130 EXTENSION 2FDD MODE: INDEX2# EXTENSION FDD MODE: INDEX2# 12t PD0 PRINTER MODE: PD031 12 36STB# 1.5 Multi-Mode Parallel Port, continued W83977EF/ CTF PRELIMINARY SYMBOL PIN I/O FUNCTION I/O Parallel port data bus bit 3. Refer to description of the parallel port for definition of this pin in ECP and EPP mode. INt This pin is for Extension FDD B; the function of this pin is the same as the RDATA# pin of FDC. It is pulled high internally. INt This pin is for Extension FDD A and B; this function of this pin is the same as the RDATA# pin of FDC. It is pulled high internally. I/O Parallel port data bus bit 4. Refer to description of the parallel port for definition of this pin in ECP and EPP mode. INt This pin is for Extension FDD B; the function of this pin is the same as the DSKCHG# pin of FDC. It is pulled high internally. INt This pin is for Extension FDD A and B; this function of this pin is the same as the DSKCHG# pin of FDC. It is pulled high internally. I/O Parallel port data bus bit 5. Refer to description of the parallel port for definition of this pin in ECP and EPP mode. -EXTENSION FDD MODE: This pin is a tri-state output. -EXTENSION 2FDD MODE: This pin is a tri-state output. I/O Parallel port data bus bit 6. Refer to description of the parallel port for definition of this pin in ECP and EPP mode. - EXTENSION FDD MODE: This pin is a tri-state output. OD This pin is for Extension FDD A; its function is the same as the MOA# pin of FDC. Publication Release Date: March 1999 -15 - Revision A1 12 EXTENSION. 2FDD MODE: MOA2# 12t PD6 PRINTER MODE: PD624 12t PD5 PRINTER MODE: PD526 EXTENSION 2FDD MODE: DSKCHG2# EXTENSION FDD MODE: DSKCHG2# 12t PD4 PRINTER MODE: PD427 EXTENSION 2FDD MODE: RDATA2# EXTENSION FDD MODE: RDATA2# 12t PD3 PRINTER MODE: PD328 1.5 Multi-Mode Parallel Port, continued W83977EF/ CTF PRELIMINARY SYMBOL PIN I/O FUNCTION I/O Parallel port data bus bit 7. Refer to description of the parallel port for definition of this pin in ECP and EPP mode. EXTENSION FDD MODE: This pin is a tri-state output.- OD This pin is for Extension FDD A; its function is the same as the DSA# pin of FDC. 1.6 FDC Interface SYMBOL PIN I/O FUNCTION 2ODDrive Density Select bit 0. 3ODDrive Density Select bit 1. (CR2A bit 1_0 = 00, default) IO (IRQIN1)Alternate Function from GP10: Interrupt channel input. IOKBC P12 I/O port. (CR2A bit 1_0 = 10) OUT 5OD head is active. WE#9ODWrite enable. An open drain output. WD#OD OD a pulse to move the head to another track. OD Logic 0 = inward motion ODMotor B On. When set to 0, this pin enables disk drive 1. This is Publication Release Date: March 1999 -16 - Revision A1 an open drain output. 24 13MOB# Logic 1 = outward motion 24 Direction of the head step motor. An open drain output.12DIR# 24 Step output pulses. This active low open drain output produces11STEP# serial data to the selected FDD. An open drain output. 24 Write data. This logic low open drain writes pre-compensation10 24 Logic 0 = side 1 Logic 1 = side 0 24 Head select. This open drain output determines which disk driveHEAD# 12t System Control Interrupt (CR2A bit 1_0 = 11)SCI# 12t P12 12t General purpose I/O port 1 bit 0. (CR2A bit 1_0 = 01)GP10 12 DRVDEN1 24 DRVDEN0 12 EXTENSION 2FDD MODE: DSA2# 12t PD7 PRINTER MODE: PD723 1.5 Multi-Mode Parallel Port, continued W83977EF/ CTF PRELIMINARY SYMBOL PIN I/O FUNCTION ODDrive Select A. When set to 0, this pin enables disk drive A. ODDrive Select B. When set to 0, this pin enables disk drive B. ODMotor A On. When set to 0, this pin enables disk drive 0. This is 4INcs whenever the diskette is removed. This input pin is pulled up internally by a 1 K W 7 of L0-CRF0 (FIPURDWN). 6INThe read data input signal from the FDD. This input pin is pulled cs up internally by a 1 K W bit 7 of L0-CRF0 (FIPURDWN). WP#7INWrite protected. This active low Schmitt input from the disk cs drive indicates that the diskette is write-protected. This input pin is pulled up internally by a 1 K W disabled by bit 7 of L0-CRF0 (FIPURDWN). 8INTrack 0. This Schmitt-triggered input from the disk drive is cs This input pin is pulled up internally by a 1 K W resistor can be disabled by bit 7 of L0-CRF0 (FIPURDWN). INThis Schmitt-triggered input from the disk drive is active low cs marked by an index hole. This input pin is pulled up internally by a 1 K W (FIPURDWN). Publication Release Date: March 1999 -17 - Revision A1 resistor. The resistor can be disabled by bit 7 of L0-CRF0 when the head is positioned over the beginning of a track 17INDEX# resistor. The active low when the head is positioned over the outermost track. TRAK0# resistor. The resistor can be resistor. The resistor can be disabled by RDATA# resistor. The resistor can be disabled by bit Diskette change. This signal is active low at power on andDSKCHG# an open drain output. 24 16MOA# This is an open drain output. 24 15DSB# This is an open drain output. 24 14DSA# 1.6 FDC Interface, continued W83977EF/ CTF PRELIMINARY 1.7 KBC Interface SYMBOL PIN I/O FUNCTION I/O MDATAI/O I/O I/O I/OKBC GATE A20 (P21) Output. (CR2A bit 6 = 0, default) I/OGeneral purpose I/O port 1 bit 1. (CR2A bit 6 = 1) (IRQIN2)Alternate Function from GP11: Interrupt channel input. I/OW83C45 Keyboard Reset (P20) Output. (CR2A bit 7 = 0, default) I/OGeneral purpose I/O port 1 bit 2. (CR2A bit 7 = 1) (WDTO)Alternate Function 1 from GP12 : Watchdog timer output. INW83C45 KINH (P17) Input. (CR2B bit 0 = 0, default) ts I/OGeneral purpose I/O port 1 bit 3. (CR2B bit 0 = 1) 1.8 POWER PINS SYMBOL PIN FUNCTION +5V power supply for the digital circuitry 1.9 ACPI Interface SYMBOL PIN I/O FUNCTION VBATBattery voltage input INC O Publication Release Date: March 1999 -18 - Revision A1 8t 32.768Khz Clock Output61XTAL2 32.768Khz Clock Input63XTAL1 NA64 120 Ground25, 62, 90,GND +5V stand-by power supply for the digital circuitry71VSB 115 20, 55, 85,VCC 16t GP13 58KBLOCK 12t GP12 12t 57KBRST 12t GP11 12t 56GA20 16u PS2 Mouse Clock68MCLK 16u Keyboard Clock67KCLK 16u PS2 Mouse Data60 16u Keyboard Data59KDATA W83977EF/ CTF PRELIMINARY 2.0 FDC FUNCTIONAL DESCRIPTION 2.1 W83977EF/CTF FDC The floppy disk controller of the W83977EF/CTF integrates all of the logic required for floppy disk control. The FDC implements a PC/AT or PS/2 solution. All programmable options default to compatible values. The FIFO provides better system performance in multi-master systems. The The FDC includes the following blocks: AT interface, Precompensation, Data Rate Selection, Digital 2.1.1 AT interface The interface consists of the standard asynchronous signals: RD#, WR#, A0-A3, IRQ, DMA control, and a data bus. The address lines select between the configuration registers, the FIFO and control/status registers. This interface can be switched between PC/AT, Model 30, or PS/2 normal 2.1.2 FIFO (Data) The FIFO is 16 bytes in size and has programmable threshold values. All command parameter information and disk data transfers go through the FIFO. Data transfers are governed by the RQM The FIFO defaults to disabled mode after any form of reset. This maintains PC/AT hardware compatibility. The default values can be changed through the CONFIGURE command. The advantage of the FIFO is that it allows the system a larger DMA latency without causing disk errors. The following tables give several examples of the delays with a FIFO. The data are based upon the following formula: ´ (1/DATA/RATE) *8 - 1.5 mS = DELAY FIFO THRESHOLD MAXIMUM DELAY TO SERVICING AT 500K BPS Data Rate 1 Byte ´ mS - 1.5 mS = 14.5 mS 2 Byte ´ mS - 1.5 mS = 30.5 mS 8 Byte ´ mS - 1.5 mS = 6.5 mS ´ mS - 1.5 mS = 238.5 mS FIFO THRESHOLD MAXIMUM DELAY TO SERVICING AT 1M BPS Data Rate 1 Byte ´ mS - 1.5 mS = 6.5 mS 2 Byte ´ mS - 1.5 mS = 14.5 mS 8 Byte ´ mS - 1.5 mS = 62.5 mS ´ mS - 1.5 mS = 118.5 mS Publication Release Date: March 1999 -19 - Revision A1 8 15 15 Byte 8 8 8 2 8 1 16 15 15 Byte 16 8 16 2 16 1 THRESHOLD # and DIO bits in the Main Status Register. modes. The PS/2 register sets are a superset of the registers found in a PC/AT. Data Separator, FIFO, and FDC Core. digital data separator supports up to 2 M bits/sec data rate. W83977EF/ CTF PRELIMINARY At the start of a command the FIFO is always disabled and command parameters must be sent based upon the RQM and DIO bit settings in the main status register. When the FDC enters the command execution phase, it clears the FIFO of any data to ensure that invalid data are not transferred. An overrun and underrun will terminate the current command and the data transfer. Disk writes will complete the current sector by generating a 00 pattern and valid CRC. Reads require the host to DMA transfers are enabled with the SPECIFY command, and are initiated by the FDC by activating the DRQ pin during a data transfer command. The FIFO is enabled directly by asserting DACK# and Note that if the DMA controller is programmed to function in verify mode, a pseudo read is performed by the FDC based only onDACK#. This mode is only available when the FDC has been configured into byte mode (FIFO disabled) and is programmed to do a read. With the FIFO enabled the above ¡ 2.1.3 Data Separator The function of the data separator is to lock onto the incoming serial read data. When a lock is achieved the serial front end logic of the chip is provided with a clock which is synchronized to the read data. The synchronized clock, called the Data Window, is used to internally sample the serial data portion of the bit cell, and the alternate state samples the clock portion. Serial to parallel The Digital Data Separator (DDS) has three parts: control logic, error adjustment, and speed tracking. The DDS circuit cycles once every 12 clock cycles ideally. Any data pulse input will be synchronized and then adjusted by immediate error adjustment. The control logic will generate RDD and RWD for every pulse input. During any cycle where no data pulse is present, the DDS cycles are based on 2.1.4 Write Precompensation The write precompensation logic is used to minimize bit shifts in the RDDATA stream from the disk drive. Shifting of bits is a known phenomenon in magnetic media and is dependent on the disk media and the floppy drive. The FDC monitors the bit stream that is being sent to the drive. The data patterns that require precompensation are well known. Depending upon the pattern, the bit is shifted either early or late relative to the surrounding bits. Publication Release Date: March 1999 -20 - Revision A1 speed. A digital integrator is used to keep track of the speed changes in the input data stream. conversion logic separates the read data into clock and data bytes. operation is performed by using the new VERIFY command. No DMA operation is needed. addresses need not be valid. remove the remaining data so that the result phase may be entered. W83977EF/ CTF PRELIMINARY 2.1.5 Perpendicular Recording Mode The FDC is also capable of interfacing directly to perpendicular recording floppy drives. Perpendicular recording differs from the traditional longitudinal method in that the magnetic bits are oriented vertically. This method packs more data bits into the same area. FDCs with perpendicular recording drives can read standard 3.5" floppy disks, and can read and write perpendicular media. Some manufacturers offer drives that can read and write standard and perpendicular media in a perpendicular media drive. A single command puts the FDC into perpendicular mode. All other commands operate as they normally do. The perpendicular mode requires a 1 Mbps data rate for the FDC. At this data rate the 2.1.6 FDC Core The W83977EF/CTF FDC is capable of performing twenty commands. Each command is initiated by a multi-byte transfer from the microprocessor. The result can also be a multi-byte transfer back to the Command The microprocessor issues all required information to the controller to perform a specific operation. Execution The controller performs the specified operation. Result After the operation is completed, status information and other housekeeping information is provided 2.1.7 FDC Commands Command Symbol Descriptions: C: D: DIR:Step Direction DIR = 1, step in rive Select 0 Disk Drive Select 1 Publication Release Date: March 1999 -21 - Revision A1 Enable CountEC: Data LengthDTL: DS1: Disk DDS0: DIR = 0, step out Data Pattern Cylinder number 0 - 256 to the microprocessor. microprocessor. Each command consists of three phases: command, execution, and result. FIFO eases the host interface bottleneck due to the speed of data transfer to or from the disk. W83977EF/ CTF PRELIMINARY EOT:End of Track EFIFO:Enable FIFO EIS:Enable Implied Seek EOT:End of track FIFOTHR: GAP: GPL: H: HUT: Lock EFIFO, FIFOTHR, PTRTRK bits prevent chip from being affected by software MFM:MFM or FM Mode MT:Multitrack N: Number OW:Overwritten Polling Disable R: Relative Cylinder Number R/W:Read/Write SK: SRT:Step Rate Time ST0: ST1: ST2: ST3: WG:Write gate alters timing of WE Publication Release Date: March 1999 -22 - Revision A1 Status Register 3 Status Register 2 Status Register 1 Status Register 0 Skip deleted data address mark Sector/per cylinderSC: RCN: Record Precompensation Start Track NumberPRETRK: POLL: Present Cylinder NumberPCN: Non-DMA ModeND: New CylinderNCN: The number of data bytes written in a sector reset LOCK: Head Unload Time Head Load TimeHLT: Head number selectHDS: Head number Gap Length Gap length selection FIFO Threshold W83977EF/ CTF PRELIMINARY (1) Read Data PHASE R/W D7 D6 D5 D4 D3 D2 D1 D0 REMARKS CommandW MT MFM SK 0 0 1 1 0 W 0 0 0 0 0 HDS DS1 DS0 W---------------------- C ------------------------Sector ID information prior to command execution W---------------------- H ------------------------ W---------------------- R ------------------------ W---------------------- N ------------------------ W-------------------- EOT ----------------------- W-------------------- GPL ----------------------- W-------------------- DTL ----------------------- Execution R-------------------- ST0 -----------------------Status information after Rcommand execution -------------------- ST1 ----------------------- R -------------------- ST2 ----------------------- R---------------------- C ------------------------Sector ID information after command execution R---------------------- H ------------------------ R---------------------- R ------------------------ R---------------------- N ------------------------ Publication Release Date: March 1999 -23 - Revision A1 Result FDD and system Data transfer between the Command codes W83977EF/ CTF PRELIMINARY (2) Read Deleted Data PHASE R/W D7 D6 D5 D4 D3 D2 D1 D0 REMARKS CommandW MT MFM SK 0 1 1 0 0 W 0 0 0 0 0 HDS DS1 DS0 W---------------------- C ------------------------Sector ID information prior to command execution W---------------------- H ------------------------ W---------------------- R ------------------------ W---------------------- N ------------------------ W-------------------- EOT ----------------------- W-------------------- GPL ----------------------- W-------------------- DTL ----------------------- Execution R-------------------- ST0 -----------------------Status information after command execution R-------------------- ST1 ----------------------- R-------------------- ST2 ----------------------- R---------------------- C ------------------------Sector ID information after command execution R---------------------- H ------------------------ R---------------------- R ------------------------ R---------------------- N ------------------------ Publication Release Date: March 1999 -24 - Revision A1 Result FDD and system Data transfer between the Command codes W83977EF/ CTF PRELIMINARY (3) Read A Track PHASE R/W D7 D6 D5 D4 D3 D2 D1 D0 REMARKS CommandW 0 MFM 0 0 0 0 1 0 W 0 0 0 0 0 HDS DS1 DS0 W---------------------- C ------------------------Sector ID information prior to command execution W---------------------- H ------------------------ W---------------------- R ------------------------ W---------------------- N ------------------------ W-------------------- EOT ----------------------- W-------------------- GPL ----------------------- W-------------------- DTL ----------------------- Execution cylinders from index hole to EOT R-------------------- ST0 -----------------------Status information after command execution R-------------------- ST1 ----------------------- R-------------------- ST2 ----------------------- R---------------------- C ------------------------Sector ID information after command execution R---------------------- H ------------------------ R---------------------- R ------------------------ R---------------------- N ------------------------ Publication Release Date: March 1999 -25 - Revision A1 Result reads contents of all FDD and system; FDD Data transfer between the Command codes W83977EF/ CTF PRELIMINARY (4) Read ID PHASE R/W D7 D6 D5 D4 D3 D2 D1 D0 REMARKS CommandW 0 MFM 0 0 1 0 1 0 W 0 0 0 0 0 HDS DS1 DS0 ExecutionThe first correct ID information on the cylinder R-------------------- ST0 -----------------------Status information after command execution R-------------------- ST1 ----------------------- R-------------------- ST2 ----------------------- R---------------------- C ------------------------ R ---------------------- H ------------------------ completed R ---------------------- R ------------------------ R ---------------------- N ------------------------ (5) Verify PHASE R/W D7 D6 D5 D4 D3 D2 D1 D0 REMARKS CommandW MT MFM SK 1 0 1 1 0 W EC 0 0 0 0 HDS DS1 DS0 W---------------------- C ------------------------Sector ID information prior to command execution W---------------------- H ------------------------ W---------------------- R ------------------------ W---------------------- N ------------------------ W-------------------- EOT ----------------------- W-------------------- GPL ----------------------- -------------------- DTL/SC ------------------- Execution R-------------------- ST0 -----------------------Status information after command execution R-------------------- ST1 ----------------------- R-------------------- ST2 ----------------------- R---------------------- C ------------------------Sector ID information after command execution R---------------------- H ------------------------ R---------------------- R ------------------------ R---------------------- N ------------------------ Publication Release Date: March 1999 -26 - Revision A1 Result place No data transfer takes Command codes command has been Disk status after the Result is stored in Data Register Command codes W83977EF/ CTF PRELIMINARY (6) Version PHASE R/W D7 D6 D5 D4 D3 D2 D1 D0 REMARKS CommandW 0 0 0 1 0 0 0 0 R 1 0 0 1 0 0 0 0 (7) Write Data PHASE R/W D7 D6 D5 D4 D3 D2 D1 D0 REMARKS CommandW MT MFM 0 0 0 1 0 1 W 0 0 0 0 0 HDS DS1 DS0 W---------------------- C ------------------------Sector ID information prior to Command execution W---------------------- H ------------------------ W---------------------- R ------------------------ W---------------------- N ------------------------ W-------------------- EOT ----------------------- W-------------------- GPL ----------------------- W-------------------- DTL ----------------------- Execution R-------------------- ST0 -----------------------Status information after Command execution R-------------------- ST1 ----------------------- R-------------------- ST2 ----------------------- R---------------------- C ------------------------Sector ID information after Command execution R---------------------- H ------------------------ R---------------------- R ------------------------ R---------------------- N ------------------------ Publication Release Date: March 1999 -27 - Revision A1 Result FDD and system Data transfer between the Command codes Enhanced controllerResult Command code W83977EF/ CTF PRELIMINARY (8) Write Deleted Data PHASE R/W D7 D6 D5 D4 D3 D2 D1 D0 REMARKS CommandW MT MFM 0 0 1 0 0 1 W 0 0 0 0 0 HDS DS1 DS0 W---------------------- C ------------------------Sector ID information prior to command execution W---------------------- H ------------------------ W---------------------- R ------------------------ W---------------------- N ------------------------ W-------------------- EOT ----------------------- W-------------------- GPL ----------------------- W-------------------- DTL ----------------------- Execution R-------------------- ST0 -----------------------Status information after command execution R-------------------- ST1 ----------------------- R-------------------- ST2 ----------------------- R---------------------- C ------------------------Sector ID information after command execution R---------------------- H ------------------------ R---------------------- R ------------------------ R---------------------- N ------------------------ Publication Release Date: March 1999 -28 - Revision A1 Result FDD and system Data transfer between the Command codes W83977EF/ CTF PRELIMINARY (9) Format A Track PHASE R/W D7 D6 D5 D4 D3 D2 D1 D0 REMARKS CommandW 0 MFM 0 0 1 1 0 1 W 0 0 0 0 0 HDS DS1 DS0 W---------------------- N ------------------------ W--------------------- SC ----------------------- W--------------------- GPL --------------------- Gap 3 W---------------------- D ------------------------ Filler Byte ExecutionW---------------------- C ------------------------ for Each W---------------------- H ------------------------ W---------------------- R ------------------------ W---------------------- N ------------------------ R-------------------- ST0 -----------------------Status information after command execution R-------------------- ST1 ----------------------- R-------------------- ST2 ----------------------- R---------------- Undefined ------------------- R ---------------- Undefined ------------------- R ---------------- Undefined ------------------- R ---------------- Undefined ------------------- (10) Recalibrate PHASE R/W D7 D6 D5 D4 D3 D2 D1 D0 REMARKS CommandW 0 0 0 0 0 1 1 1 W 0 0 0 0 0 0 DS1 DS0 Execution Publication Release Date: March 1999 -29 - Revision A1 Interrupt Head retracted to Track 0 Command codes Result Repeat: Sector Input Sector Parameters Sectors/Cylinder Bytes/Sector Command codes W83977EF/ CTF PRELIMINARY (11) Sense Interrupt Status PHASE R/W D7 D6 D5 D4 D3 D2 D1 D0 REMARKS CommandW 0 0 0 0 1 0 0 0 R ---------------- ST0 -------------------------Status information at the end R ---------------- PCN ------------------------- (12) Specify PHASE R/W D7 D6 D5 D4 D3 D2 D1 D0 REMARKS CommandW 0 0 0 0 0 0 1 1 W| ---------SRT ----------- | --------- HUT ---------- | W |------------ HLT ----------------------------------| ND (13) Seek PHASE R/W D7 D6 D5 D4 D3 D2 D1 D0 REMARKS CommandW 0 0 0 0 1 1 1 1 W 0 0 0 0 0 HDS DS1 DS0 W-------------------- NCN ----------------------- ExecutionR (14) Configure PHASE R/W D7 D6 D5 D4 D3 D2 D1 D0 REMARKS CommandW 0 0 0 1 0 0 1 1Configure information W 0 0 0 0 0 0 0 0 W0 EIS EFIFO POLL | ------ FIFOTHR ----| W| --------------------PRETRK ----------------------- | Execution Publication Release Date: March 1999 -30 - Revision A1 Internal registers written cylinder on diskette Head positioned over proper Command codes Command codes of each seek operation Result Command code W83977EF/ CTF PRELIMINARY (15) Relative Seek PHASE R/W D7 D6 D5 D4 D3 D2 D1 D0 REMARKS CommandW 1 DIR 0 0 1 1 1 1 W 0 0 0 0 0 HDS DS1 DS0 W | -------------------- RCN ---------------------------- | (16) Dumpreg PHASE R/W D7 D6 D5 D4 D3 D2 D1 D0 REMARKS CommandW 0 0 0 0 1 1 1 0 R ----------------------- PCN-Drive 0-------------------- R ----------------------- PCN-Drive 1 ------------------- R ----------------------- PCN-Drive 2-------------------- R ----------------------- PCN-Drive 3 ------------------- R --------SRT ------------------ | --------- HUT -------- R ----------- HLT -----------------------------------| ND R ------------------------ SC/EOT ---------------------- RLOCK 0 D3 D2 D1 D0 GAP WG R0 EIS EFIFO POLL | ------ FIFOTHR -------- R-----------------------PRETRK ------------------------- (17) Perpendicular Mode PHASE R/W D7 D6 D5 D4 D3 D2 D1 D0 REMARKS CommandW 0 0 0 1 0 0 1 0 W OW 0 D3 D2 D1 D0 GAP WG (18) Lock PHASE R/W D7 D6 D5 D4 D3 D2 D1 D0 REMARKS CommandWLOCK 0 0 1 0 1 0 0 R 0 0 0 LOCK 0 0 0 0 Publication Release Date: March 1999 -31 - Revision A1 Result Command Code Command Code Result Registers placed in FIFO Command codes W83977EF/ CTF PRELIMINARY (19) Sense Drive Status PHASE R/W D7 D6 D5 D4 D3 D2 D1 D0 REMARKS CommandW 0 0 0 0 0 1 0 0 W 0 0 0 0 0 HDS DS1 DS0 R ---------------- ST3 -------------------------Status information about disk drive (20) Invalid PHASE R/W D7 D6 D5 D4 D3 D2 D1 D0 REMARKS CommandW ------------- Invalid Codes -----------------Invalid codes (no R -------------------- ST0 ----------------------ST0 = 80H Publication Release Date: March 1999 -32 - Revision A1 Result standby state) operation- FDC goes to Result Command Code W83977EF/ CTF PRELIMINARY 2.2 Register Descriptions There are several status, data, and control registers in W83977EF/CTF. These registers are defined ADDRESS REGISTER OFFSET READ WRITE SA REGISTER SB REGISTER DO REGISTER TD REGISTERTD REGISTER MS REGISTERDR REGISTER DT (FIFO) REGISTERDT (FIFO) REGISTER DI REGISTERCC REGISTER 2.2.1 Status Register A (SA Register) (Read base address + 0) This register is used to monitor several disk interface pins in PS/2 and Model 30 modes. In PS/2 mode, the bit definitions for this register are as follows: 27654310 DIR WP# INDEX# HEAD TRAK0# STEP DRV2# INIT PENDING INIT PENDING (Bit 7): This bit indicates the value of the floppy disk interrupt output. DRV2# (Bit 6): 0 1 STEP (Bit 5): This bit indicates the complement of STEP# output. TRAK0#(Bit 4): This bit indicates the value of TRAK0# input. Publication Release Date: March 1999 -33 - Revision A1 A second drive has not been installed A second drive has been installed base address + 7 base address + 5 base address + 4 base address + 3 base address + 2 base address + 1 base address + 0 below: W83977EF/ CTF PRELIMINARY HEAD (Bit 3): This bit indicates the complement of HEAD# output. 0 1 This bit indicates the value of INDEX# output. WP#(Bit 1): 0 1 DIR (Bit 0) This bit indicates the direction of head movement. 0 1 In PS/2 Model 30 mode, the bit definitions for this register are as follows: 27654310 DIR# WP INDEX HEAD# TRAK0 STEP F/F DRQ INIT PENDING INIT PENDING (Bit 7): This bit indicates the value of the floppy disk interrupt output. DRQ (Bit 6): This bit indicates the value of DRQ output pin. STEP F/F (Bit 5): This bit indicates the complement of latched STEP# output. TRAK0 (Bit 4): This bit indicates the complement of TRAK0# input. HEAD# (Bit 3): This bit indicates the value of HEAD# output. 0 1 Publication Release Date: March 1999 -34 - Revision A1 side 0 side 1 inward direction outward direction disk is not write-protected disk is write-protected INDEX#(Bit 2): side 1 side 0 W83977EF/ CTF PRELIMINARY INDEX (Bit 2): This bit indicates the complement of INDEX# output. WP (Bit 1): 0 1 DIR#(Bit 0) This bit indicates the direction of head movement. 0 1 2.2.2 Status Register B (SB Register) (Read base address + 1) This register is used to monitor several disk interface pins in PS/2 and Model 30 modes. In PS/2 mode, the bit definitions for this register are as follows: 21765430 11 WE WDATA Toggle Drive SEL0 Drive SEL0 (Bit 5): This bit indicates the status of DO REGISTER bit 0 (drive select bit 0). WDATA Toggle (Bit 4): This bit changes state at every rising edge of the WD# output pin. RDATA Toggle (Bit 3): WE (Bit 2): This bit indicates the complement of the WE# output pin. MOT EN B (Bit 1) This bit indicates the complement of the MOB# output pin. MOT EN A (Bit 0) This bit indicates the complement of the MOA# output pin. In PS/2 Model 30 mode, the bit definitions for this register are as follows: Publication Release Date: March 1999 -35 - Revision A1 This bit changes state at every rising edge of the RDATA# output pin. RDATA Toggle MOT EN B MOT EN A outward direction inward direction disk is write-protected disk is not write-protected W83977EF/ CTF PRELIMINARY 21765430 DSC# DSD# WE F/F RDATA F/F WD F/F DSA# DSB# DRV2# DRV2# (Bit 7): DSB# (Bit 6): DSA# (Bit 5): WD F/F(Bit 4): This bit indicates the complement of the latched WD# output pin at every rising edge of the WD# RDATA F/F(Bit 3): This bit indicates the complement of the latched RDATA# output pin . WE F/F (Bit 2): This bit indicates the complement of latched WE# output pin. DSD# (Bit 1): 0 Drive D has been selected 1 Drive D has not been selected DSC# (Bit 0): 0 Drive C has been selected 1 Drive C has not been selected Publication Release Date: March 1999 -36 - Revision A1 output pin. This bit indicates the status of DSA# output pin. This bit indicates the status of DSB# output pin. 1 A second drive has not been installed 0 A second drive has been installed W83977EF/ CTF PRELIMINARY 2.2.3 Digital Output Register (DO Register) (Write base address + 2) The Digital Output Register is a write-only register controlling drive motors, drive selection, DRQ/IRQ enable, and FDC resetting. All the bits in this register are cleared by the MR pin. The bit definitions 765432 2.2.4 Tape Drive Register (TD Register) (Read base address + 3) This register is used to assign a particular drive number to the tape drive support mode of the data separator. This register also holds the media ID, drive type, and floppy boot drive information of the floppy disk drive. In normal floppy mode, this register includes only bit 0 and 1. The bit definitions are 21765430 XXXXXX If three mode FDD function is enabled (EN3MODE = 1 in CR9), the bit definitions are as follows: 21765430 Publication Release Date: March 1999 -37 - Revision A1 Media ID1 Media ID0 Drive type ID1 Drive type ID0 Floppy boot drive 1 Floppy boot drive 0 Tape Sel 1 Tape Sel 0 Tape sel 1 Tape sel 0 as follows: Motor Enable D. Motor D on when active high Motor Enable C. Motor C on when active high Motor Enable B. Motor B on when active high Motor Enable A. Motor A on when active high Active high enable DRQ/IRQ DMA and INT Enable Active low resets FDC Floppy Disk Controller Reset 11 select drive D 10 select drive C 01 select drive B Drive Select: 00 select drive A 1-0 are as follows: W83977EF/ CTF PRELIMINARY Media ID1 Media ID0 (Bit 7, 6): These two bits are read only. These two bits reflect the value of CR8 bit 3, 2. Drive type ID1 Drive type ID0 (Bit 5, 4): These two bits reflect two of the bits of CR7. Which two bits are reflected depends on the last drive selected in the DO REGISTER. Floppy Boot drive 1, 0 (Bit 3, 2): These two bits reflect the value of CR8 bit 1, 0. Tape Sel 1, Tape Sel 0 (Bit 1, 0): These two bits assign a logical drive number to the tape drive. Drive 0 is not available as a tape drive and is reserved as the floppy disk boot drive. TAPE SEL 1 TAPE SEL 0 DRIVE SELECTED 00 011 102 113 2.2.5 Main Status Register (MS Register) (Read base address + 4) controller. The bit definitions for this register are as follows: 76543210 FDD 0 Busy, (D0B = 1), FDD number 0 is in the SEEK mode. FDD 1 Busy, (D1B = 1), FDD number 1 is in the SEEK mode. FDD 2 Busy, (D2B = 1), FDD number 2 is in the SEEK mode. FDD 3 Busy, (D3B = 1), FDD number 3 is in the SEEK mode. FDC Busy, (CB). A read or write command is in the process when CB = HIGH. Non-DMA mode, the FDC is in the non-DMA mode, this bit is set only during the execution phase in non-DMA mode. Transition to LOW state indicates execution phase has ended. If DIO = LOW then transfer is from processor to Data Register. Request for Master (RQM). A high on this bit indicates Data Register is ready to send or receive data to or from the processor. 2.2.6 Data Rate Register (DR Register) (Write base address + 4) The Data Rate Register is used to set the transfer rate and write precompensation. The data rate of the FDC is programmed by the CC REGISTER for PC-AT and PS/2 Model 30 and PS/2 mode, and not by the DR REGISTER. The real data rate is determined by the most recent write to either of the DR REGISTER or CC REGISTER. Publication Release Date: March 1999 -38 - Revision A1 DATA INPUT/OUTPUT, (DIO). If DIO= HIGH then transfer is from Data Register to the processor. The Main Status Register is used to control the flow of data between the microprocessor and the None W83977EF/ CTF PRELIMINARY 17654320 0 DRATE0 DRATE1 POWER DOWN S/W RESET S/W RESET (Bit 7): POWER-DOWN (Bit 6): 0 FDC in normal mode PRECOMP2 PRECOMP1 PRECOMP0 (Bit 4, 3, 2): These three bits select the value of write precompensation. The following tables show the precompensation values for the combination of these bits. PRECOMP PRECOMPENSATION DELAY 2 1 02 Mbps Tape drive 0 0 0Default DelaysDefault Delays 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 DATA RATE DEFAULT PRECOMPENSATION DELAYS 1 MB/S 2 MB/S Publication Release Date: March 1999 -39 - Revision A1 20.8 nS 41.67nS 125 nS500 KB/S 125 nS300 KB/S 125 nS250 KB/S 0.00 nS (disabled)0.00 nS (disabled) 125.00 nS250.00 nS 104.2 nS208.33 nS 83.3 nS166.67 nS 62.5nS125.00 nS 41.17 nS83.34 nS 20.8 nS41.67 nS 250K - 1 Mbps 1 FDC in power-down mode This bit is the software reset bit. PRECOMP2 PRECOMP1 PRECOMP0 W83977EF/ CTF PRELIMINARY DRATE1 DRATE0 (Bit 1, 0): 00 500 KB/S (MFM), 250 KB/S (FM), RWC#= 1 01 300 KB/S (MFM), 150 KB/S (FM), RWC#= 0 10 250 KB/S (MFM), 125 KB/S (FM), RWC#= 0 11 1 MB/S (MFM), Illegal (FM), RWC#= 1 The 2 MB/S data rate for Tape drive is only supported by setting 01 to DRATE1 and DRATE0 bits, as well as setting 10 to DRT1 and DRT0 bits, which are two of the Configure Register CRF4 or CRF5 bits in logic device 0. Please refer to the function description of CRF4 or CRF5 and data rate table for individual data rates setting. 2.2.7 FIFO Register (R/W base address + 5) The Data Register consists of four status registers in a stack, with only one register presented to the data bus at a time. This register stores data, commands, and parameters and provides diskette-drive status information. Data bytes are passed through the data register to program or obtain results after a command. In the W83977EF/CTF, this register defaults to FIFO disabled mode after reset. The FIFO can change its value and enable its operation through the CONFIGURE command. Status Register 0 (ST0) 7-65321-04 US1, US0 Drive Select: HD Head address: 1 Head selected 0 Head selected NR Not Ready: EC Equipment Check: 1 When a fault signal is received from the FDD or the track 0 signal fails to occur after 77 step pulses 0 No error SE Seek end: 0 seek error IC Interrupt Code: 00 Normal termination of command 01 Abnormal termination of command 10 Invalid command issue 11 Abnormal termination because the ready signal from FDD changed state during command execution Publication Release Date: March 1999 -40 - Revision A1 1 seek end 0 Drive is ready 1 Drive is not ready 11 Drive D selected 10 Drive C selected 01 Drive B selected 00 Drive A selected These two bits select the data rate of the FDC and reduced write current control. W83977EF/ CTF PRELIMINARY Status Register 1 (ST1) 76543210 Missing Address Mark. 1 When the FDC cannot detect the data address mark or the data address mark has been deleted. NW (Not Writable). 1 If a write Protect signal is detected from the diskette drive during execution of write data. ND (No DATA). 1 If specified sector cannot be found during execution of a read, write or verifly data. Not used. This bit is always 0. OR (Over Rum). 1 If the FDC is not serviced by the host system within a certain time interval during data transfer. DE (data Error).1 When the FDC detects a CRC error in either the ID field or the data field. Not used. This bit is always 0. EN (End of track). 1 When the FDC tries to access a sector beyond the final sector of a cylinder. Status Register 2 (ST2) 74321065 1 During execution of the Scan command SH (Scan Equal Hit) WC (Wrong Cylinder) Status Register 3 (ST3) 64210753 WP Write Protected Publication Release Date: March 1999 -41 - Revision A1 FT Fault RY Ready TO Track 0 TS Two-Side HD Head Address US1 Unit Select 1 US0 Unit Select 0 Not used. This bit is always 0 0 No error 1 During execution of the read data or scan command CM (Control Mark) 0 No error 1 If the FDC detects a CRC error in the data field DD (Data error in the Data field) 1 Indicates wrong Cylinder 0 No error 1 During execution of the Scan command, if the equal condition is satisfied 0 No error SN (Scan Not satisfied) 0 No error 1 Bad Cylinder BC (Bad Cylinder) 0 No error when reading data from the media (or the address mark has been deleted) 1 If the FDC cannot find a data address mark MD (Missing Address Mark in Data Field). W83977EF/ CTF PRELIMINARY 2.2.8 Digital Input Register (DI Register) (Read base address + 7) The Digital Input Register is an 8-bit read-only register used for diagnostic purposes. In a PC/XT or AT only Bit 7 is checked by the BIOS. When the register is read, Bit 7 shows the complement , while other bits of the data bus remain in tri-state. Bit definitions are as follows: 76543210 xxxxxxx x DSKCHG In the PS/2 mode, the bit definitions are as follows: 76543201 1111 HIGH DENS# DRATE0 DRATE1 DSKCHG DSKCHG (Bit 7): This bit indicates the complement of the DSKCHG# input. DRATE1 DRATE0 (Bit 2, 1): These two bits select the data rate of the FDC. Refer to the DR register bits 1 and 0 for the settings HIGHDENS#(Bit 0): 0 500 KB/S or 1 MB/S data rate (high density FDD) 1 250 KB/S or 300 KB/S data rate Publication Release Date: March 1999 -42 - Revision A1 corresponding to the individual data rates. Bit 6-3: These bits are always a logic 1 during a read. During a read of this register, these bits are in tri-state Reserved for the hard disk controller ofDSKCHG# W83977EF/ CTF PRELIMINARY In the PS/2 Model 30 mode, the bit definitions are as follows: 76543201 000 DRATE0 DRATE1 NOPREC DMAEN DSKCHG# DSKCHG (Bit 7): DMAEN (Bit 3): This bit indicates the value of DO REGISTER bit 3. NOPREC (Bit 2): This bit indicates the value of CC REGISTER NOPREC bit. DRATE1 DRATE0 (Bit 1, 0): 2.2.9 Configuration Control Register (CC Register) (Write base address + 7) This register is used to control the data rate. In the PC/AT and PS/2 mode, the bit definitions are as 43217650 xxxxxx X: Reserved DRATE1 DRATE0 (Bit 1, 0): In the PS/2 Model 30 mode, the bit definitions are as follows: Publication Release Date: March 1999 -43 - Revision A1 These two bits select the data rate of the FDC. Bit 7-2: Reserved. These bits should be set to 0. DRATE1 DRATE0 follows: These two bits select the data rate of the FDC. Bit 6-4: These bits are always a logic 1 during a read. This bit indicates the status of DSKCHG# input. W83977EF/ CTF PRELIMINARY 21765430 XXXXX NOPREC X: NOPREC (Bit 2): DRATE1 DRATE0 (Bit 1, 0): Publication Release Date: March 1999 -44 - Revision A1 These two bits select the data rate of the FDC. This bit indicates no precompensation. It has no function and can be set by software. Bit 7-3: Reserved. These bits should be set to 0. Reserved DRATE1 DRATE0 W83977EF/ CTF PRELIMINARY 3.0 UART PORT 3.1 Universal Asynchronous Receiver/Transmitter (UART A, UART B) The UARTs are used to convert parallel data into serial format on the transmit side, and convert serial data to parallel format on the receiver side. The serial format, in order of transmission and reception, is a start bit, followed by five to eight data bits, a parity bit (if programmed) and one, one and half (five-bit format only) or two stop bits. The UARTs are capable of handling divisors of 1 to 65535 and producing a 16x clock for driving the internal transmitter logic. Provisions are also included to use this 16x clock to drive the receiver logic. The UARTs also support the MIDI data rate. Furthermore, the UARTs also include complete modem control capability, and a processor interrupt system that may be software trailed to the computing time required to handle the communication link. The UARTs have a FIFO mode to reduce the number of interrupts presented to the CPU. In each UART, there are 16-byte FIFOs for both receive and transmit mode. 3.2 Register Address 3.2.1 UART Control Register (UCR) (Read/Write) Control Register controls and defines the protocol for asynchronous data communications, 76543210 Data length select bit 0 (DLS0) Data length select bit 1(DLS1) Multiple stop bits enable (MSBE) Parity bit enable (PBE) Even parity enable (EPE) Parity bit fixed enable (PBFE) Set silence enable (SSE) Baudrate divisor latch access bit (BDLAB) Bit 7: BDLAB. When this bit is set to a logical 1, designers can access the divisor (in 16-bit binary format) from the divisor latches of the baudrate generator during a read or write operation. When this bit is reset, the Receiver Buffer Register, the Transmitter Buffer Register, or the Bit 6: SSE. A logical 1 forces the Serial Output (SOUT) to a silent state (a logical 0). Only IRTX is affected by this bit; the transmitter is not affected. Bit 5: PBFE. When PBE and PBFE of UCR are both set to a logical 1, (1) if EPE is logical 1, the parity bit is fixed as logical 0 to transmit and check. (2) if EPE is logical 0, the parity bit is fixed as logical 1 to transmit and check. Publication Release Date: March 1999 -45 - Revision A1 Interrupt Control Register can be accessed. including data length, stop bit, parity, and baud rate selection. The UART W83977EF/ CTF PRELIMINARY Bit Number Register Address Base 0 1 2 3 4 5 6 7 RRBR B R TTBR B ( IICRTBR USRHSR0000 R (EUSRI)(EHSRI) (ERDRI)(ETBREI) I"0" if00FIFOsFIFOs R () **** UARTUFRRCVR C R UARTUCR R (PBE)(EPE)(SSE) HHCRIRQ000 CRI R (DTR)(RTS) UART SUSRTBRTSR R (RDR)(OER)(PBER)(TBRE)(TSRE) (NSER)(SBD) HHSRCTSDSRDCD S (DCD) (TCTS)(TDSR)(TDCD)(CTS)(DSR)(RI) UUDR R B L D H Publication Release Date: March 1999 -46 - Revision A1 **: These bits are always 0 in 16450 Mode. *: Bit 0 is the least significant bit. The least significant bit is the first bit serially transmitted or received. igh BDLAB = 1 atch Livisor Bit 15Bit 14Bit 13Bit 12Bit 11Bit 10Bit 9Bit 8BHLaudrate B+ 1 BDLAB = 1 ow Latch Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0BLLivisor Daudrate+ 0 egister Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0efined Dser+ 7 (FERI) DetectIndicatorReadyto SendTogglingEdgeTogglingTogglingegister Rtatus Data CarrierRingData SetClearRI Fallingandshake+ 6 (RFEI) ** IndicationDetectedError ErrorEmptyEmptyByteBitErrorErrorReadyegister RX FIFOSilentNo StopParity BitOverrunRBR Datatatus+ 5 EnableInputSendReadyegister LoopbackEnabletoTerminalontrol InternalLoopbackRequestDataandshake+ 4 (BDLAB)(DLS1)(DLS0) PBFE)(MSBE) Access BitBit 1Bit 0 LatchEnableEnableEnableEnableEnableSelectSelect DivisorSilenceBit FixedParityBitStop BitsLengthLengthegister BaudrateSetParityEvenParityMultipleDataDataontrol C+ 3 (MSB)(LSB)(Write Only) Active LevelActive LevelSelectResetResetegister InterruptInterruptModeFIFOFIFOEnableontrol RXRXReversedReservedDMAXMITFIFO FIFO+ 2 Bit (2)**Bit (1)Bit (0) PendingRead Only EnabledEnabled StatusStatusStatusInterruptegister InterruptInterruptInterruptISRtatus Snterrupt+ 2 EnableEnable EnableEnableInterruptInterrupt BDLAB = 0 Interrupt InterruptEmptyReadyegister RBR Dataontrol Cnterrupt+ 1 Write Only) Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0BDLAB = 0 egister Ruffer TX DataTX DataTX DataTX DataTX DataTX DataTX DataTX Dataransmitter+ 0 (Read Only) egister Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0BDLAB = 0 uffer RX DataRX DataRX DataRX DataRX DataRX DataRX DataRX Dataeceiver+ 0 TABLE 3-1 UART Register Bit Map W83977EF/ CTF PRELIMINARY Bit 4: EPE. This bit describes the number of logic 1's in the data word bits and parity bit only when bit 3 is programmed. When this bit is set, an even number of logic 1's are sent or checked. When Bit 3: PBE. When this bit is set, the position between the last data bit and the stop bit of the SOUT will be stuffed with the parity bit at the transmitter. For the receiver, the parity bit in the same Bit 2: MSBE. This bit defines the number of stop bits in each serial character that is transmitted or received. (2) If MSBE is set to a logical 1, and data length is 5 bits, one and a half stop bits are sent and (3) If MSBE is set to a logical 1, and data length is 6, 7, or 8 bits, two stop bits are sent and Bits 0 and 1: DLS0, DLS1. These two bits define the number of data bits that are sent or checked in TABLE 3-2 WORD LENGTH DEFINITION DLS1 DLS0 DATA LENGTH 00 01 10 11 Publication Release Date: March 1999 -47 - Revision A1 8 bits 7 bits 6 bits 5 bits each serial character. checked. checked. (1) If MSBE is set to a logical 0, one stop bit is sent and checked. position as the transmitter will be detected. the bit is reset, an odd number of logic 1's are sent or checked. W83977EF/ CTF PRELIMINARY 3.2.2 UART Status Register (USR) (Read/Write) This 8-bit register provides information about the status of the data transfer during communication. 27643105 RBR Data ready (RDR) Overrun error (OER) Parity bit error (PBER) No stop bit error (NSER) Silent byte detected (SBD) Transmitter Buffer Register empty (TBRE) Transmitter Shift Register empty (TSRE) RX FIFO Error Indication (RFEI) Bit 7: RFEI. In 16450 mode, this bit is always set to a logic 0. In 16550 mode, this bit is set to a logic 1 when there is at least one parity bit error, no stop bit error or silent byte detected in the FIFO. In 16550 mode, this bit is cleared by reading from the USR if there are no remaining errors left in the FIFO. Bit 6: TSRE. In 16450 mode, when TBR and TSR are both empty, this bit will be set to a logical 1. In 16550 mode, if the transmit FIFO and TSR are both empty, it will be set to a logical 1. Other Bit 5: TBRE. In 16450 mode, when a data character is transferred from TBR to TSR, this bit will be set to a logical 1. If ETREI of ICR is a logical 1, an interrupt will be generated to notify the CPU to write the next data. In 16550 mode, this bit will be set to a logical 1 when the transmit FIFO is empty. It will be reset to a logical 0 when the CPU writes data into TBR or FIFO. Bit 4: SBD. This bit is set to a logical 1 to indicate that received data are kept in silent state for a full word time, including start bit, data bits, parity bit, and stop bits. In 16550 mode, it indicates the same condition for the data on top of the FIFO. When the CPU reads USR, it will clear this bit to a logical 0. Bit 3: NSER. This bit is set to a logical 1 to indicate that the received data have no stop bit. In 16550 mode, it indicates the same condition for the data on top of the FIFO. When the CPU reads USR, it will clear this bit to a logical 0. Bit 2: PBER. This bit is set to a logical 1 to indicate that the parity bit of received data is wrong. In 16550 mode, it indicates the same condition for the data on top of the FIFO. When the CPU reads USR, it will clear this bit to a logical 0. Bit 1: OER. This bit is set to a logical 1 to indicate received data have been overwritten by the next received data before they were read by the CPU. In 16550 mode, it indicates the same condition instead of FIFO full. When the CPU reads USR, it will clear this bit to a logical 0. Bit 0: RDR. This bit is set to a logical 1 to indicate received data are ready to be read by the CPU in the RBR or FIFO. After no data are left in the RBR or FIFO, the bit will be reset to a logical 0. Publication Release Date: March 1999 -48 - Revision A1 than in these two cases, this bit will be reset to a logical 0. W83977EF/ CTF PRELIMINARY 3.2.3 Handshake Control Register (HCR) (Read/Write) This register controls the pins of the UART used for handshaking peripherals such as modem, and controls the diagnostic mode of the UART. 27543106 000 Data terminal ready (DTR) Request to send (RTS) Loopback RI input IRQ enable Internal loopback enable Bit 4: When this bit is set to a logical 1, the UART enters diagnostic mode by an internal loopback, as (1) SOUT is forced to logical 1, and SIN is isolated from the communication link instead of the TSR. (2) Modem output pins are set to their inactive state. (3) Modem input pins are isolated from the communication link and connect internally as DTR (bit 0 of HCR) ®DSR#, RTS ( bit 1 of HCR) ®CTS#, Loopback RI input ( bit 2 of HCR) ® RI#and IRQ enable ( bit 3 of HCR) ® Aside from the above connections, the UART operates normally. This method allows the CPU to test the UART in a convenient way. Bit 3: The UART interrupt output is enabled by setting this bit to a logic 1. In the diagnostic mode this bit is internally connected to the modem control input DCD#. Bit 2: This bit is used only in the diagnostic mode. In the diagnostic mode this bit is internally connected to the modem control input RI#. Bit 1: This bit controls the RTS# output. The value of this bit is inverted and output to RTS#. Bit 0: This bit controls the DTR# output. The value of this bit is inverted and output to DTR#. 3.2.4 Handshake Status Register (HSR) (Read/Write) This register reflects the current state of four input pins for handshake peripherals such as a modem, Publication Release Date: March 1999 -49 - Revision A1 and records changes on these pins. DCD#. follows: W83977EF/ CTF PRELIMINARY 76543210 toggling (TCTS) CTS# toggling (TDSR) DSR# RI falling edge (FERI) toggling (TDCD) DCD# Clear to send (CTS) Data set ready (DSR) Ring indicator (RI) Data carrier detect (DCD) Bit 7: This bit is the opposite of the DCD# input. This bit is equivalent to bit 3 of HCR in loopback mode. Bit 6: This bit is the opposite of the RI # input. This bit is equivalent to bit 2 of HCR in loopback mode. Bit 5: This bit is the opposite of the DSR# input. This bit is equivalent to bit 0 of HCR in loopback mode. Bit 4: This bit is the opposite of the CTS# input. This bit is equivalent to bit 1 of HCR in loopback mode. Bit 2: FERI. This bit indicates that the RI # pin 3.2.5 UART FIFO Control Register (UFR) (Write only) This register is used to control the FIFO functions of the UART. 21765430 FIFO enable Receiver FIFO reset Transmitter FIFO reset DMA mode select Reserved Reserved RX interrupt active level (LSB) RX interrupt active level (MSB) Bit 6, 7: These two bits are used to set the active level for the receiver FIFO interrupt. For example, if the interrupt active level is set as 4 bytes, once there are more than 4 data characters in the receiver FIFO, the interrupt will be activated to notify the CPU to read the data from the FIFO. Publication Release Date: March 1999 -50 - Revision A1 Bit 0: TCTS. This bit indicates that the CTS# pin has changed state after HSR was read. Bit 1: TDSR. This bit indicates that the DSR# pin has changed state after HSR was read by the CPU. read by the CPU. has changed from low to high state after HSR was Bit 3: TDCD. This bit indicates that the DCD# pin has changed state after HSR was read by the CPU. W83977EF/ CTF PRELIMINARY TABLE 3-3 FIFO TRIGGER LEVEL BIT 7 BIT 6 RX FIFO INTERRUPT ACTIVE LEVEL (BYTES) 00 01 10 11 Bit 4, 5: Bit 3:When this bit is programmed to logic 1, the DMA mode will change from mode 0 to mode 1 if UFR bit 0 = 1. Bit 2: Setting this bit to a logical 1 resets the TX FIFO counter logic to initial state. This bit will clear to a logical 0 by itself after being set to a logical 1. Bit 1: Setting this bit to a logical 1 resets the RX FIFO counter logic to initial state. This bit will clear to a logical 0 by itself after being set to a logical 1. Bit 0: This bit enables the 16550 (FIFO) mode of the UART. This bit should be set to a logical 1 before other bits of UFR are programmed. 3.2.6 Interrupt Status Register (ISR) (Read only) This register reflects the UART interrupt status, which is encoded by different interrupt sources into 3 76543210 00 0 if interrupt pending Interrupt Status bit 0 Interrupt Status bit 1 Interrupt Status bit 2 FIFOs enabled FIFOs enabled Bit 7, 6: Bit 5, 4: Bit 3: In 16450 mode, this bit is 0. In 16550 mode, both bit 3 and 2 are set to a logical 1 when a time- Bit 2, 1: These two bits identify the priority level of the pending interrupt, as shown in the table below. Bit 0: This bit is a logical 1 if there is no interrupt pending. If one of the interrupt sources has occurred, this bit will be set to a logical 0. Publication Release Date: March 1999 -51 - Revision A1 out interrupt is pending. These two bits are always logic 0. These two bits are set to a logical 1 when UFR bit 0 = 1. bits. Reserved 14 08 04 01 W83977EF/ CTF PRELIMINARY ISR INTERRUPT SET AND FUNCTION 3210 0001-- 0110 0100 1100 0010 0000 3.2.7 Interrupt Control Register (ICR) (Read/Write) This 8-bit register allows the five types of controller interrupts to activate the interrupt output signal separately. The interrupt system can be totally disabled by resetting bits 0 through 3 of the Interrupt Control Register (ICR). A selected interrupt can be enabled by setting the appropriate bits of this register to a logical 1. 53764210 0000 RBR data ready interrupt enable (ERDRI) TBR empty interrupt enable (ETBREI) UART receive status interrupt enable (EUSRI) Handshake status interrupt enable (EHSRI) Bit 2: EUSRI. Setting this bit to a logical 1 enables the UART status register interrupt. Bit 1: ETBREI. Setting this bit to a logical 1 enables the TBR empty interrupt. Bit 0: ERDRI. Setting this bit to a logical 1 enables the RBR data ready interrupt. Publication Release Date: March 1999 -52 - Revision A1 Bit 3: EHSRI. Setting this bit to a logical 1 enables the handshake status register interrupt. Bit 7-4: These four bits are always logic 0. ** Bit 3 of ISR is enabled when bit 0 of UFR is logical 1. 3. FERI = 1 4. TDCD = 1 Read HSR1. TCTS = 1 2. TDSR = 1Handshake statusFourth third) 2. Read ISR (if priority is 1. Write data into TBRTBR emptyTBR EmptyThird access of RX FIFO. characters period of time since last Read RBRData present in RX FIFO for 4FIFO Data TimeoutSecond data under active level reached 2. Read RBR until FIFO2. FIFO interrupt active level 1. Read RBR1. RBR data readyRBR Data ReadySecond 3. NSER = 1 4. SBD = 1 Status Read USR1. OER = 1 2. PBER =1UART ReceiveFirst No Interrupt pending - priority Clear InterruptInterrupt SourceInterrupt TypeInterruptBitBitBitBit TABLE 3-4 INTERRUPT CONTROL FUNCTION W83977EF/ CTF PRELIMINARY 3.2.8 Programmable Baud Generator (BLL/BHL) (Read/Write) Two 8-bit registers, BLL and BHL, compose a programmable baud generator that uses 24 MHz to generate a 1.8461 MHz frequency and divides it by a divisor from 1 to 2-1. The output frequency of the baud generator is the baud rate multiplied by 16, and this is the base frequency for the transmitter and receiver. The table in the next page illustrates the use of the baud generator with a frequency of 1.8461 MHz. In high-speed UART mode (refer to CR0C bit7 and CR0C bit6), the programmable baud generator directly uses 24 MHz and the same divisor as the normal speed divisor. In high- 3.2.9 User-defined Register (UDR) (Read/Write) BAUD RATE FROM DIFFERENT PRE-DIVIDER Pre-Div: 13Pre-Div:1.625Pre-Div: 1.0 Decimal divisor used clock 2304 1536 1047 857 768 384 192 96 64 58 48 32 24 16 12 6 3 2 1 Publication Release Date: March 1999 -53 - Revision A1 Note. Pre-Divisor is determined by CRF0 of UART A and B. ** The percentage error for all baud rates, except where indicated otherwise, is 0.16%. **1497600921600115200 **74880046080057600 **49920030720038400 **24960015360019200 **124800768009600 **93600576007200 **62400384004800 **46800288003600 **31200192002400 0.53%26000160002000 **23400144001800 **1560096001200 **78004800600 **39002400300 **19501200150 0.099%1478.51076134.5 0.18%1430880110 **97560075 **65040050 24M Hz14.769M Hz1.8461M Hz desired and actualto generate 16X Error Percentage between TABLE 3-5 BAUD RATE TABLE This is a temporary register that can be accessed and defined by the user. speed mode, the data transmission rate can be as high as 1.5 Mbps. 16 W83977EF/ CTF PRELIMINARY 4.0 INFRARED (IR) PORTS 4.1 IR PORT The Infrared (IR) function provides point-to-point (or multi-point to multi-point) wireless communication which can operate under various transmission protocols including IrDA 1.0 SIR, SHARP ASK-IR. IR port shares the same port with UART B port in W83977EF/CTF. Please refer to section 11.5 for configuration information. 4.2 CIR PORT(For W83977CTF only) The CIR port of the W83977CTF is an independent device, and supports an T-period mode, Over- sampling mode and Over-sampling mode with re-sync for demodulation of cir signal. Refer to the configuration registers for more information on disabling, address selecting and IRQ selectiing .The 4.2.1 Bank0.Reg0 - Receiver Buffer Registers (RBR) (Read) Receiver Buffer Register is read only. When the CIR pulse train has been detected and passed by the internal signal filter, the data samped and shifted into shifter register will write into Receiver Buffer 4.2.2 Bank0.Reg1 - Interrupt Control Register (ICR) Bit Name Read/Write Description 7Read/WriteEnable Global Interrupt. Write 1, enable interrupt. Write 0, disable global interrupt. - 2Read/WriteEnable Timer Interrupt. 1Read/Write 0Read/WriteReceiver Thershold-Level Interrupt Enable. Publication Release Date: March 1999 -54 - Revision A1 EN_RX_I Enable Line-Status-Register interrupt.En_LSR_I EN_TMR_I ReservedReserved6-3 EN_GLBI Power on default <7:0> = 00000000 binary Register. In the CIR, this port only supports PIO mode and the address port is defined in the PnP. function of each CIR register is described below. W83977EF/ CTF PRELIMINARY 4.2.3 Bank0.Reg2 - Interrupt Status Register (ISR) Bit Name Read/Write Description - 2TMR_ITimer Interrupt. Set to 1 when timer count to 0. This bit will be affected by (1) the timer registers are defined in Bank4.Reg0 and Bank1.Reg0~1, (2) EN_TMR(Enable Timer, in Bank0.Reg3.Bit2) should be set to 1, (3) ENTMR_I (Enable Timer Interrupt, in Bank0.Reg1.Bit2) 1Line-Status-Register interrupt. Set to 1 when overrun, or time out, or RBR Ready in the Line Status Register 0Receiver Thershold-Level Interrupt. Set to 1 when (1) the Receiver Buffer Register (RBR) is equal or larger than the threshold level, (2) RBR occurs time-out if the receiver buffer register has valid data and below the threshold level. Clear to 0 when RBR is less than threshold level from reading RBR. Publication Release Date: March 1999 -55 - Revision A1 Read OnlyRXTH_I (LSR) sets to 1. Clear to 0 when LSR is read. Read OnlyLSR_I should be set to 1. Read Only ReservedReserved7-3 Power on default <7:0> = 00000000 binary W83977EF/ CTF PRELIMINARY 4.2.4 Bank0~3.Reg3 - CIR Control Register 0/Bank Select Register (CTR0/BSR) (BANK0~3) Bit Name Read/Write Description Read/WriteBank Select Register. These two bits share the same address so that Bank Select Register (BSR) can be BNK_SEL<1:0> = 00 Select Bank 0. BNK_SEL<1:0> = 01 Select Bank 1. BNK_SEL<1:0> = Reserved. BNK_SEL<1:0> = Reserved. Read/WriteReceiver FIFO Threshold Level. It sets the RXTH_I to become 1 when the Receiver FIFO Threshold Level is RXFTL<1:0> = 00 -- 1 byte 3TMR_TSTRead/WriteTimer Test. Write to 1, then reading the TMRL/TMRH will return the programmed values of TMRL/TMRH, that is, it does not return down count counter value. This bit is for test timer register. 2Read/WriteEnable timer. Write to 1, enable the timer 1Read/WriteSetting this bit to a logical 1 resets the RX FIFO counter logic to initial state. This bit will clear to a logical 0 by itself after being set to a logical 1. 0Read/WriteTimer input clock. TMR_CLK = 0, input clock set to 1K Hz. TMR_CLK = 1, input clock set to 24M Hz. This clock is Publication Release Date: March 1999 -56 - Revision A1 tested by Winbond. Do not publish. TMR_CLK RXF_RST EN_TMR RXFTL<1:0> = 11 -- 14 bytes RXFTL<1:0> = 10 -- 8 bytes RXFTL<1:0> = 01 -- 4 bytes equal or larger than the defined value shown as follows. RXFTL1/05-4 programmed to desired Bank in any Bank. BNK_SEL<1:0>7-6 Power on default <7:0> = 00000000 binary W83977EF/ CTF PRELIMINARY 4.2.5 Bank0.Reg4 - CIR Control Register (CTR) Bit Name Read/Write Description Read/WriteReceiver Frequency Range 2~0. These bits select the input frequency of the receiver ranges. For the input signal, that is through a band pass filter, i.e., if the frequency of the input signal is located at this defined range then the signal will be received. Read/WriteReceiver Frequency Select 4~0. Select the receiver RX_FR2~0 (Low Frequency) 001 010 011 RX_FSL4~0 Min. Max. Min. Max. Min. Max. 0001026.129.624.731.723.434.2 28.232.026.734.325.336.9 00011 29.433.327.835.726.338.4 00100 30.034.028.436.526.939.3 00101 0011031.435.629.638.128.141.0 0011132.136.430.339.028.742.0 0100032.837.231.039.829.442.9 33.6* 38.1*31.740.830.144.0 01001 34.439.032.541.830.845.0 01011 36.241.034.244.032.447.3 01100 0110137.242.135.145.133.248.6 0111138.243.236.046.334.149.9 1000040.345.738.149.036.152.7 41.547.139.250.437.254.3 10010 42.848.540.451.938.356.0 10011 44.150.041.753.639.557.7 10101 1011145.551.643.055.340.759.6 1101048.755.246.059.143.663.7 1101150.457.147.661.245.165.9 54.361.551.365.948.671.0 11101 Publication Release Date: March 1999 -57 - Revision A1 Note that the other non-defined values are reserved. Table: Low Frequency range select of receiver. operation frequency. RX_FSL<4:0>4-0 RX_FR<2:0>7-5 Power on default <7:0> = 0010,1001 binary W83977EF/ CTF PRELIMINARY 4.2.6 Bank0.Reg5 - UART Line Status Register (USR) Bit Name Read/Write Description -- 2Read/WriteSet to 1 when receiver FIFO or frame status FIFO occurs time-out. Read this bit to clear. 1Read/WriteReceived FIFO overrun. Read to clear. 0Read/WriteThis bit is set to a logical 1 to indicate received data are ready to be read by the CPU in the RBR or FIFO. After no data are left in the RBR or FIFO, the bit will be reset to a logical 0. 4.2.7 Bank0.Reg6 - Remote Infrared Config Register (RIR_CFG) Bit Name Read/Write Description Sampling Mode Select. Select internal decoder SMPSEL<1:0>Read/Write methodology from the internal filter. Selected decoder mode will determine the receive data format. The SMPSEL<1:0> = 00 T-Period Sample Mode. SMPSEL<1:0> = 01 Over-Sampling Mode. SMPSEL<1:0> = 10 Over-Sampling with re-sync. SMPSEL<1:0> = 11 FIFO Test Mode. The T-period code format is defined as follows. (Number of bits) - 1 B7 B6 B5 B4 B3 B2 B1 B0 Bit value The Bit value is set to 0, when the low signal will be received. The Bit value is set to 1, when the high signal will be received. The opposite results will be generated Publication Release Date: March 1999 -58 - Revision A1 when the bit RXINV (Bank0.Reg6.Bit0) is set to 1. sampling mode is shown bellow: 7-6 Power on default <7:0> = 0000,0000 binary RDR OV_ERR RX_TO Reserved7-3 Power on default <7:0> = 0000,0000 binary W83977EF/ CTF PRELIMINARY Bit Name Read/Write Description Read/Write LP_SL<1:0> = 01 Select R.B.P. signal LP_SL<1:0> = 10 Select D.B.P. signal. Receiver Demodulation Source Selection. Read/Write RXDMSL<1:0> = 00 select B.P. and L.P. filter. RXDMSL<1:0> = 01 select B.P. but not L.P. Baud Rate Pre-divisor. Set to 0, the baud rate 1Read/Write generator input clock is set to 1.8432M Hz which is set to pre-divisor into 13. When set to 0, the pre-divisor is set to 1, that is, the input clock of baud rate generator is Receiving Signal Invert. Write to 1, Invert the receiving0Read/Write 4.2.8 Bank0.Reg7 - User Defined Register (UDR/AUDR) Bit Name Read/Write Description 7Read/WriteReceive Active. Set to 1 whenever a pulse or pulse- train is detected by the receiver. If a 1 is written into the bit position, the bit is cleared and the receiver is de- actived. When this bit is set, the receiver samples the IR input continuously at the programmed baud rate and transfers the data to the receiver FIFO. 6Set to 1 whenever a pulse or pulse-train (modulated pulse) is detected by the receiver. Can be used by the 5-- FIFO Level Value. Indicates how many bytes there are in the current received FIFO. Can read these bits then get the FIFO level value and successively read RBR by the prior value. Publication Release Date: March 1999 -59 - Revision A1 Read OnlyFOLVAL4-0 Reserved sofware to detect idle condition. Cleared Upon Read. Read OnlyRX_PD RXACT Power on default <7:0> = 0000,0000 binary signal. RXINV set to 24M Hz. PRE_DIV RXDMSL<1:0> = 11 do not pass demodulation. RXDMSL<1:0> = 10 Reserved. RXDMSL<1:0>3-2 LP_SL<1:0> = 11 Reserved. LP_SL<1:0> = 00 Select raw IRRX signal. LP_SL<1:0>5-4 Low pass filter source selcetion. 4.2.7 Bank0.Reg6 - Remote Infrared Config Register (RIR_CFG), continued W83977EF/ CTF PRELIMINARY 4.2.9 Bank1.Reg0~1 - Baud Rate Divisor Latch (BLL/BHL) The two registers of BLL and BHL are baud rate divisor and are the same as for the legacy UART port. The table below illustrates the use of the baud generator with a frequency of 18,461 Mhz. The output frequency of the baud generator is the baud rate multiplied by 16. In high-speed UART mode (relies to Bank 0, Reg 6, Bit 1) the programmable baud generator directly uses 24 Mhz and the same BAUD RATE USING 24 MHZ TO GENERATE 1.8461 MHZ Decimal divisor used to 6 3 2 1 1 Publication Release Date: March 1999 -60 - Revision A1 ** The percentage error for all baud rates, except where indicated otherwise, is 0.16% Note 1: Only use in high speed mode, when Bank0.Reg6.Bit1 is set. 0%1.5M Note 1 **115200 **57600 ** 38400 **19200 **129600 **167200 **244800 **323600 **482400 0.53%582000 **641800 **961200 **192600 **384300 **768150 0.099%857134.5 0.18%1047110 **153675 **230450 desired and actualgenerate 16X clock Percent error difference between Desired Baud Rate TABLE 3-5 BAUD RATE TABLE divisor. In high-speed mode, the baud rate can be as high as 1.5 M bps. W83977EF/ CTF PRELIMINARY 4.2.10 Bank1.Reg2 - Version ID Regiister I (VID) Bit Name Read/Write Description Version ID, default is set to 0x10. 4.2.11 Bank0~3.Reg3 - CIR Control Register 0/Bank Select Register (CTR0/BSR) (BANK0~3) 4.2.12 Bank1.Reg4 - Timer Low Byte Register (TMRL) Bit Name Read/Write Description Read/WriteTimer Low Byte Register. This is a 12-bit timer (another 4-bit is defined in Bank1.Reg5) for which resolution is 1 ms, that is, the programmed maximum time is 2 ms. The timer is a down-counter. The timer starts down count when the bit EN_TMR (Enable Timer) of zero and EN_TMR=1, the TMR_I is set to 1. When the counter down counts to zero, a new initial value will be re-loaded into the timer counter. 4.2.13 Bank1.Reg5 - Timer High Byte Register (TMRH) Bit Name Read/Write Description Read/Write Publication Release Date: March 1999 -61 - Revision A1 Timer High Byte Register. See Bank1.Reg4.TMRH3-0 Reserved.Reserved7-4 Power on default <7:0> = 0000,0000 binary Bank0.Reg2. is set to 1. When the timer down counts to -1 12 TMRL7-0 Power on default <7:0> = 0000,0000 binary This register is defined same as in Bank0.Reg3. Read OnlyVID7-0 Power on default <7:0> = 0001,0000 binary W83977EF/ CTF PRELIMINARY 4.3 Demodulation Block Diagram Low Pass Filter Demodulation Selection Source LP_SL<1:0> Selection RXDMSL<1:0> 00 01Low Pass BandMUX00 CIRRX Filter Pass Demod.10 Filter SamplingShifter Block (B.P.) &01& RX MUXHold FIFO 10 11 Baud RateSampling Clock Generator Publication Release Date: March 1999 -62 - Revision A1 W83977EF/ CTF PRELIMINARY 5.0 PARALLEL PORT 5.1 Printer Interface Logic The parallel port of the W83977EF/CTF makes possible the attachment of various devices that accept eight bits of parallel data at standard TTL level. The W83977EF/CTF supports an IBM XT/AT compatible parallel port (SPP), bi-directional parallel port (BPP), Enhanced Parallel Port (EPP), Extended Capabilities Parallel Port (ECP), Extension FDD mode (EXTFDD). and Extension 2FDD mode (EXT2FDD) on the parallel port. Refer to the configuration registers for more information on Table 5-1 shows the pin definitions for different modes of the parallel port. TABLE 5-1-1 PARALLEL PORT CONNECTOR AND PIN DEFINITIONS PIN NUMBER HOST PIN OF SPP EPP ECP CONNECTOR ATTRIBUTE W83977EF/CTF 2 1OnSTBnWrite 2 I 2 InWait 2 I 2 ISLCT 2 O 12 InERR 12 OnINITnINIT 12 O Publication Release Date: March 1999 -63 - Revision A1 3. For more information, refer to the IEEE 1284 standard. 2. High Speed Mode 1. Compatible Mode n : Active Low Notes: , ECPModenSLINnAStrbnSLIN3217 , nReverseRqstnInit3316 , nPeriphRequestnFaultnError3415 nAFD, HostAcknDStrbnAFD3514 SLCT, XflagSelect1813 PEerror, nAckReversePEPE1912 BUSY, PeriphAckBUSY2111 nACK, PeriphClkIntrnACK2210 PD<0:7>PD<0:7>PD<0:7>I/O31-26, 24-232-9 nSTB, HostClk36 disabling, power-down, and on selecting the mode of operation. W83977EF/ CTF PRELIMINARY TABLE 5-1-2 PARALLEL PORT CONNECTOR AND PIN DEFINITIONS HOST PIN NUMBER OF PIN SPP PIN EXT2FDD PIN EXTFDD CONNECTOR W83977EF/CTF ATTRIBUTE ATTRIBUTE ATTRIBUTE 1OnSTB------------ 2II 3II 4IWP2#IWP2# 5IRDATA2#IRDATA2# 6IDSKCHG2#IDSKCHG2# 7--------- 8OD--- 9OD--- IODOD IODOD IODWD2#ODWD2# ISLCTODWE2#ODWE2# OODRWC2#ODRWC2# InERRODOD OnINITODOD OODSTEP2#ODSTEP2# 5.2 Enhanced Parallel Port (EPP) TABLE 5-2 PRINTER MODE AND EPP REGISTER ADDRESS A2 A1 A0 REGISTER NOTE 000Data port (R/W)1 0011 010Printer control latch (Write)1 0101 0112 100EPP data port 0 (R/W)2 101EPP data port 1 (R/W)2 110EPP data port 2 (R/W)2 111EPP data port 2 (R/W)2 Publication Release Date: March 1999 -64 - Revision A1 2. These registers are available only in EPP mode. 1. These registers are available in all modes. Notes: EPP address port (R/W) Printer control swapper (Read) Printer status buffer (Read) nSLIN3217 DIR2#DIR2#3316 HEAD2#HEAD2#3415 nAFD3514 1813 PE1912 MOB2#MOB2#BUSY2111 DSB2#DSB2#nACK2210 ---DSA2#PD7I/O23 ---MOA2#PD6I/O24 ---PD5I/O26 PD4I/O27 PD3I/O28 PD2I/O29 TRAK02#TRAK02#PD1I/O30 INDEX2#INDEX2#PD0I/O31 36 W83977EF/ CTF PRELIMINARY 5.2.1 Data Swapper The system microprocessor can read the contents of the printer's data latch by reading the data 5.2.2 Printer Status Buffer The system microprocessor can read the printer status by reading the address of the printer status buffer. The bit definitions are as follows: 76543210 11 TMOUT ERROR# SLCT ACK# BUSY# Bit 7: This signal is active during data entry, when the printer is off-line during printing, when the print head is changing position, or during an error state. When this signal is active, the printer is Bit 6: This bit represents the current state of the printer's ACK# signal. A 0 means the printer has received a character and is ready to accept another. Normally, this signal will be active for approximately 5 BUSY# Bit 4: Logical 1 means the printer is selected. Bit 0: This bit is valid in EPP mode only. It indicates that a 10 mS time-out has occurred on the EPP bus. A logic 0 means that no time-out error has occurred; a logic 1 means that a time-out error has been detected. Writing a logic 1 to this bit will clear the time-out status bit; writing a logic 0 has no effect. Publication Release Date: March 1999 -65 - Revision A1 Bit 1, 2: These two bits are not implemented and are logic one during a read of the status register. Bit 3: Logical 0 means the printer has encountered an error condition. Bit 5: Logical 1 means the printer has detected the end of paper. stops.microseconds before busy and cannot accept data. PE swapper. W83977EF/ CTF PRELIMINARY 5.2.3 Printer Control Latch and Printer Control Swapper The system microprocessor can read the contents of the printer control latch by reading the printer 76543210 11 STROBE AUTO FD INIT# SLCT IN IRQ ENABLE DIR Bit 5: Direction control bit When this bit is a logic 1, the parallel port is in input mode (read); when it is a logic 0, the parallel port is in output mode (write). This bit can be read and written. In SPP mode, this bit is invalid and fixed at zero. ACK# Bit 3: A 1 in this bit position selects the printer. Bit 2: A 0 starts the printer (50 microsecond pulse, minimum). Bit 1: A 1 causes the printer to line-feed after a line is printed. Bit 0: A 0.5 microsecond minimum high active pulse clocks data into the printer. Valid data must be present for a minimum of 0.5 microseconds before and after the strobe pulse. 5.2.4 EPP Address Port The address port is available only in EPP mode. Bit definitions are as follows: 76543210 PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 Publication Release Date: March 1999 -66 - Revision A1 changes from low to high.Bit 4: A 1 in this position allows an interrupt to occur when Bit 7, 6: These two bits are a logic one during a read. They can be written. control swapper. Bit definitions are as follows: W83977EF/ CTF PRELIMINARY The contents of DB0-DB7 are buffered (non-inverting) and output to ports PD0-PD7 during a write operation. The leading edge of IOW# causes an EPP address write cycle to be performed, and the trailing edge of IOW# latches the data for the duration of the EPP write cycle. PD0-PD7 ports are read during a read operation. The leading edge of IOR# causes an EPP address 5.2.5 EPP Data Port 0-3 These four registers are available only in EPP mode. Bit definitions of each data port are as follows: 76543210 When accesses are made to any EPP data port, the contents of DB0-DB7 are buffered (non- inverting) and output to the ports PD0-PD7 during a write operation. The leading edge of IOW# causes an EPP data write cycle to be performed, and the trailing edge of IOW# latches the data for the duration of the EPP write cycle. IOR# 5.2.6 Bit Map of Parallel Port and EPP Registers REGISTER 7 6 5 4 3 2 1 0 11 111INIT# 11IRQINIT# Publication Release Date: March 1999 -67 - Revision A1 PD0PD1PD2PD3PD4PD5PD6PD7 EPP Data Port 3 (R/W) PD0PD1PD2PD3PD4PD5PD6PD7 EPP Data Port 2 (R/W) PD0PD1PD2PD3PD4PD5PD6PD7 EPP Data Port 1 (R/W) PD0PD1PD2PD3PD4PD5PD6PD7 EPP Data Port 0 (R/W) PD0PD1PD2PD3PD4PD5PD6PD7 EPP Address Port R/W) STROBE#AUTOFD#SLINDIR Control Latch (Write) STROBE#AUTOFD#SLINIRQEN Control Swapper (Read) TMOUTERROR#SLCTPEACK#BUSY# Status Buffer (Read) PD0PD1PD2PD3PD4PD5PD6PD7Data Port (R/W) cycle to be performed and the data to be output to the host CPU. causes an EPP readDuring a read operation, ports PD0-PD7 are read, and the leading edge of PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 read cycle to be performed and the data to be output to the host CPU. W83977EF/ CTF PRELIMINARY 5.2.7 EPP Pin Descriptions EPP NAME TYPE EPP DESCRIPTION nWriteO PD<0:7>I/O IntrI nWaitIInactive to acknowledge that data transfer is completed. Active to indicate that the device is ready for the next transfer. I SelectI O I OThis signal is active low. When it is active, the EPP device is reset to its initial operating mode. O 5.2.8 EPP Operation When the EPP mode is selected in the configuration register, the standard and bi-directional modes are also available. The PDx bus is in the standard or bi-directional mode when no EPP read, write, or address cycle is currently being executed. In this condition all output signals are set by the SPP Control Port, and the direction is controlled by DIR of the Control Port. A watchdog timer is required to prevent system lockup. The timer indicates that more than 10 mS have elapsed from the start of the EPP cycle to the time WAIT# is deasserted. The current EPP cycle is aborted when a time-out occurs. The time-out condition is indicated in Status bit 0. 5.2.8.1 EPP Operation The EPP operates on a two-phase cycle. First, the host selects the register within the device for subsequent operations. Second, the host performs a series of read and/or write byte operations to the selected register. Four operations are supported on the EPP: Address Write, Data Write, Address 5.2.8.2 EPP Version 1.9 Operation a. If the nWait is active low, when the read cycle (nWrite inactive high, nDStrb/nAStrb active low) or write cycle (nWrite active low, nDStrb/nAStrb active low) starts, the read/write cycle proceeds normally and will be completed when nWait goes inactive high. b. If nWait is inactive high, the read/write cycle will not start. It must wait until nWait changes to active low, at which time it will start as described above. 5.2.8.3 EPP Version 1.7 Operation The EPP read/write cycle can start without checking whether nWait is active or inactive. Once the read/write cycle starts, however, it will not terminate until nWait changes from active low to inactive Publication Release Date: March 1999 -68 - Revision A1 high. The EPP read/write operation can be completed under the following conditions: Read, and Data Read. All operations on the EPP device are performed asynchronously. This signal is active low. It denotes an address read or write operation.nAStrb nInits Error; same as SPP mode.nError This signal is active low. It denotes a data read or write operation.nDStrb Printer selected status; same as SPP mode. Paper end; same as SPP mode.PE Used by peripheral device to interrupt the host. Bi-directional EPP address and data bus. Denotes an address or data read or write operation. W83977EF/ CTF PRELIMINARY 5.3 Extended Capabilities Parallel (ECP) Port This port is software and hardware compatible with existing parallel ports, so it may be used as a standard printer mode if ECP is not required. It provides an automatic high burst-bandwidth channel that supports DMA for ECP in both the forward (host to peripheral) and reverse (peripheral to host) Small FIFOs are used in both forward and reverse directions to improve the maximum bandwidth requirement. The size of the FIFO is 16 bytes. The ECP port supports an automatic handshake for the standard parallel port to improve compatibility mode transfer speed. The ECP port supports run-length-encoded (RLE) decompression (required) in hardware. Compression is accomplished by counting identical bytes and transmitting an RLE byte that indicates For more information about the ECP Protocol, refer to the Extended Capabilities Port Protocol and ISA Interface Standard. 5.3.1 ECP Register and Mode Definitions NAME ADDRESS I/O ECP MODES FUNCTION R/W ecpAFifoR/W RAll R/WAll cFifoR/WParallel Port Data FIFO ecpDFifoR/WECP FIFO (DATA) tFifoR/WTest FIFO cnfgAR cnfgBR/W R/WAll MODE DESCRIPTION SPP mode PS/2 Parallel Port mode Parallel Port Data FIFO mode ECP Parallel Port mode EPP mode (If this option is enabled in the CRF0 to select ECP/EPP mode) Configuration mode Publication Release Date: March 1999 -69 - Revision A1 Note: The mode selection bits are bit 7-5 of the Extended Control Register. 111 Test mode110 Reserved101 100 011 010 001 000 Note: The base addresses are specified by CR60 and 61, which are determined by configuration register or hardware setting. Extended Control RegisterBase+402hecr Configuration Register B111Base+401h Configuration Register A111Base+400h 110Base+400h 011Base+400h 010Base+400h Control RegisterBase+002hdcr Status RegisterBase+001hdsr ECP FIFO (Address)011Base+000h Data Register000-001Base+000hdata how many times the next byte is to be repeated. Hardware support for compression is optional. directions. W83977EF/ CTF PRELIMINARY 5.3.2 Data and ecpAFifo Port During a write operation, the Data Register latches the contents of the data bus on the rising edge of the input. The contents of this register are output to the PD0-PD7 ports. During a read operation, PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 A data byte written to this address is placed in the FIFO and tagged as an ECP Address/RLE. The hardware at the ECP port transmits this byte to the peripheral automatically. The operation of this register is defined only for the forward direction. The bit definitions are as follows: Address/RLE 5.3.3 Device Status Register (DSR) These bits are at low level during a read of the Printer Status Register. The bits of this status register 111 PError Publication Release Date: March 1999 -70 - Revision A1 nBusy nAck Select nFault 7 6 5 4 3 2 1 0 are defined as follows: Address or RLE 7 6 5 4 3 2 1 0 Mode 011 (ECP FIFO-Address/RLE) 7 6 5 4 3 2 1 0 ports PD0-PD7 are read and output to the host. The bit definitions are as follows: Modes 000 (SPP) and 001 (PS/2) (Data Port) W83977EF/ CTF PRELIMINARY Bit 7: This bit reflects the complement of the Busy input. Bit 6: This bit reflects the nAck input. Bit 5: This bit reflects the PError input. Bit 4: This bit reflects the Select input. Bit 3: This bit reflects the nFault input. 5.3.4 Device Control Register (DCR) The bit definitions are as follows: 11 Bit 5: This bit has no effect and the direction is always out if mode = 000 or mode = 010. Direction is valid in all other modes. 0the parallel port is in output mode. 1the parallel port is in input mode. Bit 4: Interrupt request enable. When this bit is set to a high level, it may be used to enable interrupt ACK# input. Bit 3: This bit is inverted and output to the SLIN# 0 1 Bit 2: This bit is output to the Bit 1: This bit is inverted and output to the AFD# Bit 0: This bit is inverted and output to the STB# Publication Release Date: March 1999 -71 - Revision A1 output. output. output. INIT# The printer is selected. The printer is not selected. output. requests from the parallel port to the CPU due to a low to high transition on the Bit 6, 7: These two bits are logic one during a read and cannot be written. Direction ackIntEn SelectIn nInit autofd strobe 7 6 5 4 3 2 1 0 Bit 2-0: These three bits are not implemented and are always logic one during a read. W83977EF/ CTF PRELIMINARY 5.3.5 cFifo (Parallel Port Data FIFO) Mode = 010 This mode is defined only for the forward direction. The standard parallel port protocol is used by a hardware handshake to the peripheral to transmit bytes written or DMAed from the system to this FIFO. Transfers to the FIFO are byte aligned. 5.3.6 ecpDFifo (ECP Data FIFO) Mode = 011 When the direction bit is 0, bytes written or DMAed from the system to this FIFO are transmitted by a hardware handshake to the peripheral using the ECP parallel port protocol. Transfers to the FIFO are When the direction bit is 1, data bytes from the peripheral are read under automatic hardware handshake from ECP into this FIFO. Reads or DMAs from the FIFO will return bytes of ECP data to 5.3.7 tFifo (Test FIFO Mode) Mode = 110 Data bytes may be read, written, or DMAed to or from the system to this FIFO in any direction. Data in the tFIFO will not be transmitted to the parallel port lines. However, data in the tFIFO may be 5.3.8 cnfgA (Configuration Register A) Mode = 111 This register is a read-only register. When it is read, 10H is returned. This indicates to the system that this is an 8-bit implementation. 5.3.9 cnfgB (Configuration Register B) Mode = 111 The bit definitions are as follows: 7 6 5 4 3 2 1 0 1 1 1 IRQx 0 IRQx 1 IRQx 2 intrValue Bit 7: This bit is read-only. It is at low level during a read. This means that this chip does not support Bit 6: Returns the value on the ISA IRQ line to determine possible conflicts. Publication Release Date: March 1999 -72 - Revision A1 hardware RLE compression. compress displayed on the parallel port data lines. the system. byte aligned. W83977EF/ CTF PRELIMINARY cnfgB[5:3] IRQ resource Bit 2-0: These five bits are at high level during a read and can be written. 5.3.10 ecr (Extended Control Register) Mode = all This register controls the extended ECP parallel port functions. The bit definitions are follows: Standard Parallel Port mode. The FIFO is reset in this mode. PS/2 Parallel Port mode. This is the same as 000 except that direction may be used to tri-state the data lines, and reading the data register returns the value on the data lines and not the value in the data register. Parallel Port FIFO mode. This is the same as 000 except that bytes are written or DMAed to the FIFO. FIFO data are automatically transmitted using the standard parallel port protocol. This mode is useful only when direction is 0. ECP Parallel Port Mode. When the direction is 0 (forward direction), bytes placed into the ecpDFifo and bytes written to the ecpAFifo are placed in a single FIFO and auto transmitted to the peripheral using ECP Protocol. When the direction is 1 (reverse direction), bytes are moved from the ECP parallel port and packed into bytes in the ecpDFifo. Selects EPP Mode. In this mode, EPP is activated if the EPP mode is selected. Test Mode. The FIFO may be written and read in this mode, but the data will not be transmitted on the parallel port. Publication Release Date: March 1999 -73 - Revision A1 110 Reserved.101 100 011 010 001 000 Bit 7-5: These bits are read/write and select the mode. MODE MODE MODE nErrIntrEn dmaEn service Intr full empty 7 6 5 4 3 2 1 0 IRQ5111 IRQ15110 IRQ14101 IRQ11100 IRQ10011 IRQ9010 IRQ7001 reflect other IRQ resources selected by PnP register (default)000 Bit 5-3: Reflect the IRQ resource assigned for ECP port. W83977EF/ CTF PRELIMINARY Configuration Mode. The confgA and confgB registers are accessible at 0x400 and 0x401 in this mode. Bit 4: Read/Write (Valid only in ECP Mode) 1 0Enables an interrupt pulse on the high to low edge of nFault. If nFault is asserted (interrupt) an interrupt will be generated and this bit is written from a 1 to 0. Bit 3: Read/Write 1 0 Bit 2: Read/Write 1Disables DMA and all of the service interrupts. 0Enables one of the following cases of interrupts. When one of the service interrupts has occurred, the serviceIntr bit is set to a 1 by hardware. This bit must be reset to 0 to re-enable the interrupts. Writing a 1 to this bit will not cause an interrupt. (b) dmaEn = 0 direction = 0: This bit is set to 1 whenever there are writeIntr Threshold or more bytes free in the FIFO. (c) dmaEn = 0 direction = 1: This bit is set to 1 whenever there are readIntr Threshold or more valid bytes to be read from the FIFO. Bit 1: Read only 0The FIFO has at least 1 free byte. 1The FIFO cannot accept another byte or the FIFO is completely full. Bit 0: Read only 0The FIFO contains at least 1 byte of data. 1The FIFO is completely empty. 5.3.11 Bit Map of ECP Port Registers D7 D6 D5 D4 D3 D2 D1 D0 NOTE 2ecpAFifo 1111 111 2cFifo 2ecpDFifo 2tFifo 00010000cnfgA 111111cnfgB MODE Publication Release Date: March 1999 -74 - Revision A1 2. All FIFOs use one common 16-byte FIFO. 1. These registers are available in all modes. Notes: ecr emptyfullserviceIntrdmaEnnErrIntrEn intrValuecompress Test FIFO ECP Data FIFO Parallel Port Data FIFO dcr strobeautofdnInitSelectInackIntEnDirectio dsr nFaultSelectPErrornAcknBusy Address or RLE fieldAddr/RLE data PD0PD1PD2PD3PD4PD5PD6PD7 (a) dmaEn = 1: During DMA this bit is set to a 1 when terminal count is reached. Disables DMA unconditionally. Enables DMA. Disables the interrupt generated on the asserting edge of nFault. 111 W83977EF/ CTF PRELIMINARY 5.3.12 ECP Pin Descriptions NAME TYPE DESCRIPTION OThe nStrobe registers data or address into the slave on the asserting edge during write operations. This signal handshakes PD<7:0>I/O IThis signal indicates valid data driven by the peripheral when IThis signal deasserts to indicate that the peripheral can accept data. It indicates whether the data lines contain ECP command information or data in the reverse direction. When in reverse direction, normal data are transferred when Busy (PeriphAck) IThis signal is used to acknowledge a change in the direction of the transfer (asserted = forward). The peripheral drives this signal low to acknowledge nReverseRequest. The host relies upon nAckReverse to determine when it is permitted to drive Select (Xflag)IIndicates printer on line. O This signal indicates whether the data lines contain ECP address or data in the forward direction. When in forward direction, normal data are transferred when nAutoFd (HostAck) IGenerates an error interrupt when it is asserted. This signal is valid only in the forward direction. The peripheral is permitted (but not required) to drive this pin low to request a reverse OThis signal sets the transfer direction (asserted = reverse, deasserted = forward). This pin is driven low to place the channel in the reverse direction. O Publication Release Date: March 1999 -75 - Revision A1 This signal is always deasserted in ECP mode.nSelectIn (ECPMode) nInit (nReverseRequest) transfer during ECP Mode. nFault (nPeriphRequest) is high and an 8-bit command is transferred when it is low. Requests a byte of data from the peripheral when it is asserted.nAutoFd (HostAck) the data bus. PError (nAckReverse) is high and an 8-bit command is transferred when it is low. Busy (PeriphAck) asserted. This signal handshakes with nAutoFd in reverse. nAck (PeriphClk) These signals contain address or data or RLE data. with Busy. nStrobe (HostClk) W83977EF/ CTF PRELIMINARY 5.3.13 ECP Operation The host must negotiate on the parallel port to determine if the peripheral supports the ECP protocol before ECP operation. After negotiation, it is necessary to initialize some of the port bits. The (a) Set direction = 0, enabling the drivers. (d) Set mode = 011 (ECP Mode) ECP address/RLE bytes or data bytes may be sent automatically by writing the ecpAFifo or ecpDFifo, respectively. 5.3.13.1 Mode Switching Software will execute P1284 negotiation and all operations prior to a data transfer phase under programmed I/O control (mode 000 or 001). Hardware provides an automatic control line handshake, If the port is in mode 000 or 001 it may switch to any other mode. If the port is not in mode 000 or 001 When in extended forward mode, the software should wait for the FIFO to be empty before switching back to mode 000 or 001. In ECP reverse mode the software waits for all the data to be read from the 5.3.13.2 ECP mode allows the transfer of normal 8-bit data or 8-bit commands. In the forward direction, normal data are transferred when HostAck is high and an 8-bit command is transferred when HostAck is low. The most significant bits of the command indicate whether it is a run-length count (for In the reverse direction, normal data are transferred when PeriphAck is high and an 8-bit command is 5.3.13.3 Data Compression compressed data to a peripheral. Note that the odd (RLE) compression in hardware is not supported. In order to transfer data in ECP mode, the compression count is written to the ecpAFifo and the data byte is written to the ecpDFifo. 5.3.14 FIFO Operation The FIFO threshold is set in configuration register 5. All data transfers to or from the parallel port can proceed in DMA or Programmed I/O (non-DMA) mode, as indicated by the selected mode. The FIFO is used by selecting the Parallel Port FIFO mode or ECP Parallel Port Mode. After a reset, the FIFO Publication Release Date: March 1999 -76 - Revision A1 is disabled. The W83977EF/CTF supports run length encoded (RLE) decompression in hardware and can transfer transferred when PeriphAck is low. The most significant bit of the command is always zero. compression) or a channel address. Command/Data FIFO before changing back to mode 000 or 001. it can only be switched into mode 000 or 001. The direction can be changed only in mode 001. moving data between the FIFO and the ECP port only in the data transfer phase (mode 011 or 010). (c) Set autoFd = 0, causing the nAutoFd signal to default to the deasserted state. (b) Set strobe = 0, causing the nStrobe signal to default to the deasserted state. following are required: W83977EF/ CTF PRELIMINARY 5.3.15 DMA Transfers DMA transfers are always to or from the ecpDFifo, tFifo, or CFifo. The DMA uses the standard PC DMA services. The ECP requests DMA transfers from the host by activating the PDRQ pin. The DMA will empty or fill the FIFO using the appropriate direction and mode. When the terminal count in the DMA controller is reached, an interrupt is generated and serviceIntr is asserted, which will disable the DMA. 5.3.16 Programmed I/O (NON-DMA) Mode The ECP or parallel port FIFOs can also be operated using interrupt driven programmed I/O. Programmed I/O transfers are to the ecpDFifo at 400H and ecpAFifo at 000H or from the ecpDFifo located at 400H, or to/from the tFifo at 400H. The host must set the direction, state, dmaEn = 0 and serviceIntr = 0 in the programmed I/O transfers. The ECP requests programmed I/O transfers from the host by activating the IRQ pin. The programmed I/O will empty or fill the FIFO using the appropriate direction and mode. 5.4 Extension FDD Mode (EXTFDD) In this mode, the W83977EF/CTF changes the printer interface pins to FDC input/output pins, allowing the user to install a second floppy disk drive (FDD B) through the DB-25 printer connector. After the printer interface is set to EXTFDD mode, the following occur: (1) Pins MOB# and DSB# will be forced to inactive state. (2) PinsDSKCHG#, RDATA#, WP#, TRAK0#, INDEX# will be logically ORed with pins PD4-PD0 to (3) Pins PD4-PD0 each will have an internal resistor of about 1K ohm to serve as pull-up resistor for (4) If the parallel port is set to EXTFDD mode after the system has booted DOS or another operating 5.5 Extension 2FDD Mode (EXT2FDD) In this mode, the W83977EF/CTF changes the printer interface pins to FDC input/output pins, allowing the user to install two external floppy disk drives through the DB-25 printer connector to replace internal floppy disk drives A and B. The pin assignments for the FDC input/output pins are After the printer interface is set to EXTFDD mode, the following occur: (1) Pins MOA#, DSA#, MOB#, and DSB# will be forced to inactive state. (2) Pins DSKCHG#, RDATA#, WP#, TRAK0#, and INDEX# will be logically ORed with pins PD4-PD0 (3) Pins PD4-PD0 each will have an internal resistor of about 1K ohm to serve as pull-up resistor for (4) If the parallel port is set to EXT2FDD mode after the system has booted DOS or another operating Publication Release Date: March 1999 -77 - Revision A1 system, a warm reset is needed to enable the system to recognize the extension floppy drive. FDD open drain/collector output. to serve as input signals to the FDC. shown in Table5-1. system, a warm reset is needed to enable the system to recognize the extension floppy drive. FDD open drain/collector output. serve as input signals to the FDC. The pin assignments for the FDC input/output pins are shown in Table 5-1. W83977EF/ CTF PRELIMINARY 6. KEYBOARD CONTROLLER The KBC (8042 with licensed KB BIOS) circuit of W83977EF/CTF is designed to provide the Ò-compatible personal computers or PS/2-based systems. The controller receives serial data from the keyboard or PS/2 mouse, checks the parity of the data, and presents the data to the system as a byte of data in its output buffer. The controller will then assert an interrupt to the system when data are placed in its output buffer. The keyboard and PS/2 mouse are required to acknowledge all data transmissions. No transmission should be sent to the keyboard or PS/2 mouse until an acknowledge is received for the previous data byte. P24KIRQ P25MIRQ P21GATEA20 KINHP17P20KBRST KDATP27 P10 8042 P26KCLK T0 GP I/O PINS MCLKP23 P12~P16 Multiplex I/O PINS T1 P22MDAT P11 6.1 Output Buffer The output buffer is an 8-bit read-only register at I/O address 60H (Default, PnP programmable I/O address LD5-CR60 and LD5-CR61). The keyboard controller uses the output buffer to send the scan code received from the keyboard and data bytes required by commands to the system. The output buffer can only be read when the output buffer full bit in the register is "1". 6.2 Input Buffer The input buffer is an 8-bit write-only register at I/O address 60H or 64H (Default, PnP programmable I/O address LD5-CR60, LD5-CR61, LD5-CR62, and LD5-CR63). Writing to address 60H sets a flag to indicate a data write; writing to address 64H sets a flag to indicate a command write. Data written to I/O address 60H is sent to keyboard (unless the keyboard controller is expecting a data byte) through the controller's input buffer only if the input buffer full bit in the status register is "0". ”. Publication Release Date: March 1999 -78 - Revision A1 Keyboard and Mouse Interface functions needed to interface a CPU with a keyboard and/or a PS/2 mouse, and can be used with IBM W83977EF/ CTF PRELIMINARY 6.3 Status Register The status register is an 8-bit read-only register at I/O address 64H (Default, PnP programmable I/O address LD5-CR62 and LD5-CR63), that holds information about the status of the keyboard controller and interface. It may be read at any time. BIT BIT FUNCTION DESCRIPTION 0Output Buffer Full0: Output buffer empty 1: Output buffer full 1Input Buffer Full0: Input buffer empty 1: Input buffer full 2System FlagThis bit may be set to 0 or 1 by writing to the system flag bit in the command byte of the keyboard controller. It 3 1: Command byte 4Inhibit Switch 5Auxiliary Device Output0: Auxiliary device output buffer empty Buffer1: Auxiliary device output buffer full 60: No time-out error 1: Time-out error 7Parity Error0: Odd parity 1: Even parity (error) Publication Release Date: March 1999 -79 - Revision A1 out General Purpose Time- 1: Keyboard is not inhibited 0: Keyboard is inhibited 0: Data byteCommand/Data defaults to 0 after a power-on reset. W83977EF/ CTF PRELIMINARY 6.4 Commands COMMAND FUNCTION Write Command Byte of Keyboard Controller BIT BIT DEFINITION 7 6 5 4 3 2 1 0 Disable Auxiliary Device Interface Enable Auxiliary Device Interface Interface Test BIT BIT DEFINITION Self-test Publication Release Date: March 1999 -80 - Revision A1 Returns 055h if self test succeeds AAh Auxiliary Device "Data" line is stuck low 04 Auxiliary Device "Data" line is stuck low03 Auxiliary Device "Clock" line is stuck high02 Auxiliary Device "Clock" line is stuck low 01 No Error Detected00 A9h A8h A7h Enable the checking of keystrokes for a match with the password Enable PasswordA6h Load Password until a "0" is received from the system Load PasswordA5h Returns 0F1h if Password is not loaded Returns 0Fah if Password is loaded Test PasswordA4h Enable Keyboard Interrupt Enable Auxiliary Interrupt System Flag Reserve Disable Keyboard Disable Auxiliary Device IBM Keyboard Translate Mode Reserved 60h Read Command Byte of Keyboard Controller20h W83977EF/ CTF PRELIMINARY COMMAND FUNCTION Interface Test BIT DEFINITION BIT Send Port2 value to the system Send data back to the system as if it came from Keyboard Send data back to the system as if it came from Auxiliary Device Output next received byte of data from system to Auxiliary Device mS if Command byte is even 6.5 Hardware GATEA20/Keyboard Reset Control Logic The KBC implements a hardware control logic to speed-up GATEA20 and KBRESET. This control Publication Release Date: March 1999 -81 - Revision A1 logic is controlled by LD5-CRF0 as follows: Pulse only RC(the reset line) low for 6 FXh Reports the status of the test inputsE0h D4h D3h D2h Only set/reset GateA20 line based on the system data bit 1D1h D0h Continuously puts the upper four bits of Port1 into STATUS registerC2h Continuously puts the lower four bits of Port1 into STATUS registerC1h Read Input Port(P1) and send data to the systemC0h Enable Keyboard InterfaceAEh Disable Keyboard InterfaceADh Keyboard "Data" line is stuck high04 03 Keyboard "Data" line is stuck low Keyboard "Clock" line is stuck high02 Keyboard "Clock" line is stuck low01 No Error Detected00 ABh 6.4 Commands, continued W83977EF/ CTF PRELIMINARY 6.5.1 KB Control Register (Logic Device 5, CR-F0) BIT 7 6 5 4 3 2 1 0 NAME KCLKS1, KCLKS0 This 2 bits are for the KBC clock rate selection. = 0 0KBC cl = 0 1KBC clock input is 8 Mhz = 1 0KBC clock input is 12 Mhz = 1 1KBC clock input is 16 Mhz P92EN HGA20 HKBRST When the KBC receives data that follows a "D1" command, the hardware control logic sets or clears GATE A20 according to the received data bit 1. Similarly, the hardware control logic sets or clears KBRESET depending on the received data bit 0. When the KBC receives a "FE" command, the m mS(Min.) delay. GATEA20 and KBRESET are controlled by either the software control or the hardware control logic and they are mutually exclusive. Then, GATEA20 and KBRESET are merged along with Port92 6.5.2 Port 92 Control Register (Default Value = 0x24) BIT 7 6 5 4 3 2 1 0 SGA20 (Special GATE A20 Control) A "1" on this bit drives GATE A20 signal to high. A "0" on this bit drives GATE A20 signal to low. PLKBRST A "1" on this bit causes KBRESET to drive low for 6 mS(Min.) with 14 mS(Min.) delay. Before issuing Publication Release Date: March 1999 -82 - Revision A1 another keyboard reset command, the bit must be cleared. (Pull-Low KBRESET) PLKBRSTSGA20Res. (1)Res. (0)Res. (0)Res. (1)Res. (0)Res. (0)NAME when P92EN bit is set. S(Min.) with 14KBRESET is pulse low for 6 A "0" on this bit disables hardware KB RESET control logic function. A "1" on this bit selects hardware KB RESET control logic to control KBRESET signal. (Hardware Keyboard Reset) A "0" on this bit disables hardware GATEA20 control logic function. A "1" on this bit selects hardware GATEA20 control logic to control GATE A20 signal. (Hardware GATE A20) A "0" on this bit disables Port 92 functions. A "1" on this bit enables Port 92 to control GATEA20 and KBRESET. (Port 92 Enable) ock input is 6 Mhz HKBRSTHGA20P92ENReservedReservedReservedKCLKS0KCLKS1 W83977EF/ CTF PRELIMINARY 6.6 OnNow / Security Keyboard and Mouse Wake-Up ---- Programmable Keyboard / Mouse Wake-Up Functions Winbond's unique programmable keyboard/ mouse Wake-Up functions provide the system with diversified methods for either OnNow Wake-Up application, or security control application. The keyboard or mouse can Wake-Up the system by producing a panel switch low pulse on PANSWOT# TM pin, and connect it to chipset (for example Intel chipset TX, LX PIIX4) panel switch input. The Wake-Up conditions can be programmed as pre-determined or any keys/buttons. To implement this function, a 32.768KHz crystal must be installed between XTAL1 and XTAL2, or a 32.768KHz clock to be connected to XTAL1 and leave XTAL2 open. The V pin must be connected to +5V V of ATX power supply, and an external battery should be installed on VBAT pin to store the data (the 6.6.1 Keyboard Wake-Up Function The keyboard Wake-Up function is enabled by setting LD-0A CR-E0 bit 6. The pre-determined keys data are stored in registers, and they can be accessed by an indirect method. First, write their index address to LD-0A CR-E1, then access them by reading/writing LD-0A CR-E2. A zero data is written to the register means the comparison of this register will be ignored. The pre-programmed keys may be 1 to 5 keys with various combinations. If LD-0A CR-E0 bit 0 is set, the system will be woken up after any key is struck. 6.6.2 Keyboard Password Wake-Up Function To implement this function, the bit 7 of LD-0A CR-E0 must be set, and panel switch input is connected to PANSWIN# pin. Thus PANSWIN# is blocked to PANSWOUT#, by setting LD-0A CR- 6.6.3 Mouse Wake-Up Function The mouse Wake-Up function is activated by setting bit 5 of LD-0A CR-E0. If bit 1 of LD-0A CR-E0 is set, any movement or button clicking will make up the system. Otherwise, the mouse can Wake-Up the system only by clicking its button twice successively with the mouse unmoved. The bit 4 of LD- 0A CR-E0 determines which button (left or right) is to perform Wake-Up function. Publication Release Date: March 1999 -83 - Revision A1 E0 properly so that only the keyboard can Wake-Up the system with preset keys (password). passwords and Wake-Up status which had been set already) when power fails. SBSB W83977EF/ CTF PRELIMINARY 7.0 GENERAL PURPOSE I/O W83977EF/CTF provides 14 Input/Output ports that can be individually configured to perform a simple basic I/O function or a pre-defined alternate function. These 14 GP I/O ports are divided into three groups, the first group contains 8 ports, and the second group contains only 6 ports. Each port in the first group corresponds to a configuration register in logical device 7, and those in the second group to one in logical device 8. Users can select the I/O ports' functions by independently programming these configuration registers. Figures 7.1, 7.2, and 7.3 respectively show the GP I/O port structure of logical device 7 and 8. Right after Power-on reset, these ports default to perform basic I/O functions. Publication Release Date: March 1999 -84 - Revision A1 Figure 7.1 W83977EF/ CTF PRELIMINARY Publication Release Date: March 1999 -85 - Revision A1 Figure 7.3 Figure 7.2 W83977EF/ CTF PRELIMINARY 7.1 Basic I/O functions The Basic I/O functions of W83977EF/CTF provide several I/O operations including driving a logic value to output port, latching a logic value from input port, inverting the input/output logic value, and steering Common Interrupt (only available in the second group of GP I/O ports). Common Interrupt is the ORed function of all interrupt channels in the second group of GP I/O ports, and it also connects to a 1ms debounce filter which can reject a noise of 1 ms pulse width or less. There are two 8-bit registers (GP1 and GP2) which are directly connected to these GP I/O ports. Each GP I/O port is represented as a bit in one of three 8-bit registers. Only 6 bits of GP2 are implemented. Table 7.1.1 shows their combinations of Basic I/O functions, and Table 7.1.2 shows the register bit assignments of GP1 and GP2. I/O BIT ENABLE INT BIT POLARITY BIT BASIC I/O OPERATIONS 0 = OUTPUT 0 = DISABLE 0 = NON INVERT 1 = INPUT 1 = ENABLE 1 = INVERT 000Basic non-inverting output 001Basic inverting output 010Non-inverted output bit value of GP2 drive to Common Interrupt 011Inverted output bit value of GP2 drive to Common Interrupt 100Basic non-inverting input 101Basic inverting input 110Non-inverted input drive to Common 111Inverted input drive to Common Publication Release Date: March 1999 -86 - Revision A1 Interrupt Interrupt Table 7.1.1 W83977EF/ CTF PRELIMINARY GP I/O PORT ACCESSED REGISTER BIT GP I/O PORT REGISTER ASSIGNMENT BIT 0 BIT 1 BIT 2 BIT 3 GP1BIT 4 BIT 5 BIT 6 BIT 7 BIT 0 BIT 1 GP2BIT 2 BIT 3 BIT 4 BIT 5 Publication Release Date: March 1999 -87 - Revision A1 GP25 GP24 GP23 GP22 GP21 GP20 GP17 GP16 GP15 GP14 GP13 GP12 GP11 GP10 Table 7.1.2 W83977EF/ CTF PRELIMINARY 7.2 Alternate I/O Functions W83977EF/CTF provides several alternate functions which are divided among the GP I/O ports. GP I/O PORT ALTERNATE FUNCTION Watch Dog Timer Output/IRRX input Watch Dog Timer Output 7.2.1 Interrupt Steering GP10, and GP11can be programmed to map their own interrupt channels. The selection of IRQ channel can be performed in configuration registers CR70 and CR72 of logical device 7 and logical Publication Release Date: March 1999 -88 - Revision A1 whose width is equal to or less than 1 ms. device 9. Each interrupt channel also has its own 1 ms debounce filter that is used to reject any noise GATE A20 (8042 P21)GP25 8042 P16GP24 8042 P15GP23 8042 P14GP22 8042 P13GP21 Keyboard Reset (8042 P20)GP20 Power LED outputGP17 GP16 General Purpose Write Strobe/ 8042 P12GP15 General Purpose Address Decoder/Keyboard Inhibit(P17)GP14 Power LED output/IRTX outputGP13 GP12 Interrupt SteeringGP11 Interrupt SteeringGP10 Table 7.2.1 Table 7.2.1 shows their assignments. Polarity bit can also be set to alter their polarity. W83977EF/ CTF PRELIMINARY 7.2.2 Watch Dog Timer Output Watch Dog Timer contains a one second/minute resolution down counter, CRF2 of Logical Device 8, and two Watch-Dog control registers, WDT_CTRL0 and WDT_CTRL1 of Logical Device 8. The down counter can be programmed within the range from 1 to 255 seconds/minutes. Writing any new non- zero value to CRF2 or reset signal coming from a Mouse interrupt or Keyboard interrupt (CRF2 also contains non-zero value) will cause the Watch Dog Timer to reload and start to count down from the new value. As the counter reaches zero, (1) Watch Dog Timer time-out occurs and the bit 0 of WDT_CTRL1 will be set to logic 1; (2) Watch Dog interrupt output is asserted if the interrupt is enabled in CR72 of logical device 8; and (3) Power LED starts to toggle output if the bit 3 of 7.2.3 Power LED The Power LED function provides 1~1/8 Hertz rate toggle pulse output with 50 percent duty cycle. WDT_CTRL1 BIT[1] WDT_CTRL0 BIT[3] WDT_CTRL1 BIT[0] POWER LED STATE 1XX 00X 010 011 7.2.4 General Purpose Address Decoder General Purpose Address Decoder provides two address decode as AEN equal to logic 0. The address base is stored at CR62, CR63, CR64, and CR65 of logical device 7 for GP14 and GP15. The decoding range can be programmed to 1~8 byte boundary. The decoding output is normally active low. Users can alter its polarity through the polarity bit of the GP14 and GP15 configuration register. Publication Release Date: March 1999 -89 - Revision A1 * Note: Continuous high or low depends on the polarity bit of GP13 or GP17 configuration registers. Toggle pulse Continuous high or low * Continuous high or low * Toggle pulse Table 7.2.2 Table 7.2.2 shows how to enable Power LED. WDT_CTRL0 is enabled. WDT_CTRL1 also can be accessed through GP2 I/O base address + 1. W83977EF/ CTF PRELIMINARY 8.0 PLUG AND PLAY CONFIGURATION The W83977EF/CTF uses Compatible PNP protocol to access configuration registers for setting up different types of configurations. In W83977EF/CTF, there are nine Logical Devices (from Logical Device 0 to Logical Device A, with the exception of logical device 4 and 6 for compatibility) which correspond to nine individual functions: FDC (logical device 0), PRT (logical device 1), UART1 (logical device 2), UART2 (logical device 3), KBC (logical device 5), CIR (logical device 6) (For W83977CTF only), GPIO1 (logical device 7), GPIO2 (logical device 8), and ACPI ((logical device A). Each Logical Device has its own configuration registers (above CR30). Host can access these registers by writing an appropriate logical device number into logical device select register at CR7. 8.1 Compatible PnP 8.1.1 Extended Function Registers registers. HEFRAS (CR26 bit 6) can be used to select one out of these two methods of entering the HEFRAS address and value 0 1 Publication Release Date: March 1999 -90 - Revision A1 write 87h to the location 370h twice write 87h to the location 3F0h twice Extended Function mode as follows: In Compatible PnP, there are two ways to enter Extended Function and read or write the configuration W83977EF/ CTF PRELIMINARY After Power-on reset, the value on (pin 43) is latched by HEFRAS of CR26. In Compatible PnP, a specific value (87h) must be written twice to the Extended Functions Enable Register (I/O port address 3F0h or 370h). Secondly, an index value (02h, 07h-FFh) must be written to the Extended Functions Index Register (I/O port address 3F0h or 370h, the same as the Extended Functions Enable Register) to identify which configuration register is to be accessed. The designer can then access the desired configuration register through the Extended Functions Data Register (I/O port After programming of the configuration register is finished, an additional value (AAh) should be written to EFERs to exit the Extended Function mode, to prevent unintentional access to these configuration registers. The designer can also set bit 5 of CR26 (LOCKREG) to high to protect the The configuration registers can be reset to their default or hardware settings only by a cold reset (pin MR = 1). A warm reset will not affect the configuration registers. 8.1.2 Extended Functions Enable Registers (EFERs) After a power-on reset, the W83977EF/CTF enters the default operating mode. Before the W83977EF/CTF enters the extended function mode, a specific value must be programmed into the Extended Function Enable Register (EFER) so that the extended function register can be accessed. The Extended Function Enable Registers are write-only registers. On a PC/AT system, their port 8.1.3 Extended Function Index Registers (EFIRs), Extended Function Data Registers(EFDRs) After the extended function mode is entered, the Extended Function Index Register (EFIR) must be loaded with an index value (02h, 07h-FEh) to access Configuration Register 0 (CR0), Configuration Register 7 (CR07) to Configuration Register FE (CRFE), and so forth through the Extended Function Data Register (EFDR). The EFIRs are write-only registers with port address 3F0h or 370h (as described in section 8.1.1) on PC/AT systems; the EFDRs are read/write registers with port address 8.2 Configuration Sequence To program W83977ATF configuration registers, the following configuration sequence must be followed: (1). Enter the extended function mode (3). Exit the extended function mode 8.2.1 Enter the extended function mode To place the chip into the extended function mode, two successive writes of 0x87 must be applied to Publication Release Date: March 1999 -91 - Revision A1 Extended Function Enable Registers (EFERs, i.e. 3F0h or 370h). (2). Configure the configuration registers 3F1h or 371h (as described in section 8.1.1) on PC/AT systems. addresses are 3F0h or 370h (as described in previous section). configuration registers against accidental accesses. address 3F1h or 371h). RTSA W83977EF/ CTF PRELIMINARY 8.2.2 Configurate the configuration registers The chip selects the logical device and activates the desired logical devices through Extended Function Index Register (EFIR) and Extended Function Data Register (EFDR). EFIR is located at the First, write the Logical Device Number (i.e., 0x07) to the EFIR, and then write the number of the desired logical device to the EFDR. If accessing the Chip(Global) Control Registers, this step is not Secondly, write the address of the desired configuration register within the logical device to the EFIR 8.2.3 Exit the extended function mode To exit the extended function mode, one write of 0xAA to EFER is required. Once the chip exits the extended function mode, it is in the normal running mode, and is ready to enter the configuration mode. 8.2.4 Software programming example The following example is written in Intel 8086 assembly language. It assumes that the EFER is located at 3F0h, so EFIR is located at 3F0h and EFDR is located at 3F1h. If HEFRAS (CR26 bit 6) is ;----------------------------------------------------------------------------------- ; Enter the extended function mode ,interruptible double-write | ;----------------------------------------------------------------------------------- MOV MOV OUT OUT ;----------------------------------------------------------------------------- ; Configurate logical device 1, configuration register CRF0 | ;----------------------------------------------------------------------------- MOV MOV OUT; point to Logical Device Number Reg. MOV MOV OUT; select logical device 1 ; MOV MOV OUT MOV MOV OUT ;------------------------------------------ ; Exit extended function mode | ;------------------------------------------ MOV MOV OUT Publication Release Date: March 1999 -92 - Revision A1 DX,AL AL,AAH DX,3F0H ; update CRF0 with value 3CHDX,AL AL,3CH DX,3F1H ; select CRF0DX,AL AL,F0H DX,3F0H DX,AL AL,01H DX,3F1H DX,AL AL,07H DX,3F0H DX,AL DX,AL AL,87H DX,3F0H set, 3F0h can be directly replaced by 370h and 3F1h replaced by 371h. and then write (or read) the desired configuration register through EFDR. required. same address as EFER, and EFDR is located at address (EFIR+1). W83977EF/ CTF PRELIMINARY 9.0 ACPI REGISTERS FEATURES W83977EF/CTF supports both ACPI and legacy power managements. The switch logic of the power management block generates an SMI# interrupt in the legacy mode and an SCI# interrupt in the ACPI mode. The new ACPI feature routes SMI#/SCI# logic output either to SMI# or toSCI#. The SMI#/SCI# logic routes to SMI# only when both SCI_EN = 0 and SMISCI_OE = 1. Similarly, the SMI#/SCI# logic SCI_EN SMISCI_OE IRQ events 0 1 SMISCI_OE IRQs Publication Release Date: March 1999 -93 - Revision A1 Timer Global STBY Device Trap ControlState machine Sleep/Wake Clock Timers WAK_STS Device Idle SCI# SMI# LogicSCI#SMI# / routes to SCI# only when both SCI_EN = 1 and SMISCI_OE = 1. W83977EF/ CTF PRELIMINARY 10.0 CONFIGURATION REGISTER 10.1 Chip (Global) Control Register CR02 (Default 0x00) Bit 7 - 1: Reserved. Bit 0: SWRST --> Soft Reset. CR07 Bit 7 - 0: LDNB7 - LDNB0 --> Logical Device Number Bit 7 - 0 CR20 Bit 7 - 0: DEVIDB7 - DEBIDB0 --> Device ID Bit 7 - Bit 0 = 0x52 (read only). CR21 Bit 7 - 0: DEVREVB7 - DEBREVB0 --> Device Rev Bit 7- Bit 0 = 0x7x (read only for W83977CTF). 0xFx (read only for W83977EF). CR22 (Default 0xff) Bit 7 - 6: Reserved. Bit 5: URBPWD Bit 4: URAPWD Bit 3: PRTPWD Bit 2, 1: Reserved. Bit 0: FDCPWD CR23 (Default 0xFE) Bit 7 - 1: Reserved. Bit 0: IPD (Immediate Power Down). When set to 1, it will put the whole chip into power down mode immediately. Publication Release Date: March 1999 -94 - Revision A1 = 1 No Power down = 0 Power down = 1 No Power down = 0 Power down = 1 No Power down = 0 Power down = 1 No Power down = 0 Power down W83977EF/ CTF PRELIMINARY CR24 (Default 0b1s000s0s) Bit 7: EN16SA = 0 12 bit Address Qualification = 1 16 bit Address Qualification Bit 6: EN48 = 0 Th = 1 The clock input on Pin 1 should be 48 Mhz. Bit 5 - 3: Reserved. Bit 2: ENKBC setting pin is SOUTA (pin 46). Bit 1: Reserved Bit 0: PNPCSV# = 0 The Compatible PnP address select registers have default values. = 1 The Compatible PnP address select registers have no default value. When trying to make a change to this bit, the new value of PNPCSV# must be complementary to the old one to make an effective change. For example, the user must set PNPCSV# to 0 first and then reset it to 1 to reset these PnP registers if the present value of CR25 (Default 0x00) Bit 7 - 6: Reserved Bit 5: URBTRI Bit 4: URATRI Bit 3: PRTTRI Bit 2 - 1 : Reserved Bit 0: FDCTRI. Publication Release Date: March 1999 -95 - Revision A1 PNPCSV# is 1. The corresponding power-on setting pin is NDTRA (pin 44). This bit is read only, and set/reset by power-on setting pin. The corresponding power-on = 1 KBC is enabled after hardware reset. = 0 KBC is disabled after hardware reset. The corresponding power-on setting pin is SOUTB (pin 53). e clock input on Pin 1 should be 24 Mhz. W83977EF/ CTF PRELIMINARY CR26 (Default 0b0s000000) Bit 7: SEL4FDD = 0 Select two FDD mode. = 1 Select four FDD mode. Bit 6: HEFRAS = 0 Write 87h to the location 3F0h twice. = 1 Write 87h to the location 370h twice. Bit 5: LOCKREG = 0 Enable R/W Configuration Registers. = 1 Disable R/W Configuration Registers. Bit 4: Reserved. Bit 3: DSFDLGRQ = 0 Enable FDC legacy mode on IRQ and DRQ selection, then DO register bit 3 is effective effective on selecting IRQ Bit 2: DSPRLGRQ = 0 Enable PRT legacy mode on IRQ and DRQ selection, then DCR bit 4 is effective on lection, then DCR bit 4 is not effective Bit 1: DSUALGRQ = 0 Enable UART A legacy mode IRQ selecting, then MCR bit 3 is effective on selecting IRQ = 1 Disable UART A legacy mode IRQ selecting, then MCR bit 3 is not effective on Bit 0: DSUBLGRQ = 0 Enable UART B legacy mode IRQ selecting, then MCR bit 3 is effective on selecting IRQ = 1 Disable UART B legacy mode IRQ selecting, then MCR bit 3 is not effective Publication Release Date: March 1999 -96 - Revision A1 selecting IRQ on selecting IRQ on selecting IRQ = 1 Disable PRT legacy mode on IRQ and DRQ se selecting IRQ = 1 Disable FDC legacy mode on IRQ and DRQ selection, then DO register bit 3 is not on selecting IRQ HEFRAS Address and Value setting pin is NRTSA (pin 43). These two bits define how to enable Configuration mode. The corresponding power-on W83977EF/ CTF PRELIMINARY CR28 (Default 0x00) Bit 7 - 5: Reserved. Bit 4: IRQ Sharing selection. = 0 Disable IRQ Sharing = 1 Enable IRQ Sharing Bit 3:Reserved Bit 2 - 0: PRTMODS2 - PRTMODS0 = 0xx Parallel Port Mode = 100 Reserved = 101 External FDC Mode = 110 Reserved = 111 External two FDC Mode CR2A (Default 0x00) Bit 7: PIN57S = 0 KBRST = 1 GP12 Bit 6: PIN56S = 0 GA20 = 1 GP11 Bit 5 - 4: PIN40S1, PIN40S0 = 01 GP24 = 11 Reserved Bit 3 - 2: PIN39S1, PIN39S0 = 00 SUSCIN# = 01 Reserved = 10 GP25 = 11 Reserved Bit 1 - 0: PIN3S1, PIN3S0 = 01 GP10 = 11 Publication Release Date: March 1999 -97 - Revision A1 SCI# = 10 8042 P12 = 00 DRVDEN1 = 10 8042 P13 = 00 CIRRX W83977EF/ CTF PRELIMINARY CR2B (Default 0x00) Bit 7 - 6: PIN73S1, PIN73S0 = 00 PANSWIN# = 01 GP23 = 10 = 11 Bit 5: PIN72S = 0 PANSWOUT# = 1 GP22 Bit 4 - 3: PIN70S1, PIN70S0 = 00 SMI# = 01 GP21 = 11 Bit 2 - 1: PIN69S1, PIN69S0 = 00 PWRCTL# = 01 GP20 = 10 Reserved = 11 Reserved Bit 0: PIN58S = 0 KBLOCK = 1 GP13 CR2C (Default 0x00) = 00 DRQ0 = 01 GP17 = 11 = 01 GP16 = 11 Publication Release Date: March 1999 -98 - Revision A1 Bit 3 - 2: PIN104S1, PIN104S0 Reserved = 10 8042 P15 = 00 NDACK0 Bit 5 - 4: PIN119S1, PIN119S0 SCI# = 10 8042 P14 Bit 7 - 6: PIN121S1, PIN121S0 Reserved = 10 8042 P16 Reserved Reserved W83977EF/ CTF PRELIMINARY = 00 IRQ15 = 01 GP15 = 10 WDTO = 11 Bit 1 - 0: PIN103S1, PIN103S0 = 00 IRQ14 = 01 GP14 = 10 PLEDO = 11 CR2D (Default 0x00) Test Modes: Reserved for Winbond. CR2E (Default 0x00) Test Modes: Reserved for Winbond. CR2F (Default 0x00) Test Modes: Reserved for Winbond. Publication Release Date: March 1999 -99 - Revision A1 Reserved Reserved W83977EF/ CTF PRELIMINARY 10.2 Logical Device 0 (FDC) CR30 (Default 0x01 if PNPCSV# = 0 during POR, default 0x00 otherwise) Bit 7 - 1: Reserved. Bit 0:= 1 Activates the logical device. = 0 Logical device is inactive. CR60, CR 61 (Default 0x03, 0xf0 if PNPCSV# = 0 during POR, default 0x00, 0x00 otherwise) CR70 (Default 0x06 if PNPCSV# = 0 during POR, default 0x00 otherwise) Bit 7 - 4: Reserved. Bit 3 - 0: These bits select IRQ resource for FDC. CR74 (Default 0x02 if PNPCSV# = 0 during POR, default 0x04 otherwise) Bit 7 - 3: Reserved. = 0x00 DMA0 = 0x01 DMA1 = 0x02 DMA2 = 0x03 DMA3 = 0x04 - 0x07 No DMA active CRF0 (Default 0x0E) Bit 7: FIPURDWN T DSKCHG, and WP. = 0 The internal pull-up resistors of FDC are turned on.(Default) = 1 The internal pull-up resistors of FDC are turned off. Bit 6: INTVERTZ This bit determines the polarity of all FDD interface signals. = 0 FDD interface signals are active low. = 1 FDD interface signals are active high. Bit 5: DRV2EN (PS2 mode only) When this bit is a logic 0, this indicates that a second drive is installed and is reflected in status Bit 4: Swap Drive 0, 1 Mode = 0 No Swap (Default) Publication Release Date: March 1999 -100 - Revision A1 = 1 Drive and Motor sel 0 and 1 are swapped. register A. his bit controls the internal pull-up resistors of the FDC input pins RDATA, INDEX, TRAK0, FDD Mode Register Bit 2 - 0: These bits select DRQ resource for FDC. wo registers select FDC I/O base address [0x100:0xFF8] on 8 byte boundary.These t W83977EF/ CTF PRELIMINARY Bit 3 - 2 Interface Mode = 11 AT Mode (Default) = 10 (Reserved) = 01 PS/2 = 00 Model 30 Bit 1: FDC DMA Mode = 1 Non-Burst Mode (Default) Bit 0: Floppy Mode = 0 Normal Floppy Mode (Default) = CRF1 (Default 0x00) Bit 7 - 6: Boot Floppy = 00 FDD A = 01 FDD B = 10 FDD C = 11 FDD D Bit 5, 4: Media ID1, Media ID0. These bits will be reflected on FDC's Tape Drive Register bit 7, 6. Bit 3 - 2: Density Select = 00 Normal (Default) = 01 Normal = 10 1 ( Forced to logic 1) = 11 0 ( Forced to logic 0) Bit 1: DISFDDWR = 0 Enable FDD write. = 1 Disable FDD write(forces pins WE, WD stay high). Bit 0: SWWP = 0 Normal, use WP to determine whether the FDD is write protected or not. Publication Release Date: March 1999 -101 - Revision A1 = 1 FDD is always write-protected. 1 Enhanced 3-mode FDD = 0 Burst Mode is enabled W83977EF/ CTF PRELIMINARY CRF2 (Default 0xFF) Bit 7 - 6: FDD D Drive Type Bit 5 - 4: FDD C Drive Type Bit 3 - 2: FDD B Drive Type Bit 1:0: FDD A Drive Type When FDD is in enhanced 3-mode(CRF0.bit0=1), these bits determine SELDEN value in TABLE DTYPE1 DPYTE0 DRATE1 DRATE0 SELDEN 00111 00001 00010 00100 01XX0 10XX1 11010 CRF4 (Default 0x00) FDD0 Selection: Bit 7: Reserved. Bit 6: Precomp. Disable. Bit 5: Reserved. Bit 4 - 3: DRTS1, DRTS0: Data Rate Table select (Refer to TABLE A). = 00 Select Regular drives and 2.88 format = 01Specifical application = 10 2 Meg Tape = 11 Reserved Bit 2: Reserved. Bit 1:0: DMOD0, DMOD1 : Drive Model select (Refer to TABLE B). Publication Release Date: March 1999 -102 - Revision A1 = 0 Enable FDC Precompensation. = 1 Disable FDC Precompensation. Note: X means don't care. A of CRF4 and CRF5 as follows. W83977EF/ CTF PRELIMINARY CRF5 (Default 0x00) FDD1 Selection: Same as FDD0 of CRF4. TABLE A Drive Rate Table Data Rate Selected Data Rate SELDEN Select DRTS1 DRTS0 DRATE1 DRATE0 MFM FM CRF0 bit 0=0 11---1 00001 010 100 11---1 01001 010 100 11---1 10001 01---0 100 TABLE B DMOD0 DMOD1 DRVDEN0(pin 2) DRVDEN1(pin 3) DRIVE TYPE ”“00 ” ” 01 10 11 Publication Release Date: March 1999 -103 - Revision A1 DRATE1DRATE0 SELDEN DRATE0 DRATE0DRATE1 (3-MODE)2/1.6/1 MB 3.5 2/1 MB 5.25 4/2/1 MB 3.5DRATE0SELDEN Note:Refer to CRF2 for SELDEN value in the cases when CRF0, bit0=1. 125K250K 2Meg 250K500K 1Meg 125K250K 250K500K 250K500K 1Meg 125K250K 150K300K 250K500K 1Meg W83977EF/ CTF PRELIMINARY 10.3 Logical Device 1 (Parallel Port) CR30 (Default 0x01 if PNPCSV# = 0 during POR, default 0x00 otherwise) Bit 7 - 1: Reserved. Bit 0: = 1 Activates the logical device. = 0 Logical device is inactive. CR60, CR 61 (Default 0x03, 0x78 if PNPCSV# = 0 during POR, default 0x00, 0x00 otherwise) CR70 (Default 0x07 if PNPCSV# = 0 during POR, default 0x00 otherwise) Bit 7 - 4: Reserved. Bit [3:0]: These bits select IRQ resource for Parallel Port. CR74 (Default 0x04) Bit 7 - 3: Reserved. Bit 2 - 0: 0x00=DMA0 0x01=DMA1 0x02=DMA2 0x03=DMA3 0x04 - 0x07= No DMA active CRF0 (Default 0x3F) Bit 7: PP Interrupt Type: Not valid when the parallel port is in the printer Mode (100) or the standard & Bi-directional = 0 IRQ follows nACK when parallel port in EPP Mode or [Printer, SPP, EPP] under ECP. Bit [6:3]: ECP FIFO Bit 2 - 0 Parallel Port Mode = 100 Printer Mode (Default) = 000 Standard and Bi-direction (SPP) mode = 001 EPP - 1.9 and SPP mode = 101 EPP - 1.7 and SPP mode = 010 ECP mode = 011 ECP and EPP - 1.9 mode = 111 ECP and EPP - 1.7 mode. Publication Release Date: March 1999 -104 - Revision A1 Threshold. = 1 Pulsed Low, released to high-Z . Mode (000). These bits select DRQ resource for Parallel Port. address is on 8 byte boundary). [0x100:0xFF8] on 8 byte boundary (all modes supported, EPP is only available when the base [0x100:0xFFC] on 4 byte boundary (EPP not supported) or These two registers select Parallel Port I/O base address. W83977EF/ CTF PRELIMINARY ¢) 10.4 Logical Device 2 (UART A) CR30 (Default 0x01 if PNPCSV# = 0 during POR, default 0x00 otherwise) Bit 7 - 1: Reserved. Bit 0: = 1 Activates the logical device. = 0 Logical device is inactive. CR60, CR 61 (Default 0x03, 0xF8 if PNPCSV# = 0 during POR, default 0x00, 0x00 otherwise) CR70 (Default 0x04 if PNPCSV# = 0 during POR, default 0x00 otherwise) Bit 7 - 4: Reserved. Bit 3 - 0: These bits select IRQ resource for Serial Port 1. CRF0 (Default 0x00) Bit 7 - 2: Reserved. = 10 10.5 Logical Device 3 (UART B) CR30 (Default 0x01 if PNPCSV# = 0 during POR, default 0x00 otherwise) Bit 7 - 1: Reserved. Bit 0: = 1 Activates the logical device. = 0 Logical device is inactive. CR60, CR 61 (Default 0x02, 0xF8 if PNPCSV# = 0 during POR, default 0x00, 0x00 otherwise) CR70 (Default 0x03 if PNPCSV# = 0 during POR, default 0x00 otherwise) Bit 7 - 4: Reserved. Bit [3:0]: These bits select IRQ resource for Serial Port 2. Publication Release Date: March 1999 -105 - Revision A1 These two registers select Serial Port 2 I/O base address [0x100:0xFF8] on 8 byte boundary. = 11 UART A clock source is 14.769 Mhz (24MHz/1.625) UART A clock source is 24 Mhz (24MHz/1) = 01 UART A clock source is 2 Mhz (24MHz/12) = 00 UART A clock source is 1.8462 Mhz (24MHz/13) Bit 1 - 0: SUACLKB1, SUACLKB0 These two registers select Serial Port 1 I/O base address [0x100:0xFF8] on 8 byte boundary. W83977EF/ CTF PRELIMINARY CRF0 (Default 0x00) Bit 7 - 4: Reserved. Bit 3: RXW4C = 0 = 1Reception delays 4 characters-time (40 bit-time) when SIR is changed from TX mode Bit 2: TXW4C = 0 = 1Transmi mode to TX mode. CRF1 (Default 0x00) Bit 7: Reserved. Bit 6: IRLOCSEL. IR I/O pins' location select. = 0 = 1 Bit 5: IRMODE2. IR function mode selection bit 2. Bit 4: IRMODE1. IR function mode selection bit 1. Bit 3: IRMODE0. IR function mode selection bit 0. IR MODE IR FUNCTION IRTX IRRX tri-state IrDAActive pulse 1.6 mS IrDAActive pulse 3/16 bit time Inverting IRTX/SOUTB pin Inverting IRTX/SOUTB & 500 KHZ clock Inverting IRTX/SOUTB Inverting IRTX/SOUTB & 500 KHZ clock Publication Release Date: March 1999 -106 - Revision A1 Note: The notation is normal mode in the IR function. Demodulation into SINB/IRRXASK-IR111* Demodulation into SINB/IRRXASK-IR110 routed to SINB/IRRXASK-IR101 routed to SINB/IRRXASK-IR100 Demodulation into SINB/IRRX011* Demodulation into SINB/IRRX010* highDisable00X RTX.Through IRRX/I Through SINB/SOUTB. = 11 UART B clock source is 14.769 Mhz (24MHz/1.625) = 10 UART B clock source is 24 Mhz (24MHz/1) = 01 UART B clock source is 2 Mhz (24MHz/12) = 00 UART B clock source is 1.8462 Mhz (24MHz/13) Bit 1 - 0: SUBCLKB1, SUBCLKB0 ssion delays 4 characters-time (40 bit-time) when SIR is changed from RX No transmission delay when SIR is changed from RX mode to TX mode. to RX mode. No reception delay when SIR is changed from TX mode to RX mode. W83977EF/ CTF PRELIMINARY Bit 2: HDUPLX. IR half/full duplex function select. = 0The IR function is Full Duplex. = 1The IR function is Half Duplex. Bit 1: TX2INV. = 0the SOUTB pin of UART B function or IRTX pin of IR function in normal condition. = 1inverts the SOUTB pin of UART B function or IRTX pin of IR function. Bit 0: RX2INV. = 0the SINB pin of UART B function or IRRX pin of IR function in normal condition. = 1inverts the SINB pin of UART B function or IRRX pin of IR function Publication Release Date: March 1999 -107 - Revision A1 W83977EF/ CTF PRELIMINARY 10.6 Logical Device 5 (KBC) CR30 (Default 0x01 if PENKBC= 1 during POR, default 0x00 otherwise) Bit 7 - 1: Reserved. Bit 0: = 1 Activates the logical device. = 0 Logical device is inactive. CR60, CR 61 (Default 0x00, 0x60 if PENKBC= 1 during POR, default 0x00 otherwise) x100:0xFFF] on 1 byte boundary. CR62, CR 63 (Default 0x00, 0x64 if PENKBC= 1 during POR, default 0x00 otherwise) CR70 (Default 0x01 if PENKBC= 1 during POR, default 0x00 otherwise) Bit 7 - 4: Reserved. CR72 (Default 0x0C if PENKBC= 1 during POR, default 0x00 otherwise) Bit 7 - 4: Reserved. CRF0 (Default 0x83) Bit 7 - 6: KBC clock rate selection = 00 Select 6MHz as KBC clock input. = 01 Select 8MHz as KBC clock input. = 10 Select 12Mhz as KBC clock input. = 11 Select 16Mhz as KBC clock input. Bit 5 - 3: Reserved. Bit 2: = 0 Port 92 disable. = 1 Port 92 enable. Bit 1: Bit 0: = 0 KBRST software control. Publication Release Date: March 1999 -108 - Revision A1 = 1 KBRST hardware speed up. = 1 Gate20 hardware speed up. = 0 Gate20 software control. e)Bit [3:0]: These bits select IRQ resource for MINT (PS2 Mous Bit [3:0]: These bits select IRQ resource for KINT (keyboard). These two registers select the second KBC I/O base address [0x100:0xFFF] on 1 byte boundary. These two registers select the first KBC I/O base address [0 W83977EF/ CTF PRELIMINARY 10.7 Logical Device 6 (CIR) CR30 (Default 0x00) Bit 7 - 1: Reserved. Bit 0: = 1 Activates the logical device. = 0 Logical device is inactive. CR60, CR 61 (Default 0x00) CR70 (Default 0x00) Bit 7 - 4: Reserved. Bit 3 - 0: These bits select IRQ resource for CIR. 10.8 Logical Device 7 (GP I/O Port I) CR30 (Default 0x00) Bit 7 - 1: Reserved. Bit 0:= 1 Activates the logical device. = 0 Logical device is inactive. CR60, CR 61 (Default 0x00, 0x00) CR62, CR 63 (Default 0x00, 0x00) These two registers select GP14 alternate function Primary I/O base address [0x100:0xFFx] on CR64, CR 65 (Default 0x00, 0x00) These two registers select GP15 alternate function Primary I/O base address [0x100:0xFFx] on CR70 (Default 0x00) Bit 7 - 4: Reserved. (Interrupt Steering). CR72 (Default 0x00) Bit 7 - 4: Reserved. (Interrupt Steering). Publication Release Date: March 1999 -109 - Revision A1 Bit 3 - 0: These bits select IRQ resource for GP11 as you set GP11 to be an alternate function Bit 3 - 0: These bits select IRQ resource for GP10 as you set GP10 to be an alternate function Purpose Address Decode). o be an alternate function (General byte boundary, they are available as you set GP15 t1~8 Purpose Address Decode). 1~8 byte boundary, they are available as you set GP14 to be an alternate function (General These two registers select GP1 I/O base address [0x100:0xFFF] on 1 byte boundary. These two registers select CIR I/O base address [0x100:0xFF8] on 8 byte boundary. W83977EF/ CTF PRELIMINARY CRE0 (GP10, Default 0x01) Bit 7 - 5: Reserved. Bit 4: IRQ Filter Select = Bit 3: Select Function. = 1 Select Alternate Function: Interrupt Steering. = 0 Select Basic I/O Function. Bit 2: Reserved. Bit 1: Polarity. = 1 Invert. = 0 No Invert. Bit 0: In/Out selection. = 1 Input. = 0 Output. CRE1 (GP11, Default 0x01) Bit 7 - 5: Reserved. Bit 4: IRQ Filter Select Bit 3: Select Function. = 1 Select Alternate Function: Interrupt Steering. = 0 Select Basic I/O Function. Bit 2: Reserved. Bit 1: Polarity. = 1 Invert. = 0 No Invert. Bit 0: In/Out selection. = 1 Input. = 0 Output. Publication Release Date: March 1999 -110 - Revision A1 = 0 Debounce Filter Bypassed = 1 Debounce Filter Enabled 0 Debounce Filter Bypassed = 1 Debounce Filter Enabled W83977EF/ CTF PRELIMINARY CRE2 (GP12, Default 0x01) Bit 7 - 5: Reserved. Bit 4 - 3: Select Function. = 00 Select Basic I/O function. = 01 Select 1st alternate function: Watch Dog Timer Output. = 10 Reserved = 11 Reserved Bit 2: Reserved. Bit 1: Polarity: 1: Invert, 0: No Invert Bit 0: In/Out: 1: Input, 0: Output CRE3 (GP13, Default 0x01) Bit 7 - 5: Reserved. Bit 4 - 3: Select Function. = 00 Select Basic I/O function. = 10 Reserved = 11 Reserved Bit 2: Reserved. Bit 1: Polarity: 1: Invert, 0: No Invert Bit 0: In/Out: 1: Input, 0: Output CRE4 (GP14, Default 0x01) Bit 7 - 6: Bit 5: Reserved. Bit 4 - 3: Select Function. = 00 Select Basic I/O function. = 10 Select 2nd alternate function: Keyboard Inhibit(P17). = 11 Reserved Bit 2: Reserved. Bit 1: Polarity: 1: Invert, 0: No Invert Bit 0: In/Out: 1: Input, 0: Output Publication Release Date: March 1999 -111 - Revision A1 Bit 1 = 0, Decode two byte address). = 01 Select 1st alternate function: General Purpose Address Decoder(Active Low when = 11 Address decoder is 8-Byte boundary. = 10 Address decoder is 4-Byte boundary. ecoder is 2-Byte boundary.= 01 Address d = 00 Address decoder is 1-Byte boundary. = 01 Select 1st alternate function: Power LED output. W83977EF/ CTF PRELIMINARY CRE5 (GP15, Default 0x01) Bit 7 - 6: Bit 5: Reserved. Bit 4 - 3: Select Function. = 00 Select Basic I/O function. = 01 General Purpose Write Strobe (Active Low when Bit 1 = 0). = 11 Reserved Bit 2: Reserved. Bit 1: Polarity: 1: Invert, 0: No Invert Bit 0: In/Out: 1: Input, 0: Output CRE6 (GP16, Default 0x01) Bit 7 - 5: Reserved. Bit 4 - 3: Select Function. = 00 Select Basic I/O function. = 01 Select 1st alternate function: Watch Dog Timer Output. = 1x Reserved Bit 2: Reserved. Bit 1: Polarity: 1: Invert, 0: No Invert Bit 0: In/Out: 1: Input, 0: Output CRE7 (GP17, Default 0x01) Bit 7 - 4: Reserved. Bit 4 - 3: Select Function. = 00 Select Basic I/O function. = 01 Select 1st alt = 1x Reserved Bit 2: Reserved. Bit 1: Polarity: 1: Invert, 0: No Invert Bit 0: In/Out: 1: Input, 0: Output Publication Release Date: March 1999 -112 - Revision A1 ernate function: Power LED output. Please refer to TABLE C = 10 8042 P12. = 11 Address decoder is 8-Byte boundary. = 10 Address decoder is 4-Byte boundary. = 01 Address decoder is 2-Byte boundary. = 00 Address decoder is 1-Byte boundary. W83977EF/ CTF PRELIMINARY TABLE C WDT_CTRL1* BIT[1]* WDT_CTRL0* BIT[3] WDT_CTRL1 BIT[0] POWER LED STATE 1XX 00X 010 011 CRF1 ( Default 0x00) Bit 7 - 2: Reserved Bit 1: Bit 0: 10.9 Logical Device 8 (GP I/O Port II) CR30 (Default 0x00) Bit 7 - 1: Reserved. Bit 0: = 1 Activates the logical device. = 0 Logical device is inactive. CR60, CR 61 (Default 0x00, 0x00) CR70 (Default 0x00) Bit 7 - 4: Reserved. Bit 3 - 0: These bits select IRQ resource for Common IRQ of GP20~GP26 at Logic Device 8. CR72 (Default 0x00) Bit 7 - 4: Reserved. Bit 3 - 0: These bits select IRQ resource for Watch Dog. Publication Release Date: March 1999 -113 - Revision A1 boundary. I/O base address + 1: Watch Dog I/O base address. These two registers select GP2 & Watch Dog I/O base address [0x100:0xFFE] on 2 byte *Note: If the logical device's activate bit is not set then bit 0 and 1 have no effect. = 0 Disable GP14 General Purpose Address Decode = 1 Enable GP14 General Purpose Address Decode = 0 Disable GP15 General Purpose Address Decode = 1 Enable GP15 General Purpose Address Decode General Purpose Read/Write Enable* 2). Continuous high or low depends on the polarity bit of GP13 or GP17 configure registers. *Note: 1). Regarding to the contents of WDT_CTR1 and WDT_CTRL0, please refer to CRF3 and CRF4 in Logic Device 8. 1 Hertz Toggle pulse Continuous high or low* Continuous high or low* 1 Hertz Toggle pulse W83977EF/ CTF PRELIMINARY CRE8 (GP20, Default 0x01) Bit 7 - 5: Reserved. Bit 4 - 3: Select Function. = 00 Select basic I/O function = 01 Reserved = 11 Reserved Bit 2: Int En = 1 Enable Common IRQ = 0 Disable Common IRQ Bit 1: Polarity: 1: Invert, 0: No Invert Bit 0: In/Out: 1: Input, 0: Output CRE9 (GP21, Default 0x01) Bit 7 - 5: Reserved Bit 4 - 3: Select Function. = 00 Select Basic I/O function = 01 Reserved = 10 Select 2nd alternate function: Keyboard P13 I/O = 11 Reserved Bit 2: Int En = 1 Enable Common IRQ = 0 Disable Common IRQ Bit 1: Polarity: 1: Invert, 0: No Invert Bit 0: In/Out: 1: Input, 0: Output CREA (GP22, Default 0x01) Bit 7 - 5: Reserved. Bit 4 - 3: Select Function. = 00 Select Basic I/O function. = 01 Reserved = 10 Select 2nd alternate function: Keyboard P14 I/O. = 11 Reserved Bit 2: Int En = 1 Enable Common IRQ = 0 Disable Common IRQ Bit 1: Polarity: 1: Invert, 0: No Invert ¡@¡@ Bit 0: In/Out: 1: Input, 0: Output CREB (GP23, Default 0x01) Bit 7 - 5: Reserved. Bit 4 - 3: Select Function. = 00 Select Basic I/O function Publication Release Date: March 1999 -114 - Revision A1 = 10 Select alternate function: Keyboard Reset (connected to KBC P20) W83977EF/ CTF PRELIMINARY = 01 Reserved = 10 Select 2nd alternate function: Keyboard P15 I/O = 11 Reserved Bit 2: Int En = 1 Enable Common IRQ = 0 Disable Common IRQ Bit 1: Polarity: 1: Invert, 0: No Invert ¡@ Bit 0: In/Out: 1: Input, 0: Output CREC (GP24, Default 0x01) Bit 7 - 5: Reserved. Bit 4 - 3: Select Function. = 00 Select Basic I/O function = 01 Reserved = 10 Select 2nd alternate function: Keyboard P16 I/O = 11 Reserved Bit 2: Int En = 1 Enable Common IRQ = 0 Disable Common IRQ Bit 1: Polarity: 1: Invert, 0: No Invert Bit 0: In/Out: 1: Input, 0: Output CRED (GP25, Default 0x01) Bit 7 - 4: Reserved. Bit 3: Select Function. = 1 Select alternate function: GATE A20(Connect to KBC P21). = 0 Select basic I/O function Bit 2: Int En = 1 Enable Common IRQ = 0 Disable Common IRQ Bit 1: Polarity: 1: Invert, 0: No Invert Bit 0: In/Out: 1: Input, 0: Output Publication Release Date: March 1999 -115 - Revision A1 W83977EF/ CTF PRELIMINARY CRF0 (Default 0x00) Debounce Filter Enable or Disable for General Purpose I/O Combined Interrupt. The Debounce Filter Bit 7 - 4: Reserved Bit 3: GP Common IRQ Filter Select Bit 2 - 0: Reserved CRF1 (Reserved) CRF2 (Default 0x00) Watch Dog Timer Time-out value. Writing a non-zero value to this register causes the counter to load the value to Watch Dog Counter and start to count down. If the Bit2 and Bit 1 are set, any Mouse Interrupt or Keyboard Interrupt happen will also cause reloading of the non-zero value to Watch Dog Counter and count down. If this register is read, Watch Dog Timer Time-out value can not be Bit 7 - 0: = 0x00 Time-out Disable = 0x01 Time-out occurs after 1 minute/second ................................................ = 0xFF Time-out occurs after 255 minutes CRF3 (WDT_CTRL0, Default 0x00) Watch Dog Timer Control Register #0 Bit 7 - 4: Reserved = 1 Enable = 0 Disable Publication Release Date: March 1999 -116 - Revision A1 Bit 3: When Time-out occurs, Enable or Disable Power LED with 1 Hz and 50% duty cycle output. = 0x03 Time-out occurs after 3 minutes/seconds = 0x02 Time-out occurs after 2 minutes/seconds accessed but the current value in Watch Dog Counter can be accessed. = 0 Debounce Filter Bypassed = 1 Debounce Filter Enabled can reject a pulse with 1ms width or less. W83977EF/ CTF PRELIMINARY = 1 Watch Dog Timer is reset upon a Mouse interrupt = 0 Watch Dog Timer is not affected by Mouse interrupt = 1 Watch Dog Timer is r = 0 Watch Dog Timer is not affected by Keyboard interrupt Bit 0: Reserved. CRF4 (WDT_CTRL1, Default 0x00) Watch Dog Timer Control Register #1 Bit 7: Reserved Bit 6: = 1 Watch Dog counter counts in seconds. = 0 Watch Dog counter counts in minutes. Bit 3: Enable the rising edge of Keyboard Reset(P20) to force Time-out event, R/W* = 1 Enable = 0 Disable Bit 2: Force Watch Dog Timer Time-out, Write only* = 1 Force Watch Dog Timer time-out event; this bit is self-clearing. Bit 1: Enable Power LED toggle pulse with 50% duty cycle , R/W = 1 Enable = 0 Disable Bit 0: Watch Dog Timer Status, R/W = 1 Watch Dog Timer time-out occurred. = 0 Watch Dog Timer counting e ORed signal is self-clearing. Publication Release Date: March 1999 -117 - Revision A1 connects to set the Bit 0(Watch Dog Timer Status). Th 2). The P20 signal coming from Debounce Filter is ORed with the signal generated by the Force Time-out bit, and then *Note: 1). Internal logic provides an 1us Debounce Filter to reject the width of P20 pulse less than 1us. le pulse frequency is 1/8Hz= 11 Power LED togg = 10 Power LED toggle pulse frequency is 1/4Hz = 01 Power LED toggle pulse frequency is 1/2Hz = 00 Power LED toggle pulse frequency is 1Hz Bit 5-4: Power LED toggle pulse frequency select eset upon a Keyboard interrupt Bit 1: Keyboard interrupt reset Enable or Disable Bit 2: Mouse interrupt reset Enable or Disable W83977EF/ CTF PRELIMINARY 10.10 Logical Device A (ACPI) CR30 (Default 0x00) Bit 7 - 1: Reserved. Bit 0:= 1 Activates the logical device. = 0 Logical device is inactive. CR70 (Default 0x00) Bit 7 - 4: Reserved. CRE0 (Default 0x00) = 0PANSWIN# is wire-ANDed and connected to PANSWOUT#. = 1PANSWIN# is blocked and can not affect PANSWOUT#. Bit 6: ENKBWAKEUP. Enable Keyboard to Wake-Up system via PANSWOUT#. = 0Disable Keyboard Wake-Up function. = 1Enable Keyboard Wake-Up function. Bit 5: ENMSWAKEUP. Enable Mouse to Wake-Up system via PANSWOUT#. = 0Disable Mouse Wake-Up function. = 1e Wake-Up function. Bit 4: MSRKEY. Select Mouse Left/Right Botton to Wake-Up system via PANSWOUT#. = 0Select click on Mouse Left-botton to Wake the system up. = 1Select click on Mouse right-botton to Wake the system up. Bit 3: ENCIRWAKEUP. Enable CIR to Wake-Up system via PANSWOUT#. (for W83977CTF only) = 0 Disable CIR Wake-Up function. = 1 Enable CIR Wake-Up function. = 0 = 1 Bit 1: MSXKEY. Enable any character received from Mouse to Wake-Up the system. = 0Just clicking Mouse left/right-botton twice can Wake-Up the system. = 1Just clicking Mouse left/right-botton once can Wake-Up the system. Bit 0: KBXKEY. Enable any character received from Keyboard to Wake-Up the system. = 0Only predetermined specific key combination can Wake-Up the system. = 1Any character received from Keyboard can Wake-Up the system. Publication Release Date: March 1999 -118 - Revision A1 Keyboard/Mouse ports are swapped. re not swapped.Keyboard/Mouse ports a Bit 2: KB/MS Swap. Enable Keyboard/Mouse port-swap. Enable Mous Bit 7: DIS-PANSWIN. Disable panel switch input to turn system power supply on. ources for SCI#.Bit 3 - 0: These bits select IRQ res W83977EF/ CTF PRELIMINARY CRE1 (Default 0x00) Keyboard Wake-Up Index Register This register is used to indicate which Keyboard Wake-Up Shift register or Predetermined key Register is to be read/written via CRE2. The range of Keyboard Wake-Up index register is 0x00 - 0x0E, and the range of CIR Wake-Up index register is 0x20 - 0x2F. CRE2 Keyboard Wake-Up Data Register This register holds the value of wake-up key register indicated by CRE1. This register can CRE3 (Read only) Keyboard/Mouse Wake-Up Status Register Bit 7-5: Reserved. Bit 4: PWRLOSS_STS: This bit is set when power loss occurs. Bit 3: CIR_STS. The Panel switch event is caused by CIR wake-up event. This bit is cleared by Bit 2: PANSW_STS. The Panel switch event is caused by PANSW_IN. This bit is cleared by Bit 1: Mouse_STS. The Panel switch event is caused by Mouse wake-up event. This bit is Bit 0: Keyboard_STS. The Panel switch event is caused by Keyboard wake-up event. This bit is CRE4 (Default 0x00) Bit 7: Power loss control bit 2. 0 = Disable ACPI resume. 1 = Enable ACPI resume. Bit 6-5: Power loss control bit <1:0> 00 = System always turns off when recovering from power loss state. 01 = System always turns on when recovering from power loss state. 10 = System turns on/off when recovering from power loss state, depending on the state before power loss. 11 = Reserved. Bit 4: Suspend clock source select 0 = Use internal clock source. 1 = Use external suspend clock source(32.768KHz). Bit 3: Keyboard wake-up type select for wake-up the system from S1/S2. 0 = Password or Hot keys programmed in the registers. 1 =Any key. Publication Release Date: March 1999 -119 - Revision A1 cleared by reading this register. cleared by reading this register. reading this register. reading this register. read/written. be W83977EF/ CTF PRELIMINARY Bit 2: Enable all wake-up event set in CRE0 can wake-up the system from S1/S2 state. This bit is cleared when wake-up event occurs. 0 = Disable. 1 = Enable. Bit 1 - 0: Reserved. CRE5 (Default 0x00) Bit 7: Reserved. CRE6 (Default 0x00) Bit 7 - 6: Reserved. Bit 5 - 0: CIR Baud Rate Divisor. The clock base of CIR is 32khz, so that the baud rate is 32khz divided by ( CIR Baud Rate Divisor + 1). CRE7 (Default 0x00) Bit 7 - 3: Reserved. Bit 1: Invert RX Data. = 1 Inverting RX Data. = 0 Not inverting RX Data. Bit 0: Enable Demodulation. = 1 Enable received signal to demodulate. = 0 Disable received signal to demodulate. CRF0 (Default 0x00) Bit 7: CHIPPME. Chip level auto power management enable. = 0 = 1 Bit 6: URCPME. UART C auto power management enable. = 0 = 1 Bit 3: PRTPME. Printer port auto power management enable. = 0 = 1 Publication Release Date: March 1999 -120 - Revision A1 enable the auto power management functions. disable the auto power management functions. Bit 5 - 4: Reserved. Return zero when read. enable the auto power management functions. disable the auto power management functions. enable the auto power management functions. disable the auto power management functions 1 to restart CIR power-on function. Bit 2: Reset CIR Power-On function. After using CIR power-on, the software should write logical these data lengths should be written to this register. Bit 6 - 0: Compared Code Length. When the compared codes are stored in the data register, W83977EF/ CTF PRELIMINARY = 0 = 1 = 0 = 1 = 0 = 1 CRF1 (Default 0x00) event occurs. Upon setting this bit, the sleeping/working state machine will transition the this bit position, or by the sleeping/working state machine automatically when the global standby timer expires. = 0 the chip is in the sleeping state. = 1 the chip is in the working state. Bit 6: Device's trap status. Bit 3 - 0: Devices' trap status. These bits of trap status indicate that the individual device Wakes-Up due to any I/O access, IRQ, and external input to the device. The device's idle timer reloads the preset expiry port, FDC, UART A and UART B power down machines respectively . Writing a 1 clears this Bit 6: URCTRAPSTS. UART C trap status. = 0 = 1 receiver begins receiving a start bit, the transmitter shift register begins transmitting a start bit, or any transition on MODEM control input lines. Bit 3: PRTTRAPSTS. Printer port trap status. = 0 = 1the printer port is now in the workinging state due to any printer port access, any IRQ, Publication Release Date: March 1999 -121 - Revision A1 pins. any DMA acknowledge, or any transition on BUSY, ACK#, PE, SLCT, and ERR# the printer port is now in the sleeping state. UART C is now in the working state due to any UART C access, any IRQ, the UART C is now in the sleeping state. while power management function is enabled. bit and writing a 0 has no effect. Note that: the user is not supposed to change the status depending on which device wakes up. These 5 bits are controlled by the UART C, printer Bit 5 - 4: Reserved. Return zero when read. system to the working state. This bit is only set by hardware, and is cleared by writing a 1 to Bit 7: WAK_STS. This bit is set when the chip is in the sleeping state and an enabled resume enable the auto power management functions. disable the auto power management functions. Bit 0: URBPME. UART B auto power management enable. ions.enable the auto power management funct disable the auto power management functions. Bit 1: URAPME. UART A auto power management enable. enable the auto power management functions. disable the auto power management functions. Bit 2: FDCPME. FDC auto power management enable. W83977EF/ CTF PRELIMINARY Bit 2: FDCTRAPSTS. FDC trap status. = 0 = 1 Bit 1: URATRAPSTS. UART A trap status. = 0 = 1 receiver begins receiving a start bit, the transmitter shift register begins transmitting a bit, or any transition on MODEM control input lines. Bit 0: URBTRAPSTS. UART B trap status. = 0 = 1 receiver begins receiving a start bit, the transmitter shift register begins transmitting a start bit, or any transition on MODEM control input lines. CRF3 (Default 0x00) Bit 6 - 0: Device's IRQ status. he individual device respectively. The device's IRQ status bit is set by their source device and is cleared by writing a 1. Writing a 0 has no effect. Bit 6: URCIRQSTS. UART C IRQ status. Bit 5: MOUIRQSTS. MOUSE IRQ status. Bit 4: KBCIRQSTS. KBC IRQ status. Bit 3: PRTIRQSTS. printer port IRQ status. Bit 2: FDCIRQSTS. FDC IRQ status. Bit 1: URAIRQSTS. UART A IRQ status. Bit 0: URBIRQSTS. UART B IRQ status. CRF4 (Default 0x00) Bit 4 and Bit 2 - 0:These bits indicate the status of the individual GPIO function respectively. The status is set by their source function and is cleared by writing a 1. Writing a 0 has no effect. Bit 4: WDTIRQSTS. Watch dog timer IRQ status at logical device 8. Bit 2: COMIRQSTS. Common IRQ status of GP20 - GP25 at logical device 8. Bit 1: GP11IRQSTS. GP11 interrupt steering status at logical device 7. Bit 0: GP10IRQSTS. GP10 interrupt steering status at logical device 7. Publication Release Date: March 1999 -122 - Revision A1 Bit 3: Reserved. Return zero when read. Bit 7 - 5: Reserved. Return zero when read. These bits indicate the IRQ status of t Bit 7: Reserved. Return zero when read. UART B is now in the workinging state due to any UART B access, any IRQ, the UART B is now in the sleeping state. start UART A is now in the working state due to any UART A access, any IRQ, the UART A is now in the sleeping state. acknowledge, or any enabling of the motor enable bits in the DOR register. FDC is now in the working state due to any FDC access, any IRQ, any DMA FDC is now in the sleeping state. W83977EF/ CTF PRELIMINARY CRF6 (Default 0x00) Bit 6 - 0: Enable bits of the SMI#/SCI# generation due to the device's IRQ. These bits enable the generation of an SMI#/SCI# interrupt due to any IRQ of the devices. SMI#/SCI# logic output = (URBIRQEN and URBIRQSTS) or (URAIRQEN and URAIRQSTS) or (WDTIRQEN and WDTIRQSTS) or (COMIRQEN a GP11IRQSTS) or (GP10IRQEN and GP10IRQSTS) Bit 6: URCIRQEN. = 0 = 1 Bit 5: MOUIRQEN. = 0 = 1 Bit 4: KBCIRQEN. = 0Q. = 1 Bit 3: PRTIRQEN. = 0 = 1 Bit 2: FDCIRQEN. = 0 = 1 Bit 1: URAIRQEN. = 0s IRQ. = 1 Bit 0: URBIRQEN. = 0 = 1 CRF7 (Default 0x00) Bit 4 and Bit 2 - 0:Enable bits of the SMI#/SCI# generation due to the individual GPIO IRQ functions. Bit 4: WDTIRQEN. = 0 = 1 Publication Release Date: March 1999 -123 - Revision A1 enable the generation of an SMI#/SCI# interrupt due to watch dog timer's IRQ. e generation of an SMI#/SCI# interrupt due to watch dog timer's IRQ.disable th Bit 3: Reserved. Return zero when read. Bit 7 - 5: Reserved. Return zero when read. enable the generation of an SMI#/SCI# interrupt due to UART B's IRQ. disable the generation of an SMI#/SCI# interrupt due to UART B's IRQ. enable the generation of an SMI#/SCI# interrupt due to UART A's IRQ. disable the generation of an SMI#/SCI# interrupt due to UART A' enable the generation of an SMI#/SCI# interrupt due to FDC's IRQ. disable the generation of an SMI#/SCI# interrupt due to FDC's IRQ. enable the generation of an SMI#/SCI# interrupt due to printer port's IRQ. disable the generation of an SMI#/SCI# interrupt due to printer port's IRQ. enable the generation of an SMI#/SCI# interrupt due to KBC's IRQ. disable the generation of an SMI#/SCI# interrupt due to KBC's IR enable the generation of an SMI#/SCI# interrupt due to MOUSE's IRQ. disable the generation of an SMI#/SCI# interrupt due to MOUSE's IRQ. enable the generation of an SMI#/SCI# interrupt due to UART C's IRQ. disable the generation of an SMI#/SCI# interrupt due to UART C's IRQ. nd COMIRQSTS) or (GP11IRQEN and KBCIRQSTS) or (MOUIRQEN and MOUIRQSTS) or (URCIRQEN and URCIRQSTS) or (FDCIRQEN and FDCIRQSTS) or (PRTIRQEN and PRTIRQSTS) or (KBCIRQEN and Bit 7: Reserved. Return zero when read. W83977EF/ CTF PRELIMINARY Bit 2: COMIRQEN. = 0 disable the generation of an SMI#/SCI# interrupt due to common IRQ function's IRQ. = 1 enable the generation of an SMI#/SCI# interrupt due to common IRQ function's IRQ. Bit 1: GP11IRQEN. = 0 disable the generation of an SMI#/SCI# interrupt due to GP11 interrupt steering's IRQ. = 1 enable the generation of Bit 0: GP10IRQEN. = 0 disable the generation of an SMI#/SCI# interrupt due to GP10 interrupt steering's IRQ. = 1 enable the generation of an SMI#/SCI# interrupt due to GP10 interrupt steering's IRQ. CRF9 (Default 0x00) Bit 2: SCI_EN: Select the power management events to be either an SCI# OR SMII# interrupt for the IRQ events. Note that: this bit is valid only when SMISCI_OE = 1. = 0 the power management events will generate an SMI# event. = 1 the power management events will generate an SCI# event. Bit 1: FSLEEP: This bit selects the fast expiry time of individual devices = 0 1 second. = 1 8 milli-seconds. Bit 0: SMISCI_OE: This is the SMI# and SCI# enable bit. = 0 neither SMI# nor SCI# will be generated. Only the IRQ status bit is set. = 1 an SMI# or SCI# event will be generated. CRFE, FF (Default 0x00) Reserved for Winbond test. Publication Release Date: March 1999 -124 - Revision A1 Bit 7 - 3: Reserved. Return zero when read. an SMI#/SCI# interrupt due to GP11 interrupt steering's IRQ. W83977EF/ CTF PRELIMINARY 11.0 SPECIFICATIONS 11.1 Absolute Maximum Ratings PARAMETER RATING UNIT V -0.5 to VDD+0.5V Battery Voltage VBATV V 0 to +70 ° C ° C 11.2 DC CHARACTERISTICS (Ta = 0 ° C to 70 ° C, V= 5V ± 10%, VSS = 0V) PARAMETER SYM. MIN. TYP. MAX. UNIT CONDITIONS IBATVBAT = 2.5 V £1 ImAV = 5.0 V, All ACPI I/O - TTL level bi-directional pin with source-sink capability of 8 mA 8t VV VIHV VVI = 8 mA VOHVIOH = - 8 mA IVIN = VDD mA IVIN = 0V mA I/O - TTL level bi-directional pin with source-sink capability of 6 mA 6t VV VIHV VVI = 6 mA VOHVIOH = - 6 mA IVIN = VDD mA IVIN = 0V mA Publication Release Date: March 1999 -125 - Revision A1 -10LILInput Low Leakage +10LIHInput High Leakage 2.4Output High Voltage OL0.4OLOutput Low Voltage 2.0Input High Voltage 0.8ILInput Low Voltage -10LILInput Low Leakage +10LIHInput High Leakage 2.4Output High Voltage OL0.4OLOutput Low Voltage 2.0Input High Voltage 0.8ILInput Low Voltage pins are not connected.Quiescent Current SB2.0VSBStand-by Power Supply uABattery Quiescent Current DD device. Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the -55 to +150Storage Temperature Operating Temperature 4.5 to 5.5SB5V Standby V 4.0 to 1.8 Input Voltage -0.5 to 7.0Power Supply Voltage W83977EF/ CTF PRELIMINARY PARAMETER SYM. MIN. TYP. MAX. UNIT CONDITIONS I/O - CMOS level bi-directional pin with source-sink capability of 8 mA 8 V0.3xVDDV VIH0.7xVDDV VVI = 8 mA VOHVIOH = - 8 mA I+ 10 mAVIN = VDD IVIN = 0V mA I/O - CMOS level bi-directional pin with source-sink capability of 12 mA 12 V0.3xVDDV VIH0.7xVDDV VVI = 12 mA VOHVIOH = - 12 mA I+ 10VIN = VDD mA IVIN = 0V mA I/O - CMOS level bi-directional pin with source-sink capability of 16 mA, with internal 16u pull-up resistor V0.3xVDDV VIH0.7xVDDV VVI = 16 mA VOHVIOH = - 16 mA I+ 10VIN = VDD mA IVIN = 0V mA I/OD - CMOS level Open-Drain pin with source-sink capability of 16 mA, with internal pull- 16u up resistor V0.3xVDDV VIH0.7xVDDV VVI = 16 mA VOHVIOH = - 16 mA I+ 10VIN = VDD mA IVIN = 0V mA Publication Release Date: March 1999 -126 - Revision A1 - 10LILInput Low Leakage LIHInput High Leakage 3.5Output High Voltage OL0.4OLOutput Low Voltage Input High Voltage ILInput Low Voltage - 10LILInput Low Leakage LIHInput High Leakage 3.5Output High Voltage OL0.4OLOutput Low Voltage Input High Voltage ILInput Low Voltage - 10LILInput Low Leakage LIHInput High Leakage 3.5Output High Voltage OL0.4OLOutput Low Voltage Input High Voltage ILInput Low Voltage - 10LILInput Low Leakage LIHInput High Leakage 3.5Output High Voltage OL0.4OLOutput Low Voltage Input High Voltage ILInput Low Voltage 11.2 DC CHARACTERISTICS, continued W83977EF/ CTF PRELIMINARY PARAMETER SYM. MIN. TYP. MAX. UNIT CONDITIONS I/O - TTL level bi-directional pin with source-sink capability of 12 mA 12t VV VIHV VVI = 12 mA VOHVIOH = - 12 mA I+ 10VIN = VDD mA IVIN = 0V mA I/O - TTL level bi-directional pin with source-sink capability of 24 mA 24t VV VIHV VVI = 24 mA VOHVIOH = - 24 mA I+ 10VIN = VDD mA IVIN = 0V mA OUT - TTL level output pin with source-sink capability of 8 mA 8t VVI = 8 mA VOHVIOH = - 8 mA OUT - TTL level output pin with source-sink capability of 12 mA 12t VVI = 12 mA VOHVIOH = -12 mA OD - Open-drain output pin with sink capability of 12 mA 12 VVI = 12 mA OD - Open-drain output pin with sink capability of 24 mA 24 VVI = 24 mA IN - TTL level input pin t VV VIHV IVIN = VDD mA IVIN = 0 V mA Publication Release Date: March 1999 -127 - Revision A1 -10LILInput Low Leakage +10LIHInput High Leakage 2.0Input High Voltage 0.8ILInput Low Voltage OL0.4OLOutput Low Voltage OL0.4OLOutput Low Voltage 2.4Output High Voltage OL0.4OLOutput Low Voltage 2.4Output High Voltage OL0.4OLOutput Low Voltage - 10LILInput Low Leakage LIHInput High Leakage 2.4Output High Voltage OL0.4OLOutput Low Voltage 2.0Input High Voltage 0.8ILInput Low Voltage - 10LILInput Low Leakage LIHInput High Leakage 2.4Output High Voltage OL0.4OLOutput Low Voltage 2.0Input High Voltage 0.8ILInput Low Voltage 11.2 DC CHARACTERISTICS, continued W83977EF/ CTF PRELIMINARY PARAMETER SYM. MIN. TYP. MAX. UNIT CONDITIONS IN - CMOS level input pin c V´VDDV VIHV´VDD IVIN = VDD mA IVIN = 0 V mA IN - CMOS level Schmitt-triggered input pin cs VVVDD = 5 V V 3.8VVDD = 5 V VTH2VVDD = 5 V IVIN = VDD mA IVIN = 0 V mA IN - CMOS level input pin with internal pull-up resistor cu V0.7xVDDV VIH0.7xVDDV IVIN = VDD mA IVIN = 0 V mA IN - TTL level Schmitt-triggered input pin ts VVVDD = 5 V VVVDD = 5 V VTHVVDD = 5 V ImAVIN = VDD IVIN = 0 V mA IN - TTL level Schmitt-triggered input pin with internal pull-up resistor tsu VVVDD = 5 V VVVDD = 5 V VTHVVDD = 5 V IVIN = VDD mA ImAVIN = 0 V Publication Release Date: March 1999 -128 - Revision A1 -10LILInput Low Leakage +10LIHInput High Leakage 1.20.5Hystersis 2.42.01.6t+Input High Threshold Voltage 1.10.80.5t-Input Low Threshold Voltage -10LILInput Low Leakage +10LIHInput High Leakage 1.20.5Hystersis 2.42.01.6t+Input High Threshold Voltage 1.10.80.5t-Input Low Threshold Voltage -10LILInput Low Leakage +10LIHInput High Leakage Input High Voltage ILInput Low Voltage -10LILInput Low Leakage +10LIHInput High Leakage 1.5Hystersis 3.53.2t+Input High Threshold Voltage 1.71.51.3t-Input Low Threshold Voltage -10LILInput Low Leakage +10LIHInput High Leakage 0.7 Input High Voltage 0.3ILInput Low Voltage 11.2 DC CHARACTERISTICS, continued W83977EF/ CTF PRELIMINARY 11.3 AC Characteristics 11.3.1 FDC: Data rate = 1 MB, 500 KB, 300 KB, 250 KB/sec. PARAMETER SYM. TEST MIN. TYP. MAX. UNIT (NOTE 1) CONDITIONS TAR ¡õ CS#, setup time to IOR# TAR0 ¡ô hold time for IOR# TRR IOR Data access time fromTFDCL = 100 pf ¡õ ¡õ Data hold from IOR#TDHCL = 100 pf ¡ô SD to from IOR# TDFCL = 100 pf ¡ô IRQ delay from IOR#TRI TAW ¡õ setup time to IOW# TWA0 ¡ô hold time for IOW# IOW# widthTWW ¡ô Data setup time to IOW#TDW Data hold time fromTWD0 ¡ô IOW# IRQ delay from IOW# ¡ôTWI DRQ cycle timeTmS ¡õ DRQ delay time DACK#T T0 T T0IOR# delay from TMW0IOW# delay from Publication Release Date: March 1999 -129 - Revision A1 DRQ nS DRQ nSMR /510 nS260/430AADACK# width nSMADRQ to DACK# delay nS50AM 27MCY /675 nS360/570 nS nS60 nS60 nSSA9-SA0, AEN, DACK#, nS25SA9-SA0, AEN, DACK#, /675 nS360/570 nS5010 nS10 IOR# nS80 width nS80 nSSA9-SA0, AEN, DACK#, nS25SA9-SA0, AEN, DACK#, W83977EF/ CTF PRELIMINARY PARAMETER SYM. TEST MIN. TYP. MAX. UNIT (NOTE 1) CONDITIONS TMRW mS time from DRQ TTC TRST mS 5 TmS DIR# setup time to STEP#TDST mS DIR# hold time from STEP#TSTD mS TSTP mS TSC mS TWDD mS Write precompensationTWPC mS ° Publication Release Date: March 1999 -130 - Revision A1 2. Programmable from 2 mS through 32 mS in 2 mS increments. C and normal supply voltage.1. Typical values for T = 25 Notes: /275/250/225 150/235125/210100/138 /275/250/225 150/235125/210100/185WD# pulse width Note 2Note 2Note 2STEP# cycle width /14.2/14/13.8 7.2/11.97/11.76.8/11.5STEP# pulse width 24/40/48 /2.0 1.0/1.6 /1.0 0.5/0.9IDXINDEX# width 1.8/3/3.RESET width /260 nS135/220TC width /20/24 6/12IOW# or IOR# response 11.3.1 AC Characteristics, FDC continued W83977EF/ CTF PRELIMINARY 11.3.2 UART/Parallel Port PARAMETER SYMBOL TEST MIN. MAX. UNIT CONDITIONS Delay from Stop to Set InterruptTSINT Delay from IOR# Reset InterruptTRINT1mS Delay from Initial IRQ Reset toT Transmit Start Delay from IOW#THR Delay from Initial IOW# to interruptT Delay from Stop to Set InterruptTSTI Delay from IOR# to Reset InterruptTIR Delay from IOR# to OutputTMWO Set Interrupt Delay from ModemT Reset Interrupt Delay from IOR#T Interrupt Active DelayT Interrupt Inactive DelayT 16 NBaud Divisor2 11.3.3 Parallel Port Mode Parameters PARAMETER SYM. MIN. TYP. MAX. UNIT from IOW# IRQ Delay from ACK#, nFAULT IRQ Delay from IOW# IRQ Active Low in ECP and EPP Modes ERROR# Active to IRQ Active Publication Release Date: March 1999 -131 - Revision A1 nS105t5 nS300200t4 nS105t3 nS60t2 nS100t1PD0-7, INDEX#, STROBE#, AUTOFD# Delay -1100 pF Loading nS30100 pF LoadingIID nS25100 pF LoadingIAD nS250RIM Input nS250SIM nS200100 pF Loading nS250100 pF Loading Rate Baud1/2 Rate Baud16/169/16SI nS175100 pf Loadingto Reset interrupt Rate Baud8/161/16IRS 100 pf Loading Rate Baud9/16 W83977EF/ CTF PRELIMINARY 11.3.4 EPP Data or Address Read Cycle Timing Parameters PARAMETER SYM. MIN. MAX. UNIT Ax Valid to IOR# Asserted 0 0 PD Valid to SD Valid0 0mS 0 PD Hi-Z to PDBIR Set0 0 0 Deasserted to WRITE# Modified 0 WAIT# Asserted to PD Hi-Z 0 0 WAIT# Deasserted to PD Drive 1 PBDIR Set to Command0 0 0 Time out PD Valid to WAIT# Deasserted0 PD Hi-Z to WAIT# Deasserted0mS Publication Release Date: March 1999 -132 - Revision A1 t28 nSt27 nS1210t26 nS18060t25WAIT# Deasserted to Command Deasserted nS195t24 Asserted to Command Asserted nS30t23PD Hi-Z to Command Asserted nS20t22 nSt21WRITE# Deasserted to Command nS19060t20 nSt19Command Deasserted to PD Hi-Z nSt18Command Asserted to PD Valid nS18060t17 nS50t16IOR# Asserted to PD Hi-Z nS19060t15 nS185t14WAIT# Asserted to WRITE# Deasserted nSt13WRITE# Deasserted to IOR# Asserted nSt10 nS16060t9WAIT# Deasserted to IOCHRDY Deasserted nS85t8SD Valid to IOCHRDY Deasserted 40t7IOR# Deasserted to SD Hi-Z (Hold Time) nS75t6 nS24t5IOR# Asserted to IOCHRDY Asserted 40t4IOR# Deasserted to IOW# or IOR# Asserted nS1010t3IOR# Deasserted to Ax Valid nSt2IOCHRDY Deasserted to IOR# Deasserted nS40t1 W83977EF/ CTF PRELIMINARY 11.3.5 EPP Data or Address Write Cycle Timing Parameters PARAMETER SYM. MIN. MAX. UNIT Ax Valid to IOW# Asserted IOW# Deasserted to Ax Invalid 0 IOW# Deasserted to IOW# or IOR# Asserted 0 IOW# Asserted to WAIT# Asserted0 0 WAIT# Asserted to WARIT# Asserted WAIT# Asserted to WRITE# Change IOW# Asserted to PD Valid0 WAIT# Asserted to PD Invalid0 PD Invalid to Command Asserted IOW# to Command Asserted5 0mS Time out mS 0 0 invalid Publication Release Date: March 1999 -133 - Revision A1 nSt22IOW# Deasserted to WRITE# Deasserted and PD nSt21Command Deasserted to WAIT# Asserted 1210t20 10t19Command Asserted to WAIT# Deasserted nS19060t18WAIT# Deasserted to Command Deasserted nS21060t17WAIT# Asserted to Command Asserted nS35t16 nS10t15 nSt14 nS50t13 nS18560t12 nS18560t11 nSt10PBDIR Low to WRITE# Asserted nS70t9 nS16060t8WAIT# Asserted to Command Asserted nS24t7IOCHRDY Deasserted to IOW# Deasserted nS40t6 nS10t5Command Asserted to WAIT# Deasserted nSt4WAIT# Deasserted to IOCHRDY Deasserted nS10t3 nS10t2SD Valid to Asserted nS40t1 W83977EF/ CTF PRELIMINARY 11.3.6 Parallel Port FIFO Timing Parameters PARAMETER SYMBOL MIN. MAX. UNIT DATA Valid to nSTROBE Active nSTROBE Active Pulse Width DATA Hold from nSTROBE Inactive BUSY Inactive to PD Inactive BUSY Inactive to nSTROBE Active nSTROBE Active to BUSY Active 11.3.7 ECP Parallel Port Forward Timing Parameters PARAMETER SYMBOL MIN. MAX. UNIT 0 0 0 0 11.3.8 ECP Parallel Port Reverse Timing Parameters PARAMETER SYMBOL MIN. MAX. UNIT 0 0 0 0 Publication Release Date: March 1999 -134 - Revision A1 nS20080t6PD Changed to nAUTOFD Deasserted nS20080t5nACK Deasserted to nAUTOFD Asserted nSt4nAUTOFD Deasserted to nACK Deasserted nSt3nAUTOFD Asserted to nACK Asserted nSt2nAUTOFD Deasserted to PD Changed nSt1PD Valid to nACK Asserted nS18080t8BUSY Asserted to nSTROBE Deasserted nSt7nSTROBE Asserted to BUSY Asserted nS20080t6BUSY Deasserted to nSTROBE Asserted nSt5nSTROBE Deasserted to BUSY Deasserted nS18080t4BUSY Deasserted to PD Changed nS18080t3BUSY Deasserted to nAUTOFD Changed nS60t2PD Valid to nSTROBE Asserted nS60t1nAUTOFD Valid to nSTROBE Asserted nS500t6 nS680t5 nS80t4 nS450t3 nS600t2 nS600t1 W83977EF/ CTF PRELIMINARY 11.3.9 KBC Timing Parameters NO. DESCRIPTION MIN. MAX. UNIT Address Setup Time from WRB0 Address Setup Time from RDB0 WRB Strobe Width RDB Strobe Width Address Hold Time from WRB0 Address Hold Time from RDB0 Data Setup Time Data Hold Time0 Gate Delay Time from WRB RDB to Drive Data Delay RDB to Floating Data Delay0 Data Valid After Clock Falling (SEND)4mS K/B Clock Period mS K/B Clock Pulse Width mS Data Valid Before Clock Falling (RECEIVE)4mS K/B ACK After Finish Receiving mS 23mS RC Pulse Width (8 Mhz)6mS Transmit Timeout2mS Data Valid Hold Time0mS - Duration of CLK inactive mS Duration of CLK active mS Time from inactive CLK transition, used to time when5mS the auxiliary device samples DATA Time of inhibit mode mS Time from rising edge of CLK to DATA transition5mS Duration of CLK inactive mS Duration of CLK active mS Time from DATA transition to falling edge of CLK5mS Publication Release Date: March 1999 -135 - Revision A1 25T29 5030T28 5030T27 T28-5T26 300100T25 25T24 5030T23 5030T22 12 Mhz)Input Clock Period (6 nS16783T21 T20 T19 T18 RC Fast Reset Pulse Delay (8 Mhz)T17 20T16 T15 10T14 20T13 T12 nS20T11 nS40T10 nS3010T9 nST8 nS50T7 nST6 nST5 nS20T4 nS20T3 nST2 nST1 W83977EF/ CTF PRELIMINARY 11.3.10 GPIO Timing Parameters SYMBOL PARAMETER MIN. MAX. UNIT tWrite data to GPIO update WGO 11.3.11 Keyboard/Mouse Timing Parameters SYMBOL PARAMETER MIN. MAX. UNIT PANSWIN# falling edge to PANSWOUT# falling edgetSWL tSWHPANSWIN# falling edge to PANSWOUT# Hi-Z tKCLK/MCLK falling edge to PANSWOUT# falling WKUPD t1WKUPWPANSWOUT# active pulse width Publication Release Date: March 1999 -136 - Revision A1 sec0.5 edge delay ns200 ns50 ns20 Note : Refer to Microprocessor Interface Timing for Read Timing. ns300(Note 1) W83977EF/ CTF PRELIMINARY 12.0 TIMING WAVEFORMS 12.1 FDC Write Date Processor Read Operation SA0-SA9WD# TWDD AEN CS# TAR TRA DACK# TRR IOR# TDH Index TFD TDF D0-D7 INDEX# TR IRQ TIDXTIDX Processor Write Operation Terminal Count SA0-SA9 AEN TC TAWTWA DACK# TTC TWW IOW# TWD Reset TDW D0-D7 TWI TRST IRQ DMA Operation Drive Seek operation TAM DRQ DIR# TMCY DACK# TAA TMA TSTP TDST TSTD IOW# orTMRW STEP IOR# TMW (IOW#) TMR (IOR#) TSC Publication Release Date: March 1999 -137 - Revision A1 RESET W83977EF/ CTF PRELIMINARY 12.2 UART/Parallel Receiver Timing (READ RECEIVER Transmitter Timing IOW Publication Release Date: March 1999 -138 - Revision A1 (READ TIR) IOR TIR (WRITE THR) TSI THR THR IRQ3 or IRQ4 TSTI THRS (1-2) STOP PARITYDATA (5-8) (SOUT) STAR STAR SERIAL OUT BUFFER REGISTER) IOR TRINT IRQ3 or IRQ4 TSINT STOP PARITYDATA BITS (5-8) INPUT DATA) STAR (RECEIVER SIN W83977EF/ CTF PRELIMINARY 12.2.1 Modem Control Timing IOW# ¢x ¢x ¢x ¢x ¢x ¢x ¢xTMWO ¢x ¡÷TMWO ¡÷ ¡ö ¡ö ¢xRTS#,DTR#¢x ¢x ¢x ¢x ¢x ¢x ¢x ¢ ¢x ¢x ¢x ¢x ¢x ¢x ¡÷ TSIM ¢xTSIM ¡ö ¡ö ¡÷ ¢x ¢x ¢x ¢x ¢x ¢x ¢x ¢x ¢x ¢x ¢x ¢x ¢x ¢x ¢x ¢x ¡öTRIM ¡öTRIM ¡÷ ¢x ¢x ¡÷¢x ¢x ¢x ¢x ¢x ¢x TSIM ¢x ¡÷ ¡ö ¢x ¢x ¢x ¢x ¢x ¢x ¢x ¢x ¢x ¢x ¢x ¢ ¢x ¢x ¢x ¢x ¢x ¢x ¢x ¢x ¢x ¢xTLAD ¢xTLID¡÷ ¢x¡ö ¡÷ ¡ö ¢x ¢x ¢x ¢x ¢x ¢x ¢x ¢x ¢x Publication Release Date: March 1999 -139 - Revision A1 IRQ7 ACK# Printer Interrupt Timing RI# (READ MSR) IOR# IRQ4 IRQ3 or DCD# CTS#,DSR# (WRITE MCR) MODEM Control Timing W83977EF/ CTF PRELIMINARY 12.3 Parallel Port 12.3.1 Parallel Port Timing IOW# t1 INIT#, STROBE# AUTOFD, SLCTIN# PD<0:7> ACK# t2 IRQ (SPP) IRQt3t4 (EPP or ECP) nFAULT (ECP) ERROR# (ECP) t5 t2 t4 IRQ Publication Release Date: March 1999 -140 - Revision A1 W83977EF/ CTF PRELIMINARY 12.3.2 EPP Data or Address Read Cycle (EPP Version 1.9) t3 A<0:10> t1t2t4 IOR t6 t7 SD<0:7> t8 t5 t9 IOCHRDY WRITE# PD<0:7> ADDRSTB DATASTB WAIT# Publication Release Date: March 1999 -141 - Revision A1 t26 t28t27 t24 t23 t25 t22 t21 t17 t20 t19 t18 t16 t14 t15 t13 t10 W83977EF/ CTF PRELIMINARY 12.3.3 EPP Data or Address Write Cycle (EPP Version 1.9) Publication Release Date: March 1999 -142 - Revision A1 PBDIR t22 WAIT# t20 t21 t19 ADDRSTB# DATAST# t18t17 t16 t15 PD<0:7> t14 t13 WRITE# t11 t12 t10 t9 t8t7IOCHRDY IOW# t2 t6t1 t5 SD<0:7> A10-A0 t4 t3 W83977EF/ CTF PRELIMINARY 12.3.4 EPP Data or Address Read Cycle (EPP Version 1.7) A<0:10> ADDRSTB Publication Release Date: March 1999 -143 - Revision A1 WAIT# t27 t28t26 DATASTB t24 t23 t25 t22 t21 PD<0:7> t17 t20 t19 t18 t16 WRITE# t14 t15 t13 t10 IOCHRDY t9 t5 t8 SD<0:7> t7 t6 IOR t4 t2t1 t3 W83977EF/ CTF PRELIMINARY 12.3.5 EPP Data or Address Write Cycle (EPP Version 1.7) t3 t4 A10-A0 SD<0:7> t5 t1t6 t2 IOW# t7t8 IOCHRDY t9 t10 t22 t11 WRITE# t13 t22 PD<0:7> t15 t16 t17t18 DATAST# ADDRSTB# t19 t20 WAIT# 12.3.6 Parallel Port FIFO Timing > nSTROBE Publication Release Date: March 1999 -144 - Revision A1 BUSY >| t6 >|>| t5t2t1 PD<0:7> >| t3 >| t4 W83977EF/ CTF PRELIMINARY 12.3.7 ECP Parallel Port Forward Timing t3 t4 t1 t2 t6t8 t5t5 t7 12.3.8 ECP Parallel Port Reverse Timing t2 PD<0:7> t1 t3t4 nACK t5 t5t6 nAUTOFD Publication Release Date: March 1999 -145 - Revision A1 BUSY nSTROBE PD<0:7> nAUTOFD W83977EF/ CTF PRELIMINARY 12.4 KBC 12.4.1 Write Cycle Timing A2, CSB T1T5 T3 WRB T8 T7 D0~D7 T9 GA20 OUTPUT PORT T17T18 FAST RESET PULSE RC FE COMMAND 12.4.2 Read Cycle Timing A2,CSB AEN T2T6 T4 RDB T10T11 D0-D7 12.4.3 Send Data to K/B CLOCK (KCLK) T12 T14T13T16 SERIAL DATA STARTPSTOP (KDAT) T19 Publication Release Date: March 1999 -146 - Revision A1 D7D6D4D3D2D0 D5D1 DATA OUT ACTIVE DATA IN ACTIVE W83977EF/ CTF PRELIMINARY 12.4.4 Receive Data from K/B (KCLK) T14T13 T15 STARTPSTOP T20 12.4.5 Input Clock 12.4.6 Send Data to Mouse START P Bit STOP Bit 12.4.7 Receive Data from Mouse MCLK T29T26T27 T28 MDAT STARTPSTOP Publication Release Date: March 1999 -147 - Revision A1 Bit D7D6D4D3D2D1D0 D5 D7D6D4D3D2D1D0 D5 MDAT T22 T24 T23T25 MCLK T21 CLOCK CLOCK (T1) D7D6D4D3D2D1D0 D5 SERIAL DATA CLOCK W83977EF/ CTF PRELIMINARY 12.5 GPIO Write Timing Diagram VALID VALID PREVIOUS STATE VALID tWGO 12.6 Master Reset (MR) Timing Vcc tVMR 12.7 Keyboard/Mouse Wake-up Timing Publication Release Date: March 1999 -148 - Revision A1 tSWL tSWZ tWKUPD HI-Z PANSWOUT# tWKUPW PANSWIN# MCLK KCLK MR GPIO20-25 GPIO10-17 D0-7 IOW# A0-A15 W83977EF/ CTF PRELIMINARY 13.0 APPLICATION CIRCUITS 13.1 Parallel Port Extension FDD JP13 13 WE2#/SLCT 25 JP 13A 12 WD2#/PE 24 DCH2# 3433 11 MOB2#/BUSYHEAD2# 3231 23 RDD2# 3029 10 DSB2#/ACKWP2# 222827 TRK02#92625 PD7 WE2# 21 2423 WD2#82221 PD6STEP2# 20 2019 DIR2#71817 PD5 MOB2# 19 1615 61413 DCH2#/PD4DSB2# 181211 RDD2#/PD35109 IDX2# 1787STEP2#/SLIN# 465WP2#/PD2 1643RWC2# DIR2#/INIT# 321 TRK02#/PD1 15 EXT FDC HEAD2#/ERR#2 IDX2#/PD0 14 RWC2#/AFD#1 STB# PRINTER PORT Parallel Port Extension FDD Mode Connection Diagram Publication Release Date: March 1999 -149 - Revision A1 W83977EF/ CTF PRELIMINARY 13.2 Parallel Port Extension 2FDD JP13 13 WE2#/SLCT 25 JP 13A 12 WD2#/PE DCH2# 24 3433 MOB2#/BUSY11HEAD2# 32 31 23 RDD2# 3029 10 DSB2#/ACKWP2# 2827 22 TRK02# 26 259 DSA2#/PD7WE2# 212423 WD2#822 21 MOA2#/PD6 STEP2# 2020 19 DIR2# 71817 PD5 MOB2# 16 1915 DSA2# 14136DCH2#/PD4 DSB2# 1211 18 MOA2# RDD2#/PD31095IDX2# 87STEP2#/SLIN#17 654WP2#/PD2 4316 DIR2#/INIT#RWC2# 213TRK02#/PD1# 15 EXT FDC HEAD2#/ERR# 2 IDX2#/PD0 14 RWC2#/AFD#1 STB# PRINTER PORT Parallel Port Extension 2FDD Connection Diagram Publication Release Date: March 1999 -150 - Revision A1 W83977EF/ CTF PRELIMINARY 13.3 Four FDD Mode 14.0 ORDERING INFORMATION PART NO. KBC FIRMWARE REMARKS TM W83977EF-PWPhoenix MultiKey/42 TM W83977EF-AWAMIKEY TM W83977CTF-PWPhoenix MultiKey/42 TM W83977CTF-AWAMIKEY 15.0 HOW TO READ THE TOP MARKING Example: The top marking of W83977EF-AW inbond ã 1st line: Winbond logo 2nd line: the type number: W83977EF-AW TM 3rd line: the source of KBC F/W -- American Megatrends Incorporated 4th line: the tracking code821 A 2 C 282012345 821: packages made in '9821 A: assembly house ID; A means ASE, S means SPIL.... etc. 2: Winbond internal use. B: IC revision; A means version A, B means version B 282012345: wafer production series lot number Publication Release Date: March 1999 -151 - Revision A1 , week 821A2B282012345 AM. MEGA. 87-96 W83977EF-AW with OnNow / security keyboard Wake-Up-2 with OnNow / security keyboard Wake-Up with OnNow / security keyboard Wake-Up-2 with OnNow / security keyboard Wake-Up B2 MOD# 2Y3A2 MOC# 2Y2MOB# G2 MOB# 2Y1 MOA# MOA#2Y0 DSD#1Y3 DSB# DSC#1Y2B1 DSB# 1Y1A1DSA# DSA# 1Y0 G1 W83977EF 7407(2)74LS139 W83977EF/ CTF PRELIMINARY 16.0 PACKAGE DIMENSIONS (128-pin PQFP) Dimension in mm Dimension in inch H E Symbol Min Nom Max Min Nom Max E 102 65 A1 0.25 0.35 0.45 0.010 0.014 0.018 A2 2.57 2.72 2.87 0.101 0.107 0.113 103 64 0.004 0.008 0.012 b 0.10 0.20 0.30 c 0.10 0.15 0.20 0.004 0.006 0.008 D 13.90 14.00 14.10 0.547 0.551 0.555 19.90 20.00 20.10 0.783 0.787 0.791 E D HD e 0.50 0.020 HD 17.20 17.40 0.669 0.677 0.685 17.00 23.00 23.20 23.40 0.905 0.913 0.921 HE 0.95 L 0.65 0.80 0.025 0.031 0.037 39 128 1.60 0.063 1 L 0.08 1 y 0.003 38 e b 7 0 7 0 0 c Note: A 1.Dimension D & E do not include interlead flash. A2 2.Dimension b does not include dambar protrusion/intrusion . 3.Controlling dimension : Millimeter See Detail F A1 L y Seating Plane 4.General appearance spec. should be based L 1 on final visual inspection spec. Detail F Winbond Electronics (H.K.) Ltd. Winbond Electronics North America Corp. Headquarters Rm. 803, World Trade Square, Tower II, Winbond Memory Lab. No. 4, Creation Rd. III, Science-Based Industrial Park, 123 Hoi Bun Rd., Kwun Tong, Winbond Microelectronics Corp. Hsinchu, Taiwan Kowloon, Hong Kong Winbond Systems Lab. TEL: 886-3-5770066 TEL: 852-27513100 2727 N. First Street, San Jose, FAX: 852-27552064 FAX: 886-3-5792646 CA 95134, U.S.A. http://www.winbond.com.tw/ Voice & Fax-on-demand: 886-2-27197006 TEL: 408-9436666 FAX: 408-5441798 Taipei Office 11F, No. 115, Sec. 3, Min-Sheng East Rd., Taipei, Taiwan TEL: 886-2-27190505 FAX: 886-2-27197502 Note: All data and specifications are subject to change without notice. Please note that all data and specifications are subject to change without notice. All the trade marks of products and companies mentioned in this data sheet belong to their original owners. Publication Release Date: March 1999 -152 - Revision A1 5. PCB layout please use the "mm".