Preliminary W29C011A 128K ´ 8 CMOS FLASH MEMORY GENERAL DESCRIPTION The W29C011A is a 1-megabit, 5-volt only CMOS flash memory organized as 128K ´ 8 bits. The device can be programmed and erased in-system with a standard 5V power supply. A 12-volt V is not required. The unique cell architecture of the W29C011A results in fast program/erase operations with extremely low current consumption (compared to other comparable 5-volt flash memory FEATURES · · · -Active current: 25 mA (typ.) - - mA (typ.) -Page program cycle: 10 mS (max.) ·Automatic program timing with internal V -Effective byte-program cycle time: 39 mS ·End of program detection - -Toggle bit · -Data polling · · · ·TTL compatible I/O · · · · Available packages: 32-pin 600 mil DIP, 450 mil SOP and PLCC Publication Release Date: December 1997 - 1 - Revision A1 Software and hardware data protection JEDEC standard byte-wide pinouts Ten-year data retention Page program/erase cycles: 1,000 Latched address and data Read access time: 150 nS Fast chip-erase operation: 50 mS Software-protected data write generation PP Standby current: 20 128 bytes per page Fast page-write operations Low power consumptionSingle 5-volt program and erase operations products). The device can also be programmed and erased using standard EPROM programmers. PP Preliminary W29C011A PIN CONFIGURATIONS BLOCK DIAGRAM V NC1VVSS 2WE 3NC. .4OE 5A7 WE 6A8 A6 7A9 A5 8DIP A4 A39OE A2 A0 A1CE .A0 . GND AAAV/ 111NDWN 26CDEC5 PIN DESCRIPTION 4312 5SYMBOL PIN NAME A7 6A6 7A8 - A5 8A9 A4 9PLCC - A3 A2OE A1 A0CE OE Write Enable WE DDGDDDD QQNQQQQVDD 12D4356 - 2 - No ConnectionNC GroundGND Power Supply 20191817161514 DQ0 Output EnableDQ72113 2212 CE 23 Chip EnableA1011 24 10 DQ7DQ0A1125 Data Inputs/Outputs 32-pin 26 A16A027 Address Inputs A1328 29 A14 32 3031 DQ3 1716 DQ41815DQ2 A16 DQ5 1914DQ1 DQ6DQ0 2013 ARRAY DECODER DQ72112 CORE 2211 A102310 24 A1125 32-pin 26 27 A1328 DQ7 BUFFER A14 CONTROL29A12 OUTPUT A15 30 DQ0CE A16 31 DD 32 DD Preliminary W29C011A FUNCTIONAL DESCRIPTION Read Mode The read operation of the W29C011A is controlled by and OE, both of which have to be low for the host to obtain data from the outputs. is used for device selection. When is high, the chip OE is the output control and is used to gate data from the output pins. The data bus is in high impedance state when either or OE is high. Refer to the timing waveforms for further details. Page Write Mode The W29C011A is programmed on a page basis. Every page contains 128 bytes of data. If a byte of data within a page is to be changed, data for the entire page must be loaded into the device. Any byte The write operation is initiated by forcing WEOE of two steps. Step 1 is the byte-load cycle, in which the host writes to the page buffer of the device. Step 2 is an internal programming cycle, during which the data in the page buffers are simultaneously written into the memory array for non-volatile storage. During the byte-load cycle, the addresses are latched by the falling edge of either or WE, whichever occurs last. The data are latched by the rising edge of either or WE, whichever occurs first. If the host loads a second byte into the page buffer within a byte-load cycle time (T) of 200 mS, after the initial byte-load cycle, the W29C011A will stay in the page load cycle. Additional bytes can then be loaded consecutively. The page load cycle will be terminated and the internal programming cycle will start if no additional byte is loaded into the page buffer within 300 mS (TBLCO) from the last byte-load cycle, i.e., there is no subsequent WE high-to-low transition after the last rising edge of WE. A7 to A specify the page address. All bytes that are loaded into the page buffer must have the same page address. A0 to A6 specify the byte address within the page. The bytes may In the internal programming cycle, all data in the page buffers, i.e., 128 bytes of data, are written simultaneously into the memory array. Before the completion of the internal programming cycle, the host is free to perform other tasks such as fetching data from other locations in the system to prepare Software-protected Data Write The device provides a JEDEC-approved software-protected data write. Once this scheme is enabled, any write operation requires a series of three-byte program commands (with specific data to a specific address) to be performed before the data load operation. The three-byte load command sequence begins the page load cycle, without which the write operation will not be activated. This write scheme provides optimal protection against inadvertent write cycles, such as cycles triggered by noise during The W29C011A is shipped with the software data protection enabled. To enable the software data protection scheme, perform the three-byte command cycle at the beginning of a page load cycle. The device will then enter the software data protection mode, and any subsequent write operation must be Publication Release Date: December 1997 - 3 - Revision A1 preceded by the three-byte program command cycle. system power-up and power-down. to write the next page. be loaded in any order; sequential loading is not required. 16 BLC CE CE high. The write procedure consists low and and CE that is not loaded will be erased to "FFh" during programming of the page. CE is de-selected and only standby power will be consumed. CECE CE Preliminary W29C011A Hardware Data Protection Noise/Glitch Protection: A WE pulse of less than 15 nS in duration will not initiate a write cycle. VDD DD (3) Write Inhibit Mode: Forcing OE high, or WE high will inhibit the write operation. This prevents inadvertent w Data Polling (DQ7)-Write Status Detection The W29C011A includes a data polling feature to indicate the end of a programming cycle. When the W29C011A is in the internal programming cycle, any attempt to read DQof the last byte loaded during the page/byte-load cycle will receive the complement of the true data. Once the programming cycle is completed. DQ7 Toggle Bit (DQ6)-Write Status Detection In addition to data polling, the W29C011A provides another method for determining the end of a program cycle. During the internal programming cycle, any consecutive attempts to read DQ6 will produce alternating 0's and 1's. When the programming cycle is completed, this toggling between 0's and 1's will stop. The device is then ready for the next operation. 5-Volt-Only Software Chip Erase The chip-erase mode can be initiated by a six-byte command sequence. After the command loading cycles, the device enters the internal chip erase mode, which is automatically timed and will be completed in 50 mS. The host system is not required to provide any control or timing during this Product Identification The product ID operation outputs the manufacturer code and device code. Programming equipment automatically matches the device with its proper erase and programming algorithms. The manufacturer and device codes can be accessed by software or hardware operation. In the software access mode, a six-byte command sequence can be used to access the product ID. A read from address 0000H outputs the manufacturer code (DAh). A read from address 0001H outputs the In the hardware access mode, access to the product ID is activated by forcing and OE low, WE high, and raising A9 to 12 volts. - 4 - CE device code (C1h). The product ID operation can be terminated by a three-byte command sequence. operation. will show the true data. 7 rites during power-up or power-down periods. CE low, 3.8V. is less than Power Up/Down Detection: The programming operation is inhibited when V(2) (1) The integrity of the data stored in the W29C011A is also hardware protected in the following ways: Preliminary W29C011A TABLE OF OPERATING MODES Operating Mode Selection °DD = ± %SS MODE PINS ADDRESS DQ. OEWE VVVIHAIN WriteVVIHVAINDin VIHXXXHigh Z Write InhibitXVXXHigh Z/DOUT XXVIHXHigh Z/DOUT XVIHXXHigh Z VVIHVAINDIN VVVIHA0 = V; A1-A16 = V; A9 = VHHDA (Hex) VVVIHA0 = VIH; A1-A16 = V;Device Code A9 = VHHC1 (Hex) Publication Release Date: December 1997 - 5 - Revision A1 ILILIL Manufacturer CodeILILILILProduct ID ILIL5-Volt Software Chip Erase Output Disable IL Standby ILIL DoutILILRead CE = 12VHH = 0V, V, V105V C (Ambient Temperature), VOperating Range = 0 to 70 Preliminary W29C011A Command Codes for Software Data Protection Write BYTE SEQUENCE ADDRESS DATA 0 Write 1 Write 2 Write Software Data Protection Acquisition Flow - - - 6 - A0 (Hex)Address Format: A14 DQ0 (Hex)Data Format: DQ7 Notes for software program code: Exit Pause 10 mS page data 128 bytes of Load 0 to address 5555 to Load data A0 address 2AAA to Load data 55 address 5555 to Load data AA Write Flow Software Data Protection A0H 5555H 55H 2AAAH AAH 5555H Preliminary W29C011A Command Codes for Software Chip Erase BYTE SEQUENCE ADDRESS DATA 0 Write 1 Write 2 Write 3 Write 4 Write 5 Write Software Chip Erase Acquisition Flow - - Publication Release Date: December 1997 - 7 - Revision A1 A0 (Hex)Address Format: A14 DQ0 (Hex)Data Format: DQ7 Notes for software chip erase: Exit Pause 50 mS address 5555 to Load data 10 address 2AAA to Load data 55 address 5555 to Load data AA address 5555 to Load data 80 address 2AAA to Load data 55 address 5555 to Load data AA 10H 5555H 55H2AAAH AAH 5555H 80H 5555H 55H2AAAH AAH 5555H Preliminary W29C011A Command Codes for Product Identification BYTE SEQUENCE SOFTWARE PRODUCT SOFTWARE PRODUCT IDENTIFICATION ENTRY IDENTIFICATION EXIT ADDRESS DATA ADDRESS DATA 0 Write 1 Write 2 Write 3 Write-- 4 Write-- 5 Write-- mSmS Software Product Identification Acquisition Flow Product Identification Entry(1)Product Identification Exit(1) Product Identification Mode(2,3) mmS m - - -. - 8 - (4) The device returns to standard operation mode. (3) The device does not remain in identification mode if power down. IH; device code is read for A0 = VIL; manufacture code is read for A0 = VILA16 = V(2) A1 A0 (Hex).DQ0 (Hex); address format: A14(1) Data format: DQ7 Notes for software product identification: Pause 10 S address 5555 Normal Mode to Load data 60 (4) address 2AAA data = C1 Pause 10 to Read address = 1 Load data 55 address 5555 address 5555 to to Load data FO Load data AA address 2AAA address 5555 data = DA to to Read address = 0 Load data 55 Load data 80 address 5555 address 2AAA to to Load data AA Load data 55 address 5555 to Load data AA Pause 10 Pause 10 60H5555H 55H2AAAH AAH5555H F0H5555H80H5555H 55H2AAAH55H2AAAH AAH5555HAAH5555H Preliminary W29C011A DC CHARACTERISTICS Absolute Maximum Ratings PARAMETER RATING UNIT ss Potential-0.5 to +7.0V 0 to +70 °C °C -0.5 to VDD +1.0V D.C. Voltage on Any Pin to Ground Potential except OE ¡Õ 20 nS ) on Any Pin to Ground Potential-1.0 to VDD +1.0V V OE Pin to Ground Potential Operating Characteristics (V± %SSA ° PARAMETER SYM. TEST CONDITIONS LIMITS UNIT MIN. TYP. MAX. ICC--mA OEWE = = V, = VIH, all I/Os open /VIH, at f = 5 MHz DDI1-23mA = VIH, all I/Os open Other inputs = V/VIH DD I2-mA = VDD -0.3V, all I/Os open (CMOS input) Other inputs = VDD IVIN = GND to VDD--1mA IVIN = GND to VDD--mA V--V VIH--VDD +0.5V VI= 2.1 mA--V VOHIOH = -0.4 mA--V Power-up Timing PARAMETER SYMBOL TYPICAL UNIT TPU mS Power-up to Write OperationTPU.WRITE 5mS Publication Release Date: December 1997 - 9 - Revision A1 100.READPower-up to Read Operation 2.4Output High Voltage 0.45OL OLOutput Low Voltage 2.0Input High Voltage 0.8-0.3ILInput Low Voltage Current 10LOOutput Leakage Current LIInput Leakage -0.3V/GND CE 10020SBCurrentStandby V IL Current (TTL input) CE SBStandby V ILAddress inputs = V Current IL CE 50Power Supply C)= 0 to 70 = 0V, T, V10 = 5.0V DD device. Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the Voltage on -0.5 to 12.5 Transient Voltage ( -65 to +150Storage Temperature Operating Temperature Power Supply Voltage to V Preliminary W29C011A CAPACITANCE (VA ° PARAMETER SYMBOL CONDITIONS MAX. UNIT I/O Pin CapacitanceCV= 0V CINVIN = 0V6 AC CHARACTERISTICS AC Test Conditions (V± %) PARAMETER CONDITIONS Input Rise/Fall Time Input/Output Timing Level L = 100 pF AC Test Load and Waveforms +5V 1.8K ohm D 100 pF 1.3K ohm Input/Output 2.4V 2.0V 2.0V 0.8V0.8V 0.45V Test PointTest Point - 10 - OUT 1 TTL Gate and COutput Load 0.8V/2.0V 10 nS 0.45V to 2.4VInput Pulse Levels 10 = 5V DD pFInput Capacitance pF12I/O I/O C, f = 1 MHz)= 25 = 5.0V, TDD Preliminary W29C011A Read Cycle Timing Parameters (V± %SSA ° PARAMETER SYM. W29C011A-15 UNIT MIN. MAX. Read Cycle TimeTRC- TCE- T- TOE- T0- Low to Active Output T0- OE Low to Active Output TCHZ- High to High-Z Output TOHZ- OE High to High-Z Output TOH0- Byte/Page-Write Cycle Timing Parameters PARAMETER SYMBOL MIN. TYP. MAX. UNIT Write Cycle (erase and program)TWC--mS T0-- TAH-- TCS0-- WE Setup Time TCH0--WE Hold Time TOES-- OE High Setup Time TOEH-- OE High Hold Time TCP-- Pulse Width TWP--WE Pulse Width TWPH-- WE High Width Data Setup TimeTDS-- Data Hold TimeTDH-- Byte Load Cycle TimeT-mS Byte Load Cycle Time-outTBLCO--mS . Publication Release Date: December 1997 - 11 - Revision A1 IL and (b) low level signal's reference level is VIH is V(a) High level signal's reference level Note: All AC timing signals observe the following guidelines for determining setup and hold times: 300 2000.22BLC nS10 nS50 nS150 nS70 CE nS70 nS10 nS10 CE and nS CE and nS nS50Address Hold Time nSASAddress Setup Time 10 nSOutput Hold from Address change nS45 CE nS45 nSOLZ CE nSCLZ nS70Output Enable Access Time nS150AAAddress Access Time nS150Chip Enable Access Time nS150 C)= 0 to 70 = 0V, T, V10 = 5.0V DD Preliminary W29C011A Data Polling and Toggle Bit Timing Parameters PARAMETER SYM. W29C011A-15 UNIT MIN. MAX. TOEP-OE to Data Polling Output Delay TCEP- to Data Polling Output Delay TOET- OE to Toggle Bit Output Delay TCET- to Toggle Bit Output Delay TIMING WAVEFORMS Read Cycle Timing Diagram TRC TCE TOE OE T TOLZVIH WE TCLZ TT High-Z High-Z TAA - 12 - Data Valid Data Valid DQ7-0 CHZ OH OHZ CE Address A16-0 CE nS150 nS70 CE nS150 nS70 Preliminary W29C011A Page Write Timing Diagram T Byte/page load cycle starts software data protection mode Address A16-0 55552AAA5555 AA 55A0 CE TTT WE T SW1SW2 Byte 0 SW0 (last byte) Internal write starts Note CE(WE WE Controlled Write Cycle Timing Diagram T TWC TT CETT TT OE TTWP WE T T Publication Release Date: December 1997 - 13 - Revision A1 Internal write starts DH Data Valid DQ7-0 DS WPH OEHOES CH CS Address A16-0 AH AS BLCO ) Controlled Write Cycle Timing Diagram" for a detailed timing diagram.Notes: Refer to " Byte N-1 Byte N WPH BLCOWP BLC OE DQ6 Three-byte sequence for WC Timing Waveforms, continued Preliminary W29C011A CE Controlled Write Cycle Timing Diagram TTTWC T TCPH TCP CE TTOEH WE TDS DQ7-0 TDH DATA Polling Timing Diagram WE T CE TOESTOEH TOEP DQ7-0X TWC - 14 - X X X OE CEP Address A16-0 Internal Write Starts Data Valid High Z OE OES Address A16-0 AH AS BLCO Timing Waveforms, continued Preliminary W29C011A Toggle Bit Timing Diagram WE TTOES OE TWC 5 Volt-Only Software Chip Erase Timing Diagram WC WPTTBLCT WE WPHT SW0SW1SW2SW3SW4 SW5 Publication Release Date: December 1997 - 15 - Revision A1 Internal programming starts BLCO OE CE 10 AA 55AA80 55DQ7-0 2AAA5555 55552AAA55555555 Address A16-0 chip erase T Six-byte code for 5V-only software DQ6 OEH CE Address A16-0 Timing Waveforms, continued Preliminary W29C011A ORDERING INFORMATION PART NO. ACCESS TIME POWER SUPPLY STANDBY VDD PACKAGE (nS) CURRENT MAX. (mA) CURRENT MAX. (mA) 600 mil DIP 450 mil SOP - 16 - applications where personal injury might occur as a consequence of product failure. 2. Purchasers are responsible for performing appropriate quality assurance testing on products intended for use in 1. Winbond reserves the right to make changes to its products without prior notice. Notes: 32-pin PLCC10050150W29C011AP-15 10050150W29C011AS-15 10050150W29C011A-15 Preliminary W29C011A PACKAGE DIMENSIONS 32-pin P-DIP A A1 A2 B B1 cD 3217D E E1 e1 E1 L a015015 eA S 116 ES tie bar burrs.c A2AA1 . L Be1eaA B1 final visual inspection spec. 32-pin SO Wide Body e1A A1 A2 b cEHE D E eL HE L1b LE S y q010010 e1Notes:D or tie bar burrs. c AA2 protrusion/intrusion. .Se yALE1 See Detail F on final visual inspection spec. Publication Release Date: December 1997 - 17 - Revision A1 Seating Plane 5. General appearance spec should be based 4. Controlling dimension: Inches. and determined at the mold parting line. 3. Dimensions D & E include mold mismatch 2. Dimension b does not include dambar 1. Dimensions D Max. & S include mold flash 0.004 0.10 0.91 0.036 1.601.401.190.0630.0550.047 16 0.990.790.580.0390.0310.023 Detail F 14.3814.1213.870.5560.5560.546 1.421.271.120.0560.0500.044 11.300.4500.4450.440 11.4311.18 20.7520.450.8170.805 0.310.200.150.0120.0080.006 0.020 0.510.410.360.0160.014 2.822.692.57 0.1110.1060.101 0.100.004 3.000.118 Max.Nom.Min.Max.Nom.Min. 1732 Symbol Dimension in mmDimension in Inches 6.General appearance spec. should be based on 5.Controlling dimension: Inches. protrusion/intrusion. Seating Plane 4.Dimension B1 does not include dambar are determined at the mold parting line. 3.Dimensions D & E1 include mold mismatch and Base Plane 2.Dimension E1 does not include interlead flash. 1.Dimensions D Max. & S include mold flash or Notes: 2.160.085 17.0216.5116.000.6700.6500.630 3.563.303.050.1400.1300.120 2.792.542.290.1100.1000.090 13.970.5550.5500.545 14.1013.84 14.990.6000.590 15.4915.240.610 42.1641.91 1.6601.650 0.360.250.200.0140.0100.008 1.371.271.220.0540.0500.048 0.022 0.560.460.410.0180.016 4.063.943.810.1600.1550.150 0.250.010 5.330.210 Max.Nom.Min.Max.Nom.Min. Symbol Dimension in mmDimension in inches Preliminary W29C011A 32-pin PLCC Min.Min. HE0.1403.56AE 0.50 0.020A1 413230 0.1050.1100.1152.672.802.93A2 0.0260.0320.660.81 0.0280.71b1 0.0160.0180.0220.410.460.56b 529 0.0080.0100.0140.200.250.35c 0.5470.55313.8914.05 0.55013.97D 0.4470.4500.45311.3511.4311.51E 0.0440.0500.0561.121.271.42e 0.4900.5100.53012.4512.9513.46GD GD0.3900.4100.4309.9110.4110.92GEDHD 0.5850.5900.59514.8614.9915.11HD 0.4850.4900.49512.3212.4512.57HE 0.0750.0900.0951.912.292.41L y0.0040.10 ° ° ° °010010 q 21 13 Notes: 1420c L 2AA e1bA b1 yGE VERSION HISTORY VERSION DATE PAGE DESCRIPTION - 18 - Initial IssuedDec. 1997A1 Seating Plane visual inspection sepc. 4. General appearance spec. should be based on final 3. Controlling dimension: Inches. 2. Dimension b1 does not include dambar protrusion/intrusion. 1. Dimensions D & E do not include interlead flash. Max.Nom.Max.Nom. Symbol Dimension in mmDimension in Inches Package Dimensions, continued Preliminary W29C011A Winbond Electronics (H.K.) Ltd. Winbond Electronics North America Corp. Headquarters Winbond Memory Lab. No. 4, Creation Rd. III, Rm. 803, World Trade Square, Tower II, 123 Hoi Bun Rd., Kwun Tong, Science-Based Industrial Park, Winbond Microelectronics Corp. Kowloon, Hong Kong Hsinchu, Taiwan Winbond Systems Lab. TEL: 886-3-5770066 TEL: 852-27513100 2727 N. First Street, San Jose, FAX: 886-3-5796096 FAX: 852-27552064 CA 95134, U.S.A. http://www.winbond.com.tw/ TEL: 408-9436666 Voice & Fax-on-demand: 886-2-7197006 FAX: 408-5441798 Taipei Office 11F, No. 115, Sec. 3, Min-Sheng East Rd., Taipei, Taiwan TEL: 886-2-7190505 FAX: 886-2-7197502 Note: All data and specifications are subject to change without notice. Publication Release Date: December 1997 - 19 - Revision A1