VMIMCN-5521L Micro Channel-to-VMEbus Adapter • Connects IBM RISC 6000 workstations to VMEbus-based systems • Supports A32, A24, A16, D32, D16, D8 master(s) and slave(s) in the VMEbus chassis • Software-controlled dynamic address mapping • Generates all VMEbus signals required of a VMEbus master • Supports a variety of cable lengths • Link consists of one 6U VMEbus board, one Micro Channel interface board, and cable assembly • Meets ANSI/IEEE STD 1014-1987 PRODUCT OVERVIEW — The VMIMCN-5521L is PHOTO NOT AVAILABLE a high performance Micro Channel-to-VMEbus link. This link allows a RISC 6000 Series host, that supports a 32-bit Micro Channel Bus, to function as a VMEbus master controlling an external VMEbus chassis. The VMIMCN-5521L can function as a master in the remote VMEbus chassis; or if placed in slot one of the VMEbus, can function as the only master in the chassis. CONFIGURATION — The VMIMCN-5521L consists of two boards and an interconnecting cable. One Several operating system calls are required to initialize board is an interrupting Micro Channel Bus single-slot slave the host system for accessing the VMIMCN-5521. VMIC and the other board is a 6U form factor VMEbus master. offers an AIX Driver, model number VMIMCN/SW-5521. Figure 1 is a block diagram of the VMIMCN-5521L. VMEbus BUS MASTER OPERATION — The OPERATION — All single Micro Channel Bus cycles VMIMCN-5521L operates in single cycle mode. Each to the memory area mapped by the Micro Channel Interface access to the VMEbus may require the VMIMCN-5521L to slave board are repeated to memory-mapped cycles in the arbitrate for VMEbus mastership. The VMIMCN-5521L is VMEbus chassis. Micro Channel streaming data transfers a Release-on-Request (ROR) VMEbus master, thus, and VMEbus block transfers are not supported. If the cycle arbitration may not be required every cycle. VMEbus addresses a VMEbus slave, the link completes the cycle. If arbitration will never be required when the no slave is addressed, cycle is completed and an Error Flag VMIMCN-5521L is the only bus master in the VMEbus is set. VMEbus interrupts may be individually configured chassis. by the user for handling by the workstation CPU or by a local VMEbus CPU. 8-, 16-, and 32-bit data transfers are Micro Channel TIMING CONSTRAINTS — The supported. Micro Channel specification contains a very restrictive limit on the access time of any slave device. Full compliance with DYNAMIC ADDRESS MAPPING — The this specification requires the VMIMCN-5521L to be the VMIMCN-5521L provides mapping registers for only bus master in the VMEbus chassis and all VMEbus translating Micro Channel Bus address cycles into VMEbus address space cycles. Ordering Options The VMIMCN-5521L occupies 128 Mbyte of Feb. 18, 1994 800-705521-000 A ABC – D E F contiguous Micro Channel memory space. This space may VMIMCN-5521L –0 – be mapped into any VMEbus address space (short I/O, ABC = Cable Lengths standard, and extended, in either user or supervisory mode). 010 = 10-foot Cable 020 = 20-foot Cable A byte swapping Control Register greatly enhances transfer 025 = 25-foot Cable of floating-point numbers between little Endian and big Note Endian processors. All seven VMEbus interrupt levels may VMIMCN-5521L-025 consists of a VMEbus Board, a Micro Channel Interface Board, and be monitored, and translated into up to seven Micro a 25-foot cable. Channel interrupt requests as configured by software. Error For Ordering Information, Call: 1-800-322-3616 or 1-256-880-0444 • FAX (256) 882-0859 conditions may be reported by a request on any chosen E-mail: info@vmic.com Web Address: www.vmic.com interrupt level. Copyright © July 1992 by VMIC Specifications subject to change without notice. VMIC • 12090 South Memorial Parkway • Huntsville, Alabama 35803-3308 1 VME Microsystems Intl. Corp. 12090 South Memorial Parkway, Huntsville, AL 35803-3308 USA VMIMCN-5521L CABLE Micro Channel MIO ADC CMD SO S1 BE(0..3) CO SETUP CONTROL CHRESET CONTROL SIGNAL CD SFDBK SIGNAL BUFFER CD DS16 BUFFER CD D532 CD CHRDY IRQ[3..7] IRQ[9..11] INTERFACE CONTROL DATA LOGIC D0 to D31 BUFFER ADDRESS AND DATA BUFFER MADE 24 ADDRESS BUFFER A0 to A31 Micro Channel Board VMEbus CABLE ADDRESS BUS 31 AM0 to AM5 6 DATA BUS 32 CONTROL DTACK SIGNAL BUFFER AS DSO B DSI U WRITE VME F CONTROL LWORD F LOGIC IACK E ADDRESS SYSRESET R AND DATA S IR1 to IR7 BUFFER BR0 to BR3 BG0 to BG3 BGIN0 to BGIN3 BGOUT0 to BGOUT3 BBSY BERR VME BOARD Figure 1. VMIMCN-5521L Block Diagram 2 For Ordering Information, Call: 1-800-322-3616 or 1-256-880-0444 • FAX (256) 882-0859 VMIMCN-5521L TIMING slaves in the chassis must always access in less than 2.0 μs. Use of another VMEbus master and/or slower slaves will Interface Overhead (25-foot cable): result in possible degradation of Micro Channel AS (rd/wr): (780 ns/820 ns) performance. In any case, all VMEbus slaves accessed by DS (rd/wr): (860 ms/900 ns) the VMIMCN-5521L must always access in less than 3.5 DTACK (rd/wr): (520 ns/240 ns) microseconds (excluding arbitration time). PERFORMANCE PHYSICAL/ENVIRONMENTAL Measure Transfer Rate (25-foot cable, SRAM 5; PS/2 70): Temperature Range: Read Write 10 to +35 °C, operating (Micro Channel) 1.98 Mbyte/s 2.24 Mbyte/s -20 to +85 °C, storage CONNECTION Relative Humidity Range: 20 to 80 percent, noncondensing Requirement: One 80-conductor round cable, up to 25 feet long Cooling: Forced air convection TRADEMARKS Size: Double Eurocard form factor (Slave Board) The VMIC logo is a registered trademark of VME Micro Channel board type 3 adapter form factor Microsystems International Corporation. Other registered (Master Board) trademarks are the property of their respective owners. POWER Requirement: 5 V at 4.5 A (for VME board) 5 V at 1.5 A (for Micro Channel Interface board) Micro Channel BUS Micro Channel BOARD Up to 25 feet VME BOARD VMEbus GLOBAL I/O CPU MEMORY SLAVE Figure 2. Typical Configuration Utilizing the VMIMCN-5521L Adapter Link VMIC • 12090 South Memorial Parkway • Huntsville, Alabama 35803-3308 3