VMIMB1-5576 Multibus I Fiber-Optic Reflective Memory • High-speed, easy-to-use fiber-optic network (170 Mbaud serially) • Data written to memory in one node is also written to memory in all nodes on the network • Data transferred at 6.2 Mbyte/s without redundant transfer • Data transferred at 3.2 Mbyte/s with redundant transfer • Any node on the network can generate an interrupt in any other node with a single command • Error detection • Redundant transmission mode for suppressing errors • No processor overhead • No processor involvement in the operation of the network • Up to 1 Mbyte of Reflective Memory • Byte or word memory access • Communication link compatible with the VMIVME-5576 and VMIPCI-5576 • ANSI/IEEE standard 796-1983 Multibus I-compliant board • Also jumper configurable as a Reliance AutoMax Multibus-compatible board INTRODUCTION — The VMIMB1-5576 is a Multibus I board which may be used with other 5576 family boards to form a high-performance, daisy-chained, fiber-optic network. Data is transferred by writing to on-board global RAM. The data is automatically sent to the same location in accessing an on-board register. In some applications, this memory on all Reflective Memory boards on the network. The node number would be useful in establishing the function of network can include Multibus I, VMEbus, and PCI bus the node. systems. VMIMB1-5576 Multibus Reflective Memory has a PRODUCT OVERVIEW — The Reflective Memory jumper-selectable little memory option, which limits the concept provides a very fast and efficient way of sharing data accessible SRAM to 64 Kbyte. In addition, the little memory across distributed computer systems. option activates several P2 connector inputs, which make the VMIMB1-5576 compatible with the Reliance AutoMax VMIC’s VMIMB1-5576 Reflective Memory interface Multibus system. allows data to be shared between up to 256 independent systems (nodes) at rates up to 6.2 Mbyte/s. Each LINK ARBITRATION — The VMIMB1-5576 system VMIMB1-5576 Reflective Memory board may be configured is a fiber-optic daisy chain ring as shown in Figure 1. Each with 256 Kbyte, 512 Kbyte, or 1 Mbyte of on-board SRAM. transfer is passed from node to node until it has gone all the The local SRAM provides fast Read access times to stored way around the ring and reaches the originating node. Each data. Writes are stored in local SRAM and broadcast over a node retransmits all transfers that it receives except those that high-speed, fiber-optic data path to other Reflective Memory it had originated. Nodes are allowed to insert transfers nodes. The transfer of data between nodes is software between transfers passing through. transparent, so no I/O overhead is required. Transmit and Receive FIFOs buffer data during peak data rates to optimize INTERRUPT TRANSFERS — In addition to CPU and bus performance to maintain high data throughput. transferring data between nodes, the VMIMB1-5576 will allow any processor in any node to generate an interrupt on The Reflective Memory also allows interrupts to one or any other node. These interrupts would generally be used to more nodes by writing to a byte register. Three separate, indicate to the receiving node that new data has been sent and user-definable interrupts may be used to synchronize a system is ready for processing. These interrupts are also used to process, or used to follow any data that may have preceded it. indicate that processing of old data is completed and the The interrupt always follows the data to ensure the reception receiving node is ready for new data. of the data before the interrupt is acknowledged. Three interrupts are available. The user may define the The VMIMB1-5576 requires no initialization unless function, priority, and vector for each interrupt. Any interrupts are being used. If interrupts are used, both vectored processor can generate an interrupt on any other node on the and nonvectored interrupts are supported. network. In addition, any processor on the network can generate an interrupt on all nodes on the network. Interrupts Each node on the system has a unique identification are generated by simply writing to a single VMIMB1-5576 number between 0 and 255. The node number is established register. during hardware system integration by placement of jumpers on the board. This node number can be read by software by VMIC • 12090 South Memorial Parkway • Huntsville, Alabama 35803-3308 1 VMIMB1-5576 facilities of the TAXI chipset and additional parity encoding and checking. When a node detects an error, the erroneous Ordering Options transfer is removed from the system and a VMEbus interrupt January 14, 1998 800-335576-000 D ABC – D E F is generated, if enabled. The error rate of the VMIMB1-5576 VMIMB1-5576 – – is a function of the rate of errors produced in the optical A = Memory Options portion of the system. This optical error rate depends on the 0 = 256 Kbyte -12 1 = 512 Kbyte length and type of fiber-optic cable. Error rates of 10 are 2 = 1 Mbyte -12 achievable. Assuming an optical error rate of 10 , the error B = FIFO Option -10 0 = 512 Transfer FIFO rate of the VMIMB1-5576 is 10 transfers/transfer. 1 = 4 K Transfer FIFO C = Enclosure Options 0 = No Enclosure (Standard Multibus) The VMIMB1-5576 can be operated in a redundant 1 = AutoMax Enclosure transfer mode in which each transfer is transmitted twice. In Connector Data this mode of operation, the first of the two transfers is used Compatible Connector ST Connector unless an error is detected in which case the second transfer is PC Board Fiber-Optic Fiber-Optic Receiver HFBR-2100 used. In the event that an error is detected in both transfers, the Transmitter/Receiver (Hewlett-Packard) Fiber-Optic Transmitter HFBR-1100 node removes the transfer from the system. The probability of (Hewlett-Packard) -20 both transfers containing an error is 10 , or about one error Cable Specifications every 3,731,000 years at maximum data rate. Fiber-Optic Cable – Multimode; 62.5 Micron core. Transmitters operate at 1,300 nm at 170 Mbaud. Maximum attenuation between nodes is 9 dB. PROTECTION AGAINST LOST DATA — Data Minimum attenuation between nodes is .5 dB. received by the node from the fiber-optic cable is error Fiber-Optic Cable Assemblies ABC – D E F checked and placed in a receive FIFO. Arbitration with VMICBL-000-F3 – – accesses from the VMEbus then takes place and the data is A = Fiber-Optic Connector Type 0 = Ceramic Ferrule ST Connector written to the node’s SRAM and to the node’s transmit FIFO. 1 = Stainless Steel Ferrule ST Connector Data written to the board from the VMEbus is placed directly BC = Cable Lengths 00 = Not Used 09 = 1,000 ft (304.8 m) into SRAM and into the transmit FIFO. Data in the transmit 01 = 5 ft (1.5 m) 10 = 1,500 ft (457.3 m) 02 = 25 ft (7.6 m) 11 = 2,000 ft (609.7 m) FIFO is transmitted by the node over the fiber-optic cable to 03 = 50 ft (15.2 m) 12 = 2,460 ft (750.0 m) 04 = 100 ft (30.4 m) 13 = 3,280 ft (1,000 m) the next node. Data could be lost if either FIFO were allowed 05 = 150 ft (45.7 m) 14 = 4,100 ft (1,250 m) to become full. 06 = 200 ft (60.9 m) 15 = 4,920 ft (1,500 m) 07 = 350 ft (106.7 m) 16 = 5,740 ft (1,750 m) 08 = 500 ft (152.4 m) 17 = 6,560 ft (2,000 m) The product is designed to prevent either FIFO becoming Note full and overflowing. It is important to note the only way that VMIC offers single fiber cable assemblies that are compatible with the VMIVME-5576 in length ranging from 1.5 to 2,000 m. These cable assemblies data can start to accumulate in FIFOs is for data to enter the are U.L./NEC-rated OFNP and have a 2.5 mm ST-style bayonet connector node at a rate greater than 6.2 Mbyte/s or 3.2 Mbyte/s in on each end. redundant mode. Since data can enter from the fiber and from For Ordering Information, Call: 1-800-322-3616 or 1-256-880-0444 • FAX (256) 882-0859 the VMEbus, it is possible to exceed these rates. If the E-mail: info@vmic.com Web Address: www.vmic.com transmit FIFO becomes half-full, a bit in the Status Register Copyright © April 1990 by VMIC Specifications subject to change without notice. is set and, if enabled, an interrupt is generated. This condition is an indication to the software in the node that writes to the All data and interrupt command transfers contain the Reflective Memory should be suspended until the FIFO node number of the node that originated the transfer. This becomes less than half-full. If the half-full indication is information is used primarily so the originating node can ignored and the transmit FIFO becomes full, then writes to the remove the transfer from the network after the transfer has Reflective Memory will result in the VMIMB1-5576 traversed the ring. The node identification is also used by ‘waiting’ the Multibus by not issuing the bus acknowledge nodes receiving interrupt commands. When a node receives signal. an interrupt command for itself, it places the identification number of the originating node in a FIFO. Up to 512 NETWORK MONITOR — There is a bit in a Status interrupts can be stacked in the FIFO. During the interrupt Register that can be used to verify that data is traversing the service routine, the identification of the interrupting node can ring (that is, the ring is not broken). This can also be used to be read from the FIFO. measure network latency. ERROR MANAGEMENT — Errors are detected by the VMIMB1-5576 with the use of the error detection 2 For Ordering Information, Call: 1-800-322-3616 or 1-256-880-0444 • FAX (256) 882-0859 VMIMB1-5576 SPECIFICATIONS Multibus Interrupts: This product is compatible with both the (V0) nonvectored interrupt convention and the (V2) two INTA cycle vectored interrupt convention. Memory Size: Little memory configuration - 64 K This product does not support the three INTA cycle Big memory configuration: 256 Kbyte, 512 Kbyte, or vectored interrupt convention. The activation and 1 Mbyte modes of each interrupt are controlled through software accessible control registers. Access Times: Writes: 150 ns (best-case arbitration) AutoMax Multibus Compatibility: As mentioned 450 ns (worst-case arbitration) above, the memory address can be specified through P2 Reads: 230 ns (best-case arbitration) pins defined by the AutoMax Multibus Specification. In 480 ns (worst-case arbitration) addition, while in the little memory configuration, the Note: The above times are based on a Multibus I unique AutoMax P2 signals MPRO/, WDOK/, and system capable of operating at the maximum speed BDRST/ are also implemented. Also, the -xx1 option per the specification. The actual access times are includes an AutoMax enclosure around the board. highly dependent on the Multibus I system used. The timing of typical Multibus systems vary Byte Swapping: The VMIMB1-5576 can be used in significantly. systems that incorporate big-endian CPUs such as the 680x0 processor family or little-endian CPUs such as Network Transfer Rate: 6.2 Mbyte/s (longword the 80x86 processor family. The VMIMB1-5576 accesses) without redundant transfer provides a byte-swapping feature for endian conversion. 3.2 Mbyte/s (longword accesses) with redundant transfer INTERCONNECTION COMPATIBILITY Cable Requirements: Two fiber-optic cables Multibus: This product complies with the Multibus I specification (ANSI/IEEE STD 796-1983). The Cable Length: 2,000 m maximum between nodes compliance levels are (D16) and (M20 or M24) and (V0 or V2). This product complies with the AutoMax Configuration: Daisy chain ring up to 256 nodes Multibus Specification of Reliance, (revision date April 11, 1996). PHYSICAL/ENVIRONMENTAL Big Memory Configuration: Compatible with both Temperature Range: 0 to 55 °C, operating the 20 address line (M20) and the 24 address line (M24) -40 to 85 °C, storage Multibus I systems. Relative Humidity: 20 to 80 percent, noncondensing Addressable on 256 Kbyte boundaries for the 256 Kbyte memory option. Power Requirements: 2.1 A maximum at +5 VDC ±5 percent Addressable on 512 Kbyte boundaries for the 512 Kbyte memory option. DATA TRANSFERS Addressable on 1 Mbyte boundary for the 1 Mbyte memory option. Data written into the Reflective Memory is broadcast to all nodes on the network without further involvement of the Little Memory Configuration: On-board jumpers sending or receiving nodes. Data is transferred from memory can locate the 64 Kbyte of board memory on 64 Kbyte locations on the sending nodes to corresponding memory boundaries with the 1 Mbyte (20 address line) address locations on the receiving nodes. space. Optionally, the on-board jumpers can be arranged to allow off-board address specification through the P2 A functional block diagram of the VMIMB1-5576 is connector as indicated by the AutoMax Multibus shown in Figure 2. Specification. TRADEMARKS Multibus Data Width: This product complies with the (D16) specification, which permits data transfers in both The VMIC logo is a registered trademark of VMIC. 8- and 16-bit widths. Other registered trademarks are the property of their respective owners. VMIC • 12090 South Memorial Parkway • Huntsville, Alabama 35803-3308 3 VMIMB1-5576 C 5 P 5 VMEbus CHASSIS U 7 NODE 0 WITH CPU AND 6 VMIVME-5576 C 5 P 5 U 7 Multibus CHASSIS 6 NODE 1 WITH CPU AND VMIMB1-5576 VME COMPUTER NODES CAN BE VMEbus-BASED COMPUTERS OR COMPUTERS 5 WITH VMEbus I/O CHANNELS 5 SUCH AS SUN, HARRIS NIGHT NODE 2 7 HAWK, CONCURRENT, SILICON 6 GRAPHICS, DATA GENERAL, MOTOROLA DELTA SERIES, ENCORE 91 SERIES, ANY VMEbus CHASSIS, ETC. NODE 255 PCI bus PCI bus CHASSIS WORKSTATION WITH VMIPCI-5576 UP TO 2,000 m BETWEEN NODES Figure 1. Network Example Using Reflective Memory System FIBER-OPTIC FIBER-OPTIC CABLE CABLE FO FO REC'D TX TAXI TAXI RECEIVER TRANSMITTER INT0 8 • INTERRUPT • LOGIC • INT7 TAXI INTERFACE 4 Kbyte/ 4 Kbyte/ CONTROL 512 DEEP 512 DEEP LOGIC IN FIFO OUT FIFO CTRL CTRL CS FIFO/RCV CTRL RAM CTRL WR RAM ADDRESS CONTROL Multi- Multibus I/F bus 1 Mbyte RAM MAXIMUM DATA MULTI- PLEXER Figure 2. VMIMB1-5576 Functional Block Diagram 4 For Ordering Information, Call: 1-800-322-3616 or 1-256-880-0444 • FAX (256) 882-0859