128Mb: x32 SDRAM Features Synchronous DRAM MT48LC4M32B2 – 1 Meg x 32 x 4 banks For the latest data sheet, please refer to the Micron Web site: www.micron.com/sdram Figure 1: Pin Assignment (Top View) 86-Pin Features TSOP • PC100 functionality Fully synchronous; all signals registered on positive edge of system clock VDD 1 86 VSS DQ0 2 85 DQ15 Internal pipelined operatio n; column address can be VDDQ 3 84 VSSQ DQ1 4 83 DQ14 changed every clock cycle DQ2 5 82 DQ13 Internal banks for hiding row access/precharge VSSQ 6 81 VDDQ DQ3 7 80 DQ12 Programmable burst lengths: 1, 2, 4, 8, or full page DQ4 8 79 DQ11 VDDQ 9 78 VSSQAuto precharge, includes co ncurrent auto precharge, DQ5 10 77 DQ10 and auto refresh modes DQ6 11 76 DQ9 VSSQ 12 75 VDDQ Self Refresh Mode DQ7 13 74 DQ8 NC 14 73 NC64ms, 4,096-cycle refresh (15.6µs/row) VDD 15 72 VSS LVTTL-compatible inputs and outputs DQM0 16 71 DQM1 WE# 17 70 NC Single +3.3V ±0.3V power supply CAS# 18 69 NC RAS# 19 68 CLKSupports CAS latency (CL) of 1, 2, and 3 CS# 20 67 CKE A11 21 66 A9 BA0 22 65 A8 Options Marking BA1 23 64 A7 A10 24 63 A6 Configuration A0 25 62 A5 A1 26 61 A4 4M32B2 – 4 Meg x 32 (1 Meg x 32 x 4 banks) A2 27 60 A3 1 DQM2 28 59 DQM3 Package – OCPL VDD 29 58 VSS NC 30 57 NC TG – 86-pin TSOP (400 mil) DQ16 31 56 DQ31 VSSQ 32 55 VDDQ P – 86-pin TSOP (400 mil) lead-free DQ17 33 54 DQ30 – 90-ball FBGA (8mm x 13mm) F5 DQ18 34 53 DQ29 VDDQ 35 52 VSSQ B5 – 90-ball FBGA (8mm x 13mm) lead-free DQ19 36 51 DQ28 DQ20 37 50 DQ27 Timing (cycle time) VSSQ 38 49 VDDQ DQ21 39 48 DQ26 – 6ns (166 MHz) -6 DQ22 40 47 DQ25 VDDQ 41 46 VSSQ -7 – 7ns (143 MHz) DQ23 42 45 DQ24 Die revision :G VDD 43 44 VSS Operating temperature range None – Commercial (0° to +70°C) Table 2: Configurations IT – Extended (–40°C to +85°C) 4 Meg x 32 Notes: 1. Off-center parting line Configuration 1 Meg x 32 x 4 banks Table 1: Key Timing Parameters 4K Refresh count CL = CAS (READ) latency Row addressing 4K (A0–A11) Bank addressing 4 (BA0, BA1) Access Time Speed Clock Setup Hold Column addressing 256 (A0–A7) Grade Frequency Cl = 3 Time Time Part Number Example: -6 166 MHz 5.5ns 1.5ns 1ns -7 143 MHz 5.5ns 2ns 1ns MT48LC4M32B2TG-7:G PDF: 09005aef80872800/Source: 09005aef80863355 Micron Technology, Inc., reserves the right to change products or specifications without notice. 128MbSDRAMx32_1.fm - Rev. J 6/06 EN 1 ©2001 Micron Technology, Inc. All rights reserved. Products and specifications discussed herein are subject to change by Micron without notice. 128Mb: x32 SDRAM Table of Contents Table of Contents General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 Ball Assignments and Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 Burst Length (BL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 Burst Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 CAS Latency (CL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 Operating Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 Write Burst Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 COMMAND INHIBIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 NO OPERATION (NOP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 LOAD MODE REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 ACTIVE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 PRECHARGE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 Auto Precharge. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 BURST TERMINATE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 AUTO REFRESH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 SELF REFRESH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 BANK/ROW ACTIVATION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 READs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 WRITEs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 PRECHARGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 Power-Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 Clock Suspend. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 Burst READ/Single WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 Concurrent Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 READ with Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 WRITE with Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 Electrical Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 Temperature and Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47 Timing Diagrams. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65 PDF: 09005aef80872800/Source: 09005aef80863355 Micron Technology, Inc., reserves the right to change products or specifications without notice. 128MbSDRAMx32TOC.fm - Rev. J 6/06 EN 2 ©2001 Micron Technology, Inc. All rights reserved. 128Mb: x32 SDRAM List of Figures List of Figures Figure 1: Pin Assignment (Top View) 86-Pin TSOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 Figure 2: Functional Block Diagram 4 Meg x 32 SDRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 Figure 3: 90-Ball FBGA Pin Assignment (Top View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 Figure 4: Mode Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Figure 5: CAS Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 Figure 6: Activating a Specific Row in a Specific Bank . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 Figure 7: Example: Meeting tRCD (MIN) When 2 < tRCD (MIN)/tCK< 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 Figure 8: READ Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 Figure 9: CAS Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 Figure 10: Consecutive READ Bursts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 Figure 11: Random READ Accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 Figure 12: READ-to-WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 Figure 13: READ-to-WRITE with Extra Clock Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 Figure 14: READ-to-PRECHARGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 Figure 15: Terminating a READ Burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 Figure 16: WRITE Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 Figure 17: WRITE Burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 Figure 18: WRITE-to0WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 Figure 19: Random WRITE Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 Figure 20: WRITE-to-READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 Figure 21: WRITE-to-PRECHARGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 Figure 22: Terminating a WRITE Burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 Figure 23: PRECHARGE Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 Figure 24: Power-Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 Figure 25: CLOCK SUSPEND During WRITE Burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 Figure 26: CLOCK SUSPEND During READ Burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 Figure 27: READ With Auto Precharge Interrupted by a READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 Figure 28: READ With Auto Precharge Interrupted by a WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 Figure 29: WRITE With Auto Precharge Interrupted by a READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 Figure 30: WRITE With Auto Precharge Interrupted by a WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 Figure 31: Example Temperature Test Point Location, 54-Pin TSOP: Top View . . . . . . . . . . . . . . . . . . . . . . . . . . .43 Figure 32: Example Temperature Test Point Location, 90-Ball VFBGA: Top View . . . . . . . . . . . . . . . . . . . . . . . . .43 Figure 33: Initialize and Load Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 Figure 34: Power-Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 Figure 35: Clock Suspend Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 Figure 36: Auto Refresh Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 Figure 37: Self Refresh Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 Figure 38: Single READ – Without Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 Figure 39: Read – With Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 Figure 40: Alternating Bank Read Accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 Figure 41: Read – Full-page Burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 Figure 42: Read – DQM Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 Figure 43: Single Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 Figure 44: Write – Without Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 Figure 45: Write – With Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 Figure 46: Alternating Bank Write Accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62 Figure 47: Write – Full-page Burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63 Figure 48: Write – DQM Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64 Figure 49: 86-Pin Plastic TSOP (400 mil) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65 Figure 50: 90-Ball FBGA (8mm x 13mm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66 PDF: 09005aef80872800/Source: 09005aef80863355 Micron Technology, Inc., reserves the right to change products or specifications without notice. 128MbSDRAMx32LOF.fm - Rev. J 6/06 EN 3 ©2001 Micron Technology, Inc. All rights reserved. 128Mb: x32 SDRAM List of Tables List of Tables Table 1: Key Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 Table 2: Configurations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 Table 3: 128Mb (x32) SDRAM Part Number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 Table 4: Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 Table 5: Ball Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 Table 6: Burst Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 Table 7: CAS Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 Table 8: Truth Table–Commands and DQM Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 Table 9: Truth Table – CKE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 Table 10: Truth Table – Current State Bank n, Command To Bank n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 Table 11: Truth Table – CURRENT STATE BANK n, COMMAND TO BANK m. . . . . . . . . . . . . . . . . . . . . . . . . . . .39 Table 12: Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 Table 13: Temperature Limits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 Table 14: Thermal Impedance Simulated Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 Table 15: DC Electrical Characteristics and Operating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 Table 16: IDD Specifications and Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 Table 17: Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 Table 18: Electrical Characteristics and Recommended AC Operating Conditions . . . . . . . . . . . . . . . . . . . . . . .45 Table 19: AC Functional Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 PDF: 09005aef80872800/Source: 09005aef80863355 Micron Technology, Inc., reserves the right to change products or specifications without notice. 128MbSDRAMx32LOT.fm - Rev. J 6/06 EN 4 ©2001 Micron Technology, Inc. All rights reserved. 128Mb: x32 SDRAM General Description Table 3: 128Mb (x32) SDRAM Part Number Part Number Architecture MT48LC4M32B2TG 4 Meg x 32 MT48LC4M32B2P 4 Meg x 32 MT48LC4M32B2F5 4 Meg x 32 MT48LC4M32B2B5 4 Meg x 32 General Description The 128Mb SDRAM is a high-speed CMOS, dynamic random-access memory containing 134,217,728-bits. It is internally configured as a quad-bank DRAM with a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK). Each of the 33,554,432-bit banks is organized as 4,096 rows by 256 columns by 32 bits. Read and write accesses to the SDRAM are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVE command, which is then followed by a READ or WRITE command. The address bits registered coincident with the ACTIVE command are used to select the bank and row to be accessed (BA0, BA1 select the bank, A0–A11 select the row). The address bits registered coincident with the READ or WRITE command are used to select the starting column location for the burst access. The SDRAM provides for programmable read or write burst lengths (BL) of 1, 2, 4, or 8 locations, or the full page, with a burst terminate option. An auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst sequence. The 128Mb SDRAM uses an internal pipelined architecture to achieve high-speed oper- ation. This architecture is compatible with the 2n rule of prefetch architectures, but it also allows the column address to be changed on every clock cycle to achieve a high- speed, fully random access. Precharging one bank while accessing one of the other three banks will hide the precharge cycles and provide seamless, high-speed, random-access operation. The 128Mb SDRAM is designed to operate in 3.3V, low-power memory systems. An auto refresh mode is provided, along with a power-saving, power-down mode. All inputs and outputs are LVTTL-compatible. SDRAMs offer substantial advances in DRAM operating performance, including the ability to synchronously burst data at a high data rate with automatic column-address generation, the ability to interleave between internal banks to hide precharge time and the capability to randomly change column addresses on each clock cycle during a burst access. PDF: 09005aef80872800/Source: 09005aef80863355 Micron Technology, Inc., reserves the right to change products or specifications without notice. 128MbSDRAMx32_2.fm - Rev. J 6/06 EN 5 ©2001 Micron Technology, Inc. All rights reserved. 128Mb: x32 SDRAM General Description Figure 2: Functional Block Diagram 4 Meg x 32 SDRAM CKE CLK CONTROL CS# LOGIC WE# BANK3 CAS# BANK2 BANK1 RAS# BANK0 REFRESH 12 MODE REGISTER COUNTER BANK0 ROW- 12 ROW- ADDRESS BANK0 ADDRESS MUX MEMORY 4 4 12 4096 LATCH ARRAY DQM0– 12 & (4,096 x 256 x 32) DQM3 DECODER DATA SENSE AMPLIFIERS OUTPUT 32 REGISTER 8192 DQ0– 2 I/O GATING 32 DQM MASK LOGIC DQ31 BANK READ DATA LATCH A0–A11, ADDRESS CONTROL WRITE DRIVERS 14 BA0, BA1 REGISTER DATA LOGIC 2 INPUT 32 256 REGISTER (x32) COLUMN DECODER COLUMN- ADDRESS 8 8 COUNTER/ LATCH PDF: 09005aef80872800/Source: 09005aef80863355 Micron Technology, Inc., reserves the right to change products or specifications without notice. 128MbSDRAMx32_2.fm - Rev. J 6/06 EN 6 ©2001 Micron Technology, Inc. All rights reserved. COMMAND DECODE 128Mb: x32 SDRAM Ball Assignments and Descriptions Ball Assignments and Descriptions Figure 3: 90-Ball FBGA Pin Assignment (Top View) 1234 5 6 789 A DQ26 DQ24 VSS VDD DQ23 DQ21 B DQ28 VDDQ VSSQ VDDQ VSSQ DQ19 C VSSQ DQ27 DQ25 DQ22 DQ20 VDDQ D VSSQ DQ29 DQ30 DQ17 DQ18 VDDQ E VDDQ DQ31 NC NC DQ16 VSSQ F VSS DQM3 A3 A2 DQM2 VDD G A4 A5 A6 A10 A0 A1 H A7 A8 NC NC BA1 A11 J CLK CKE A9 BA0 CS# RAS# K DQM1 NC NC CAS# WE# DQM0 L VDDQ DQ8 VSS VDD DQ7 VSSQ M VSSQ DQ10 DQ9 DQ6 DQ5 VDDQ N VSSQ DQ12 DQ14 DQ1 DQ3 VDDQ P DQ11 VDDQ VSSQ VDDQ VSSQ DQ4 R DQ13 DQ15 VSS VDD DQ0 DQ2 Ball and Array PDF: 09005aef80872800/Source: 09005aef80863355 Micron Technology, Inc., reserves the right to change products or specifications without notice. 128MbSDRAMx32_2.fm - Rev. J 6/06 EN 7 ©2001 Micron Technology, Inc. All rights reserved. 128Mb: x32 SDRAM Ball Assignments and Descriptions Table 4: Pin Descriptions Pin Numbers Symbol Type Description 68 CLK Input Clock: CLK is driven by the system clock. All SDRAM input signals are sampled on the positive edge of CLK. CLK also increments the internal burst counter and controls the output registers. 67 CKE Input Clock enable: CKE activates (HIGH) and deactivates (LOW) the CLK signal. Deactivating the clock provides precharge power-down and SELF REFRESH operation (all banks idle), active power-down (row active in any bank) or CLOCK SUSPEND operation (burst/access in progress). CKE is synchronous except after the device enters power-down and self refresh modes, where CKE becomes asynchronous until after exiting the same mode. The input buffers, including CLK, are disabled during power-down and self refresh modes, providing low standby power. CKE may be tied HIGH. 20 CS# Input Chip select: CS# enables (registered LOW) and disables (registered HIGH) the command decoder. All commands are masked when CS# is registered HIGH, but READ/WRITE bursts already in progress will continue and DQM operation will retain its DQ mask capability while CS# is HIGH. CS# provides for external bank selection on systems with multiple banks. CS# is considered part of the command code. 17, 18, 19 WE#, Input Command Inputs: WE#, CAS#, and RAS# (along with CS#) define the command CAS#, being entered. RAS# 16, 71, 28, 59 DQM0– Input Input/Output mask: DQM is sampled HIGH and is an input mask signal for write DQM3 accesses and an output enable signal for read accesses. Input data is masked during a WRITE cycle. The output buffers are placed in a High-Z state (two- clock latency) during a READ cycle. DQM0 corresponds to DQ0–DQ7, DQM1 corresponds to DQ8–DQ15, DQM2 corresponds to DQ16–DQ23 and DQM3 corresponds to DQ24–DQ31. DQM0–DQM3 are considered same state when referenced as DQM. 22, 23 BA0, BA1 Input Bank address input(s): BA0 and BA1 define to which bank the ACTIVE, READ, WRITE, or PRECHARGE command is being applied. 25–27, 60–66, 24, A0–A11 Input Address inputs: A0–A11 are sampled during the ACTIVE command (row- 21 address A0–A10) and READ/WRITE command (column-address A0–A7 with A10 defining auto precharge) to select one location out of the memory array in the respective bank. A10 is sampled during a PRECHARGE command to determine if all banks are to be precharged (A10 [HIGH]) or bank selected by BA0, BA1 (LOW). The address inputs also provide the op-code during a LOAD MODE REGISTER command. 2, 4, 5, 7, 8, 10, 11, DQ0– Input/ Data I/Os: Data bus. 13, 74, 76, 77, 79, DQ31 Output 80, 82, 83, 85, 31, 33, 34, 36, 37, 39, 40, 42, 45, 47, 48, 50, 51, 53, 54, 56 14, 30, 57, 69, 70, NC – No connect: These pins should be left unconnected. Pin 70 is reserved for SSTL 73 reference voltage supply. 3, 9, 35, 41, 49, 55, VDDQ Supply DQ power supply: Isolated on the die for improved noise immunity. 75, 81 6, 12, 32, 38, 46, VSSQ Supply DQ ground: Provide isolated ground to DQs for improved noise immunity. 52, 78, 84 1, 15, 29, 43 VDD Supply Power supply: +3.3V ±0.3V. 44, 58, 72, 86 VSS Supply Ground. PDF: 09005aef80872800/Source: 09005aef80863355 Micron Technology, Inc., reserves the right to change products or specifications without notice. 128MbSDRAMx32_2.fm - Rev. J 6/06 EN 8 ©2001 Micron Technology, Inc. All rights reserved. 128Mb: x32 SDRAM Ball Assignments and Descriptions Table 5: Ball Descriptions 90-Ball FBGA Symbol Type Description J1 CLK Input Clock: CLK is driven by the system clock. All SDRAM input signals are sampled on the positive edge of CLK. CLK also increments the internal burst counter and controls the output registers. J2 CKE Input Clock enable: CKE activates (HIGH) and deactivates (LOW) the CLK signal. Deactivating the clock provides precharge power-down and SELF REFRESH operation (all banks idle), active power-down (row active in any bank) or CLOCK SUSPEND operation (burst/access in progress). CKE is synchronous except after the device enters power-down and self refresh modes, where CKE becomes asynchronous until after exiting the same mode. The input buffers, including CLK, are disabled during power-down and self refresh modes, providing low standby power. CKE may be tied HIGH. J8 CS# Input Chip select: CS# enables (registered LOW) and disables (registered HIGH) the command decoder. All commands are masked when CS# is registered HIGH, but READ/WRITE bursts already in progress will continue and DQM operation will retain its DQ mask capability while CS# is HIGH. CS# provides for external bank selection on systems with multiple banks. CS# is considered part of the command code. J9, K7, K8 RAS#, Input Command inputs: RAS#, CAS#, and WE# (along with CS#) define the command CAS#, being entered. WE# K9, K1, F8, F2 DQM0–3 Input Input/Output mask: DQM is sampled HIGH and is an input mask signal for write accesses and an output enable signal for read accesses. Input data is masked during a WRITE cycle. The output buffers are placed in a High-Z state (two- clock latency) when during a READ cycle. DQM0 corresponds to DQ0–DQ7, DQM1 corresponds to DQ8–DQ15, DQM2 corresponds to DQ16–DQ23 and DQM3 corresponds to DQ24–DQ31. DQM0–3 are considered same state when referenced as DQM. J7, H8 BA0, BA1 Input Bank address input(s): BA0 and BA1 define to which bank the ACTIVE, READ, WRITE or PRECHARGE command is being applied. These pins also provide the op-code during a LOAD MODE REGISTER command. G8, G9, F7, F3, G1, A0–A11 Input Address inputs: A0–A11 are sampled during the ACTIVE command (row- G2, G3, H1, H2, J3, address A0–A11) and READ/WRITE command (column-address A0–A7; with A10 G7, H9 defining auto precharge) to select one location out of the memory array in the respective bank. A10 is sampled during a PRECHARGE command to determine if all banks are to be precharged (A10 HIGH) or bank selected by BA0, BA1 (LOW). The address inputs also provide the op-code during a LOAD MODE REGISTER command. R8, N7, R9, N8, P9, DQ0– I/O Data input/output: Data bus M8, M7, L8, L2, DQ31 M3, M2, P1, N2, R1, N3, R2, E8, D7, D8, B9, C8, A9, C7, A8, A2, C3, A1, C2, B1, D2, D3, E2 E3, E7, H3, H7, K2, NC – No connect: These pins should be left unconnected. H7 is a not connect for this K3 part but may be used as A12 in future designs. B2, B7, C9, D9, E1, VDDQ Supply DQ power: Provide isolated power to DQs for improved noise immunity. L1, M9, N9, P2, P7 B8, B3, C1, D1, E9, VSSQ Supply DQ ground: Provide isolated ground to DQs for improved noise immunity. L9, M1, N1, P3, P8 A7, F9, L7, R7 VDD Supply Power supply: Voltage dependant on option. A3, F1, L3, R3 VSS Supply Ground. PDF: 09005aef80872800/Source: 09005aef80863355 Micron Technology, Inc., reserves the right to change products or specifications without notice. 128MbSDRAMx32_2.fm - Rev. J 6/06 EN 9 ©2001 Micron Technology, Inc. All rights reserved. 128Mb: x32 SDRAM Functional Description Functional Description In general, this 128Mb SDRAM (1 Meg x 32 x 4 banks) is a quad-bank DRAM that oper- ates at 3.3V and includes a synchronous interface (all signals are registered on the posi- tive edge of the clock signal, CLK). Each of the 33,554,432-bit banks is organized as 4,096 rows by 256 columns by 32-bits. Read and write accesses to the SDRAM are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVE command, which is then followed by a READ or WRITE command. The address bits registered coincident with the ACTIVE command are used to select the bank and row to be accessed (BA0 and BA1 select the bank, A0–A11 select the row). The address bits (A0–A7) registered coincident with the READ or WRITE command are used to select the starting column location for the burst access. Prior to normal operation, the SDRAM must be initialized. The following sections provide detailed information covering device initialization, register definition, command descriptions and device operation. Initialization SDRAMs must be powered up and initialized in a predefined manner. Operational procedures other than those specified may result in undefined operation. Once power is applied to VDD and VDDQ (simultaneously) and the clock is stable (stable clock is defined as a signal cycling within timing constraints specified for the clock pin), the SDRAM requires a 100µs delay prior to issuing any command other than a COMMAND INHIBIT or NOP. Starting at some point during this 100µs period and continuing at least through the end of this period, COMMAND INHIBIT or NOP commands must be applied. Once the 100µs delay has been satisfied with at least one COMMAND INHIBIT or NOP command having been applied, a PRECHARGE command should be applied. All banks must then be precharged, thereby placing the device in the all banks idle state. Once in the idle state, at least two AUTO REFRESH cycles must be performed. After the AUTO REFRESH cycles are complete, the SDRAM is ready for mode register program- ming. Because the mode register will power up in an unknown state, it must be loaded prior to applying any operational command. If desired, the two AUTO REFRESH commands can be issued after the LMR command. The recommended power-up sequence for SDRAMs: 1. Simultaneously apply power to VDD and VDDQ. 2. Assert and hold CKE at a LVTTL logic LOW since all inputs and outputs are LVTTL- compatible. 3. Provide stable CLOCK signal. Stable clock is defined as a signal cycling within timing constraints specified for the clock pin. 4. Wait at least 100µs prior to issuing any command other than a COMMAND INHIBIT or NOP. 5. Starting at some point during this 100µs period, bring CKE HIGH. Continuing at least through the end of this period, 1 or more COMMAND INHIBIT or NOP commands must be applied. 6. Perform a PRECHARGE ALL command. PDF: 09005aef80872800/Source: 09005aef80863355 Micron Technology, Inc., reserves the right to change products or specifications without notice. 128MbSDRAMx32_2.fm - Rev. J 6/06 EN 10 ©2001 Micron Technology, Inc. All rights reserved. 128Mb: x32 SDRAM Register Definition t 7. Wait at least RP time, during this time NOPs or DESELECT commands must be given. All banks will complete their precharge, thereby placing the device in the all banks idle state. 8. Issue an AUTO REFRESH command. t 9. Wait at least RFC time, during which only NOPs or COMMAND INHIBIT commands are allowed. 10. Issue an AUTO REFRESH command. t 11. Wait at least RFC time, during which only NOPs or COMMAND INHIBIT commands are allowed. 12. The SDRAM is now ready for mode register programming. Because the mode register will power up in an unknown state, it should be loaded with desired bit values prior to applying any operational command. Using the LMR command, program the mode register. The mode register is programmed via the MODE REGISTER SET command with BA1 = 0, BA0 = 0 and retains the stored information until it is programmed again or the device loses power. Not programming the mode register upon initialization will result in default settings which may not be desired. Outputs are guaranteed High-Z after the LMR command is issued. Outputs should be High-Z already before the LMR command is issued. t 13. Wait at least MRD time, during which only NOP or DESELECT commands are allowed. At this point the DRAM is ready for any valid command. Note: If desired, more than two AUTO REFRESH commands can be issued in the sequence. After steps 9 and 10 are complete, repeat them until the desired number of AUTO t REFRESH + RFC loops is achieved. Register Definition Mode Register The mode register is used to define the specific mode of operation of the SDRAM. This definition includes the selection of a burst length (BL), a burst type, a CAS latency (CL), an operating mode and a write burst mode, as shown in Figure 4 on page 12. The mode register is programmed via the LOAD MODE REGISTER command and will retain the stored information until it is programmed again or the device loses power. Mode register bits M0–M2 specify the, M3 specifies the type of burst (sequential or inter- leaved), M4–M6 specify the CL, M7 and M8 specify the operating mode, M9 specifies the write burst mode, and M10, M11, BA0, and BA1 are reserved for future use. The mode register must be loaded when all banks are idle, and the controller must wait the specified time before initiating the subsequent operation. Violating either of these requirements will result in unspecified operation. Burst Length (BL) Read and write accesses to the SDRAM are burst oriented, with BL being programmable, as shown in Figure 4 on page 12. The BL determines the maximum number of column locations that can be accessed for a given READ or WRITE command. Burst lengths of 1, 2, 4, or 8 locations are available for both the sequential and the interleaved burst types, and a full-page burst is available for the sequential type. The full-page burst is used in conjunction with the BURST TERMINATE command to generate arbitrary BLs. PDF: 09005aef80872800/Source: 09005aef80863355 Micron Technology, Inc., reserves the right to change products or specifications without notice. 128MbSDRAMx32_2.fm - Rev. J 6/06 EN 11 ©2001 Micron Technology, Inc. All rights reserved. 128Mb: x32 SDRAM Register Definition Reserved states should not be used, as unknown operation or incompatibility with future versions may result. When a READ or WRITE command is issued, a block of columns equal to BL is effectively selected. All accesses for that burst take place within this block, meaning that the burst will wrap within the block if a boundary is reached. The block is uniquely selected by A1– A7 when BL = 2; by A2–A7 when BL = 4; and by A3–A7 when BL = 8. The remaining (least significant) address bit(s) is (are) used to select the starting location within the block. Full-page bursts wrap within the page if the boundary is reached. Burst Type Accesses within a given burst may be programmed to be either sequential or interleaved; this is referred to as the burst type and is selected via bit M3. The ordering of accesses within a burst is determined by BL, the burst type and the starting column address, as shown in Table 6 on page 13. Figure 4: Mode Register Definition A11 A10 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Bus A9 11 10 9 8 7 65 4 3 2 1 0 Mode Register (Ax) Reserved WB Op Mode CAS Latency BT Burst Length Program Burst Length M11, M10, BA0, BA1 = “0” to ensure compatibility A2 A1 A0 M3 = 0 M3 = 1 with future devices. 0 0 0 1 1 0 0 1 2 2 Write Burst Mode M9 0 1 0 4 4 0 Programmed Burst Length 0 1 1 8 8 1 Single Location Access 1 0 0 Reserved Reserved 1 0 1 Reserved Reserved M8 M7 M6–M0 Operating Mode 1 1 0 Reserved Reserved 0 0 Defined Standard Operation 1 1 1 Full Page Reserved – – – All other states reserved M3 Burst Type 0 Sequential 1 Interleaved CAS Latency M6 M5 M4 0 0 0 Reserved 1 0 0 1 0 1 0 2 3 0 1 1 1 0 0 Reserved 1 0 1 Reserved Reserved 1 1 0 1 1 1 Reserved PDF: 09005aef80872800/Source: 09005aef80863355 Micron Technology, Inc., reserves the right to change products or specifications without notice. 128MbSDRAMx32_2.fm - Rev. J 6/06 EN 12 ©2001 Micron Technology, Inc. All rights reserved. 128Mb: x32 SDRAM Register Definition Table 6: Burst Definition Order of Accesses Within a Burst Burst Starting Column Length Address Type = Sequential Type = Interleaved 2A0 00-1 0-1 11-0 1-0 4A1A0 0 0 0-1-2-3 0-1-2-3 0 1 1-2-3-0 1-0-3-2 1 0 2-3-0-1 2-3-0-1 1 1 3-0-1-2 3-2-1-0 8A2A1A0 0 0 0 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7 0 0 1 1-2-3-4-5-6-7-0 1-0-3-2-5-4-7-6 0 1 0 2-3-4-5-6-7-0-1 2-3-0-1-6-7-4-5 0 1 1 3-4-5-6-7-0-1-2 3-2-1-0-7-6-5-4 1 0 0 4-5-6-7-0-1-2-3 4-5-6-7-0-1-2-3 1 0 1 5-6-7-0-1-2-3-4 5-4-7-6-1-0-3-2 1 1 0 6-7-0-1-2-3-4-5 6-7-4-5-2-3-0-1 1 1 1 7-0-1-2-3-4-5-6 7-6-5-4-3-2-1-0 Full Page n = A0–A7 (Location Cn, Cn + 1, Cn + 2 Not supported (256) 0–256) Cn + 3, Cn + 4... Cn - 1, Cn… Notes: 1. For a BL = 2, A1–A7 select the block-of-two burst; A0 selects the starting column within the block. 2. For a BL = 4, A2–A7 select the block-of-four burst; A0–A1 select the starting column within the block. 3. For a BL = 8, A3–A7 select the block-of-eight burst; A0–A2 select the starting column within the block. 4. For a full-page burst, the full row is selected and A0–A7 select the starting column. 5. Whenever a boundary of the block is reached within a given sequence above, the following access wraps within the block. 6. For a BL = 1, A0–A7 select the unique column to be accessed, and mode register bit M3 is ignored. PDF: 09005aef80872800/Source: 09005aef80863355 Micron Technology, Inc., reserves the right to change products or specifications without notice. 128MbSDRAMx32_2.fm - Rev. J 6/06 EN 13 ©2001 Micron Technology, Inc. All rights reserved. 128Mb: x32 SDRAM Register Definition CAS Latency (CL) The CL is the delay, in clock cycles, between the registration of a READ command and the availability of the first piece of output data. The latency can be set to one, two or three clocks. If a READ command is registered at clock edge n, and the latency is m clocks, the data will be available by clock edge n + m. The DQs will start driving as a result of the clock edge one cycle earlier (n + m - 1), and provided that the relevant access times are met, the data will be valid by clock edge n + m. For example, assuming that the clock cycle time is such that all relevant access times are met, if a read command is registered at T0 and the latency is programmed to two clocks, the DQs will start driving after T1 and the data will be valid by T2, as shown in Figure 5. Table 7 below indicates the operating frequencies at which each CL setting can be used. Figure 5: CAS Latency T0 T1 T2 CLK COMMAND READ NOP t t LZ OH DOUT DQ t AC CL = 1 T0 T1 T2 T3 CLK COMMAND READ NOP NOP t t LZ OH DOUT DQ t AC CL = 2 T0 T1 T2 T3 T4 CLK COMMAND READ NOP NOP NOP t t LZ OH DQ DOUT t AC CL = 3 DON’T CARE UNDEFINED Reserved states should not be used as unknown operation or incompatibility with future versions may result. PDF: 09005aef80872800/Source: 09005aef80863355 Micron Technology, Inc., reserves the right to change products or specifications without notice. 128MbSDRAMx32_2.fm - Rev. J 6/06 EN 14 ©2001 Micron Technology, Inc. All rights reserved. 128Mb: x32 SDRAM Register Definition Operating Mode The normal operating mode is selected by setting M7 and M8 to zero; the other combi- nations of values for M7 and M8 are reserved for future use and/or test modes. The programmed BL applies to both read and write bursts. Test modes and reserved states should not be used because unknown operation or incompatibility with future versions may result. Write Burst Mode When M9 = 0, BL programmed via M0–M2 applies to both read and write bursts; when M9 = 1, the programmed BL applies to read bursts, but write accesses are single-location (nonburst) accesses. Table 7: CAS Latency Allowable Operating Frequency (MHz) Speed CL = 1 CL = 2 CL = 3 -6 ≤ 50 ≤ 100 ≤ 166 -7 ≤ 50 ≤ 100 ≤ 143 PDF: 09005aef80872800/Source: 09005aef80863355 Micron Technology, Inc., reserves the right to change products or specifications without notice. 128MbSDRAMx32_2.fm - Rev. J 6/06 EN 15 ©2001 Micron Technology, Inc. All rights reserved. 128Mb: x32 SDRAM Register Definition Commands Table 8 provides a quick reference of available commands. This is followed by a written description of each command. Three additional Truth Tables appear following the Operation section; these tables provide current state/next state information. Table 8: Truth Table–Commands and DQM Operation (Note: 1) NAME (FUNCTION) CS# RAS# CAS# WE# DQM ADDR DQs NOTES H XXXX X X COMMAND INHIBIT (NOP) NO OPERATION (NOP) LHHH X X X ACTIVE (Select bank and activate row) L L H H X Bank/Row X 3 READ (Select bank and column, and start READ burst) L H L H L/H8 Bank/Col X 4 L H L L L/H8 Bank/Col Valid 4 WRITE (Select bank and column, and start WRITE burst) LHH L X X Active BURST TERMINATE PRECHARGE (Deactivate row in bank or banks) L L H L X Code X 5 AUTO REFRESH or SELF REFRESH LL LH X X X 6, 7 (Enter self refresh mode) LOAD MODE REGISTER L L L L X Op-Code X 2 Write Enable/Output Enable – –––L – Active 8 Write Inhibit/Output High-Z – ––– H – High-Z 8 Notes: 1. CKE is HIGH for all commands shown except SELF REFRESH. 2. A0–A11 define the op-code written to the mode register. 3. A0–A11 provide row address, BA0 and BA1 determine which bank is made active. 4. A0–A7 provide column address; A10 HIGH enables the auto precharge feature (nonpersis- tent), while A10 LOW disables the auto precharge feature; BA0 and BA1 determine which bank is being read from or written to. 5. A10 LOW: BA0 and BA1 determine the bank being precharged. A10 HIGH: All banks pre- charged and BA0 and BA1 are “Don’t Care.” 6. This command is AUTO REFRESH if CKE is HIGH; SELF REFRESH if CKE is LOW. 7. Internal refresh counter controls row addressing; all inputs and I/Os are “Don’t Care” except for CKE. 8. Activates or deactivates the DQs during WRITEs (zero-clock delay) and READs (two-clock delay). DQM0 controls DQ0–DQ7; DQM1 controls DQ8–DQ15; DQM2 controls DQ16–DQ23; and DQM3 controls DQ24–DQ31. COMMAND INHIBIT The COMMAND INHIBIT function prevents new commands from being executed by the SDRAM, regardless of whether the CLK signal is enabled. The SDRAM is effectively dese- lected. Operations already in progress are not affected. NO OPERATION (NOP) The NO OPERATION (NOP) command is used to perform a NOP to an SDRAM which is selected (CS# is LOW). This prevents unwanted commands from being registered during idle or wait states. Operations already in progress are not affected. PDF: 09005aef80872800/Source: 09005aef80863355 Micron Technology, Inc., reserves the right to change products or specifications without notice. 128MbSDRAMx32_2.fm - Rev. J 6/06 EN 16 ©2001 Micron Technology, Inc. All rights reserved. 128Mb: x32 SDRAM Register Definition LOAD MODE REGISTER The mode register is loaded via inputs A0–A11. See the Mode Register heading in the “Register Definition” section. The LOAD MODE REGISTER command can only be issued when all banks are idle, and a subsequent executable command cannot be issued until t MRD is met. ACTIVE The ACTIVE command is used to open (or activate) a row in a particular bank for a subsequent access. The value on the BA0 and BA1 inputs selects the bank, and the address provided on inputs A0–A11 selects the row. This row remains active (or open) for accesses until a precharge command is issued to that bank. A precharge command must be issued before opening a different row in the same bank. READ The READ command is used to initiate a burst read access to an active row. The value on the BA0 and BA1 (B1) inputs selects the bank, and the address provided on inputs A0–A7 selects the starting column location. The value on input A10 determines whether or not auto precharge is used. If auto precharge is selected, the row being accessed will be precharged at the end of the read burst; if auto precharge is not selected, the row will remain open for subsequent accesses. Read data appears on the DQs subject to the logic level on the DQM inputs two clocks earlier. If a given DQMx signal was registered HIGH, the corresponding DQs will be High-Z two clocks later; if the DQMx signal was registered LOW, the corresponding DQs will provide valid data. DQM0 corresponds to DQ0–DQ7, DQM1 corresponds to DQ8–DQ15, DQM2 corresponds to DQ16–DQ23 and DQM3 corresponds to DQ24–DQ31. WRITE The WRITE command is used to initiate a burst write access to an active row. The value on the BA0 and BA1 inputs selects the bank, and the address provided on inputs A0–A7 selects the starting column location. The value on input A10 determines whether or not auto precharge is used. If auto precharge is selected, the row being accessed will be precharged at the end of the write burst; if auto precharge is not selected, the row will remain open for subsequent accesses. Input data appearing on the DQs is written to the memory array subject to the DQM input logic level appearing coincident with the data. If a given DQM signal is registered LOW, the corresponding data will be written to memory; if the DQM signal is registered HIGH, the corresponding data inputs will be ignored, and a write will not be executed to that byte/column location. PRECHARGE The PRECHARGE command is used to deactivate the open row in a particular bank or the open row in all banks. The bank(s) will be available for a subsequent row access a t specified time ( RP) after the precharge command is issued. Input A10 determines whether one or all banks are to be precharged, and in the case where only one bank is to be precharged, inputs BA0 and BA1 select the bank. Otherwise BA0 and BA1 are treated as “Don’t Care.” Once a bank has been precharged, it is in the idle state and must be activated prior to any READ or WRITE commands being issued to that bank. Auto Precharge Auto precharge is a feature which performs the same individual-bank precharge func- tion described above, without requiring an explicit command. This is accomplished by using A10 to enable auto precharge in conjunction with a specific READ or WRITE PDF: 09005aef80872800/Source: 09005aef80863355 Micron Technology, Inc., reserves the right to change products or specifications without notice. 128MbSDRAMx32_2.fm - Rev. J 6/06 EN 17 ©2001 Micron Technology, Inc. All rights reserved. 128Mb: x32 SDRAM Register Definition command. A precharge of the bank/row that is addressed with the READ or WRITE command is automatically performed upon completion of the READ or WRITE burst, except in the full-page burst mode, where auto precharge does not apply. Auto precharge is nonpersistent in that it is either enabled or disabled for each individual Read or Write command. auto precharge ensures that the precharge is initiated at the earliest valid stage within a burst. The user must not issue another command to the same bank until the precharge t time ( RP) is completed. This is determined as if an explicit PRECHARGE command was issued at the earliest possible time, as described for each burst type in the “Operation” section of this data sheet. BURST TERMINATE The BURST TERMINATE command is used to truncate either fixed-length or full-page bursts. The most recently registered READ or WRITE command prior to the BURST TERMINATE command will be truncated, as shown in the “Operation” section. The BURST TERMINATE command does not precharge the row; the row will remain open until a PRECHARGE command is issued. AUTO REFRESH AUTO REFRESH is used during normal operation of the SDRAM and is analogous to CAS#-BEFORE-RAS# (CBR) refresh in conventional DRAMs. This command is nonper- sistent, so it must be issued each time a refresh is required. The addressing is generated by the internal refresh controller. This makes the address bits “Don’t Care” during an AUTO REFRESH command. The 128Mb SDRAM requires t 4,096 AUTO REFRESH cycles every 64ms ( REF), regardless of width option. Providing a distributed AUTO REFRESH command every 15.625µs will meet the refresh requirement and ensure that each row is refreshed. Alternatively, 4,096 AUTO REFRESH commands t can be issued in a burst at the minimum cycle rate ( RFC), once every 64ms. SELF REFRESH The SELF REFRESH command can be used to retain data in the SDRAM, even if the rest of the system is powered down. When in the self refresh mode, the SDRAM retains data without external clocking. The SELF REFRESH command is initiated like an AUTO REFRESH command except CKE is disabled (LOW). Once the SELF REFRESH command is registered, all the inputs to the SDRAM become “Don’t Care” with the exception of CKE, which must remain LOW. Once self refresh mode is engaged, the SDRAM provides its own internal clocking, causing it to perform its own auto refresh cycles. The SDRAM must remain in self refresh t mode for a minimum period equal to RAS and may remain in self refresh mode for an indefinite period beyond that. The procedure for exiting self refresh requires a sequence of commands. First, CLK must be stable (stable clock is defined as a signal cycling within timing constraints specified for the clock pin) prior to CKE going back HIGH. Once CKE is HIGH, the SDRAM must t have NOP commands issued (a minimum of two clocks) for XSR because time is required for the completion of any internal refresh in progress. Upon exiting SELF REFRESH mode, AUTO REFRESH commands must be issued every 15.625µs or less as both SELF REFRESH and AUTO REFRESH utilize the row refresh counter. PDF: 09005aef80872800/Source: 09005aef80863355 Micron Technology, Inc., reserves the right to change products or specifications without notice. 128MbSDRAMx32_2.fm - Rev. J 6/06 EN 18 ©2001 Micron Technology, Inc. All rights reserved. 128Mb: x32 SDRAM Register Definition Operation BANK/ROW ACTIVATION Before any READ or WRITE commands can be issued to a bank within the SDRAM, a row in that bank must be “opened.” This is accomplished via the ACTIVE command, which selects both the bank and the row to be activated. See Figure 6. After opening a row (issuing an ACTIVE command), a READ or WRITE command may be t t issued to that row, subject to the RCD specification. RCD (MIN) should be divided by the clock period and rounded up to the next whole number to determine the earliest clock edge after the ACTIVE command on which a READ or WRITE command can be t issued. For example, a RCD specification of 20ns with a 125 MHz clock (8ns period) results in 2.5 clocks, rounded to 3. This is reflected in Figure 7, which covers any case t t where 2 < RCD (MIN)/ CK - 3. (The same procedure is used to convert other specifica- tion limits from time units to clock cycles.) A subsequent ACTIVE command to a different row in the same bank can only be issued after the previous active row has been “closed” (precharged). The minimum time t interval between successive ACTIVE commands to the same bank is defined by RC. A subsequent ACTIVE command to another bank can be issued while the first bank is being accessed, which results in a reduction of total row-access overhead. The minimum time interval between successive ACTIVE commands to different banks is t defined by RRD. Figure 6: Activating a Specific Row in a Specific Bank CLK CKE HIGH CS# RAS# CAS# WE# ROW A0–A11 ADDRESS BANK BA0, BA1 ADDRESS DON´T CARE PDF: 09005aef80872800/Source: 09005aef80863355 Micron Technology, Inc., reserves the right to change products or specifications without notice. 128MbSDRAMx32_2.fm - Rev. J 6/06 EN 19 ©2001 Micron Technology, Inc. All rights reserved. 128Mb: x32 SDRAM Register Definition t t t Figure 7: Example: Meeting RCD (MIN) When 2 < RCD (MIN)/ CK< 3 T0 T1 T2 T3 CLK t t t CK CK CK READ or COMMAND ACTIVE NOP NOP WRITE t RCD (MIN) t t RCD (MIN) +0.5 CK DON’T CARE t t Notes: 1. RCD (MIN) = 20ns, CK = 8ns t t RCD (MIN) × CK where x = number of clocks for equation to be true. READs READ bursts are initiated with a READ command, as shown in Figure 8. The starting column and bank addresses are provided with the READ command, and auto precharge is either enabled or disabled for that burst access. If auto precharge is enabled, the row being accessed is precharged at the completion of the burst. For the generic READ commands used in the following illustrations, auto precharge is disabled. During READ bursts, the valid data-out element from the starting column address will be available following the CL after the READ command. Each subsequent data-out element will be valid by the next positive clock edge. Figure 9 shows general timing for each possible CL setting. Figure 8: READ Command CLK CKE HIGH CS# RAS# CAS# WE# COLUMN A0–A7 ADDRESS A8, A9, A11 ENABLE AUTO PRECHARGE A10 DISABLE AUTO PRECHARGE BANK BA0,1 ADDRESS DON’T CARE PDF: 09005aef80872800/Source: 09005aef80863355 Micron Technology, Inc., reserves the right to change products or specifications without notice. 128MbSDRAMx32_2.fm - Rev. J 6/06 EN 20 ©2001 Micron Technology, Inc. All rights reserved. 128Mb: x32 SDRAM Register Definition Upon completion of a burst, assuming no other commands have been initiated, the DQs will go High-Z. A full-page burst will continue until terminated. (At the end of the page, it will wrap to column 0 and continue.) Data from any READ burst may be truncated with a subsequent READ command, and data from a fixed-length READ burst may be immediately followed by data from a READ command. In either case, a continuous flow of data can be maintained. The first data element from the new burst follows either the last element of a completed burst or the last desired data element of a longer burst that is being truncated. The new READ command should be issued x cycles before the clock edge at which the last desired data element is valid, where x = CL - 1. This is shown in Figure 10 on page 22 for CAS latencies of one, two and three; data element n + 3 is either the last of a burst of four or the last desired of a longer burst. This 128Mb SDRAM uses a pipelined architecture and there- fore does not require the 2n rule associated with a prefetch architecture. Figure 9: CAS Latency T0 T1 T2 CLK COMMAND READ NOP t t LZ OH DOUT DQ t AC CL = 1 T0 T1 T2 T3 CLK COMMAND READ NOP NOP t t LZ OH DOUT DQ t AC CL = 2 T0 T1 T2 T3 T4 CLK COMMAND READ NOP NOP NOP t t LZ OH DQ DOUT t AC CL = 3 DON’T CARE UNDEFINED A READ command can be initiated on any clock cycle following a previous READ command. Full-speed random read accesses can be performed to the same bank, as shown in Figure 11 on page 23, or each subsequent READ may be performed to a different bank. PDF: 09005aef80872800/Source: 09005aef80863355 Micron Technology, Inc., reserves the right to change products or specifications without notice. 128MbSDRAMx32_2.fm - Rev. J 6/06 EN 21 ©2001 Micron Technology, Inc. All rights reserved. 128Mb: x32 SDRAM Register Definition Figure 10: Consecutive READ Bursts T0 T1 T2 T3 T4 T5 CLK READ NOP NOP NOP READ NOP COMMAND X = 0 cycles BANK, BANK, ADDRESS COL n COL b DOUT DOUT DOUT DOUT DOUT DQ n n + 1 n + 2 n + 3 b CL = 1 T0 T1 T2 T3 T4 T5 T6 CLK READ NOP NOP NOP READ NOP NOP COMMAND X = 1 cycle BANK, BANK, ADDRESS COL n COL b DOUT DOUT DOUT DOUT DOUT DQ n n + 1 n + 2 n + 3 b CL = 2 T0 T1 T2 T3 T4 T5 T6 T7 CLK READ NOP NOP NOP READ NOP NOP NOP COMMAND X = 2 cycles BANK, BANK, ADDRESS COL n COL b DOUT DOUT DOUT DOUT DOUT DQ n n + 1 n + 2 n + 3 b CL = 3 DON’T CARE Notes: 1. Each READ command may be to either bank. DQM is LOW. PDF: 09005aef80872800/Source: 09005aef80863355 Micron Technology, Inc., reserves the right to change products or specifications without notice. 128MbSDRAMx32_2.fm - Rev. J 6/06 EN 22 ©2001 Micron Technology, Inc. All rights reserved. 128Mb: x32 SDRAM Register Definition Figure 11: Random READ Accesses T0 T1 T2 T3 T4 CLK READ READ READ READ NOP COMMAND BANK, BANK, BANK, BANK, ADDRESS COL n COL a COL x COL m DOUT DOUT DOUT DOUT DQ n a x m CL = 1 T0 T1 T2 T3 T4 T5 CLK READ READ READ READ NOP NOP COMMAND BANK, BANK, BANK, BANK, ADDRESS COL n COL a COL x COL m DOUT DOUT DOUT DOUT DQ n a x m CL = 2 T0 T1 T2 T3 T4 T5 T6 CLK COMMAND READ READ READ READ NOP NOP NOP BANK, BANK, BANK, BANK, ADDRESS COL n COL a COL x COL m DOUT DOUT DOUT DOUT DQ n a x m CL = 3 DON’T CARE Notes: 1. Each READ command may be to either bank. DQM is LOW. Data from any READ burst may be truncated with a subsequent WRITE command, and data from a fixed-length READ burst may be immediately followed by data from a WRITE command (subject to bus turnaround limitations). The WRITE burst may be initiated on the clock edge immediately following the last (or last desired) data element from the READ burst, provided that I/O contention can be avoided. In a given system design, there may be a possibility that the device driving the input data will go Low-Z before the SDRAM DQs go High-Z. In this case, at least a single-cycle delay should occur between the last read data and the WRITE command. PDF: 09005aef80872800/Source: 09005aef80863355 Micron Technology, Inc., reserves the right to change products or specifications without notice. 128MbSDRAMx32_2.fm - Rev. J 6/06 EN 23 ©2001 Micron Technology, Inc. All rights reserved. 128Mb: x32 SDRAM Register Definition Figure 12: READ-to-WRITE T0 T1 T2 T3 T4 CLK DQM READ NOP NOP NOP WRITE COMMAND BANK, BANK, ADDRESS COL n COL b t CK t HZ DOUT n DIN b DQ t DS DON’T CARE Notes: 1. CL = 3is used for illustration. The READ command may be to any bank, and the WRITE com- mand may be to any bank. If a burst of one is used, then DQM is not required. The DQM input is used to avoid I/O contention, as shown in Figures 12 and 13. The DQM signal must be asserted (HIGH) at least two clocks prior to the WRITE command (DQM latency is two clocks for output buffers) to suppress data-out from the READ. Once the WRITE command is registered, the DQs will go High-Z (or remain High-Z), regardless of the state of the DQM signal; provided the DQM was active on the clock just prior to the WRITE command that truncated the READ command. If not, the second WRITE will be an invalid WRITE. For example, if DQM was low during T4 in Figure 13, then the WRITEs at T5 and T7 would be valid, while the WRITE at T6 would be invalid. The DQM signal must be de-asserted prior to the WRITE command (DQM latency is zero clocks for input buffers) to ensure that the written data is not masked. Figure 12 shows the case where the clock frequency allows for bus contention to be avoided without adding a NOP cycle, and Figure 13 shows the case where the additional nop is needed. Figure 13: READ-to-WRITE with Extra Clock Cycle T0 T1 T2 T3 T4 T5 CLK DQM READ NOP NOP NOP NOP WRITE COMMAND BANK, BANK, ADDRESS COL b COL n t HZ DOUT n DIN b DQ t DS DON’T CARE Notes: 1. CL = 3 is used for illustration. The READ command may be to any bank, and the WRITE com- mand may be to any bank. A fixed-length READ burst may be followed by, or truncated with, a PRECHARGE command to the same bank (provided that auto precharge was not activated), and a full- page burst may be truncated with a PRECHARGE command to the same bank. The PRECHARGE command should be issued x cycles before the clock edge at which the last PDF: 09005aef80872800/Source: 09005aef80863355 Micron Technology, Inc., reserves the right to change products or specifications without notice. 128MbSDRAMx32_2.fm - Rev. J 6/06 EN 24 ©2001 Micron Technology, Inc. All rights reserved. 128Mb: x32 SDRAM Register Definition desired data element is valid, where x = CL - 1. This is shown in Figure 14 for each possible CL; data element n + 3 is either the last of a burst of four or the last desired of a longer burst. Following the PRECHARGE command, a subsequent command to the t same bank cannot be issued until RP is met. Note that part of the row precharge time is hidden during the access of the last data element(s). Figure 14: READ-to-PRECHARGE T0 T1 T2 T3 T4 T5 T6 T7 CLK t RP READ NOP NOP NOP PRECHARGE NOP NOP ACTIVE COMMAND X = 0 cycles BANK BANK a, BANK a, ADDRESS COL n (a or all) ROW DOUT DOUT DOUT DOUT DQ n n + 1 n + 2 n + 3 CL = 1 T0 T1 T2 T3 T4 T5 T6 T7 CLK t RP COMMAND READ NOP NOP NOP PRECHARGE NOP NOP ACTIVE X = 1 cycle BANK a, BANK BANK a, ADDRESS COL n (a or all) ROW DOUT DOUT DOUT DOUT DQ n n + 1 n + 2 n + 3 CL = 2 T0 T1 T2 T3 T4 T5 T6 T7 CLK t RP READ NOP NOP NOP PRECHARGE NOP NOP ACTIVE COMMAND X = 2 cycles BANK a, BANK BANK a, ADDRESS COL n (a or all) ROW DOUT DOUT DOUT DOUT DQ n n + 1 n + 2 n + 3 CL = 3 DON’T CARE Notes: 1. DQM is LOW. In the case of a fixed-length burst being executed to completion, a PRECHARGE command issued at the optimum time (as described above) provides the same opera- tion that would result from the same fixed-length burst with auto precharge. The disad- vantage of the PRECHARGE command is that it requires that the command and address buses be available at the appropriate time to issue the command; the advantage of the PRECHARGE command is that it can be used to truncate fixed-length or full-page bursts. PDF: 09005aef80872800/Source: 09005aef80863355 Micron Technology, Inc., reserves the right to change products or specifications without notice. 128MbSDRAMx32_2.fm - Rev. J 6/06 EN 25 ©2001 Micron Technology, Inc. All rights reserved. 128Mb: x32 SDRAM Register Definition Full-page READ bursts can be truncated with the BURST TERMINATE command, and fixed-length READ bursts may be truncated with a BURST TERMINATE command, provided that auto precharge was not activated. The BURST TERMINATE command should be issued x cycles before the clock edge at which the last desired data element is valid, where x = CL - 1. This is shown in Figure 15 for each possible CL; data element n + 3 is the last desired data element of a longer burst. Figure 15: Terminating a READ Burst T0 T1 T2 T3 T4 T5 T6 CLK BURST READ NOP NOP NOP NOP NOP COMMAND TERMINATE X = 0 cycles BANK, ADDRESS COL n DOUT DOUT DOUT DOUT DQ n n + 1 n + 2 n + 3 CL = 1 T0 T1 T2 T3 T4 T5 T6 CLK BURST READ NOP NOP NOP NOP NOP COMMAND TERMINATE X = 1 cycle BANK, ADDRESS COL n DOUT DOUT DOUT DOUT DQ n n + 1 n + 2 n + 3 CL = 2 T0 T1 T2 T3 T4 T5 T6 T7 CLK BURST READ NOP NOP NOP NOP NOP NOP COMMAND TERMINATE X = 2 cycles BANK, ADDRESS COL n DOUT DOUT DOUT DOUT DQ n n + 1 n + 2 n + 3 CL = 3 DON’T CARE Notes: 1. DQM is LOW. PDF: 09005aef80872800/Source: 09005aef80863355 Micron Technology, Inc., reserves the right to change products or specifications without notice. 128MbSDRAMx32_2.fm - Rev. J 6/06 EN 26 ©2001 Micron Technology, Inc. All rights reserved. 128Mb: x32 SDRAM Register Definition WRITEs WRITE bursts are initiated with a WRITE command, as shown in Figure 16. The starting column and bank addresses are provided with the WRITE command, and auto precharge is either enabled or disabled for that access. If auto precharge is enabled, the row being accessed is precharged at the completion of the burst. For the generic WRITE commands used in the following illustrations, auto precharge is disabled. During WRITE bursts, the first valid data-in element will be registered coincident with the WRITE command. Subsequent data elements will be registered on each successive positive clock edge. Upon completion of a fixed-length burst, assuming no other commands have been initiated, the DQs will remain High-Z and any additional input data will be ignored (see Figure 17 on page 28). A full-page burst will continue until terminated. (At the end of the page, it will wrap to column 0 and continue.) Figure 16: WRITE Command CLK CKE HIGH CS# RAS# CAS# WE# COLUMN A0–A7 ADDRESS A8, A9, A11 ENABLE AUTO PRECHARGE A10 DISABLE AUTO PRECHARGE BANK BA0,1 ADDRESS VALID ADDRESS DON’T CARE Data for any WRITE burst may be truncated with a subsequent WRITE command, and data for a fixed-length WRITE burst may be immediately followed by data for a WRITE command. The new WRITE command can be issued on any clock following the previous WRITE command, and the data provided coincident with the new command applies to the new command. An example is shown in Figure 18 on page 28. Data n + 1 is either the last of a burst of two or the last desired of a longer burst. This 128Mb SDRAM uses a pipelined architecture and therefore does not require the 2n rule associated with a prefetch architecture. A WRITE command can be initiated on any clock cycle following a previous WRITE command. Full-speed random write accesses within a page can be performed to the same bank, as shown in Figure 19 on page 28, or each subsequent WRITE may be performed to a different bank. PDF: 09005aef80872800/Source: 09005aef80863355 Micron Technology, Inc., reserves the right to change products or specifications without notice. 128MbSDRAMx32_2.fm - Rev. J 6/06 EN 27 ©2001 Micron Technology, Inc. All rights reserved. 128Mb: x32 SDRAM Register Definition Figure 17: WRITE Burst T0 T1 T2 T3 CLK WRITE NOP NOP NOP COMMAND BANK, ADDRESS COL n DIN DIN DQ n n + 1 DON’T CARE Notes: 1. BL = 2. DQM is LOW. Figure 18: WRITE-to0WRITE T0 T1 T2 CLK WRITE NOP WRITE COMMAND BANK, BANK, ADDRESS COL n COL b DIN DIN DIN DQ n n + 1 b DON’T CARE Notes: 1. DQM is LOW. Each WRITE command may be to any bank. Figure 19: Random WRITE Cycles T0 T1 T2 T3 CLK WRITE WRITE WRITE WRITE COMMAND BANK, BANK, BANK, BANK, ADDRESS COL n COL a COL x COL m DIN DIN DIN DIN DQ m n a x DON’T CARE Notes: 1. Each WRITE command may be to any bank. DQM is LOW. PDF: 09005aef80872800/Source: 09005aef80863355 Micron Technology, Inc., reserves the right to change products or specifications without notice. 128MbSDRAMx32_2.fm - Rev. J 6/06 EN 28 ©2001 Micron Technology, Inc. All rights reserved. 128Mb: x32 SDRAM Register Definition Figure 20: WRITE-to-READ T0 T1 T2 T3 T4 T5 CLK WRITE NOP READ NOP NOP NOP COMMAND BANK, BANK, ADDRESS COL n COL b DIN DIN DOUT DOUT DQ n n + 1 b b + 1 DON’T CARE Notes: 1. The WRITE command may be to any bank, and the READ command may be to any bank. DQM is LOW. CL = 2 for illustration. Data for any WRITE burst may be truncated with a subsequent READ command, and data for a fixed-length WRITE burst may be immediately followed by a READ command. Once the READ command is registered, the data inputs will be ignored, and writes will not be executed. An example is shown in Figure 20. Data n + 1 is either the last of a burst of two or the last desired of a longer burst. Data for a fixed-length WRITE burst may be followed by, or truncated with, a PRECHARGE command to the same bank (provided that auto precharge was not acti- vated), and a full-page WRITE burst may be truncated with a PRECHARGE command to t the same bank. The PRECHARGE command should be issued WR after the clock edge at which the last desired input data element is registered. The “two-clock” write-back requires at least one clock plus time, regardless of frequency, in auto precharge mode. In addition, when truncating a WRITE burst, the DQM signal must be used to mask input data for the clock edge prior to, and the clock edge coincident with, the PRECHARGE command. An example is shown in Figure 21. Data n + 1 is either the last of a burst of two or the last desired of a longer burst. Following the PRECHARGE command, a subse- t quent command to the same bank cannot be issued until RP is met. The precharge will actually begin coincident with the clock-edge (T2 in Figure 21 on page 30) on a “one- t t clock” WR and sometime between the first and second clock on a “two-clock” WR (between T2 and T3 in Figure 21.) In the case of a fixed-length burst being executed to completion, a PRECHARGE command issued at the optimum time (as described above) provides the same opera- tion that would result from the same fixed-length burst with auto precharge. The disad- vantage of the PRECHARGE command is that it requires that the command and address buses be available at the appropriate time to issue the command; the advantage of the PRECHARGE command is that it can be used to truncate fixed-length or full-page bursts. PDF: 09005aef80872800/Source: 09005aef80863355 Micron Technology, Inc., reserves the right to change products or specifications without notice. 128MbSDRAMx32_2.fm - Rev. J 6/06 EN 29 ©2001 Micron Technology, Inc. All rights reserved. 128Mb: x32 SDRAM Register Definition Figure 21: WRITE-to-PRECHARGE T0 T1 T2 T3 T4 T5 T6 CLK t t t WR = 1 CLK ( CK > WR) DQM t RP NOP NOP NOP COMMAND WRITE NOP PRECHARGE ACTIVE BANK a, BANK BANK a, ADDRESS COL n (a or all) ROW t WR DIN DIN DQ n n + 1 t t t WR = 2 CLK (when WR > CK) DQM t RP NOP NOP WRITE NOP NOP PRECHARGE ACTIVE COMMAND BANK a, BANK BANK a, ADDRESS (a or all) COL n ROW t WR DIN DIN DQ n n + 1 DON’T CARE Notes: 1. DQM could remain LOW in this example if the WRITE burst is a fixed length of two. Fixed-length or full-page WRITE bursts can be truncated with the BURST TERMINATE command. When truncating a WRITE burst, the input data applied coincident with the BURST TERMINATE command will be ignored. The last data written (provided that DQM is LOW at that time) will be the input data applied one clock previous to the BURST TERMINATE command. This is shown in Figure 22, where data n is the last desired data element of a longer burst. Figure 22: Terminating a WRITE Burst T0 T1 T2 CLK BURST NEXT WRITE COMMAND TERMINATE COMMAND BANK, (ADDRESS) ADDRESS COL n DIN (DATA) DQ n DON’T CARE Notes: 1. DQMs are LOW. PDF: 09005aef80872800/Source: 09005aef80863355 Micron Technology, Inc., reserves the right to change products or specifications without notice. 128MbSDRAMx32_2.fm - Rev. J 6/06 EN 30 ©2001 Micron Technology, Inc. All rights reserved. 128Mb: x32 SDRAM Register Definition Figure 23: PRECHARGE Command CLK CKE HIGH CS# RAS# CAS# WE# A0-A9, A11 All Banks A10 Bank Selected BANK BA0,1 ADDRESS VALID ADDRESS DON’T CARE PRECHARGE The PRECHARGE command (Figure 23) is used to deactivate the open row in a partic- ular bank or the open row in all banks. The bank(s) will be available for a subsequent t row access some specified time ( RP) after the precharge command is issued. Input A10 determines whether one or all banks are to be precharged, and in the case where only one bank is to be precharged, inputs BA0 and BA1 select the bank. When all banks are to be precharged, inputs BA0 and BA1 are treated as “Don’t Care.” Once a bank has been precharged, it is in the idle state and must be activated prior to any READ or WRITE commands being issued to that bank. Power-Down Power-down occurs if CKE is registered low coincident with a NOP or COMMAND INHIBIT when no accesses are in progress (see Figure 24 on page 32). If power-down occurs when all banks are idle, this mode is referred to as precharge power-down; if power-down occurs when there is a row active in either bank, this mode is referred to as active power-down. Entering power-down deactivates the input and output buffers, excluding CKE, for maximum power savings while in standby. The device may not remain in the power-down state longer than the refresh period (64ms) since no refresh operations are performed in this mode. The power-down state is exited by registering a NOP or COMMAND INHIBIT and CKE t HIGH at the desired clock edge (meeting CKS). PDF: 09005aef80872800/Source: 09005aef80863355 Micron Technology, Inc., reserves the right to change products or specifications without notice. 128MbSDRAMx32_2.fm - Rev. J 6/06 EN 31 ©2001 Micron Technology, Inc. All rights reserved. 128Mb: x32 SDRAM Register Definition Figure 24: Power-Down ( ( ) ) CLK ( ( ) ) > t t CKS CKS CKE ( ( ) ) ( ( ) ) COMMAND NOP NOP ACTIVE ( ( ) ) t All banks idle RCD Input buffers gated off t RAS t RC Enter power-down mode. Exit power-down mode. DON’T CARE Clock Suspend The clock suspend mode occurs when a column access/burst is in progress and CKE is registered low. In the clock suspend mode, the internal clock is deactivated, “freezing” the synchronous logic. For each positive clock edge on which CKE is sampled LOW, the next internal positive clock edge is suspended. Any command or data present on the input pins at the time of a suspended internal clock edge is ignored; any data present on the DQ pins remains driven; and burst counters are not incremented, as long as the clock is suspended. (See examples in Figures 22 and 23.) Clock suspend mode is exited by registering CKE HIGH; the internal clock and related operation will resume on the subsequent positive clock edge. Figure 25: CLOCK SUSPEND During WRITE Burst T0 T1 T2 T3 T4 T5 CLK CKE INTERNAL CLOCK COMMAND NOP WRITE NOP NOP BANK, ADDRESS COL n DIN DIN DIN DIN n n + 1 n + 2 DON’T CARE Notes: 1. For this example, BL = 4 or greater, and DM is LOW. PDF: 09005aef80872800/Source: 09005aef80863355 Micron Technology, Inc., reserves the right to change products or specifications without notice. 128MbSDRAMx32_2.fm - Rev. J 6/06 EN 32 ©2001 Micron Technology, Inc. All rights reserved. 128Mb: x32 SDRAM Register Definition Figure 26: CLOCK SUSPEND During READ Burst T0 T1 T2 T3 T4 T5 T6 CLK CKE INTERNAL CLOCK READ NOP NOP NOP NOP NOP COMMAND BANK, ADDRESS COL n DOUT DOUT DOUT DOUT DQ n n + 1 n + 2 n + 3 DON’T CARE Notes: 1. For this example, CL = 2, BL = 4 or greater, and DQM is LOW. Burst READ/Single WRITE The burst read/single write mode is entered by programming the write burst mode bit (M9) in the mode register to a logic 1. In this mode, all WRITE commands result in the access of a single column location (burst of one), regardless of the programmed BL. READ commands access columns according to the programmed BL and sequence, just as in the normal mode of operation (M9 = 0). Concurrent Auto Precharge An access command to (READ or WRITE) another bank while an access command with auto precharge enabled is executing is not allowed by SDRAMs, unless the SDRAM supports concurrent auto precharge. Micron SDRAMs support concurrent auto precharge. Four cases where concurrent auto precharge occurs are defined below. READ with Auto Precharge 1. Interrupted by a READ (with or without auto precharge): A READ to bank m will inter- rupt a READ on bank n, CL later. The precharge to bank n will begin when the READ to bank m is registered (see Figure 27 on page 34). 2. Interrupted by a WRITE (with or without auto precharge): A WRITE to bank m will interrupt a READ on bank n when registered. DQM should be used two clocks prior to the WRITE command to prevent bus contention. The precharge to bank n will begin when the WRITE to bank m is registered (see Figure 28 on page 34). PDF: 09005aef80872800/Source: 09005aef80863355 Micron Technology, Inc., reserves the right to change products or specifications without notice. 128MbSDRAMx32_2.fm - Rev. J 6/06 EN 33 ©2001 Micron Technology, Inc. All rights reserved. 128Mb: x32 SDRAM Register Definition Figure 27: READ With Auto Precharge Interrupted by a READ T0 T1 T2 T3 T4 T5 T6 T7 CLK READ - AP READ - AP NOP NOP NOP NOP NOP NOP COMMAND BANK n BANK m Page Active READ with Burst of 4 Interrupt Burst, Precharge Idle BANK n t t RP - BANK n RP - BANK m Internal States Page Active READ with Burst of 4 Precharge BANK m BANK n, BANK m, ADDRESS COL a COL d DOUT DOUT DOUT DOUT DQ a a + 1 d d + 1 CL = 3 (BANK n) CL = 3 (BANK m) DON’T CARE Notes: 1. DQM is LOW. Figure 28: READ With Auto Precharge Interrupted by a WRITE T0 T1 T2 T3 T4 T5 T6 T7 CLK READ - AP WRITE - AP NOP NOP NOP NOP NOP NOP COMMAND BANK n BANK m Page READ with Burst of 4 Interrupt Burst, Precharge Idle BANK n Active t t Internal RP - BANK n WR - BANK m States Page Active WRITE with Burst of 4 Write-Back BANK m BANK n, BANK m, ADDRESS COL a COL d 1 DQM DOUT DIN DIN DIN DIN DQ a d d + 1 d + 2 d + 3 CL = 3 (BANK n) DON’T CARE Notes: 1. DQM is HIGH at T2 to prevent DOUT a + 1 from contending with DIN d at T4. WRITE with Auto Precharge 2. Interrupted by a READ (with or without auto precharge): A READ to bank m will inter- rupt a WRITE on bank n when registered, with the data-out appearing CL later. The t t precharge to bank n will begin after WR is met, where WR begins when the READ to bank m is registered. The last valid WRITE to bank n will be data-in registered one clock prior to the READ to bank m (see Figure 29 on page 35). 3. Interrupted by a WRITE (with or without auto precharge): A WRITE to bank m will interrupt a WRITE on bank n when registered. The precharge to bank n will begin t t after WR is met, where WR begins when the WRITE to bank m is registered. The last valid data WRITE to bank n will be data registered one clock prior to a WRITE to bank m (see Figure 30 on page 35). PDF: 09005aef80872800/Source: 09005aef80863355 Micron Technology, Inc., reserves the right to change products or specifications without notice. 128MbSDRAMx32_2.fm - Rev. J 6/06 EN 34 ©2001 Micron Technology, Inc. All rights reserved. 128Mb: x32 SDRAM Register Definition Figure 29: WRITE With Auto Precharge Interrupted by a READ T0 T1 T2 T3 T4 T5 T6 T7 CLK WRITE - AP READ - AP NOP NOP NOP NOP NOP NOP COMMAND BANK n BANK m Page Active WRITE with Burst of 4 Interrupt Burst, Write-Back Precharge BANK n t RP - BANK n t WR - BANK n Internal t RP - BANK m States Page Active READ with Burst of 4 BANK m BANK n, BANK m, ADDRESS COL a COL d DIN DIN DOUT DOUT DQ a a + 1 d d + 1 CL = 3 (BANK m) DON’T CARE Notes: 1. DQM is LOW. Figure 30: WRITE With Auto Precharge Interrupted by a WRITE T0 T1 T2 T3 T4 T5 T6 T7 CLK WRITE - AP WRITE - AP NOP NOP NOP NOP NOP NOP COMMAND BANK n BANK m Page Active WRITE with Burst of 4 Interrupt Burst, Write-Back Precharge BANK n t t RP - BANK n WR - BANK n Internal t WR - BANK m States Page Active WRITE with Burst of 4 Write-Back BANK m BANK n, BANK m, ADDRESS COL a COL d DIN DIN DIN DIN DIN DIN DIN DQ a a + 1 a + 2 d d + 1 d + 2 d + 3 DON’T CARE Notes: 1. DQM is LOW. PDF: 09005aef80872800/Source: 09005aef80863355 Micron Technology, Inc., reserves the right to change products or specifications without notice. 128MbSDRAMx32_2.fm - Rev. J 6/06 EN 35 ©2001 Micron Technology, Inc. All rights reserved. 128Mb: x32 SDRAM Register Definition Table 9: Truth Table – CKE (Notes: 1–4) CKE CKE Current State COMMAND ACTION Notes n-1 n n n L L Power-Down X Maintain power-Down Self refresh X Maintain self refresh Clock Suspend X Maintain clock suspend L H Power-Down COMMAND INHIBIT or NOP Exit power-down 5 Self refresh COMMAND INHIBIT or NOP Exit self refresh 6 Clock suspend X Exit clock suspend 7 H L All banks idle COMMAND INHIBIT or NOP Power-Down entry All banks idle AUTO REFRESH self refresh Entry Reading or writing VALID Clock suspend entry H H See Table 10 on page 37 Notes: 1. CKE is the logic state of CKE at clock edge n; CKE was the state of CKE at the previous n n-1 clock edge. 2. Current state is the state of the SDRAM immediately prior to clock edge n. 3. COMMAND is the command registered at clock edge n, and ACTION is a result of COM- n n MAND . n 4. All states and sequences not shown are illegal or reserved. 5. Exiting power-down at clock edge n will put the device in the all banks idle state in time for t clock edge n + 1 (provided that CKS is met). t 6. Exiting self refresh at clock edge n will put the device in the all banks idle state once XSR is met. COMMAND INHIBIT or NOP commands should be issued on any clock edges occurring t t during the XSR period. A minimum of two NOP commands must be provided during XSR period. 7. After exiting clock suspend at clock edge n, the device will resume operation and recognize the next command at clock edge n + 1. PDF: 09005aef80872800/Source: 09005aef80863355 Micron Technology, Inc., reserves the right to change products or specifications without notice. 128MbSDRAMx32_2.fm - Rev. J 6/06 EN 36 ©2001 Micron Technology, Inc. All rights reserved. 128Mb: x32 SDRAM Register Definition Table 10: Truth Table – Current State Bank n, Command To Bank n Notes: 1–6; notes appear below table Current State CS# RAS# CAS# WE# COMMAND (ACTION) Notes Any H XXX COMMAND INHIBIT (NOP/Continue previous operation) L HHH NO OPERATION (NOP/Continue previous operation) Idle L L H H ACTIVE (Select and activate row) LLL H AUTO REFRESH 7 LLLL 7 LOAD MODE REGISTER LL H L 11 PRECHARGE Row active LHLH READ (Select column and start READ burst) 10 LHL L WRITE (Select column and start WRITE burst) 10 LL H L PRECHARGE (Deactivate row in bank or banks) 8 Read (auto LHLH 10 READ (Select column and start new READ burst) precharge LHL L 10 WRITE (Select column and start WRITE burst) disabled) LL H L PRECHARGE (Truncate READ burst, start precharge) 8 LH HL BURST TERMINATE Write (auto LHLH READ (Select column and start READ burst) 10 precharge LHL L 10 WRITE (Select column and start new WRITE burst) disabled) LL H L 8 PRECHARGE (Truncate WRITE burst, start precharge) LH HL BURST TERMINATE 9 Notes: 1. This table applies when CKE was HIGH and CKE is HIGH (see Table 9 on page 36) and n-1 n t after XSR has been met (if the previous state was self refresh). 2. This table is bank-specific, except where noted; i.e., the current state is for a specific bank and the commands shown are those allowed to be issued to that bank when in that state. Exceptions are covered in the notes below. 3. Current state definitions: t Idle: The bank has been precharged, and RP has been met. t Row active: A row in the bank has been activated, and RCD has been met. No data bursts/accesses and no register accesses are in progress. Read: A READ burst has been initiated, with auto precharge disabled, and has not yet terminated or been terminated. Write: A WRITE burst has been initiated, with auto precharge disabled, and has not yet terminated or been terminated. 4. The following states must not be interrupted by a command issued to the same bank. COM- MAND INHIBIT or NOP commands, or allowable commands to the other bank should be issued on any clock edge occurring during these states. Allowable commands to the other bank are determined by its current state and Table 10 on page 37, and according to Table 11 on page 39. Precharging: Starts with registration of a PRECHARGE command and ends when t t RP is met. Once RP is met, the bank will be in the idle state. t Row activating: Starts with registration of an ACTIVE command and ends when RCD t is met. Once RCD is met, the bank will be in the row active state. Read w/auto Starts with registration of a READ command with auto precharge t t precharge enabled: enabled and ends when RP has been met. Once RP is met, the bank will be in the idle state. Write w/auto Starts with registration of a WRITE command with auto precharge t t precharge enabled: enabled and ends when RP has been met. Once RP is met, the bank will be in the idle state. PDF: 09005aef80872800/Source: 09005aef80863355 Micron Technology, Inc., reserves the right to change products or specifications without notice. 128MbSDRAMx32_2.fm - Rev. J 6/06 EN 37 ©2001 Micron Technology, Inc. All rights reserved. 128Mb: x32 SDRAM Register Definition 5. The following states must not be interrupted by any executable command; COMMAND INHIBIT or NOP commands must be applied on each positive clock edge during these states. Refreshing: Starts with registration of an AUTO REFRESH command and ends t t when RFC is met. Once RFC is met, the SDRAM will be in the all banks idle state. Accessing mode Starts with registration of a LOAD MODE REGISTER command and t t register: ends when MRD has been met. Once MRD is met, the SDRAM will be in the all banks idle state. Precharging all: Starts with registration of a PRECHARGE ALL command and ends t t when RP is met. Once RP is met, all banks will be in the idle state. 6. All states and sequences not shown are illegal or reserved. 7. Not bank-specific; requires that all banks are idle. 8. May or may not be bank-specific; if all banks are to be precharged, all must be in a valid state for precharging. 9. Not bank-specific; BURST TERMINATE affects the most recent READ or WRITE burst, regard- less of bank. 10. READs or WRITEs listed in the Command (Action) column include READs or WRITEs with auto precharge enabled and READs or WRITEs with auto precharge disabled. 11. Does not affect the state of the bank and acts as a NOP to that bank. PDF: 09005aef80872800/Source: 09005aef80863355 Micron Technology, Inc., reserves the right to change products or specifications without notice. 128MbSDRAMx32_2.fm - Rev. J 6/06 EN 38 ©2001 Micron Technology, Inc. All rights reserved. 128Mb: x32 SDRAM Register Definition Table 11: Truth Table – CURRENT STATE BANK n, COMMAND TO BANK m Notes: 1–6; notes appear below and on next page Current State CS# RAS# CAS# WE# COMMAND (ACTION) Notes Any H XXX COMMAND INHIBIT (NOP/Continue previous operation) L HHH NO OPERATION (NOP/Continue previous operation) Idle XXXX Any Command Otherwise Allowed to Bank m Row activating, LL H H ACTIVE (Select and activate row) active, or LH LH 7 READ (Select column and start READ burst) precharging LH L L 7 WRITE (Select column and start WRITE burst) LL H L PRECHARGE Read (auto LL H H ACTIVE (Select and activate row) precharge LH LH READ (Select column and start new READ burst) 7, 10 disabled) LH L L 7, 11 WRITE (Select column and start WRITE burst) LL H L 9 PRECHARGE Write (auto LL H H ACTIVE (Select and activate row) precharge LH LH READ (Select column and start READ burst) 7, 12 disabled) LH L L WRITE (Select column and start new WRITE burst) 7, 13 LL H L 9 PRECHARGE Read (with LL H H ACTIVE (Select and activate row) auto precharge) LH LH READ (Select column and start new READ burst) 7, 8, 14 LH L L WRITE (Select column and start WRITE burst) 7, 8, 15 LL H L PRECHARGE 9 Write (with LL H H ACTIVE (Select and activate row) auto precharge) LH LH 7, 8, 16 READ (Select column and start READ burst) LH L L WRITE (Select column and start new WRITE burst) 7, 8, 17 LL H L PRECHARGE 9 Notes: 1. This table applies when CKE was HIGH and CKE is HIGH (see Table 9 on page 36) and n-1 n t after XSR has been met (if the previous state was self refresh). 2. This table describes alternate bank operation, except where noted; i.e., the current state is for bank n and the commands shown are those allowed to be issued to bank m (assuming that bank m is in such a state that the given command is allowable). Exceptions are covered in the notes below. 3. Current state definitions: t Idle: The bank has been precharged, and RP has been met. t Row Active: A row in the bank has been activated, and RCD has been met. No data bursts/accesses and no register accesses are in progress. Read: A READ burst has been initiated, with auto precharge disabled, and has not yet terminated or been terminated. Write: A WRITE burst has been initiated, with auto precharge disabled, and has not yet terminated or been terminated. Read w/Auto Starts with registration of a READ command with auto precharge t t Precharge Enabled: enabled, and ends when RP has been met. Once RP is met, the bank will be in the idle state. Write w/Auto Starts with registration of a WRITE command with auto precharge t t Precharge Enabled: enabled, and ends when RP has been met. Once RP is met, the bank will be in the idle state. 4. AUTO REFRESH, SELF REFRESH and LOAD MODE REGISTER commands may only be issued when all banks are idle. 5. A BURST TERMINATE command cannot be issued to another bank; it applies to the bank represented by the current state only. PDF: 09005aef80872800/Source: 09005aef80863355 Micron Technology, Inc., reserves the right to change products or specifications without notice. 128MbSDRAMx32_2.fm - Rev. J 6/06 EN 39 ©2001 Micron Technology, Inc. All rights reserved. 128Mb: x32 SDRAM Register Definition 6. All states and sequences not shown are illegal or reserved. 7. READs or WRITEs to bank m listed in the Command (Action) column include READs or WRITEs with auto precharge enabled and READs or WRITEs with auto precharge disabled. 8. Concurrent auto precharge: Bank n will initiate the auto precharge command when its burst has been interrupted by bank m’s burst. 9. Burst in bank n continues as initiated. 10. For a READ without auto precharge interrupted by a READ (with or without auto pre- charge), the READ to bank m will interrupt the READ on bank n, CL later (see Figure 10). 11. For a READ without auto precharge interrupted by a WRITE (with or without auto pre- charge), the WRITE to bank m will interrupt the READ on bank n when registered (see Figure 12 and Figure 13). DQM should be used one clock prior to the WRITE command to prevent bus contention. 12. For a WRITE without auto precharge interrupted by a READ (with or without auto pre- charge), the READ to bank m will interrupt the WRITE on bank n when registered (see Figure 20), with the data-out appearing CL later. The last valid WRITE to bank n will be data-in registered one clock prior to the READ to bank m. 13. For a WRITE without auto precharge interrupted by a WRITE (with or without auto pre- charge), the WRITE to bank will interrupt the WRITE on bank n when registered (see Figure 18). The last valid WRITE to bank n will be data-in registered one clock prior to the READ to bank m. 14. For a READ with auto precharge interrupted by a READ (with or without auto precharge), the READ to bank m will interrupt the READ on bank n, CL later. The PRECHARGE to bank n will begin when the READ to bank m is registered (see Figure 27). 15. For a READ with auto precharge interrupted by a WRITE (with or without auto precharge), the WRITE to bank m will interrupt the READ on bank n when registered. DQM should be used two clocks prior to the WRITE command to prevent bus contention. The PRECHARGE to bank n will begin when the WRITE to bank m is registered (see Figure 28). 16. For a WRITE with auto precharge interrupted by a READ (with or without auto precharge), the READ to bank m will interrupt the WRITE on bank n when registered, with the data-out t t appearing CL later. The PRECHARGE to bank n will begin after WR is met, where WR begins when the READ to bank m is registered. The last valid WRITE bank n will be data-in registered one clock prior to the READ to bank m (see Figure 29). 17. For a WRITE with auto precharge interrupted by a WRITE (with or without auto precharge), the WRITE to bank m will interrupt the WRITE on bank n when registered. The PRECHARGE t t to bank n will begin after WR is met, where WR begins when the WRITE to bank m is reg- istered. The last valid WRITE to bank n will be data registered one clock to the WRITE to bank m (see Figure 30). PDF: 09005aef80872800/Source: 09005aef80863355 Micron Technology, Inc., reserves the right to change products or specifications without notice. 128MbSDRAMx32_2.fm - Rev. J 6/06 EN 40 ©2001 Micron Technology, Inc. All rights reserved. 128Mb: x32 SDRAM Electrical Specifications Electrical Specifications Stresses greater than those listed Table 12 may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Table 12: Absolute Maximum Ratings Parameter Min Max Units –1 +4.6 V Voltage on VDD, VDDQ supply relative to VSS Voltage on inputs, NC or I/O pins relative to VSS –1 +4.6 V Operating temperature, T 0+70 °C A Storage temperature (plastic) –55 +150 °C Power dissipation 1W –40 +85 °C Operating temperature, T (IT) A Temperature and Thermal Impedance It is imperative that the SDRAM device’s temperature specifications, shown in Table 13 on page 42, be maintained in order to ensure the junction temperature is in the proper operating range to meet data sheet specifications. An important step in maintaining the proper junction temperature is using the device’s thermal impedances correctly. The thermal impedances are listed in Table 14 on page 42 for the applicable die revision and packages being made available. These thermal impedance values vary according to the density, package, and particular design used for each device. Incorrectly using thermal impedances can produce significant errors. Read Micron technical note TN-00-08, “Thermal Applications” prior to using the thermal impedances listed in Table 14. To ensure the compatibility of current and future designs, contact Micron Applications Engineering to confirm thermal impedance values. The SDRAM device’s safe junction temperature range can be maintained when the T C specification is not exceeded. In applications where the device's ambient temperature is too high, use of forced air and/or heat sinks may be required in order to satisfy the case temperature specifications. PDF: 09005aef80872800/Source: 09005aef80863355 Micron Technology, Inc., reserves the right to change products or specifications without notice. 128MbSDRAMx32_2.fm - Rev. J 6/06 EN 41 ©2001 Micron Technology, Inc. All rights reserved. 128Mb: x32 SDRAM Electrical Specifications Table 13: Temperature Limits Parameter Symbol Min Max Units Notes °C 1, 2, 3, 4 Operating case temperature: T C 0 80 Commercial Industrial -40 90 Junction temperature: T °C 3 J Commercial 0 85 Industrial -40 95 Ambient temperature: T °C 3, 5 A Commercial 0 70 Industrial -40 85 Peak reflow temperature T –260 °C PEAK Notes: 1. MAX operating case temperature, T , is measured in the center of the package on the top C side of the device, as shown in Figure 31 and Figure 32 on page 43. 2. Device functionality is not guaranteed if the device exceeds maximum T during operation. C 3. Both temperature specifications must be satisfied 4. The case temperature should be measured by gluing a thermocouple to the top center of the component. This should be done with a 1mm bead of conductive epoxy, as defined by the JEDEC EIA/JESD51 standards. Care should be taken to ensure the thermocouple bead is touching the case. 5. Operating ambient temperature surrounding the package. Table 14: Thermal Impedance Simulated Values θ JA (°C/W) θ JA (°C/W) θ JA (°C/W) Airflow = Airflow = Airflow = Die Revision Package Substrate 0m/s 1m/s 2m/s θ JB (°C/W) θ JC (°C/W) 86-pin 2-layer 82.2 65 59.7 49.4 10.3 G TSOP 4-layer 55 47.2 45.1 40.6 90-ball 2-layer 64.6 50.8 45.3 37.5 1.8 VFBGA 4-layer 48.2 41.1 38.1 32.1 Notes: 1. For designs expected to last beyond the die revision listed, contact Micron Applications Engineering to confirm thermal impedance values. 2. Thermal resistance data is sampled from multiple lots and the values should be viewed as typical. 3. These are estimates; actual results may vary. PDF: 09005aef80872800/Source: 09005aef80863355 Micron Technology, Inc., reserves the right to change products or specifications without notice. 128MbSDRAMx32_2.fm - Rev. J 6/06 EN 42 ©2001 Micron Technology, Inc. All rights reserved. 128Mb: x32 SDRAM Electrical Specifications Figure 31: Example Temperature Test Point Location, 54-Pin TSOP: Top View 22.22mm 11.11mm Test point 10.16mm 5.08mm Figure 32: Example Temperature Test Point Location, 90-Ball VFBGA: Top View 8.00mm 4.00mm Test point 13.00mm 6.50mm PDF: 09005aef80872800/Source: 09005aef80863355 Micron Technology, Inc., reserves the right to change products or specifications without notice. 128MbSDRAMx32_2.fm - Rev. J 6/06 EN 43 ©2001 Micron Technology, Inc. All rights reserved. 128Mb: x32 SDRAM Electrical Specifications Table 15: DC Electrical Characteristics and Operating Conditions Notes: 1, 6; notes appear on page 47; VDD = +3.3V ±0.3V, VDDQ = +3.3V ±0.3V Parameter/Condition Symbol Min Max Units Notes VDD, VDDQ3 3.6 V Supply voltage Input high voltage: Logic 1; All inputs VIH 2VDD + 0.3 V 22 Input low voltage: Logic 0; All inputs Vil –0.3 0.8 V 22 Input leakage current: II –5 5 µA Any input 0V ≤ VIN ≤ VDD (All other pins not under test = 0V) Output leakage current: IOZ –5 5 µA DQs are disabled; 0V ≤ VOUT ≤ VDDQ VOH 2.4 – V Output levels: )Output high voltage (IOUT = –4mA) VOL –0.4 V Output low voltage (IOUT = 4mA) Table 16: IDD Specifications and Conditions (Notes: 1, 6, 11, 13; notes appear on page 47) (VDD, VDDQ = +3.3V ±0.3V) Max Parameter/Condition Symbol -6 -7 Units Notes Operating current: Active mode; IDD1 190 165 mA 3, 18, 19, t t Burst = 2; READ or WRITE; RC = RC (MIN); CL = 3 26 Standby current: Power-Down mode; IDD22 2 mA CKE = LOW; All banks idle Standby current: Active mode; CS# = HIGH; IDD3 65 55 mA 19, 26 t CKE = HIGH; All banks active after RCD met; No accesses in progress IDD4 195 175 mA 3, 18, 19, Operating current: Burst mode; Continuous burst; READ or WRITE; All banks active, CL = 3 26 t t Auto refresh current: RFC = RFC (MIN) IDD5 320 320 mA 3, 12, 18, 19, 26 CL = 3; CKE, CS# = HIGH Self refresh current: CKE ≤ 0.2V IDD62 2 mA 4 Table 17: Capacitance (Note: 2) Parameter Symbol Min Max Units Input Capacitance: CLK CI12.5 4.0 pF Input Capacitance: All other input-only pins CI22.5 4.0 pF CIo4.0 6.5 pF Input/Output Capacitance: DQs PDF: 09005aef80872800/Source: 09005aef80863355 Micron Technology, Inc., reserves the right to change products or specifications without notice. 128MbSDRAMx32_2.fm - Rev. J 6/06 EN 44 ©2001 Micron Technology, Inc. All rights reserved. 128Mb: x32 SDRAM Electrical Specifications Table 18: Electrical Characteristics and Recommended AC Operating Conditions Notes: 5, 6, 7, 8, 9, 11; notes appear on page 47 -6 -7 AC Characteristics Parameter Symbol Min Max Min Max Units Notes t Access time from CLK (pos. edge) CL = 3 AC (3) 5.5 5.5 ns t CL = 2 AC (2) 7.5 8 ns t CL = 1 AC (1) 17 17 ns t Address hold time AH 1 1 ns t AS 1.5 2 ns Address setup time t CLK high-level width CH 2.5 2.75 ns t CLK low-level width CL 2.5 2.75 ns t Clock cycle time CL = 3 CK (3) 6 7 ns 23 t CL = 2 CK (2) 10 10 ns 23 t CK (1) 20 20 ns 23 CL = 1 t CKE hold time CKH 1 1 ns t CKE setup time CKS 1.5 2 ns t CS#, RAS#, CAS#, WE#, DQM hold time CMH 1 1 ns t CS#, RAS#, CAS#, WE#, DQM setup time CMS 1.5 2 ns t DH 1 1 ns Data-in hold time t Data-in setup time DS 1.5 2 ns t Data-out High-Z time CL = 3 HZ (3) 5.5 5.5 ns 10 t CL = 2 HZ (2) 7.5 8 ns 10 t CL = 1 HZ (1) 17 17 ns 10 t LZ 1 1 ns Data-out Low-Z time t Data-out hold time OH 2 2.5 ns t ACTIVE to PRECHARGE command RAS 42120K42120K ns t ACTIVE to ACTIVE command period RC 60 70 ns t AUTO REFRESH period RFC 60 70 ns t RCD 18 20 ns ACTIVE to READ or WRITE delay t Refresh period (4,096 rows) REF 64 64 ms t PRECHARGE command period RP 18 20 ns t ACTIVE bank a to ACTIVE bank b command RRD 12 14 ns 25 t Transition time T 0.3 1.2 0.3 1.2 ns 7 t t WR 1 CLK+ 1 CLK+ CK 24 Write recovery time 6ns 7ns 12ns 14ns ns 27 t XSR 70 70 ns 20 Exit self refresh to ACTIVE command PDF: 09005aef80872800/Source: 09005aef80863355 Micron Technology, Inc., reserves the right to change products or specifications without notice. 128MbSDRAMx32_2.fm - Rev. J 6/06 EN 45 ©2001 Micron Technology, Inc. All rights reserved. 128Mb: x32 SDRAM Electrical Specifications Table 19: AC Functional Characteristics Notes: 5, 6, 7, 8, 9, 11; notes appear on page 47 PARAMETER SYMBOL -6 -7 UNITS NOTES t t CCD 1 1 CK READ/WRITE command to READ/WRITE command t t CKE to clock disable or power-down entry mode CKED 1 1 CK t t CKE to clock enable or power-down exit setup mode PED 1 1 CK t t DQM to input data delay DQD 0 0 CK t t DQM 0 0 CK DQM to data mask during WRITEs t t DQZ 2 2 CK DQM to data High-Z during READs t t WRITE command to input data delay DWD 0 0 CK t t Data-in to ACTIVE command CL = 3 DAL (3) 5 5 CK t t CL = 2 DAL (2) 4 4 CK t t DAL (1) 3 3 CK CL = 1 t t DPL 2 2 CK Data-in to PRECHARGE command t t Last data-in to burst STOP command BDL 1 1 CK t t Last data-in to new READ/WRITE command CDL 1 1 CK t t Last data-in to PRECHARGE command RDL 2 2 CK t t MRD 2 2 CK LOAD MODE REGISTER command to ACTIVE or REFRESH command t t ROH (3) 3 3 CK Data-out to High-Z from PRECHARGE command CL = 3 t t CL = 2 ROH (2) 2 2 CK t t CL = 1 ROH (1) 1 1 CK PDF: 09005aef80872800/Source: 09005aef80863355 Micron Technology, Inc., reserves the right to change products or specifications without notice. 128MbSDRAMx32_2.fm - Rev. J 6/06 EN 46 ©2001 Micron Technology, Inc. All rights reserved. 128Mb: x32 SDRAM Notes Notes 1. All voltages referenced to VSS. 2. This parameter is sampled. VDD, VDDQ = +3.3V; f = 1 MHz, T = 25°C; pin under test A biased at 1.4V. AC can range from 0pF to 6pF. 3. IDD is dependent on output loading and cycle rates. Specified values are obtained with minimum cycle time and the outputs open. 4. Enables on-chip refresh and address counters. 5. The minimum specifications are used only to indicate cycle time at which proper operation over the full temperature range (0°C ≤ T ≤ +70°C and –40°C ≤ T ≤ +85°C for A A IT parts) is ensured. 6. An initial pause of 100µs is required after power-up, followed by two AUTO Refresh commands, before proper device operation is ensured. (VDD and VDDQ must be pow- ered up simultaneously. VSS and VSSQ must be at same potential.) The two AUTO t Refresh command wake-ups should be repeated any time the REF refresh require- ment is exceeded. t 7. AC characteristics assume T = 1ns. 8. In addition to meeting the transition rate specification, the clock and CKE must tran- sit between VIH and VIL (or between VIL and VIH) in a monotonic manner. 9. Outputs measured at 1.5V with equivalent load: Q 30pF t 10. HZ defines the time at which the output achieves the open circuit condition; it is not t a reference to VOH or VOL. The last valid data element will meet OH before going High-Z. 11. AC timing and IDD tests have VIL = 0.25 and VIH = 2.75, with timing referenced to 1.5V crossover point. 12. Other input signals are allowed to transition no more than once in any two-clock period and are otherwise at valid VIH or VIL levels. 13. IDD specifications are tested after the device is properly initialized. t 14. Timing actually specified by CKS; clock(s) specified as a reference only at minimum cycle rate. t t 15. Timing actually specified by WR plus RP; clock(s) specified as a reference only at minimum cycle rate. t 16. Timing actually specified by WR. 17. Required clocks are specified by JEDEC functionality and are not dependent on any timing parameter. 18. The IDD current will decrease as CL is reduced. This is due to the fact that the maxi- mum cycle rate is slower as CL is reduced. 19. Address transitions average one transition every two clocks. 20. CLK must be toggled a minimum of two times during this period. t 21. Based on CK = 143 MHz for -7, 166 MHz for -6. 22. VIH overshoot: VIH (MAX) = VDDQ + 1.2V for a pulse width ≤ 3ns, and the pulse width cannot be greater than one third of the cycle rate. VIL undershoot: VIL (MIN) = –1.2V for a pulse width ≤ 3ns, and the pulse width cannot be greater than one third of the cycle rate. 23. The clock frequency must remain constant during access or precharge states (READ, t WRITE, including WR, and PRECHARGE commands). CKE may be used to reduce the data rate. PDF: 09005aef80872800/Source: 09005aef80863355 Micron Technology, Inc., reserves the right to change products or specifications without notice. 128MbSDRAMx32_2.fm - Rev. J 6/06 EN 47 ©2001 Micron Technology, Inc. All rights reserved. 128Mb: x32 SDRAM Notes 24. Auto precharge mode only. 25. JEDEC and PC100 specify three clocks. t 26. CK = 7ns for -7, 6ns for -6. t t 27. Check factory for availability of specially screened devices having WR = 10ns. WR = 1 t t CK for 100 MHz and slower ( CK = 10ns and higher) in manual precharge. PDF: 09005aef80872800/Source: 09005aef80863355 Micron Technology, Inc., reserves the right to change products or specifications without notice. 128MbSDRAMx32_2.fm - Rev. J 6/06 EN 48 ©2001 Micron Technology, Inc. All rights reserved. 128Mb: x32 SDRAM Timing Diagrams Timing Diagrams Figure 33: Initialize and Load Mode Register T0 T1 Tn + 1 To + 1 Tp + 1 Tp + 2 Tp + 3 ( ( ( ( ( ( t t CK CL ) ) ) ) ) ) CLK (( ( ( t ( ( ( ( CH )) ) ) ) ) ) ) t t CKH CKS (( (( ( ( ( ( )) )) ) ) ) ) CKE ( ( ( ( ) ) ) ) t t t t t t CMS CMH CMS CMH CMS CMH ( ( ( ( ( ( ( ( ) ) ) ) ) ) ) ) AUTO AUTO LOAD MODE COMMAND NOP PRECHARGE NOP NOP NOP NOP NOP ACTIVE ( ( ( ( REFRESH ( ( REFRESH ( ( REGISTER ) ) ) ) ) ) ) ) ( ( ( ( ( ( ( ( ) ) ) ) ) ) ) ) DQM 0-3 ( ( ( ( ( ( ( ( ) ) ) ) ) ) ) ) t t AS AH ( ( ( ( ( ( ( ( ) ) ) ) ) ) ) ) CODE ROW A0-A9, A11 ( ( ( ( ( ( ( ( ) ) ) ) ) ) ) ) t t AS AH ( ( ( ( ( ( ALL BANKS ( ( ) ) ) ) ) ) ) ) A10 CODE ROW ( ( ( ( ( ( ( ( ) ) ) ) ) ) ) ) SINGLE BANK ( ( ( ( ( ( ( ( ) ) ) ) ) ) ALL ) ) BA0, BA1 BANK ( ( ( ( ( ( BANKS ( ( ) ) ) ) ) ) ) ) High-Z DQ (( (( )) )) T = 100µs t t t t RP (MIN) RFC RFC MRD Power-up: 1, 2 Program Mode Register VDD and Precharge AUTO REFRESH AUTO REFRESH CK stable all banks DON’T CARE UNDEFINED Notes: 1. The mode register may be loaded prior to the AUTO REFRESH cycles if desired. 2. Outputs are guaranteed High-Z after command is issued. PDF: 09005aef80872800/Source: 09005aef80863355 Micron Technology, Inc., reserves the right to change products or specifications without notice. 128MbSDRAMx32_2.fm - Rev. J 6/06 EN 49 ©2001 Micron Technology, Inc. All rights reserved. 128Mb: x32 SDRAM Timing Diagrams Figure 34: Power-Down Mode T0 T1 T2 Tn + 1 Tn + 2 ( ( t t ) ) CK CL CLK ( ( t CH ) ) t t CKS CKS CKE ( ( ) ) t t CKS CKH t t CMS CMH ( ( ) ) COMMAND PRECHARGE NOP NOP NOP ACTIVE ( ( ) ) ( ( ) ) DQM 0-3 ( ( ) ) ( ( ) ) A0-A9, A11 ROW ( ( ) ) ALL BANKS ( ( ) ) A10 ROW ( ( ) ) SINGLE BANK t t AS AH ( ( ) ) BANK BA0, BA1 BANK(S) ( ( ) ) High-Z ( ( DQ ) ) Two clock cycles Input buffers gated off while in power-down mode Precharge all All banks idle, enter All banks idle active banks power-down mode Exit power-down mode DON’T CARE UNDEFINED Notes: 1. Violating refresh requirements during power-down may result in a loss of data. PDF: 09005aef80872800/Source: 09005aef80863355 Micron Technology, Inc., reserves the right to change products or specifications without notice. 128MbSDRAMx32_2.fm - Rev. J 6/06 EN 50 ©2001 Micron Technology, Inc. All rights reserved. 128Mb: x32 SDRAM Timing Diagrams Figure 35: Clock Suspend Mode T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 t t CK CL CLK t CH t t CKS CKH CKE t t CKS CKH t t CMS CMH COMMAND READ NOP NOP NOP NOP NOP WRITE NOP t t CMS CMH DQM0-3 t t AS AH 2 2 A0-A9, A11 COLUMN m COLUMN e t t AS AH A10 t t AS AH BA0, BA1 BANK BANK t AC t t t t t OH HZ DS DH AC DOUT m DOUT m + 1 DOUT e DOUT e + 1 DQ t LZ DON’T CARE UNDEFINED Notes: 1. For this example, BL = 2, CL = 3, and auto precharge is disabled. 2. A8, A9, and A11 = “Don’t Care.” PDF: 09005aef80872800/Source: 09005aef80863355 Micron Technology, Inc., reserves the right to change products or specifications without notice. 128MbSDRAMx32_2.fm - Rev. J 6/06 EN 51 ©2001 Micron Technology, Inc. All rights reserved. 128Mb: x32 SDRAM Timing Diagrams Figure 36: Auto Refresh Mode T0 T1 T2 Tn + 1 To + 1 ( ( ( ( t CL ) ) ) ) CLK t t ( ( ( ( CK CH ) ) ) ) ( ( ( ( ) ) ) ) CKE t t CKS CKH t t CMS CMH ( ( ( ( ) ) ) ) AUTO AUTO COMMAND PRECHARGE NOP NOP NOP NOP NOP ACTIVE REFRESH ( ( REFRESH ( ( ) ) ) ) ( ( ( ( ) ) ) ) DQM 0-3 ( ( ( ( ) ) ) ) ( ( ( ( ) ) ) ) A0–A9, A11 ROW ( ( ( ( ) ) ) ) ( ( ( ( ( ( ALL BANKS ) ) ) ) ) ) A10 ROW ( ( ( ( ( ( ) ) ) ) ) ) SINGLE BANK t t AS AH ( ( ( ( ) ) ) ) BANK(S) BA0, BA1 BANK ( ( ( ( ) ) ) ) High-Z DQ ( ( ( ( ) ) ) ) t t t RP RFC RFC Precharge all DON’T CARE UNDEFINED active banks t Notes: 1. RFC must not be interrupted by any executable command; COMMAND INHIBIT or NOP t commands must be applied on each positive clock edge during RFC. PDF: 09005aef80872800/Source: 09005aef80863355 Micron Technology, Inc., reserves the right to change products or specifications without notice. 128MbSDRAMx32_2.fm - Rev. J 6/06 EN 52 ©2001 Micron Technology, Inc. All rights reserved. 128Mb: x32 SDRAM Timing Diagrams Figure 37: Self Refresh Mode T0 T1 T2 Tn + 1 To + 1 To + 2 ( ( ( ( t CL ) ) ) ) CLK t ( ( ( ( t CK CH ) ) ) ) t > t CKS RAS ( ( ) ) CKE ( ( ( ( ) ) ) ) t t t CKS CKH CKS t t CMS CMH ( ( ( ( ) ) ) ) AUTO AUTO COMMAND PRECHARGE NOP NOP REFRESH ( ( ( ( REFRESH ) ) ) ) ( ( ( ( ) ) ) ) DQM0–3 ( ( ( ( ) ) ) ) ( ( ( ( ) ) ) ) A0–A9, A11 ( ( ( ( ) ) ) ) ALL BANKS ( ( ( ( ) ) ) ) A10 ( ( ( ( ) ) ) ) SINGLE BANK t t AS AH ( ( ( ( ) ) ) ) BA0, BA1 BANK(S) ( ( ( ( ) ) ) ) High-Z ( ( ( ( DQ ) ) ) ) t t RP XSR Precharge all Enter self refresh mode Exit self refresh mode active banks (Restart refresh time base) DON’T CARE CLK stable prior to exiting self refresh mode UNDEFINED t Notes: 1. No maximum time limit for self refresh. RAS(MAX) applies to non-self refresh mode. t 2. XSR requires minimum of two clocks regardless of frequency or timing. 3. As a general rule, any time self refresh is exited, the DRAM may not reenter the self refresh mode until all rows have been refreshed by the AUTO REFRESH command at the distributed t refresh rate, REF, or faster. However, the following exceptions are allowed: 3a. The DRAM has been in self refresh mode for a minimum of 64µs prior to exiting. t 3b. XSR is not violated. 3c. At least two AUTO REFRESH commands are preformed during each 15.6µs interval while the DRAM remains out of the self refresh mode. PDF: 09005aef80872800/Source: 09005aef80863355 Micron Technology, Inc., reserves the right to change products or specifications without notice. 128MbSDRAMx32_2.fm - Rev. J 6/06 EN 53 ©2001 Micron Technology, Inc. All rights reserved. 128Mb: x32 SDRAM Timing Diagrams Figure 38: Single READ – Without Auto Precharge T0 T1 T2 T3 T4 T5 t t CK CL CLK t CH t t CKS CKH CKE t t CMS CMH COMMAND ACTIVE NOP READ PRECHARGE NOP ACTIVE t t CMS CMH DQM / DQML, DQMH t t AS AH 2 A0–A9, A11 ROW ROW COLUMN m t t AS AH ALL BANKS ROW ROW A10 SINGLE BANK DISABLE AUTO PRECHARGE t t AS AH BA0, BA1 BANK BANK BANK BANK t t AC OH DQ DOUTm t t LZ HZ t RCD CAS Latency t t RP RAS t RC DON’T CARE UNDEFINED Notes: 1. For this example, BL = 4, CL = 2, and the READ burst is followed by a “manual” PRECHARGE. 2. x16: A9 and A11 = “Don’t Care” x32: A8, A9,and A11 = “Don’t Care” See Table 18 on page 45. PDF: 09005aef80872800/Source: 09005aef80863355 Micron Technology, Inc., reserves the right to change products or specifications without notice. 128MbSDRAMx32_2.fm - Rev. J 6/06 EN 54 ©2001 Micron Technology, Inc. All rights reserved. 128Mb: x32 SDRAM Timing Diagrams Figure 39: Read – With Auto Precharge T0 T1 T2 T3 T4 T5 T6 T7 T8 t t CK CL CLK t CH t t CKS CKH CKE t t CMS CMH COMMAND ACTIVE NOP READ NOP NOP NOP NOP NOP ACTIVE t t CMS CMH DQM0–3 t t AS AH A0–A9, A11 2 ROW ROW COLUMN m t t AS AH ENABLE AUTO PRECHARGE ROW ROW A10 t t AS AH BA0, BA1 BANK BANK BANK t t t AC AC AC t t t t t AC OH OH OH OH DOUT m DOUT m + 1 DOUT m + 2 DOUT m + 3 DQ t t LZ HZ t t RCD CAS Latency RP t RAS t RC DON’T CARE UNDEFINED Notes: 1. For this example, BL = 4, and CL = 2. 2. A8, A9, and A11 = “Don’t Care.” PDF: 09005aef80872800/Source: 09005aef80863355 Micron Technology, Inc., reserves the right to change products or specifications without notice. 128MbSDRAMx32_2.fm - Rev. J 6/06 EN 55 ©2001 Micron Technology, Inc. All rights reserved. 128Mb: x32 SDRAM Timing Diagrams Figure 40: Alternating Bank Read Accesses T0 T1 T2 T3 T4 T5 T6 T7 T8 t t CK CL CLK t CH t t CKS CKH CKE t CMS t CMH COMMAND ACTIVE NOP READ NOP ACTIVE NOP READ NOP ACTIVE t t CMS CMH DQM 0–3 t t AS AH 2 2 ROW COLUMN m ROW COLUMN b ROW A0–A9, A11 t t AS AH ENABLE AUTO PRECHARGE ENABLE AUTO PRECHARGE ROW ROW ROW A10 t t AS AH BA0, BA1 BANK 0 BANK 0 BANK 4 BANK 4 BANK 0 t t t t t AC AC AC AC AC t t t t t t AC OH OH OH OH OH DOUT m DOUT m + 1 DOUT m + 2 DOUT m + 3 DOUT b DQ t LZ t t t RCD - BANK 0 CAS Latency - BANK 0 RP - BANK 0 RCD - BANK 0 t RAS - BANK 0 t RC - BANK 0 t t RCD - BANK 4 CAS Latency - BANK 4 RRD DON’T CARE UNDEFINED Notes: 1. For this example, BL = 4, and CL = 2. 2. A8, A9, and A11 = “Don’t Care.” PDF: 09005aef80872800/Source: 09005aef80863355 Micron Technology, Inc., reserves the right to change products or specifications without notice. 128MbSDRAMx32_2.fm - Rev. J 6/06 EN 56 ©2001 Micron Technology, Inc. All rights reserved. 128Mb: x32 SDRAM Timing Diagrams Figure 41: Read – Full-page Burst T0 T1 T2 T3 T4 T5 T6 Tn + 1 Tn + 2 Tn + 3 Tn + 4 ( ( t t ) ) CL CK CLK ( ( t CH ) ) t t CKS CKH ( ( ) ) CKE ( ( ) ) t t CMS CMH ( ( ) ) COMMAND ACTIVE NOP READ NOP NOP NOP NOP NOP BURST TERM NOP NOP ( ( ) ) t t CMS CMH ( ( ) ) DQM 0–3 ( ( ) ) t t AS AH ( ( ) ) A0–A9, A11 2 ROW COLUMN m ( ( ) ) t t AS AH ( ( ) ) ROW A10 ( ( ) ) t t AS AH ( ( ) ) BA0, BA1 BANK BANK ( ( ) ) t t t t t AC AC AC AC AC ( ( ) ) t t t t t t t AC OH OH OH OH OH OH ( ( ) ) Dout m DOUT m+1 DOUT m+2 DOUT m-1 DOUT m DOUT m+1 DQ ( ( ) ) t LZ t HZ t 256 locations within same row RCD CAS Latency DON’T CARE Full page completed UNDEFINED Full-page burst does not self-terminate. 3 Can use BURST TERMINATE command. Notes: 1. For this example, CL = 2. 2. A8, A9, and A11 = “Don’t Care.” t 3. Page left open; no RP. PDF: 09005aef80872800/Source: 09005aef80863355 Micron Technology, Inc., reserves the right to change products or specifications without notice. 128MbSDRAMx32_2.fm - Rev. J 6/06 EN 57 ©2001 Micron Technology, Inc. All rights reserved. 128Mb: x32 SDRAM Timing Diagrams Figure 42: Read – DQM Operation T0 T1 T2 T3 T4 T5 T6 T7 T8 t t CK CL CLK t CH t t CKS CKH CKE t t CMS CMH COMMAND ACTIVE NOP READ NOP NOP NOP NOP NOP NOP t t CMS CMH DQM 0-3 t t AS AH A0-A9, A11 2 ROW COLUMN m t t AS AH ENABLE AUTO PRECHARGE ROW A10 DISABLE AUTO PRECHARGE t t AS AH BA0, BA1 BANK BANK t AC t t t t t AC OH AC OH OH DQ DOUT m DOUT m + 2 DOUT m + 3 t t t t LZ HZ LZ HZ t RCD CAS Latency DON’T CARE UNDEFINED Notes: 1. For this example, CL = 2. 2. A8, A9, and A11 = “Don’t Care.” PDF: 09005aef80872800/Source: 09005aef80863355 Micron Technology, Inc., reserves the right to change products or specifications without notice. 128MbSDRAMx32_2.fm - Rev. J 6/06 EN 58 ©2001 Micron Technology, Inc. All rights reserved. 128Mb: x32 SDRAM Timing Diagrams Figure 43: Single Write T0 T1 T2 T3 T4 T5 T6 t t CK CL CLK t CH t t CKS CKH CKE t t CMS CMH COMMAND ACTIVE NOP WRITE NOP PRECHARGE NOP ACTIVE t t CMS CMH DQM / DQML, DQMH t t AS AH A0-A9, A11 ROW 3 ROW COLUMN m t t AS AH ALL BANKS ROW ROW A10 DISABLE AUTO PRECHARGE SINGLE BANK t t AS AH BA0, BA1 BANK BANK BANK BANK t t DS DH DQ DIN m 2 t t t RCD RP WR t RAS t RC DON’T CARE Notes: 1. For this example, BL = 1, and the WRITE burst is followed by a “manual” PRECHARGE. t 2. WR is required between and the PRECHARGE command, regardless of frequency. 3. A8, A9, and A11 = “Don’t Care.” PDF: 09005aef80872800/Source: 09005aef80863355 Micron Technology, Inc., reserves the right to change products or specifications without notice. 128MbSDRAMx32_2.fm - Rev. J 6/06 EN 59 ©2001 Micron Technology, Inc. All rights reserved. 128Mb: x32 SDRAM Timing Diagrams Figure 44: Write – Without Auto Precharge T0 T1 T2 T3 T4 T5 T6 T7 T8 t t CK CL CLK t CH t t CKS CKH CKE t t CMS CMH COMMAND ACTIVE NOP WRITE NOP NOP NOP PRECHARGE NOP ACTIVE t t CMS CMH DQM0–3 t t AS AH 3 A0–A9, A11 ROW ROW COLUMN m t t AS AH ALL BANKs ROW ROW A10 DISABLE AUTO PRECHARGE SINGLE BANK t t AS AH BANK BANK BANK BANK BA0, BA1 t t t t t t t t DS DH DS DH DS DH DS DH DIN m DIN m + 1 DIN m + 2 DIN m + 3 DQ 2 t t t RCD WR RP t RAS t RC DON’T CARE UNDEFINED Notes: 1. For this example, BL = 4, and the WRITE burst is followed by a “manual” PRECHARGE. t t 2. Faster frequencies require two clocks (when WR > CK). 3. A8, A9, and A11 = “Don’t Care.” t 4. WR of 1 CLK available if running 100 MHz or slower. Check factory for availability. PDF: 09005aef80872800/Source: 09005aef80863355 Micron Technology, Inc., reserves the right to change products or specifications without notice. 128MbSDRAMx32_2.fm - Rev. J 6/06 EN 60 ©2001 Micron Technology, Inc. All rights reserved. 128Mb: x32 SDRAM Timing Diagrams Figure 45: Write – With Auto Precharge T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 t t CK CL CLK t CH t t CKS CKH CKE t t CMS CMH COMMAND ACTIVE NOP WRITE NOP NOP NOP NOP NOP NOP ACTIVE t t CMS CMH DQM 0-3 t t AS AH A0-A9, A11 3 ROW ROW COLUMN m t t AS AH ENABLE AUTO PRECHARGE ROW ROW A10 t t AS AH BA0, BA1 BANK BANK BANK t t t t t t t t DS DH DS DH DS DH DS DH DIN m DIN m + 1 DIN m + 2 DIN m + 3 DQ 2 t t t RCD WR RP t RAS t RC DON’T CARE UNDEFINED Notes: 1. For this example, BL = 4. t t 2. Faster frequencies require two clocks (when WR > CK). 3. A8, A9, and A11 = “Don’t Care.” PDF: 09005aef80872800/Source: 09005aef80863355 Micron Technology, Inc., reserves the right to change products or specifications without notice. 128MbSDRAMx32_2.fm - Rev. J 6/06 EN 61 ©2001 Micron Technology, Inc. All rights reserved. 128Mb: x32 SDRAM Timing Diagrams Figure 46: Alternating Bank Write Accesses T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 t t CK CL CLK t CH t t CKS CKH CKE t t CMS CMH COMMAND ACTIVE NOP WRITE NOP ACTIVE NOP WRITE NOP NOP ACTIVE t t CMS CMH DQM0–3 t t AS AH 3 3 ROW ROW ROW COLUMN m COLUMN b A0–A9, A11 t t AS AH ENABLE AUTO PRECHARGE ENABLE AUTO PRECHARGE ROW ROW ROW A10 t t AS AH BANK 0 BANK 0 BANK 1 BANK 1 BA0, BA1 BANK 0 t t t t t t t t t t t t t t t t DS DH DS DH DS DH DS DH DS DH DS DH DS DH DS DH DIN m DIN m + 1 DIN m + 2 DIN m + 3 DIN b DIN b + 1 DIN b + 2 DIN b + 3 DQ t t 2 t t RCD - BANK 0 WR - BANK 0 RP - BANK 0 RCD - BANK 0 t RAS - BANK 0 t RC - BANK 0 t t t RCD - BANK 1 WR - BANK 1 RRD DON’T CARE Notes: 1. For this example, BL = 4. t t 2. Faster frequencies require two clocks (when WR > CK). 3. A8, A9, and A11 = “Don’t Care.” PDF: 09005aef80872800/Source: 09005aef80863355 Micron Technology, Inc., reserves the right to change products or specifications without notice. 128MbSDRAMx32_2.fm - Rev. J 6/06 EN 62 ©2001 Micron Technology, Inc. All rights reserved. 128Mb: x32 SDRAM Timing Diagrams Figure 47: Write – Full-page Burst T0 T1 T2 T3 T4 T5 Tn + 1 Tn + 2 Tn + 3 ( ( t t ) ) CL CK CLK ( ( t CH ) ) t t CKS CKH ( ( ) ) CKE ( ( ) ) t t CMS CMH ( ( ) ) COMMAND ACTIVE NOP WRITE NOP NOP NOP NOP BURST TERM NOP ( ( ) ) t t CMH CMS ( ( ) ) DQM 0-3 ( ( ) ) t t AS AH ( ( ) ) 1 ROW COLUMN m A0-A9, A11 ( ( ) ) t t AS AH ( ( ) ) ROW A10 ( ( ) ) t t AS AH ( ( ) ) BA0, BA1 BANK BANK ( ( ) ) t t t t t t t t t t DS DH DS DH DS DH DS DH DS DH ( ( ) ) DQ DIN m DIN m + 1 DIN m + 2 DIN m + 3 DIN m - 1 ( ( ) ) t RCD Full-page burst does 256 locations within same row not self-terminate. Can use BURST TERMINATE 2, 3 command to stop. Full page completed DON’T CARE Notes: 1. A8, A9, and A11 = “Don’t Care.” t 2. WR must be satisfied prior to PRECHARGE command. t 3. Page left open; no RP. PDF: 09005aef80872800/Source: 09005aef80863355 Micron Technology, Inc., reserves the right to change products or specifications without notice. 128MbSDRAMx32_2.fm - Rev. J 6/06 EN 63 ©2001 Micron Technology, Inc. All rights reserved. 128Mb: x32 SDRAM Timing Diagrams Figure 48: Write – DQM Operation T0 T1 T2 T3 T4 T5 T6 T7 t t CK CL CLK t CH t t CKS CKH CKE t t CMS CMH COMMAND ACTIVE NOP WRITE NOP NOP NOP NOP NOP t t CMS CMH DQM 0-3 t t AS AH A0-A9, A11 2 ROW COLUMN m t t AS AH ENABLE AUTO PRECHARGE ROW A10 t t DISABLE AUTO PRECHARGE AS AH BA0, BA1 BANK BANK t t t t t t DS DH DS DH DS DH DIN m DIN m + 2 DIN m + 3 DQ t RCD DON’T CARE Notes: 1. For this example, BL = 4. 2. A8, A9, and A11 = “Don’t Care.” PDF: 09005aef80872800/Source: 09005aef80863355 Micron Technology, Inc., reserves the right to change products or specifications without notice. 128MbSDRAMx32_2.fm - Rev. J 6/06 EN 64 ©2001 Micron Technology, Inc. All rights reserved. 128Mb: x32 SDRAM Package Dimensions Package Dimensions Figure 49: 86-Pin Plastic TSOP (400 mil) 22.22 ±0.08 0.61 SEE DETAIL A 0.50 2X 0.10 TYP +0.07 0.20 -0.03 2X 2.80 11.76 ±0.20 10.16 ±0.08 2X R 0.75 +0.03 PIN #1 ID 0.15 2X R 1.00 -0.02 0.25 GAGE PLANE 0.10 1.20 MAX +0.10 0.10 -0.05 PLATED LEAD FINISH: 0.50 ±0.10 TG (90% Sn, 10% Pb) OR P (100% Sn) 0.01 ±0.005 THICK PER SIDE 0.80 PLASTIC PACKAGE MATERIAL: EPOXY NOVOLAC TYP PACKAGE WIDTH AND LENGTH DO NOT INCLUDE DETAIL A MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.25 PER SIDE. Notes: 1. All dimensions are in millimeters. 2. Package width and length do not include mold protrusion; allowable mold protrusion is 0.25mm per side. 3. “2X” means the notch is present in two locations (both ends of the device). PDF: 09005aef80872800/Source: 09005aef80863355 Micron Technology, Inc., reserves the right to change products or specifications without notice. 128MbSDRAMx32_2.fm - Rev. J 6/06 EN 65 ©2001 Micron Technology, Inc. All rights reserved. 128Mb: x32 SDRAM Package Dimensions Figure 50: 90-Ball FBGA (8mm x 13mm) 0.65 ±0.05 SEATING PLANE SOLDER BALL MATERIAL: A 62% Sn, 36% Pb, 2% Ag OR 0.10 A 96.5% Sn, 3%Ag, 0.5% Cu SUBSTRATE MATERIAL: 90X Ø0.45 PLASTIC LAMINATE DIMENSIONS APPLY MOLD COMPOUND: TO SOLDER BALLS POST 6.40 EPOXY NOVOLAC REFLOW. THE PRE- 0.80 TYP REFLOW DIAMETER IS BALL A1 ID 0.42 ON A 0.40 SMD BALL PAD BALL A1 ID BALL A9 BALL A1 11.20 ±0.10 C L 13.00 ±0.10 5.60 ±0.05 6.50 ±0.05 C L 1.00 MAX 3.20 4.00 ±0.05 8.00 ±0.10 Notes: 1. 1. All dimensions in millimeters. 2. 2. Package width and length do not include mold protrusion; allowable mold protrusion is 0.25mm per side. 3. Recommended pad size for PCB is 0.33mm ±0.025mm. ® 8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900 prodmktg@micron.com www.micron.com Customer Comment Line: 800-932-4992 Micron, the M logo, and the Micron logo are trademarks of Micron Technology, Inc. All other trademarks are the property of their respective owners. This data sheet contains minimum and maximum limits specified over the complete power supply and temperature range for production devices. Although considered final, these specifications are subject to change, as further product development and data characterization sometimes occur. PDF: 09005aef80872800/Source: 09005aef80863355 Micron Technology, Inc., reserves the right to change products or specifications without notice. 128MbSDRAMx32_2.fm - Rev. J 6/06 EN 66 ©2001 Micron Technology, Inc. All rights reserved.