OBSOLETE 4, 8 MEG x 36 ECC-OPTIMIZED DRAM SIMMs MT9D436 X DRAM MT18D836 X For the latest data sheet revisions, please refer to the Micron Web site: www.micron.com/mti/msp/html/datasheet.html MODULE FEATURES PIN ASSIGNMENT (Front View) • Four-CAS#, ECC-optimized configuration in a 72-pin, single in-line memory module (SIMM) 72-Pin SIMM • 16MB (4 Meg x 36) and 32MB (8 Meg x 36) 4 Meg x 36 (shown) • High-performance CMOS silicon-gate process 8 Meg x 36 • Single 5V ±10% power supply • All inputs, outputs and clocks are TTL-compatible • Refresh modes: RAS#-ONLY, CAS#-BEFORE-RAS# (CBR) and HIDDEN • 2,048-cycle refresh distributed across 32ms • Extended Data-Out (EDO) PAGE MODE access 13637 72 PIN SYMBOL PIN SYMBOL PIN SYMBOL PIN SYMBOL OPTIONS MARKING 1VSS 19 A10 37 DQ18 55 DQ13 • Timing 2 DQ1 20 DQ5 38 DQ36 56 DQ31 50ns access -5 3 DQ19 21 DQ23 39 VSS 57 DQ14 60ns access -6 4 DQ2 22 DQ6 40 CAS0# 58 DQ32 5 DQ20 23 DQ24 41 CAS2# 59 VDD • Package 6 DQ3 24 DQ7 42 CAS3# 60 DQ33 72-pin SIMM M 7 DQ21 25 DQ25 43 CAS1# 61 DQ15 8 DQ4 26 DQ8 44 RAS0# 62 DQ34 9 DQ22 27 DQ26 45 NC/RAS1#* 63 DQ16 KEY TIMING PARAMETERS 10 VDD 28 A7 46 NC 64 DQ35 11 NC 29 NC (A11) 47 WE# 65 DQ17 t t t t t t SPEED RC RAC PC AA CAC CAS 12 A0 30 VDD 48 NC 66 NC -5 84ns 50ns 20ns 25ns 13ns 8ns 13 A1 31 A8 49 DQ10 67 PRD1 -6 104ns 60ns 25ns 30ns 15ns 10ns 14 A2 32 A9 50 DQ28 68 PRD2 15 A3 33 NC/RAS3#* 51 DQ11 69 PRD3 16 A4 34 RAS2# 52 DQ29 70 PRD4 PART NUMBERS 17 A5 35 DQ27 53 DQ12 71 NC 18 A6 36 DQ9 54 DQ30 72 VSS PART NUMBER CONFIGURATION FEATURES MODE *32MB version only NOTE: Symbols in parentheses are not used on these modules but may be used MT9D436M-x X 4 Meg x 36 4 CAS#, ECC EDO for other modules in this product family. They are for reference only. MT18D836M-x X 8 Meg x 36 4 CAS#, ECC EDO x = speed occurs when WE# goes LOW prior to CAS# going LOW, and the output pin(s) remain open (High-Z) until the next GENERAL DESCRIPTION CAS# cycle. The MT9D436 X and MT18D836 X are randomly ac- cessed, 16MB and 32MB solid-state memories organized in EDO PAGE MODE a x36 configuration. These modules are designed for sys- tems that utilize ECC and do not conduct single-byte ac- EDO PAGE MODE is an accelerated FAST-PAGE-MODE cesses. These modules do not support parity functionality. cycle. The primary advantage of EDO is the availability of During READ or WRITE cycles, each bit is uniquely data-out even after CAS# goes back HIGH. EDO provides t addressed through 20 address bits that are entered 10 bits for CAS# precharge time ( CP) to occur without the output (A0 -A9) at a time. RAS# is used to latch the first 10 bits and data going invalid. This elimination of CAS# output control CAS# the latter 10 bits. READ or WRITE cycles are selected provides for pipelined READs. with the WE# input. A logic HIGH on WE# dictates read FAST-PAGE-MODE modules have traditionally turned mode, while a logic LOW on WE# dictates write mode. the output buffers off (High-Z) with the rising edge of During a WRITE cycle, data-in (D) is latched by the falling CAS#. EDO operates like FAST-PAGE-MODE READs, ex- edge of WE# or CAS#, whichever occurs last. EARLY WRITE cept data will be held valid or become valid after CAS# goes 4, 8 Meg x 36 ECC-Optimized DRAM SIMMs Micron Technology, Inc., reserves the right to change products or specifications without notice. DM65.p65 – Rev. 9/98 1 1998, Micron Technology, Inc. Micron is a registered trademark of Micron Technology, Inc. OBSOLETE 4, 8 MEG x 36 ECC-OPTIMIZED DRAM SIMMs EDO PAGE MODE (continued) HIGH, as long as RAS# is held LOW. (Refer to the the RAS# HIGH time. Memory cell data is retained in its MT4C4M4E8 DRAM data sheet for additional information correct state by maintaining power and executing any on EDO functionality.) RAS# cycle (READ, WRITE) or RAS# REFRESH cycle (RAS# ONLY, CBR or HIDDEN) so that all 2,048 combinations of RAS# addresses are executed at least every 32ms, regard- REFRESH less of sequence. The CBR REFRESH cycle will invoke the Returning RAS# and CAS# HIGH terminates a memory refresh counter for automatic RAS# addressing. cycle and decreases chip current to a reduced standby level. Also, the chip is preconditioned for the next cycle during JEDEC-DEFINED JEDEC-DEFINED PRESENCE-DETECT – MT9D436 (16MB) PRESENCE-DETECT – MT18D836 (32MB) SYMBOL PIN -5 -6 SYMBOL PIN -5 -6 PRD1 67 Vss Vss PRD1 67 NC NC PRD2 68 NC NC PRD2 68 Vss Vss PRD3 69 Vss NC PRD3 69 Vss NC PRD4 70 Vss NC PRD4 70 Vss NC 4, 8 Meg x 36 ECC-Optimized DRAM SIMMs Micron Technology, Inc., reserves the right to change products or specifications without notice. DM65.p65 – Rev. 9/98 2 1998, Micron Technology, Inc. OBSOLETE 4, 8 MEG x 36 ECC-OPTIMIZED DRAM SIMMs FUNCTIONAL BLOCK DIAGRAM MT9D436 (16MB) DQ1 DQ8 DQ9, 18, 27, 36 DQ10 DQ17 DQ1 - 4 DQ1 - 4 DQ1 - 4 DQ1 - 4 DQ1 - 4 WE# WE# WE# WE# WE# U1 U2 U5 U3 U4 CAS0# CAS# CAS# CAS# CAS# CAS# RAS0# RAS# RAS# RAS# RAS# RAS# A0–A10 A0–A10 A0–A10 A0–A10 A0–A10 OE# OE# OE# OE# OE# 11 11 11 11 11 CAS1# WE# DQ19 DQ26 DQ28 DQ35 DQ1 - 4 DQ1 - 4 DQ1 - 4 DQ1 - 4 WE# WE# WE# WE# U6 U7 U3 U8 U9 CAS2# CAS# CAS# CAS# CAS# RAS2# RAS# RAS# RAS# RAS# OE# A0–A10 OE# A0–A10 OE# A0–A10 OE# A0–A10 11 11 11 11 CAS3# A0–A10 VDD U1-U9 U1-U9 = 4 Meg x 4 DRAMs VSS U1-U9 4, 8 Meg x 36 ECC-Optimized DRAM SIMMs Micron Technology, Inc., reserves the right to change products or specifications without notice. DM65.p65 – Rev. 9/98 3 1998, Micron Technology, Inc. OBSOLETE 4, 8 MEG x 36 ECC-OPTIMIZED DRAM SIMMs FUNCTIONAL BLOCK DIAGRAM MT18D836 (32MB) DQ1 DQ8 DQ9, 18, 27, 36 DQ10 DQ17 DQ1 - 4 DQ1 - 4 DQ1 - 4 DQ1 - 4 DQ1 - 4 WE# WE# WE# WE# WE# U1 U2 U3 U4 U5 CAS0# CAS# CAS# CAS# CAS# CAS# RAS0# RAS# RAS# RAS# RAS# RAS# OE# A0–A10 OE# A0–A10 OE# A0–A10 OE# A0–A10 OE# A0–A10 11 11 11 11 11 CAS1# WE# DQ19 DQ26 DQ28 DQ35 DQ1 - 4 DQ1 - 4 DQ1 - 4 DQ1 - 4 WE# WE# WE# WE# U6 U7 U8 U9 CAS2# CAS# CAS# CAS# CAS# RAS2# RAS# RAS# RAS# RAS# OE# A0–A10 OE# A0–A10 OE# A0–A10 OE# A0–A10 11 11 11 11 CAS3# A0–A10 DQ8 DQ1 DQ9, 18, 27, 36 DQ10 DQ17 DQ1 - 4 DQ1 - 4 DQ1 - 4 DQ1 - 4 DQ1 - 4 WE# WE# WE# WE# WE# U10 U11 U14 U12 U13 CAS# CAS# CAS# CAS# CAS# RAS# RAS# RAS# RAS# RAS# RAS1# OE# A0–A10 OE# A0–A10 OE# A0–A10 OE# A0–A10 OE# A0–A10 11 11 11 11 11 DQ19 DQ26 DQ28 DQ35 DQ1 - 4 DQ1 - 4 DQ1 - 4 DQ1 - 4 WE# WE# WE# WE# CAS# U15 CAS# U16 CAS# U17 CAS# U18 RAS3# RAS# RAS# RAS# RAS# OE# A0–A10 OE# A0–A10 OE# A0–A10 OE# A0–A10 11 11 11 11 U1-U18 = 4 Meg x 4 DRAMs VDD U1-U18 VSS U1-U18 4, 8 Meg x 36 ECC-Optimized DRAM SIMMs Micron Technology, Inc., reserves the right to change products or specifications without notice. DM65.p65 – Rev. 9/98 4 1998, Micron Technology, Inc. OBSOLETE 4, 8 MEG x 36 ECC-OPTIMIZED DRAM SIMMs *Stresses greater than those listed under “Absolute Maxi- ABSOLUTE MAXIMUM RATINGS* mum Ratings” may cause permanent damage to the device. Voltage on VDD Supply Relative to VSS ............. -1V to +7V This is a stress rating only, and functional operation of the Operating Temperature, T (ambient) .......... 0°C to +70°C A device at these or any other conditions above those indi- Storage Temperature (plastic) .................... -55°C to +125°C cated in the operational sections of this specification is not Power Dissipation ............................................................. 9W implied. Exposure to absolute maximum rating conditions Short Circuit Output Current ..................................... 50mA for extended periods may affect reliability. DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS (Notes: 1, 5, 6) (VDD = +5V ±10%) PARAMETER/CONDITION SYMBOL MIN MAX UNITS NOTES SUPPLY VOLTAGE VDD 4.5 5.5 V INPUT HIGH VOLTAGE: Logic 1; All inputs VIH 2.4 VDD + 1 V INPUT LOW VOLTAGE: Logic 0; All inputs VIL -1.0 0.8 V INPUT LEAKAGE CURRENT: CAS0#-CAS3# II1 -12 12 μA22 Any input 0V ≤ VIN ≤ 5.5V A0-A10, WE# II2 -36 36 μA22 (All other pins not under test = 0V) RAS0#-RAS3# II3 -10 10 μA OUTPUT LEAKAGE CURRENT: DQ1-DQ36 IOZ -10 10 μA22 (DQ is disabled; 0V ≤ VOUT ≤ 5.5V) OUTPUT LEVELS: VOH 2.4 – V Output High Voltage (IOUT = -5mA) Output Low Voltage (IOUT = 4.2mA) VOL – 0.4 V Icc SPECIFICATIONS AND CONDITIONS (Notes: 1, 5, 6) (VDD = +5V ±10%) MAX PARAMETER/CONDITION SYMBOL SIZE -5 -6 UNITS NOTES STANDBY CURRENT: (TTL) ICC1 16MB 9 9 mA (RAS# = CAS# = VIH) 32MB 18 18 STANDBY CURRENT: (CMOS) ICC2 16MB 5 5 mA (RAS# = CAS# = Other Inputs = VDD - 0.2V) 32MB 9 9 OPERATING CURRENT: Random READ/WRITE 16MB 1,260 1,170 mA 3, 21 Average power supply current ICC3 32MB 1,269 1,179 t t (RAS#, CAS#, address cycling: RC = RC [MIN]) OPERATING CURRENT: EDO PAGE MODE 16MB 990 900 mA 3, 21 Average power supply current ICC4 32MB 999 909 t t (RAS# = VIL, CAS#, address cycling: PC = PC [MIN]) REFRESH CURRENT: RAS#-ONLY 16MB 1,260 1,170 mA 3, 21 Average power supply current ICC5 32MB 1,269 1,179 t t (RAS# cycling, CAS# = VIH: RC = RC [MIN]) REFRESH CURRENT: CBR 16MB 1,260 1,170 mA 3, 4 CC6 Average power supply current I 32MB 1,269 1,179 t t (RAS#, CAS#, address cycling; RC = RC [MIN]) 4, 8 Meg x 36 ECC-Optimized DRAM SIMMs Micron Technology, Inc., reserves the right to change products or specifications without notice. DM65.p65 – Rev. 9/98 5 1998, Micron Technology, Inc. OBSOLETE 4, 8 MEG x 36 ECC-OPTIMIZED DRAM SIMMs CAPACITANCE MAX PARAMETER SYMBOL 16MB 32MB UNITS NOTES Input Capacitance: A0-A10 CI1 52 105 pF 2 Input Capacitance: WE# CI2 70 140 pF 2 Input Capacitance: RAS0#-RAS3# CI3 42 42 pF 2 Input Capacitance: CAS0#-CAS3# CI4 25 50 pF 2 Input/Output Capacitance: DQ1-DQ36 CIO 10 18 pF 2 AC ELECTRICAL CHARACTERISTICS (Notes: 5, 6, 7, 8, 9, 10, 11, 12) (VDD = +5V ±10%) AC CHARACTERISTICS -5 -6 PARAMETER SYMBOL MIN MAX MIN MAX UNITS NOTES t Access time from column address AA 25 30 ns t Column-address setup to CAS# precharge during WRITE ACH 12 15 ns t Column-address hold time (referenced to RAS#) AR 38 45 ns t Column-address setup time ASC 0 0 ns t Row-address setup time ASR 0 0 ns t Access time from CAS# CAC 13 15 ns t Column-address hold time CAH 8 10 ns t CAS# pulse width CAS 8 10,000 10 10,000 ns t CAS# hold time (CBR Refresh) CHR 8 10 ns 4 t CAS# to output in Low-Z CLZ 0 0 ns t Data output hold after next CAS# LOW COH 3 3 ns t CAS# precharge time CP 8 10 ns 13 t Access time from CAS# precharge CPA 28 35 ns t CAS# to RAS# precharge time CRP 5 5 ns t CAS# hold time CSH 38 45 ns t CAS# setup time (CBR Refresh) CSR 5 5 ns 4 t WRITE command to CAS# lead time CWL 8 10 ns t Data-in hold time DH 8 10 ns 18 t Data-in setup time DS 0 0 ns 18 t Output buffer turn-off delay OFF 0 12 0 15 ns 17 t EDO-PAGE-MODE READ or WRITE cycle time PC 20 25 ns t Access time from RAS# RAC 50 60 ns t RAS# to column-address delay time RAD 9 12 ns 15 t Row-address hold time RAH 9 10 ns t RAS# pulse width RAS 50 10,000 60 10,000 ns t RAS# pulse width (EDO PAGE MODE) RASP 50 125,000 60 125,000 ns t Random READ or WRITE cycle time RC 84 104 ns t RAS# to CAS# delay time RCD 11 14 ns 14 t READ command hold time (referenced to CAS#) RCH 0 0 ns 16 t READ command setup time RCS 0 0 ns t Refresh period (2,048 cycles) REF 32 32 ms 4, 8 Meg x 36 ECC-Optimized DRAM SIMMs Micron Technology, Inc., reserves the right to change products or specifications without notice. DM65.p65 – Rev. 9/98 6 1998, Micron Technology, Inc. OBSOLETE 4, 8 MEG x 36 ECC-OPTIMIZED DRAM SIMMs AC ELECTRICAL CHARACTERISTICS (Notes: 5, 6, 7, 8, 9, 10, 11, 12) (VDD = +5V ±10%) AC CHARACTERISTICS -5 -6 PARAMETER SYMBOL MIN MAX MIN MAX UNITS NOTES t RAS# precharge time RP 30 40 ns t RAS# to CAS# precharge time RPC 5 5 ns t READ command hold time (referenced to RAS#) RRH 0 0 ns 16 t RAS# hold time RSH 13 15 ns t WRITE command to RAS# lead time RWL 13 15 ns t Transition time (rise or fall) T2 50 2 50 ns t WRITE command hold time WCH 8 10 ns t WRITE command hold time (referenced to RAS#) WCR 38 45 ns t WE# command setup time WCS 0 0 ns t Output disable delay from WE# (CAS# HIGH) WHZ 0 12 0 15 ns t WRITE command pulse width WP 5 5 ns t WE# pulse width for output disable when CAS# HIGH WPZ 10 10 ns t WE# hold time (CBR Refresh) WRH 8 10 ns t WE# setup time (CBR Refresh) WRP 8 10 ns 4, 8 Meg x 36 ECC-Optimized DRAM SIMMs Micron Technology, Inc., reserves the right to change products or specifications without notice. DM65.p65 – Rev. 9/98 7 1998, Micron Technology, Inc. OBSOLETE 4, 8 MEG x 36 ECC-OPTIMIZED DRAM SIMMs NOTES 1. All voltages referenced to VSS. cycle and clear the data-out buffer, CAS# must be t 2. This parameter is sampled. Capacitance is measured CP. pulsed HIGH for t t using MIL-STD-883C, Method 3012.1 (1 MHz AC, 14. The RCD (MAX) limit is no longer specified. RCD VDD = 4.5V, DC bias = 2.4V at 15mV RMS). (MAX) was specified as a reference point only. If t t 3. ICC is dependent on output loading and cycle rates. RCD was greater than the specified RCD (MAX) Specified values are obtained with minimum cycle limit, then access time was controlled exclusively by t t time and the outputs open. CAC ( RAC [MIN] no longer applied). With or t t t 4. Enables on-chip refresh and address counters. without the RCD (MAX) limit, AA and CAC must 5. The minimum specifications are used only to indicate always be met. t t cycle time at which proper operation over the full 15. The RAD (MAX) limit is no longer specified. RAD temperature range is ensured. (MAX) was specified as a reference point only. If t t 6. An initial pause of 100μs is required after power-up, RAD was greater than the specified RAD (MAX) followed by eight RAS# refresh cycles (RAS#-ONLY limit, then access time was controlled exclusively by t t t or CBR with WE# HIGH), before proper device AA ( RAC and CAC no longer applied). With or t t t t operation is ensured. The eight RAS# cycle wake-ups without the RAD (MAX) limit, AA, RAC and CAC t should be repeated any time the REF refresh must always be met. t t requirement is exceeded. 16. Either RCH or RRH must be satisfied for a READ t 7. AC characteristics assume T = 2.5ns. cycle. t 8. VIH (MIN) and VIL (MAX) are reference levels for 17. OFF (MAX) defines the time at which the output measuring timing of input signals. Transition times achieves the open circuit condition and is not are measured between VIH and VIL (or between VIL referenced to VOH or VOL. and VIH). 18. These parameters are referenced to CAS# leading 9. In addition to meeting the transition rate specifica- edge in EARLY WRITE cycles. tion, all input signals must transit between VIH and 19. OE# is tied permanently LOW; LATE WRITE or VIL (or between VIL and VIH) in a monotonic manner. READ-MODIFY-WRITE operations are not permis- 10. If CAS# = V IH, data output is High-Z. sible and should not be attempted. 11. If CAS# = V IL, data output may contain data from the 20. A HIDDEN REFRESH may also be performed after last valid READ cycle. a WRITE cycle. In this case, WE# = LOW and 12. Measured with a load equivalent to two TTL gates OE# = HIGH. and 100pF, and VOL = 0.8V and VOH = 2V. 21. Column address changed once each cycle. 13. If CAS# is LOW at the falling edge of RAS#, Q will be 22. 16MB module values will be half of those shown. maintained from the previous cycle. To initiate a new 4, 8 Meg x 36 ECC-Optimized DRAM SIMMs Micron Technology, Inc., reserves the right to change products or specifications without notice. DM65.p65 – Rev. 9/98 8 1998, Micron Technology, Inc. OBSOLETE 4, 8 MEG x 36 ECC-OPTIMIZED DRAM SIMMs READ CYCLE t RC t t RAS RP V IH RAS# V IL t CSH t t RSH RRH t t t RCD CAS CRP V CAS# IH V IL t AR t t t RAD ASC CAH t t t ASR RAH ACH V IH ROW COLUMN ROW ADDR V IL t tRCH RCS V WE# IH V IL tAA t RAC NOTE 1 t t CAC OFF t CLZ V OH DQ OPEN OPEN VALID DATAV OL DON’T CARE UNDEFINED TIMING PARAMETERS -5 -6 -5 -6 SYMBOL MIN MAX MIN MAX UNITS SYMBOL MIN MAX MIN MAX UNITS t t AA 25 30 ns RAC 50 60 ns t t AR 38 45 ns RAD 9 12 ns t t ASC 0 0 ns RAH 9 10 ns t t ASR 0 0 ns RAS 50 10,000 60 10,000 ns t t CAC 13 15 ns RC 84 104 ns t t CAH 8 10 ns RCD 11 14 ns t t CAS 8 10,000 10 10,000 ns RCH 0 0 ns t t CLZ 0 0 ns RCS 0 0 ns t t CRP 5 5 ns RP 30 40 ns t t CSH 38 45 ns RRH 0 0 ns t t OFF 0 12 0 15 ns RSH 13 15 ns t NOTE: 1. OFF is referenced from rising edge of RAS# or CAS#, whichever occurs last. 4, 8 Meg x 36 ECC-Optimized DRAM SIMMs Micron Technology, Inc., reserves the right to change products or specifications without notice. DM65.p65 – Rev. 9/98 9 1998, Micron Technology, Inc. OBSOLETE 4, 8 MEG x 36 ECC-OPTIMIZED DRAM SIMMs EARLY WRITE CYCLE t RC t t RAS RP V IH RAS# V IL t CSH t RSH t t t CRP RCD CAS CAS# V IH V IL t AR t t t RAD ASC CAH t t t ASR RAHACH VIH ADDR ROW COLUMN ROW V IL tCWL t RWL t WCR t t WCS WCH t WP WE#V IH V IL t tDS DH V IOHDQ VALID DATA V IOL DON’T CARE UNDEFINED TIMING PARAMETERS -5 -6 -5 -6 SYMBOL MIN MAX MIN MAX UNITS SYMBOL MIN MAX MIN MAX UNITS t t ACH 12 15 ns RAH 9 10 ns t t AR 38 45 ns RAS 50 10,000 60 10,000 ns t t ASC 0 0 ns RC 84 104 ns t t ASR 0 0 ns RCD 11 14 ns t t CAH 8 10 ns RP 30 40 ns t t CAS 8 10,000 10 10,000 ns RSH 13 15 ns t t CRP 5 5 ns RWL 13 15 ns t t CSH 38 45 ns WCH 8 10 ns t t CWL 8 10 ns WCR 38 45 ns t t DH 8 10 ns WCS 0 0 ns t t DS 0 0 ns WP 5 5 ns t RAD 9 12 ns 4, 8 Meg x 36 ECC-Optimized DRAM SIMMs Micron Technology, Inc., reserves the right to change products or specifications without notice. DM65.p65 – Rev. 9/98 10 1998, Micron Technology, Inc. OBSOLETE 4, 8 MEG x 36 ECC-OPTIMIZED DRAM SIMMs EDO-PAGE-MODE READ CYCLE t t RASP RP V IH RAS# V IL t t t CSH PC RSH t t t t t t t t CRP RCD CAS CP CAS CP CAS CP V CAS# IH V IL t AR t t t t RAD ACH ACH ACH t t t t t t t t ASR RAH ASCCAH ASC CAH ASC CAH V IH ADDR V ROW COLUMN COLUMN COLUMN ROW IL t t RCH RCS VWE#IH V t IL t RRH AA t t t AA AA CPA t t t RAC CPACAC t t t CAC CAC CLZ t OFF t COH t CLZ V OH VALID VALID VALID DQ OPEN OPEN V OL DATA DATA DATA DON’T CARE UNDEFINED TIMING PARAMETERS -5 -6 -5 -6 SYMBOL MIN MAX MIN MAX UNITS SYMBOL MIN MAX MIN MAX UNITS t t AA 25 30 ns CSH 38 45 ns t t ACH 12 15 ns OFF 0 12 0 15 ns t t AR 38 45 ns PC 20 25 ns t t ASC 0 0 ns RAC 50 60 ns t t ASR 0 0 ns RAD 9 12 ns t t CAC 13 15 ns RAH 9 10 ns t t CAH 8 10 ns RASP 50 125,000 60 125,000 ns t t CAS 8 10,000 10 10,000 ns RCD 11 14 ns t t CLZ 0 0 ns RCH 0 0 ns t t COH 3 3 ns RCS 0 0 ns t t CP 8 10 ns RP 30 40 ns t t CPA 28 35 ns RRH 0 0 ns t t CRP 5 5 ns RSH 13 15 ns 4, 8 Meg x 36 ECC-Optimized DRAM SIMMs Micron Technology, Inc., reserves the right to change products or specifications without notice. DM65.p65 – Rev. 9/98 11 1998, Micron Technology, Inc. OBSOLETE 4, 8 MEG x 36 ECC-OPTIMIZED DRAM SIMMs EDO-PAGE-MODE EARLY-WRITE CYCLE t t RASP RP V IH RAS# V IL t t t CSH PC RSH t t t t t t t t CRP RCD CAS CP CAS CP CAS CP V IH CAS# V IL t t AR ACH t t t RAD ACH ACH t t t t t t t t ASR RAH ASC CAH ASC CAH ASC CAH V IH ADDR V ROW COLUMNCOLUMN COLUMN ROW IL t t t CWL CWL CWL t t t t t tWCS WCH WCS WCH WCS WCH t t tWP WP WP V IH WE# V IL t t WCR RWL t t t t t tDS DH DS DH DS DH V IOH DQ VVALID DATA VALID DATA VALID DATA IOL DON’T CARE UNDEFINED TIMING PARAMETERS -5 -6 -5 -6 SYMBOL MIN MAX MIN MAX UNITS SYMBOL MIN MAX MIN MAX UNITS t t ACH 12 15 ns PC 20 25 ns t t AR 38 45 ns RAD 9 12 ns t t RAH 9 10 ns ASC 0 0 ns t t ASR 0 0 ns RASP 50 125,000 60 125,000 ns t t CAH 8 10 ns RCD 11 14 ns t t CAS 8 10,000 10 10,000 ns RP 30 40 ns t t CP 8 10 ns RSH 13 15 ns t t RWL 13 15 ns CRP 5 5 ns t t CSH 38 45 ns WCH 8 10 ns t t CWL 8 10 ns WCR 38 45 ns t t DH 8 10 ns WCS 0 0 ns t t DS 0 0 ns WP 5 5 ns 4, 8 Meg x 36 ECC-Optimized DRAM SIMMs Micron Technology, Inc., reserves the right to change products or specifications without notice. DM65.p65 – Rev. 9/98 12 1998, Micron Technology, Inc. OBSOLETE 4, 8 MEG x 36 ECC-OPTIMIZED DRAM SIMMs EDO-PAGE-MODE READ-EARLY-WRITE CYCLE (Pseudo READ-MODIFY-WRITE) t t RP RASP V IH RAS# V IL t CSH t t t PC PC RSH t t t t t t t t CRP RCD CAS CP CAS CP CAS CP V IH CAS# V IL t AR t t RAD ACH t t t t t t t t ASR RAH ASC CAH ASC CAH ASC CAH VIH ADDR ROW COLUMN (A)COLUMN (B) ROW COLUMN (N) V IL tRCHt RCS t t WCS WCH V IH WE# V IL t AA t AA t CPA t RAC t t t t CAC DS DH CAC t t COH WHZ V DQ IOH VALID VALID DATA OPEN VALID DATA (A) V IOL DATA (B) IN DON’T CARE UNDEFINED TIMING PARAMETERS -5 -6 -5 -6 SYMBOL MIN MAX MIN MAX UNITS SYMBOL MIN MAX MIN MAX UNITS t t AA 25 30 ns DS 0 0 ns t t ACH 12 15 ns PC 20 25 ns t t AR 38 45 ns RAC 50 60 ns t t RAD 9 12 ns ASC 0 0 ns t t ASR 0 0 ns RAH 9 10 ns t t CAC 13 15 ns RASP 50 125,000 60 125,000 ns t t CAH 8 10 ns RCD 11 14 ns t t CAS 8 10,000 10 10,000 ns RCH 0 0 ns t t RCS 0 0 ns COH 3 3 ns t t CP 8 10 ns RP 30 40 ns t t CPA 28 35 ns RSH 13 15 ns t t CRP 5 5 ns WCH 8 10 ns t t CSH 38 45 ns WCS 0 0 ns t t WHZ 0 12 0 15 ns DH 8 10 ns 4, 8 Meg x 36 ECC-Optimized DRAM SIMMs Micron Technology, Inc., reserves the right to change products or specifications without notice. DM65.p65 – Rev. 9/98 13 1998, Micron Technology, Inc. OBSOLETE 4, 8 MEG x 36 ECC-OPTIMIZED DRAM SIMMs EDO READ CYCLE (with WE#-controlled disable) V IH RAS# V IL t CSH t t t t CRP RCD CAS CP V CAS# IH V IL t AR t RAD t t t t t ASR RAHASC CAH ASC V IH ROW COLUMN COLUMN ADDR V IL t t t t RCH WPZ RCS RCS V WE# IH V IL tAA t RAC t CAC t t t WHZ CLZ CLZ V OH DQ OPEN VALID DATA OPEN V OL DON’T CARE UNDEFINED TIMING PARAMETERS -5 -6 -5 -6 SYMBOL MIN MAX MIN MAX UNITS SYMBOL MIN MAX MIN MAX UNITS t t AA 25 30 ns CSH 38 45 ns t t AR 38 45 ns RAC 50 60 ns t t ASC 0 0 ns RAD 9 12 ns t t ASR 0 0 ns RAH 9 10 ns t t CAC 13 15 ns RCD 11 14 ns t t CAH 8 10 ns RCH 0 0 ns t t CAS 8 10,000 10 10,000 ns RCS 0 0 ns t t CLZ 0 0 ns WHZ 0 12 0 15 ns t t CP 8 10 ns WPZ 10 10 ns t CRP 5 5 ns 4, 8 Meg x 36 ECC-Optimized DRAM SIMMs Micron Technology, Inc., reserves the right to change products or specifications without notice. DM65.p65 – Rev. 9/98 14 1998, Micron Technology, Inc. OBSOLETE 4, 8 MEG x 36 ECC-OPTIMIZED DRAM SIMMs RAS#-ONLY REFRESH CYCLE t RC t t RAS RP V IH RAS# V IL t t CRP RPC V IH CAS# V IL t t ASR RAH VIH ADDR ROW ROW VIL V OH DQ OPEN VOL V IH WE# V IL CBR REFRESH CYCLE (Addresses = DON’T CARE) t t t t RP RAS NOTE 1 RP RAS V IH RAS# V IL t RPC t t t t RPC t t CP CSR CHR CSR CHR V IH CAS# V IL V OH OPEN DQ V OL t t t tWRP WRH WRP WRH V IH WE# V IL DON’T CARE UNDEFINED TIMING PARAMETERS -5 -6 -5 -6 SYMBOL MIN MAX MIN MAX UNITS SYMBOL MIN MAX MIN MAX UNITS t t ASR 0 0 ns RAS 50 10,000 60 10,000 ns t t CHR 8 10 ns RC 84 104 ns t t CP 8 10 ns RP 30 40 ns t t CRP 5 5 ns RPC 5 5 ns t t CSR 5 5 ns WRH 8 10 ns t t RAH 9 10 ns WRP 8 10 ns 4, 8 Meg x 36 ECC-Optimized DRAM SIMMs Micron Technology, Inc., reserves the right to change products or specifications without notice. DM65.p65 – Rev. 9/98 15 1998, Micron Technology, Inc. OBSOLETE 4, 8 MEG x 36 ECC-OPTIMIZED DRAM SIMMs 20 HIDDEN REFRESH CYCLE (WE# = HIGH) t t t RAS RP RAS V IH RAS# V IL t t t CRP RCD RSH t CHR CAS# V IH V IL t AR t RAD t t t tASR RAH ASC CAH V IH ADDR ROW COLUMN V IL tAA t RAC t t OFF CAC t CLZ VOH DQ OPEN VALID DATA OPEN V OL DON’T CARE UNDEFINED TIMING PARAMETERS -5 -6 -5 -6 SYMBOL MIN MAX MIN MAX UNITS SYMBOL MIN MAX MIN MAX UNITS t t AA 25 30 ns OFF 0 12 0 15 ns t t AR 38 45 ns RAC 50 60 ns t t ASC 0 0 ns RAD 9 12 ns t t ASR 0 0 ns RAH 9 10 ns t t CAC 13 15 ns RAS 50 10,000 60 10,000 ns t t CAH 8 10 ns RCD 11 14 ns t t CHR 8 10 ns RP 30 40 ns t t CLZ 0 0 ns RSH 13 15 ns t CRP 5 5 ns 4, 8 Meg x 36 ECC-Optimized DRAM SIMMs Micron Technology, Inc., reserves the right to change products or specifications without notice. DM65.p65 – Rev. 9/98 16 1998, Micron Technology, Inc. OBSOLETE 4, 8 MEG x 36 ECC-OPTIMIZED DRAM SIMMs 72-Pin SIMM (16MB) 4.260 (108.20) .200 (5.08) 4.240 (107.70) MAX .133 (3.38) TYP .125 (3.18) 1.010 (25.65) TYP .990 (25.15) .400 (10.16) TYP .250 (6.35) .054 (1.37) .235 (5.97) .047 (1.19) 1.75 (44.45) TYP MIN .080 (2.03) PIN 1 .250 (6.35) .050 (1.27) .040 (1.02) TYP TYP 3.75 (95.25) 72-Pin SIMM (32MB) 4.260 (108.20) .350 (8.98) 4.240 (107.70) MAX .133 (3.38) TYP .125 (3.18) 1.010 (25.65) TYP .990 (25.15) .400 (10.16) TYP .250 (6.35) .054 (1.37) 1.75 (44.45) TYP .235 (5.97) .047 (1.19) MIN .080 (2.03) PIN 1 .250 (6.35) .050 (1.27) .040 (1.02) TYP TYP 3.75 (95.25) MAX NOTE: 1. All dimensions in inches (millimeters) or typical where noted. MIN 8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900 E-mail: prodmktg@micron.com, Internet: http://www.micron.com, Customer Comment Line: 800-932-4992 Micron is a registered trademark of Micron Technology, Inc. 4, 8 Meg x 36 ECC-Optimized DRAM SIMMs Micron Technology, Inc., reserves the right to change products or specifications without notice. DM65.p65 – Rev. 9/98 17 1998, Micron Technology, Inc.