256MB, 512MB (x64, DR) 144-PIN SDRAM SODIMM MT16LSDF3264(L)H – 256MB SMALL-OUTLINE MT16LSDF6464(L)H – 512MB ® SDRAM MODULE For the latest data sheet, please refer to the Micron Web site: www.micron.com/products/modules Features Figure 1: 144-Pin SODIMM (MO-190) • PC100- and PC133-compliant, 144-pin, small- PCB height: 1.25in (31.75mm) outline, dual in-line memory module (SODIMM) Utilizes 100 MHz and 133 MHz SDRAM components Unbuffered 256MB (32 Meg x 64) and 512MB (64 Meg x 64) Single +3.3V power supply Fully synchronous; all signals registered on positive edge of system clock Internal pipelined operat ion; column address can be changed every clock cycle Internal SDRAM banks for hiding row access/ precharge Programmable burst lengths: 1, 2, 4, 8, or full page Auto precharge and auto refresh modes Options MarkingSelf refresh mode: standard and low-power 256MB module: 64ms, 4,096-cycle refresh (15.625µs Self refresh current refresh interval); 512MB: 64ms, 8,192-cycle refresh Standard None 1 (7.81µs refresh interval) Low power L LVTTL-compatible inputs and outputs Package Serial presence-detect (SPD) 144-pin SODIMM (standard) G 1 Gold edge connectors 144-pin SODIMM (lead-free) Y Memory Clock/CL Table 1: Timing Parameters 7.5ns (133 MHz)/CL = 2 -13E CL = CAS (READ) latency 7.5ns (133 MHz)/CL = 3 -133 10ns (100 MHz)/CL = 2 -10E ACCESS TIME PCB MODULE CLOCK SETUP HOLD MARKING FREQUENCY CL = 2 CL = 3 TIME TIME Height 1.25in (31.75mm) See page 2 note -13E 133 MHz 5.4ns – 1.5ns 0.8ns NOTE: 1. Contact Micron for product availability. -133 133 MHz – 5.4ns 1.5ns 0.8ns -10E 100 MHz 6ns – 2ns 1ns Table 2: Address Table 256MB 512MB 4K 8K Refresh count Device banks 4 (BA0, BA1) 4 (BA0, BA1) Device configuration 128Mb (16 Meg x 8) 256Mb (32 Meg x 8) Row addressing 4K (A0–A11) 8K (A0–A12) Column addressing 1K (A0–A9) 1K (A0–A9) 2 (S0#, S1#) 2 (S0#, S1#)) Module ranks pdf: 09005aef807924d2, source: 09005aef807924f1 SDF16C32_64x64HG.fm - Rev. E 4/06 EN 1 ©2006 Micron Technology, Inc. All rights reserved. PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE. 256MB, 512MB (x64, DR) 144-PIN SDRAM SODIMM Table 3: Part Numbers SYSTEM PART NUMBER MODULE DENSITY CONFIGURATION BUS SPEED 256MB 32 Meg x 64 133 MHz MT16LSDF3264(L)HG-13E_ MT16LSDF3264(L)HY-13E_ 256MB 32 Meg x 64 133 MHz MT16LSDF3264(L)HG-133_ 256MB 32 Meg x 64 133 MHz MT16LSDF3264(L)HY-133_ 256MB 32 Meg x 64 133 MHz 256MB 32 Meg x 64 100 MHz MT16LSDF3264(L)HG-10E_ 256MB 32 Meg x 64 100 MHz MT16LSDF3264(L)HY-10E_ MT16LSDF6464(L)HG-13E_ 512MB 64 Meg x 64 133 MHz MT16LSDF6464(L)HY-13E_ 512MB 64 Meg x 64 133 MHz MT16LSDF6464(L)HG-133_ 512MB 64 Meg x 64 133 MHz 512MB 64 Meg x 64 133 MHz MT16LSDF6464(L)HY-133_ 512MB 64 Meg x 64 100 MHz MT16LSDF6464(L)HG-10E_ MT16LSDF6464(L)HY-10E_ 512MB 64 Meg x 64 100 MHz NOTE: 1. The designators for component and PCB revision are the last two characters of each part number Consult factory for current revision codes. Example: MT16LSDF32264(L)HG-133B1. pdf: 09005aef807924d2, source: 09005aef807924f1 Micron Technology, Inc., reserves the right to change products or specifications without notice. SDF16C32_64x64HG.fm - Rev. E 4/06 EN 2 ©2006 Micron Technology, Inc. All rights reserved. 256MB, 512MB (x64, DR) 144-PIN SDRAM SODIMM Table 4: Pin Assignment Table 5: Pin Assignment (144-Pin SODIMM Front) (144-Pin SODIMM Back) PIN SYMBOL PIN SYMBOL PIN SYMBOL PIN SYMBOL PIN SYMBOL PIN SYMBOL PIN SYMBOL PIN SYMBOL 1VSS 37 DQ8 73 NC 109 A9 2Vss 38 DQ40 74 CK1 110 BA1 3DQ0 39 DQ9 75 Vss 111 A10 4 DQ32 40 DQ41 76 VSS 112 A11 DD DD 5 DQ1 41 DQ10 77 NC 113 V 6 DQ33 42 DQ42 78 NC 114 V 7DQ2 43 DQ11 79 NC 115 DQMB2 8 DQ34 44 DQ43 80 NC 116 DQMB6 9DQ3 45 VDD 81 VDD 117 DQMB3 10 DQ35 46 VDD 82 VDD 118 DQMB7 DD 47 DQ12 83 DQ16 119 VSS DD 48 DQ44 84 DQ48 120 VSS 11 V 12 V 13 DQ4 49 DQ13 85 DQ17 121 DQ24 14 DQ36 50 DQ45 86 DQ49 122 DQ56 15 DQ5 51 DQ14 87 DQ18 123 DQ25 16 DQ37 52 DQ46 88 DQ50 124 DQ57 17 DQ6 53 DQ15 89 DQ19 125 DQ26 18 DQ38 54 DQ47 90 DQ51 126 DQ58 19 DQ7 55 VSS 91 VSS 127 DQ27 20 DQ39 56 VSS 92 VSS 128 DQ59 21 VSS 57 NC 93 DQ20 129 VDD 22 VSS 58 NC 94 DQ52 130 VDD 23 DQMB0 59 NC 95 DQ21 131 DQ28 24 DQMB4 60 NC 96 DQ53 132 DQ60 25 DQMB1 61 CK0 97 DQ22 133 DQ29 26 DQMB5 62 CKE0 98 DQ54 134 DQ61 27 VDD 63 VDD 99 DQ23 135 DQ30 28 VDD 64 VDD 100 DQ55 136 DQ62 DD 137 DQ31 DD 138 DQ63 29 A0 65 RAS# 101 V 30 A3 66 CAS# 102 V 31 A1 67 WE# 103 A6 139 VSS 32 A4 68 CKE1 104 A7 140 VSS 1 33 A2 69 S0# 105 A8 141 SDA 34 A5 70 NC/A12 106 BA0 142 SCL SS 71 S1# 107 VSS 143 VDD SS 72 NC 108 VSS 144 VDD 35 V 36 V NOTE: 1. Pin 70 is No Connect for 256MB modules, or A12 for 512MB modules. Figure 2: Pin Locations (144-Pin SODIMM) Front View Back View U1 U2 U17 U10 U9 U3 U4 U5 U6 U7 U8 U16 U15 U14 U13 U12 U11 PIN 1 (all odd pins) PIN 143 PIN 144 PIN 2 (all even pins) Indicates a VDD or VDDQ pin Indicates a VSS pin pdf: 09005aef807924d2, source: 09005aef807924f1 Micron Technology, Inc., reserves the right to change products or specifications without notice. SDF16C32_64x64HG.fm - Rev. E 4/06 EN 3 ©2006 Micron Technology, Inc. All rights reserved. 256MB, 512MB (x64, DR) 144-PIN SDRAM SODIMM Table 6: Pin Descriptions Pin numbers may not correlate with symbols; refer to the Pin Assignment tables on page 3 for more information PIN NUMBERS SYMBOL TYPE DESCRIPTION 65, 66, 67 RAS#, CAS#, WE# Input Command inputs: RAS#, CAS#, and WE# (along with S#) define the command being entered. 61, 74 CK0, CK1 Input Clock: CK is driven by the system clock. All SDRAM input signals are sampled on the positive edge of CK. CK also increments the internal burst counter and controls the output registers. 62, 68 CKE0, CKE1 Input Clock enable: CKE activates (HIGH) and deactivates (LOW) the CK signal. Deactivating the clock provides PRECHARGE power- down and SELF REFRESH operation (all device banks idle), ACTIVE power-down (row ACTIVE in any device bank), or CLOCK SUSPEND operation (burst access in progress). CKE is synchronous except after the device enters power-down and self refresh modes, where CKE becomes asynchronous until after exiting the same mode. The input buffers, including CK, are disabled during power-down and self refresh modes, providing low standby power. 69, 71 S0#,S1# Input Chip select: S# enables (registered LOW) and disables (registered HIGH) the command decoder. All commands are masked when S# is registered HIGH. S# is considered part of the command code. 23, 24, 25, 26, 115, 116, 117, DQMB0–DQMB7 Input Input/output mask: DQMB is an input mask signal for write 118 accesses and an output enable signal for read accesses. Input data is masked when DQMB is sampled HIGH during a WRITE cycle. The output buffers are placed in a High-Z state (two- clock latency) when DQMB is sampled HIGH during a READ cycle. 106, 110 BA0, BA1 Input Bank address: BA0 and BA1 define to which device bank the ACTIVE, READ, WRITE, or PRECHARGE command is being applied. 29, 30, 31, 32, 33, 34, A0–A11 Input Address inputs: Provide the row address for ACTIVE commands 70 (512MB), 103, 104, 105, (256MB) and the column address and auto precharge bit (A10) for 109, 111, 112 A0–A12 READ/WRITE commands, to select one location out of the (512MB) memory array in the respective device bank. A10 sampled during a PRECHARGE command determines whether the PRECHARGE applies to one device bank (A10 LOW, device bank selected by BA0, BA1) or all device banks (A10 HIGH). The address inputs also provide the op-code during a MODE REGISTER SET command. 142 SCL Input Serial clock for presence-detect: scl is used to synchronize the presence-detect data transfer to and from the module. 141 SDA Input/ Serial presence-detect data: sda is a bidirectional pin used to Output transfer addresses and data into and data out of the presence- detect portion of the module. 3, 4, 5, 6, 7, 8, 9, 10, 13, 14, 15, DQ0–DQ63 Input/ Data I/O: Data bus. 16, 17, 18,19, 20, 37, 38, 39, Output 40, 41, 42, 43, 44, 47, 48, 49, 50, 51, 52, 53, 54, 83, 84, 85, 86, 87, 88, 89, 90, 93, 94, 95, 96, 97, 98, 99, 100, 121, 122, 123, 124, 125, 126, 127, 128, 131, 132, 133, 134, 135, 136, 137, 138 pdf: 09005aef807924d2, source: 09005aef807924f1 Micron Technology, Inc., reserves the right to change products or specifications without notice. SDF16C32_64x64HG.fm - Rev. E 4/06 EN 4 ©2006 Micron Technology, Inc. All rights reserved. 256MB, 512MB (x64, DR) 144-PIN SDRAM SODIMM Table 6: Pin Descriptions (Continued) Pin numbers may not correlate with symbols; refer to the Pin Assignment tables on page 3 for more information PIN NUMBERS SYMBOL TYPE DESCRIPTION 11, 12, 27, 28, 45, 46, 63, 64, VDD Supply Power supply: +3.3V ±0.3V. 81, 82, 101, 102, 113, 114, 129, 130, 143, 144 1, 21, 35, 55, 75, 91, 107, 119, VSS Supply Ground. 139, 2, 22, 36, 56, 76, 92, 108, 120, 140 57, 58, 59, 60, 70 (256MB), 72, NC – Not connected: These pins should be left unconnected. 73, 77, 78, 79, 80 pdf: 09005aef807924d2, source: 09005aef807924f1 Micron Technology, Inc., reserves the right to change products or specifications without notice. SDF16C32_64x64HG.fm - Rev. E 4/06 EN 5 ©2006 Micron Technology, Inc. All rights reserved. 256MB, 512MB (x64, DR) 144-PIN SDRAM SODIMM Figure 3: Functional Block Diagram 0Ω S1# 0Ω S0# 0Ω 0Ω DQMB0 DQMB4 DQM CS# CS# DQM CS# DQM DQM CS# DQ DQ32 DQ DQ0 DQ DQ DQ33 DQ DQ1 DQ DQ DQ DQ34 DQ DQ2 DQ DQ DQ DQ DQ35 DQ U1 U9 DQ3 DQ U3 DQ U11 DQ36 DQ DQ DQ4 DQ DQ DQ37 DQ DQ5 DQ DQ DQ DQ38 DQ DQ DQ6 DQ DQ DQ DQ39 DQ DQ7 DQ DQ 0Ω 0Ω DQMB1 DQMB5 CS# DQM CS# DQM DQM CS# DQM CS# DQ DQ DQ8 DQ DQ40 DQ DQ DQ DQ9 DQ DQ41 DQ DQ DQ DQ DQ10 DQ DQ42 U5 DQ DQ U12 DQ11 DQ U13 DQ43 U4 DQ DQ DQ DQ12 DQ DQ44 DQ DQ DQ DQ13 DQ DQ45 DQ DQ DQ DQ DQ14 DQ DQ46 DQ DQ DQ15 DQ DQ47 DQ 0Ω 0Ω DQMB2 DQMB6 CS# DQM DQM CS# CS# DQM DQM CS# DQ16 DQ DQ DQ DQ48 DQ DQ17 DQ DQ49 DQ DQ DQ DQ18 DQ DQ DQ50 DQ DQ U7 DQ19 U15 U6 U14 DQ DQ DQ51 DQ DQ DQ20 DQ DQ52 DQ DQ DQ DQ21 DQ DQ53 DQ DQ DQ DQ22 DQ DQ DQ54 DQ DQ DQ23 DQ DQ DQ DQ55 DQ 0Ω 0Ω DQMB7 DQMB3 CS# DQM DQM CS# DQM CS# CS# DQM DQ24 DQ DQ56 DQ DQ DQ DQ25 DQ DQ DQ57 DQ DQ DQ26 DQ DQ DQ58 DQ DQ U8 DQ DQ59 DQ U2 DQ U10 DQ27 DQ U16 DQ28 DQ DQ60 DQ DQ DQ DQ29 DQ DQ DQ61 DQ DQ DQ DQ DQ DQ30 DQ DQ62 DQ31 DQ DQ63 DQ DQ DQ 0Ω RAS# RAS#: SDRAMs VDD SDRAMs CLK (U1, U3, U9, U11) CAS# CAS#: SDRAMs CK0 VSS SDRAMs CLK (U4, U5, U12, U13) WE# WE#: SDRAMs (256MB) A0–A11 A0-A11: SDRAMs CLK (U6, U7, U14, U15) SERIAL PD CK1 (512MB) A0–A12 A0-A12: SDRAMs SCL U17 CLK (U2, U8, U10, U16) SDA BA0, BA1 BA0, BA1: SDRAMs WP A0 A1 A2 CKE0 (U1–U8) CKE0 CKE1 CKE1 (U9–U16) Standard modules use the following SDRAM devices: NOTE: MT48LC16M8A2FB (256MB); MT48LC32M8A2FB (512MB) 1. All resistor values are 10Ω unless otherwise specified. 2. Per industry standard, Micron utilizes various component speed grades Lead-free modules use the following SDRAM devices: as referenced in the module part numbering guide at www.micron.com/ MT48LC16M8A2BB (256MB); MT48LC32M8A2BB (512MB) support/numbering.html. pdf: 09005aef807924d2, source: 09005aef807924f1 Micron Technology, Inc., reserves the right to change products or specifications without notice. SDF16C32_64x64HG.fm - Rev. E 4/06 EN 6 ©2006 Micron Technology, Inc. All rights reserved. 256MB, 512MB (x64, DR) 144-PIN SDRAM SODIMM General Description Serial Presence Detect Operation The MT16LSDF3264(L)H and MT16LSDF6464(L)H These modules incorporate serial presence-detect are high-speed CMOS, dynamic random-access (SPD). The SPD function is implemented using a 256MB and 512MB unbuffered memory modules, 2,048-bit EEPROM. This nonvolatile storage device organized in x64 configurations. These modules use contains 256 bytes. The first 128 bytes are programmed internally configured quad-bank SDRAMs with a syn- by Micron to identify the module type, SDRAM charac- chronous interface (all signals are registered on the teristics and module timing parameters. The remain- positive edge of the clock signal CK). ing 128 bytes of storage are available for use by the Read and write accesses to the SDRAM modules are customer. System READ/WRITE operations between burst oriented; accesses start at a selected location and the master (system logic) and the slave EEPROM 2 continue for a programmed number of locations in a device (DIMM) occur via a standard I C bus using the programmed sequence. Accesses begin with the regis- DIMM’s SCL (clock) and SDA (data) signals, together tration of an ACTIVE command, which is then fol- with SA[2:0], which provide eight unique DIMM/ lowed by a READ or WRITE command. The address EEPROM addresses. Write protect (WP) is tied to bits registered coincident with the ACTIVE command ground on the module, permanently disabling hard- are used to select the device bank and row to be ware write protect. accessed (BA0, BA1 select the device bank, A0–A11 [256MB] or A0–A12 [512MB] select the device row). Initialization The address bits A0–A9 (for both 256MB and 512MB SDRAMs must be powered up and initialized in a modules) registered coincident with the READ or predefined manner. Operational procedures other WRITE command are used to select the starting device than those specified may result in undefined opera- column location for the burst access. tion. When power is applied to VDD and VDDQ (simul- These modules provide for programmable READ or taneously), and the clock is stable (stable clock is WRITE burst lengths of 1, 2, 4, or 8 locations, or the full defined as a signal cycling within timing constraints page, with a burst terminate option. An auto precharge specified for the clock pin), the SDRAM requires a function may be enabled to provide a self-timed row 100µs delay prior to issuing any command other than a precharge that is initiated at the end of the burst COMMAND INHIBIT or NOP. Starting at some point sequence. during this 100µs period and continuing at least These modules use an internal pipelined architec- through the end of this period, COMMAND INHIBIT ture to achieve high-speed operation. This architec- or NOP commands should be applied. ture is compatible with the 2n rule of prefetch When the 100µs delay has been satisfied with at architectures, but it also enables the column address least one COMMAND INHIBIT or NOP command hav- to be changed on every clock cycle to achieve a high- ing been applied, a PRECHARGE command should be speed, fully random access. Precharging one device applied. All device banks must then be precharged, bank while accessing one of the other three device thereby placing the device in the all banks idle state. banks will hide the precharge cycles and provide When in the idle state, two AUTO REFRESH cycles seamless, high-speed, random-access operation. must be performed. After the AUTO REFRESH cycles These modules are designed to operate in 3.3V, low- are complete, the SDRAM is ready for mode register power memory systems. An auto refresh mode is pro- programming. Because the mode register will power vided, along with a power-saving, power-down mode. up in an unknown state, it should be loaded prior to All inputs and outputs are LVTTL-compatible. applying any operational command. SDRAM modules offer substantial advances in DRAM operating performance, including the ability to Mode Register Definition synchronously burst data at a fast data rate with auto- The mode register is used to define the specific matic column-address generation, the ability to inter- mode of operation of the SDRAM. This definition leave between internal banks in order to hide includes the selection of a burst length, a burst type, a precharge time and the capability to randomly change CL, an operating mode, and a write burst mode, as column addresses on each clock cycle during a burst shown in Figure 4 on page 8. The mode register is pro- access. For more information regarding SDRAM opera- grammed via the LOAD MODE REGISTER command tion, refer to the 128Mb or 256Mb SDRAM component and will retain the stored information until it is pro- data sheets. grammed again or the device loses power. pdf: 09005aef807924d2, source: 09005aef807924f1 Micron Technology, Inc., reserves the right to change products or specifications without notice. SDF16C32_64x64HG.fm - Rev. E 4/06 EN 7 ©2006 Micron Technology, Inc. All rights reserved. 256MB, 512MB (x64, DR) 144-PIN SDRAM SODIMM Mode register bits M0–M2 specify the burst length, Figure 4: Mode Register Definition M3 specifies the type of burst (sequential or inter- Diagram leaved), M4–M6 specify the CL, M7 and M8 specify the operating mode, M9 specifies the write burst mode, 256MB Module and M10 and M11 are reserved for future use. For the A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Bus 256MB and 512MB, M12 (A12) is undefined, but should be driven LOW during loading of the mode reg- ister. 11 109782 6 54 310 Mode Register (Mx) Reserved* WB Op Mode CAS LatencyBT Burst Length The mode register must be loaded when all device *Should program banks are idle, and the controller must wait the speci- M11 and M10 = “0, 0” fied time before initiating the subsequent operation. to ensure compatibility with future devices. Violating either of these requirements will result in unspecified operation. 512MB Module A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Bus Burst Length Read and write accesses to the SDRAM are burst ori- ented, with the burst length being programmable, as 12 11 109782 6 54 310 Mode Register (Mx) shown in Figure 4. The burst length determines the Reserved*WB Op Mode CAS LatencyBT Burst Length maximum number of column locations that can be accessed for a given READ or WRITE command. Burst *Should program Burst Length lengths of 1, 2, 4, or 8 locations are available for both M12, M11, and M2 M1 M0 M3 = 0 M3 = 1 M10 = “0, 0, 0” the sequential and the interleaved burst types, and a to ensure 0 0 0 1 1 compatibility with full-page burst is available for the sequential type. The 0 0 1 2 2 future devices. full-page burst is used in conjunction with the BURST 0 1 0 4 4 TERMINATE command to generate arbitrary burst 0 1 1 8 8 1 0 0 Reserved Reserved lengths. 1 0 1 Reserved Reserved Reserved states should not be used, as unknown 1 1 0 Reserved Reserved operation or incompatibility with future versions may 1 1 1 Full Page Reserved result. When a READ or WRITE command is issued, a block M3 Burst Type of columns equal to the burst length is effectively 0 Sequential selected. All accesses for that burst take place within 1 Interleaved this block, meaning that the burst will wrap within the block if a boundary is reached, as shown in Table 7 on CAS Latency M6 M5 M4 page 9. The block is uniquely selected by A1–A9 when Reserved 0 0 0 0 0 1 Reserved the burst length is set to two; by A2–A9 when the burst 0 1 0 2 length is set to four; and by A3–A9 when the burst 3 0 1 1 length is set to eight. The remaining (least significant) 1 0 0 Reserved address bit(s) is (are) used to select the starting loca- 1 0 1 Reserved tion within the block. Full-page bursts wrap within the Reserved 1 1 0 page if the boundary is reached, as shown in Table 7 on Reserved 1 1 1 page 9. M8 M7 M6-M0 Operating Mode 0 0 Defined Standard operation - - - All other states reserved Write Burst Mode M9 0 Programmed burst length 1 Single location access pdf: 09005aef807924d2, source: 09005aef807924f1 Micron Technology, Inc., reserves the right to change products or specifications without notice. SDF16C32_64x64HG.fm - Rev. E 4/06 EN 8 ©2006 Micron Technology, Inc. All rights reserved. 256MB, 512MB (x64, DR) 144-PIN SDRAM SODIMM Table 7: Burst Definition Table Figure 5: CL Diagram T0 T1 T2 T3 ORDER OF ACCESSES CLK WITHIN A BURST STARTING BURST COLUMN TYPE = TYPE = COMMAND READ NOP NOP LENGTH ADDRESS SEQUENTIAL INTERLEAVED t t LZ OH A0 DQ DOUT t 2 00-1 0-1 AC 11-0 1-0 CAS Latency = 2 A1 A0 0 0 0-1-2-3 0-1-2-3 4 0 1 1-2-3-0 1-0-3-2 T0 T1 T2 T3 T4 1 0 2-3-0-1 2-3-0-1 CLK 1 1 3-0-1-2 3-2-1-0 COMMAND READ NOP NOP NOP A2 A1 A0 t t LZ OH 0 0 0 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7 DQ DOUT 0 0 1 1-2-3-4-5-6-7-0 1-0-3-2-5-4-7-6 t AC 0 1 0 2-3-4-5-6-7-0-1 2-3-0-1-6-7-4-5 CAS Latency = 3 8 0 1 1 3-4-5-6-7-0-1-2 3-2-1-0-7-6-5-4 DON’T CARE 1 0 0 4-5-6-7-0-1-2-3 4-5-6-7-0-1-2-3 UNDEFINED 1 0 1 5-6-7-0-1-2-3-4 5-4-7-6-1-0-3-2 1 1 0 6-7-0-1-2-3-4-5 6-7-4-5-2-3-0-1 1 1 1 7-0-1-2-3-4-5-6 7-6-5-4-3-2-1-0 Burst Type Accesses within a given burst may be programmed Full n = A0-A9 Cn, Cn + 1, Cn + 2 Not supported Page (location Cn + 3, Cn + 4... to be either sequential or interleaved; this is referred to (y) 0-y) …Cn - 1, Cn… as the burst type and is selected via bit M3. The ordering of accesses within a burst is deter- NOTE: mined by the burst length, the burst type, and the 1. For full-page accesses: y = 1,024 (both 256MB and starting column address, as shown in Table 7. 512MB modules) 2. For a burst length of two, A1–A9 select the block-of- two burst; A0 selects the starting column within the CAS Latency (CL) block. CL is the delay, in clock cycles, between the registra- 3. For a burst length of four, A2–A9 select the block-of- tion of a READ command and the availability of the four burst; A0–A1 select the starting column within the first piece of output data. The latency can be set to two block. or three clocks. 4. For a burst length of eight, A3–A9 select the block-of- If a READ command is registered at clock edge n, eight burst; A0–A2 select the starting column within and the latency is m clocks, the data will be available the block. by clock edge n + m. The DQ will start driving as a 5. For a full-page burst, the full row is selected and A0–A9 result of the clock edge one cycle earlier (n + m - 1), select the starting column. and provided that the relevant access times are met, 6. Whenever a boundary of the block is reached within a given sequence above, the following access wraps the data will be valid by clock edge n + m. For example, within the block. assuming that the clock cycle time is such that all rele- 7. For a burst length of one, A0–A9 select the unique col- vant access times are met, if a READ command is regis- umn to be accessed, and mode register bit M3 is tered at T0 and the latency is programmed to two ignored. clocks, the DQ will start driving after T1 and the data will be valid by T2, as shown in Figure 4 on page 8. Table 8 on page 10 indicates the operating frequencies at which each CL setting can be used. Reserved states should not be used as unknown operation or incompatibility with future versions may result. pdf: 09005aef807924d2, source: 09005aef807924f1 Micron Technology, Inc., reserves the right to change products or specifications without notice. SDF16C32_64x64HG.fm - Rev. E 4/06 EN 9 ©2006 Micron Technology, Inc. All rights reserved. 256MB, 512MB (x64, DR) 144-PIN SDRAM SODIMM Operating Mode Table 8: CL Table The normal operating mode is selected by setting ALLOWABLE OPERATING M7 and M8 to zero; the other combinations of values CLOCK FREQUENCY (MHz) for M7 and M8 are reserved for future use and/or test SPEED CL = 2 CL = 3 modes. The programmed burst length applies to both READ and WRITE bursts. -13E ≤ 133 < 143 Test modes and reserved states should not be used -133 ≤ 100 < 133 because unknown operation or incompatibility with -10E ≤ 100 ≤ NA future versions may result. Write Burst Mode When M9 = 0, the burst length programmed via M0- M2 applies to both READ and WRITE bursts; when M9 = 1, the programmed burst length applies to READ bursts, but write accesses are single-location (non- burst) accesses. pdf: 09005aef807924d2, source: 09005aef807924f1 Micron Technology, Inc., reserves the right to change products or specifications without notice. SDF16C32_64x64HG.fm - Rev. E 4/06 EN 10 ©2006 Micron Technology, Inc. All rights reserved. 256MB, 512MB (x64, DR) 144-PIN SDRAM SODIMM Commands The Truth Table provides a quick reference of avail- description of commands and operations, refer to the able commands. This is followed by written descrip- 128Mb or 256Mb SDRAM component data sheet. tion of each command. For a more detailed Table 9: Truth Table – SDRAM Commands and DQMB Operation CKE is HIGH for all commands shown except SELF REFRESH NAME (FUNCTION) CS# RAS# CAS# WE# DQMB ADDR DQ NOTES COMMAND INHIBIT (NOP) H XXX X X X NO OPERATION (NOP) L HHH X X X ACTIVE (select bank and activate row) L L H H X Bank/Row X 1 8 READ (select bank and column, and start READ burst) LH L H Bank/Col X 2 L/H 8 WRITE (select bank and column, and start WRITE burst)LH L L Bank/Col Valid 2 L/H BURST TERMINATE LH H L X X Active PRECHARGE (deactivate row in bank or banks) LL H L X Code X 3 LL L H X X X 4, 5 AUTO REFRESH or SELF REFRESH (enter self refresh mode) LOAD MODE REGISTER L LLL X Op-code X 6 Write enable/output enable – ––– L – Active 7 Write inhibit/output High-Z – ––– H – High-Z 7 NOTE: 1. A0–A11 (256MB) or A0–A12 (512MB) provide device row address, and BA0, BA1 determine which device bank is made active. 2. A0–A9 (256MB and 512MB) provide device column address; A10 HIGH enables the auto precharge feature (nonpersis- tent), while A10 LOW disables the auto precharge feature; BA0, BA1 determine which device bank is being read from or written to. 3. A10 LOW: BA0, BA1 determine which device bank is being precharged. A10 HIGH: all device banks are precharged and BA0, BA1 are “Don’t Care.” 4. This command is AUTO REFRESH if CKE is HIGH, SELF REFRESH if CKE is LOW. 5. Internal refresh counter controls row addressing; all inputs and I/Os are “Don’t Care” except for CKE. 6. A0–A11 define the op-code written to the mode register; for the 256MB and 512MB, A12 should be driven low. 7. Activates or deactivates the DQs during WRITEs (zero-clock delay) and READs (two-clock delay). pdf: 09005aef807924d2, source: 09005aef807924f1 Micron Technology, Inc., reserves the right to change products or specifications without notice. SDF16C32_64x64HG.fm - Rev. E 4/06 EN 11 ©2006 Micron Technology, Inc. All rights reserved. 256MB, 512MB (x64, DR) 144-PIN SDRAM SODIMM Absolute Maximum Ratings Stresses greater than those listed may cause perma- tional sections of this specification is not implied. nent damage to the device. This is a stress rating only, Exposure to absolute maximum rating conditions for and functional operation of the device at these or any extended periods may affect reliability. other conditions above those indicated in the opera- Voltage on VDD Supply, Operating Temperature, Relative to VSS . . . . . . . . . . . . . . . . . . . . -1V to +4.6V T (Commercial - ambient) . . . . . .0°C to +65°C OPR Voltage on Inputs, NC or I/O Pins Storage Temperature (plastic) . . . . . . -55°C to +125°C Relative to VSS . . . . . . . . . . . . . . . . . . . -1V to +4.6V Short Circuit Output Current. . . . . . . . . . . . . . . . 50mA Table 10: DC Electrical Characteristics and Operating Conditions Notes: 1, 5, 6; notes appear on page 16; VDD, VDDQ = +3.3V ±0.3V PARAMETER/CONDITION SYMBOL MIN MAX UNITS NOTES Supply voltage VDD, VDDQ3 3.6 V Input high voltage: Logic 1; All inputs VIH 2VDD + 0.3 V 22 Input low voltage: Logic 0; All inputs VIL –0.3 0.8 V 22 Input leakage current: Command and II µA 33 Any input 0V ≤ VIN ≤ VDD Address Inputs –80 80 (All other pins not under test = 0V) CK, CKE, S# –40 40 DQMB –10 10 Output leakage current: DQ pins are disabled; DQ IOZ –10 10 µA 33 0V ≤ VOUT ≤ VDDQ Output levels: VOH 2.4 – V Output High Voltage (IOUT = -4mA) VOL –0.4 V Output Low Voltage (IOUT = 4mA) Table 11: IDD Specifications and Conditions – 256MB Notes: 1, 5, 6, 11, 13; SDRAM components only; notes appear on page 16; VDD, VDDQ = +3.3V ±0.3V MAX PARAMETER/CONDITION SYMBOL -13E -133 -10E UNITS NOTES a Operating current: Active mode; Burst = 2; READ or WRITE; 1,296 1,216 1,136 mA 3, 17, 19, 32 IDD1 t t RC = RC (MIN) b Standby current: Power-down mode; All device banks idle; 32 32 32 mA 32 IDD2 CKE = LOW a Standby current: Active mode; 416 416 336 mA 3, 12, 19, 32 IDD3 t CKE = HIGH; CS# = HIGH; All device banks active after RCD met; No accesses in progress a Operating current: Burst mode; Continuous burst; READ or 1,336 1,216 1,136 mA 3, 18, 19, 32 IDD4 WRITE; All device banks active b t t Auto refresh current 5,280 4,960 4,320 mA 3, 12, 18, 19, RFC = RFC (MIN) IDD5 CKE = HIGH; S# = HIGH 32,30 t b 48 48 48 mA RFC = 15.625µs IDD6 b Self refresh current: CKE ≤ 0.2V Standard 32 32 32 mA 4 IDD7 b Low power (L) 16 16 16 mA IDD7 a - Value calculated as one module rank in this operating condition, and all other ranks in power-down mode. b - Value calculated reflects all module ranks in this operation condition. pdf: 09005aef807924d2, source: 09005aef807924f1 Micron Technology, Inc., reserves the right to change products or specifications without notice. SDF16C32_64x64HG.fm - Rev. E 4/06 EN 12 ©2006 Micron Technology, Inc. All rights reserved. 256MB, 512MB (x64, DR) 144-PIN SDRAM SODIMM Table 12: IDD Specifications and Conditions – 512MB Notes: 1, 5, 6, 11, 13; SDRAM components only; notes appear on page 16; VDD, VDDQ = +3.3V ±0.3V MAX PARAMETER/CONDITION SYMBOL -13E -133 -10E UNITS NOTES a 1,096 1,016 1,016 mA 3, 17,19, 32 Operating current: Active mode; Burst = 2; READ or WRITE; IDD1 t t RC = RC (MIN) b Standby current: Power-down mode; All device banks idle; 32 32 32 mA 32 IDD2 CKE = LOW a STANDBY CURRENT: Active mode; 336 336 336 mA 3, 12, 19, 32 IDD3 t CKE = HIGH; CS# = HIGH; All device banks active after RCD met; No accesses in progress a OPERATING CURRENT: Burst mode; Continuous burst; READ 1,096 1,096 1,096 mA 3, 18, 19, 32 IDD4 or WRITE; All device banks active t t b Auto refresh current RFC = RFC (MIN) 4,560 4,320 4,320 mA 3, 12, 18, 19, IDD5 CKE = HIGH; S# = HIGH 32,30 t b RFC = 7.8125µs 56 56 56 mA IDD6 b Self refresh current: CKE < 0.2V Standard 40 40 40 mA 4 IDD7 b Low power (L) 24 24 24 mA IDD7 a - Value calculated as one module rank in this operating condition, and all other ranks in power-down mode. b - Value calculated reflects all module ranks in this operation condition. Table 13: Capacitance Note 2; notes appear on page 16 PARAMETER SYMBOL MIN MAX UNITS Input capacitance: Address and command CI1 40 60.8 pF Input capacitance: CK CI2 20 28 pF Input capacitance: CKE, S# CI3 20 30.4 pF I4 57.6 pF Input capacitance: DQMB C Input/output capacitance: DQ CIO 812 pF pdf: 09005aef807924d2, source: 09005aef807924f1 Micron Technology, Inc., reserves the right to change products or specifications without notice. SDF16C32_64x64HG.fm - Rev. E 4/06 EN 13 ©2006 Micron Technology, Inc. All rights reserved. 256MB, 512MB (x64, DR) 144-PIN SDRAM SODIMM Table 14: Electrical Characteristics and Recommended AC Operating Conditions Notes: 5, 6, 8, 9, 11, 31; notes appear on page 16; comply with PC100 and PC133 specifications, based on SDRAM device AC CHARACTERISTICS -13E -133 -10E PARAMETER SYMBOL MIN MAX MIN MAX MIN MAX UNITS NOTES t 5.4 5.4 6 ns 27 Access time from CL = 3 AC(3) CLK (positive edge) t CL = 2 5.4 6 6 ns AC(2) t 0.8 0.8 1 ns Address hold time AH t Address setup time 1.5 1.5 2 ns AS t CLK high-level width 2.5 2.5 3 ns CH t 2.5 2.5 3 ns CLK low-level width CL t Clock cycle time CL = 3 77.5 8 ns23 CK(3) t CL = 2 7.5 10 10 ns 23 CK(2) t CKE hold time 0.8 0.8 1 ns CKH t CKE setup time 1.5 1.5 2 ns CKS t CS#, RAS#, CAS#, WE#, DQM hold 0.8 0.8 1 ns CMH time t CS#, RAS#, CAS#, WE#, DQM setup 1.5 1.5 2 ns CMS time t Data-in hold time 0.8 0.8 1 ns DH t Data-in setup time 1.5 1.5 2 ns DS t Data-out High-Z time CL = 3 5.4 5.4 6 ns 10 HZ(3) t CL = 2 5.4 6 6 ns 10 HZ(2) t 111 ns Data-out Low-Z time LZ t Data-out hold time (load) 333 ns OH t 1.8 1.8 1.8 ns 28 Data-out hold time (no load) OHN t ACTIVE-to-PRECHARGE command 37 120,000 44 120,000 50 120,000 ns 32 RAS t ACTIVE-to-ACTIVE command period 60 66 70 ns RC t 15 20 20 ns ACTIVE-to-READ or WRITE delay RCD t Refresh period 64 64 64 ms REF t AUTO REFRESH period 66 66 70 ns RFC t PRECHARGE command period 15 20 20 ns RP t ACTIVE bank a to ACTIVE bank b 14 15 20 ns RRD command t 0.3 1.2 0.3 1.2 0.3 1.2 ns 7 Transition time T t WRITE recovery time 1 CLK 1 CLK + 1 CLK ns 24 WR + 7ns 7.5ns + 7ns 14 15 15 ns 25 t Exit SELF REFRESH to ACTIVE 67 75 80 ns 20 XSR command pdf: 09005aef807924d2, source: 09005aef807924f1 Micron Technology, Inc., reserves the right to change products or specifications without notice. SDF16C32_64x64HG.fm - Rev. E 4/06 EN 14 ©2006 Micron Technology, Inc. All rights reserved. 256MB, 512MB (x64, DR) 144-PIN SDRAM SODIMM Table 15: AC Functional Characteristics Notes: 5, 6, 7, 8, 9, 11, 31; notes appear on page 16; comply with PC100 and PC133 specifications, based on SDRAM device PARAMETER SYMBOL -13E -133 -10E UNITS NOTES t t READ/WRITE command to READ/WRITE command 11 1 17 CCD CK t t CKE to clock disable or power-down entry mode 11 1 14 CKED CK t t CKE to clock enable or power-down exit setup mode 11 1 14 PED CK t t DQM to input data delay 00 0 17 DQD CK t t DQM to data mask during WRITEs 00 0 17 DQM CK t t 22 2 17 DQM to data High-Z during READs DQZ CK t t WRITE command to input data delay 00 0 17 DWD CK t t 45 4 15, 21 Data-in to ACTIVE command DAL CK t t Data-in to PRECHARGE command 22 2 16, 21 DPL CK t t Last data-in to burst STOP command 11 1 17 BDL CK t t 11 1 17 Last data-in to new READ/WRITE command CDL CK t t Last data-in to PRECHARGE command 22 2 16, 21 RDL CK t t LOAD MODE REGISTER command to ACTIVE or REFRESH 22 2 26 MRD CK command t t 33 3 17 Data-out to High-Z from PRECHARGE command CL = 3 ROH(3) CK t t 22 2 17 CL = 2 ROH(2) CK pdf: 09005aef807924d2, source: 09005aef807924f1 Micron Technology, Inc., reserves the right to change products or specifications without notice. SDF16C32_64x64HG.fm - Rev. E 4/06 EN 15 ©2006 Micron Technology, Inc. All rights reserved. 256MB, 512MB (x64, DR) 144-PIN SDRAM SODIMM Notes t 1. All voltages referenced to VSS. 16. Timing actually specified by WR. 2. This parameter is sampled. VDD, VDDQ = +3.3V; f = 17. Required clocks are specified by JEDEC function- 1 MHz, T = 25°C; pin under test biased at 1.4V. A ality and are not dependent on any timing param- 3. IDD is dependent on output loading and cycle eter. rates. Specified values are obtained with mini- 18. The IDD current will increase or decrease propor- mum cycle time and the outputs open. tionally according to the amount of frequency 4. Enables on-chip refresh and address counters. alteration for the test condition. 5. The minimum specifications are used only to 19. Address transitions average one transition every indicate cycle time at which proper operation two clocks. over the full temperature range is ensured (0°C ≤ 20. CLK must be toggled a minimum of two times T ≤ +70°C). during this period. A t t 6. An initial pause of 100µs is required after power- 21. Based on CK = 10ns for -10E, and CK = 7.5ns for - up, followed by two AUTO REFRESH commands, 133 and -13E. before proper device operation is ensured. (VDD 22. VIH overshoot: VIH (MAX) = VDDQ + 2V for a pulse and VDDQ must be powered up simultaneously. width ≤ 3ns, and the pulse width cannot be greater VSS and VSSQ must be at same potential.) The two than one third of the cycle rate. VIL undershoot: AUTO REFRESH-command wake-ups should be VIL (MIN) = -2V for a pulse width ≤ 3ns. t repeated any time the REF refresh requirement is 23. The clock frequency must remain constant (stable exceeded. clock is defined as a signal cycling within timing t constraints specified for the clock pin) during 7. AC characteristics assume T = 1ns. access or precharge states (READ, WRITE, includ- 8. In addition to meeting the transition rate specifi- t ing WR, and PRECHARGE commands). CKE may cation, the clock and CKE must transit between be used to reduce the data rate. VIH and VIL (or between VIL and VIH) in a mono- 24. Auto precharge mode only. The precharge time tonic manner. t 9. Outputs measured at 1.5V with equivalent load: ( RP) begins at 7ns for -13E; 7.5ns for -133 and 7ns for -10E after the first clock delay, after the last Q WRITE is executed. May not exceed limit set for 50pF precharge mode. 25. Precharge mode only. t 26. JEDEC and PC100 specify three clocks. 10. HZ defines the time at which the output achieves t the open circuit condition; it is not a reference to 27. AC for -133/-13E at CL = 3 with no load is 4.6ns VOH or VOL. The last valid data element will meet and is guaranteed by design. t 28. Parameter guaranteed by design. OH before going High-Z. t 11. AC timing and IDD tests have VIL = 0V and VIH = 3V, 29. For -10E, CL = 2 and CK = 10ns; for -133, CL = 3 with timing referenced to 1.5V crossover point. If t t and CK = 7.5ns; for -13E, CL = 2 and CK = 7.5ns. the input transition time is longer than 1ns, then 30. CKE is HIGH during refresh command period the timing is referenced at VIL (MAX) and VIH t RFC (MIN), else CKE is LOW. The IDD6 limit is (MIN) and no longer at the 1.5V crossover point. actually a nominal value and does not result in a 12. Other input signals can change no more than fail value. once every two clocks and are otherwise at valid 31. Refer to device data sheet for timing waveforms. VIH or VIL levels. t 32. The value of RAS used in -13E speed grade mod- 13. IDD specifications are tested after the device is t t properly initialized. ule SPDs is calculated from RC - RP = 45ns. t 33. Leakage number reflects the worst case leakage 14. Timing actually specified by CKS; clock(s) speci- possible through the module pin, not what each fied as a reference only at minimum cycle rate. memory device contributes. t t 15. Timing actually specified by WR plus RP; clock(s) specified as a reference only at minimum cycle rate. pdf: 09005aef807924d2, source: 09005aef807924f1 Micron Technology, Inc., reserves the right to change products or specifications without notice. SDF16C32_64x64HG.fm - Rev. E 4/06 EN 16 ©2006 Micron Technology, Inc. All rights reserved. 256MB, 512MB (x64, DR) 144-PIN SDRAM SODIMM SPD Clock and Data Conventions SPD Acknowledge Data states on the SDA line can change only during Acknowledge is a software convention used to indi- SCL LOW. SDA state changes during SCL HIGH are cate successful data transfers. The transmitting device, reserved for indicating start and stop conditions (see either master or slave, will release the bus after trans- Figures 6, and 7). mitting eight bits. During the ninth clock cycle, the receiver will pull the SDA line LOW to acknowledge that it received the eight bits of data (see Figure 8). SPD Start Condition The SPD device will always respond with an All commands are preceded by the start condition, acknowledge after recognition of a start condition and which is a HIGH-to-LOW transition of SDA when SCL its slave address. If both the device and a WRITE oper- is HIGH. The SPD device continuously monitors the ation have been selected, the SPD device will respond SDA and SCL lines for the start condition and will not with an acknowledge after the receipt of each subse- respond to any command until this condition has been quent eight bit word. In the read mode the SPD device met. will transmit eight bits of data, release the SDA line and monitor the line for an acknowledge. If an acknowl- SPD Stop Condition edge is detected and no stop condition is generated by All communications are terminated by a stop condi- the master, the slave will continue to transmit data. If tion, which is a LOW-to-HIGH transition of SDA when an acknowledge is not detected, the slave will termi- SCL is HIGH. The stop condition is also used to place nate further data transmissions and await the stop the SPD device into standby power mode. condition to return to standby power mode. Figure 6: Data Validity Figure 7: Definition of Start and Stop SCL SCL SDA SDA Start Stop bit bit Data stable Data change Data stable Figure 8: Acknowledge Response From Receiver (( )) SCL from master (( )) Data output (( from transmitter )) (( Data output )) from receiver Acknowledge pdf: 09005aef807924d2, source: 09005aef807924f1 Micron Technology, Inc., reserves the right to change products or specifications without notice. SDF16C32_64x64HG.fm - Rev. E 4/06 EN 17 ©2006 Micron Technology, Inc. All rights reserved. 256MB, 512MB (x64, DR) 144-PIN SDRAM SODIMM Table 16: EEPROM Device Select Code Most significant bit (b7) is sent first DEVICE TYPE IDENTIFIER CHIP ENABLE RW b7 b6 b5 b4 b3 b2 b1 b0 Memory area select code (two arrays) 1010 SA2 SA1 SA0 RW Protection register select code 0110 SA2 SA1 SA0 RW Table 17: EEPROM Operating Modes MODE RW# BIT WC BYTES INITIAL SEQUENCE Current address READ 1VIH or VIL 1 START, device select, RW = 1 Random address READ 0VIH or VIL 1 START, device select, RW = 0, Address 1VIH or VIL RESTART, device select, RW = 1 1VIH or VIL ≥1 Sequential READ similar to current or random address READ Byte WRITE 0VIL 1 START, device select, RW = 0 Page WRITE 0VIL ≤16 START, device select, RW# = 0 Figure 9: SPD EEPROM Timing Diagram t t t F HIGH R t LOW SCL t t t t t SU:STA HD:STA HD:DAT SU:DAT SU:STO SDA In t t t DH AA BUF SDA Out UNDEFINED pdf: 09005aef807924d2, source: 09005aef807924f1 Micron Technology, Inc., reserves the right to change products or specifications without notice. SDF16C32_64x64HG.fm - Rev. E 4/06 EN 18 ©2006 Micron Technology, Inc. All rights reserved. 256MB, 512MB (x64, DR) 144-PIN SDRAM SODIMM Table 18: Serial Presence-Detect EEPROM DC Operating Conditions All voltages referenced to VSS; VDDSPD = 2.3V to 3.6V PARAMETER/CONDITION SYMBOL MIN MAX UNITS Supply voltage VDD 33.6 V Input high voltage: Logic 1; All inputs VIH VDD × 0.7 VDD × 0.5 V Input low voltage: Logic 0; All inputs VIL –1 VDD × 0.3 V Output low voltage: IOUT = 3mA VOL –0.4 V IN = GND to VDD ILI –10 µA Input leakage current: V Output leakage current: VOUT = GND to VDD ILO –10 µA Standby current: SCL = SDA = VDD - 0.3V; All other inputs = GND or 3.3V ±10% ISB –30 µA Power supply current: SCL clock frequency = 100 KHz ICC –2 mA Table 19: Serial Presence-Detect EEPROM AC Operating Conditions All voltages referenced to VSS; VDDSPD = 2.3V to 3.6V PARAMETER/CONDITION SYMBOL MIN MAX UNITS NOTES t SCL LOW to SDA data-out valid AA 0.2 0.9 µs 1 t Time the bus must be free before a new transition can start BUF 1.3 µs t DH 200 ns Data-out hold time t SDA and SCL fall time F300ns2 t Data-in hold time HD:DAT 0 µs t Start condition hold time HD:STA 0.6 µs t Clock HIGH period HIGH 0.6 µs t I50ns Noise suppression time constant at SCL, SDA inputs t Clock LOW period LOW 1.3 µs t SDA and SCL rise time R0.3µs2 f SCL clock frequency SCL 400 KHz t Data-in setup time SU:DAT 100 ns t SU:STA 0.6 µs 3 Start condition setup time t Stop condition setup time SU:STO 0.6 µs t WRITE cycle time WRC 10 ms 4 NOTE: 1. To avoid spurious START and STOP conditions, a minimum delay is placed between SCL = 1 and the falling or rising edge of SDA. 2. This parameter is sampled. 3. For a restart condition, or following a WRITE cycle. t 4. The SPD EEPROM WRITE cycle time ( WRC) is the time from a valid stop condition of a write sequence to the end of the EEPROM internal erase/program cycle. During the WRITE cycle, the EEPROM bus interface circuit is disabled, SDA remains HIGH due to pull-up resistor, and the EEPROM does not respond to its slave address. pdf: 09005aef807924d2, source: 09005aef807924f1 Micron Technology, Inc., reserves the right to change products or specifications without notice. SDF16C32_64x64HG.fm - Rev. E 4/06 EN 19 ©2006 Micron Technology, Inc. All rights reserved. 256MB, 512MB (x64, DR) 144-PIN SDRAM SODIMM Table 20: Serial Presence-Detect Matrix “1”/“0”: Serial Data, “driven to HIGH”/“driven to LOW”; VDD = +3.3V ±0.3V BYTE DESCRIPTION ENTRY (VERSION) MT16LSDF3264H MT16LSDF6464H 0 Number of bytes used by Micron 128 80 80 1 Total number of SPD memory bytes 256 08 08 2 Memory type SDRAM 04 04 3 Number of row addresses 12 or 13 0C 0D 4 10 0A 0A Number of column addresses 5 Number of banks 202 02 6 Module data width 64 40 40 7 Module data width (continued) 000 00 8 Module voltage interface levels LVTTL 01 01 t 9 7ns (-13E) 70 70 SDRAM cycle time, CK 7.5ns (-133) 75 75 (CL = 3) 8ns (-10E) 80 80 t 10 5.4ns (-13E/-133) 54 54 SDRAM access from clock, AC 6ns (-10E) 60 60 (CL = 3) 11 Module configuration type NONE 00 00 12 Refresh rate/type 15.6µs 80 82 or 7.81µs/self 13 SDRAM width (primary SDRAM) 808 08 14 00 00 Error-checking SDRAM data width 15 101 01 MIN clock delay from back-to-back random t column addresses, CCD 16 Burst lengths supported 1, 2, 4, 8, page 8F 8F 17 404 4 Number of banks on SDRAM device 18 CAS latencies supported 2, 3 06 6 19 CS latency 001 01 20 WE latency 001 01 21 SDRAM module attributes Unbuffered 00 00 22 14 0E 0E SDRAM device attributes: General t 23 7.5ns (13E) 75 75 SDRAM cycle time, CK 10ns (-133/-10E) A0 A0 (CL = 2) t 24 5.4ns (-13E) 54 54 SDRAM access from CLK, AC 6ns (-133/-10E) 60 60 (CL = 2) t 25 –00 00 SDRAM cycle time, CK (CL = 1) t 26 –00 00 SDRAM access from CLK, AC (CL = 1) t 27 15ns (-13E) 0F 0F MIN row precharge time, RP 20ns (-133/-10E) 14 14 t 28 14ns (-13E) 0E 0E MIN row active-to-row active, RRD 15ns (-133) 0F 0F 20ns (-10E) 14 14 t 29 15ns (-13E) 0F 0F MIN RAS#-to-CAS# delay, RCD 20ns (-133/-10E) 14 14 t 30 45ns (-13E) 2D 2D MIN RAS# pulse width, RAS 44ns (133) 2C 2C 50ns (-10E) 32 32 pdf: 09005aef807924d2, source: 09005aef807924f1 Micron Technology, Inc., reserves the right to change products or specifications without notice. SDF16C32_64x64HG.fm - Rev. E 4/06 EN 20 ©2006 Micron Technology, Inc. All rights reserved. 256MB, 512MB (x64, DR) 144-PIN SDRAM SODIMM Table 20: Serial Presence-Detect Matrix (Continued) “1”/“0”: Serial Data, “driven to HIGH”/“driven to LOW”; VDD = +3.3V ±0.3V BYTE DESCRIPTION ENTRY (VERSION) MT16LSDF3264H MT16LSDF6464H 31 Module rank density 128MB or 256MB 20 40 t t 32 1.5ns (-13E/-133) 15 15 Command and address setup time, AS, CMS 2ns (-10E) 20 20 t t 33 0.8ns (-13E/-133) 08 08 Command and address hold time, AH, CMH 1ns (-10E) 10 10 t 34 1.5ns (-13E/-133) 15 15 Data signal input setup time, DS 2ns (-10E) 20 20 t 35 0.8ns (-13E/-133) 08 08 Data signal input hold time, DH 1ns (-10E) 10 10 36–40 Reserved 00 00 t 41 Device MIN ACTIVE/AUTO-REFRESH time, RC 66ns (-13E) 3C 3C 71ns (-133) 42 42 66ns (-10E) 46 46 42–61 Reserved 00 00 62 SPD revision REV. 2.0 02 02 63 Checksum for bytes 0-62 (-13E) 95 B8 (-133) E1 04 (-10E) 2D 50 64 MICRON 2C 2C Manufacturer’s JEDEC ID code 65–71 FF FF Manufacturer’s JEDEC ID code (continued) 72 Manufacturing location 1–12 01–0C 01– 0C 73–90 Module part number (ASCII) Variable Data Variable Data 91 PCB identification code 1–9 01–09 01–09 92 000 00 Identification code (continued) 93 Variable Data Variable Data Year of manufacture in BCD 94 Week of manufacture in BCD Variable Data Variable Data 95-98 Module serial number Variable Data Variable Data 99–125 Manufacturer-specific data (RSVD) 126 100 MHz/133 MHz 64 64 System frequency (-13E/-133/-10E) 127 CF CF SDRAM component and clock detail NOTE: t t t 1. The value of RAS used for the -13E module is calculated from RC - RP. Actual device spec value is 37ns. pdf: 09005aef807924d2, source: 09005aef807924f1 Micron Technology, Inc., reserves the right to change products or specifications without notice. SDF16C32_64x64HG.fm - Rev. E 4/06 EN 21 ©2006 Micron Technology, Inc. All rights reserved. 256MB, 512MB (x64, DR) 144-PIN SDRAM SODIMM Figure 10: 144-Pin SODIMM Dimensions 0.150 (3.80) FRONT VIEW MAX 2.666 (67.72) 2.655 (67.45) U17 U1 U2 0.079 (2.00) R (2X) 1.255 (31.88) 0.071 (1.80) U3 U4 U5 U6 U7 U8 1.245 (31.62) (2X) 0.787 (20.00) TYP 0.236 (6.00) 0.157 (4.00) 0.100 (2.55) 0.043 (1.10) 0.035 (0.90) 0.079 (2.00) 0.059 (1.50) 0.024 (0.60) 0.0315 (0.80) PIN 1 PIN 143 83.82 (3.30) TYP TYP TYP 2.386 (60.60) 2.504 (63.60) BACK VIEW U10 U9 U16 U15 U14 U13 U12 U11 PIN 144 PIN 2 NOTE: MAX All dimensions in inches (millimeters); or typical where noted. MIN Data Sheet Designation Released (No Mark): This data sheet contains mini- devices. Although considered final, these specifica- mum and maximum limits specified over the complete tions are subject to change, as further product devel- power supply and temperature range for production opment and data characterization sometimes occur. ® 8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900 E-mail: prodmktg@micron.com, Internet: http://www.micron.com, Customer Comment Line: 800-932-4992 Micron, the M logo, and the Micron logo are trademarks and/or service marks of Micron Technology, Inc. All other trademarks are the property of their respective owners. pdf: 09005aef807924d2, source: 09005aef807924f1 Micron Technology, Inc., reserves the right to change products or specifications without notice. SDF16C32_64x64HG.fm - Rev. E 4/06 EN 22 ©2006 Micron Technology, Inc. All rights reserved.