E192.01 DC M DC MO OT TOR F OR FU ULL B LL BR RI IDGE DGE 11A A E192.01 PRODUCTION DATA - JUL 25, 2011 Features General Description ÿ Supply voltage range 5.5V to 19V This IC combines several key functions of DC Motor ÿ Two push pull low drop power outputs for Controller used in an automotive under-hood applica- 1A nominal current with slew rate control tion. It contains all function blocks to run the motor ÿ Internal charge pump bidirectional or to brake it. ÿ Control logic ÿ Shut down capabilities via an integrated timer or a trigger signal Applications ÿ Over voltage protection ÿ Under voltage detection ÿ Intake manifold ÿ Over temperature protection ÿ Powertrain ÿ A clamped 12V supply voltage for an external hall cell ÿ Power on circuit ÿ 50mA Open-drain low side driver with battery voltage capability ÿ Operating temperature range – 40°C to + 132°C ÿ QSOP36 package VSUP Logic Level Voltage Clamp HALLSUP Hall TRIGIN Cell Supply 20mA POR Overvoltage Charge Over Temp. Shutdown Shutdown Undervoltage Pump Lockout OUTA R DIR DIR Fault Off board Gate C MOT INVDIR Control and M Driver Input Logic DMOS Start-up Logic OUTB TRIGIN H-Bridge H-Bridge Shutdown R Open TRIGOUT TRIGOUT Control Logic Off board Collector Buffer Timer Module E192.01 MODE RL GND R ext ELMOS Semiconductor AG Data Sheet QM-No.: 25DS0008E.00 DATA SHEET Jul 25, 2011 1 General Device Specification 1.1 Absolute Maximum Ratings Operation of the device above these ratings is not permitted! Parameter Condition Symbol Min Max Unit Long term Power Dissipation Ta < +105°C P 800 mW NO105 Ta = +125°C P 450 mW NO125 Ta = +132°C P 330 mW NO132 Thermal resistance (Junction to 1 Continuously ) R 55 K/W TJ-A Ambient) Junction Temperature TJ -40 150 °C Operating Temperature Range T -40 132 °C OPT Storage Temperature Range T -40 150 °C STG Supply voltage VSUP T=0.5ms V - 0.3 50 V SUP_pku Output voltage TRIGOUT T=500ms VSUP_pkm - 0.3 40 V Input voltage DIR Continuously V - 0.3 26.5 V SUP_max 2 Output current TRIGOUT Peak, T=500ms I -25 ) mA TRIGOUT Continuously 0 25 mA Voltage at OUTA, OUTB Continuously - 0.3 19 V Current OUTA, OUTB Peak, T=50ms I -3.8 3.8 A PEAK Continuously I -1 +1 A NOM 3 Input voltage of all digital input pins Peak ) V - 0.3 VDD+0.3 V DIGin_p 1 Output current HALLSUP ) Peak, T=500ms IHALLSUP_p -5 mA Continuously I 0 20 mA HALLSUP_c 1 2 ) with a 2inch copper area on board as heat sink connected to the six fused pins and two additional one. 2 ) Internally limited 3 ) VDD = 4…6V, if VSUP>6.5V Page 1 of E192.01 QM-No.: 18 DC Motor Full Bridge 1A 25DS0008E.00 DATA SHEET Jul 25, 2011 1.2 Recommended Operating Conditions The following conditions apply unless otherwise stated. Parameter Conditions Symbol Min Typ Max Unit T Operating Temperature Range -40 105 °C OPT Extended Operating Temperature T -40 132 °C OPTEXT Range Supply Voltage Range VSUP 13.6 16 V 6,5 5.5 13.6 16 V For the TRIGOUT 4 function only ) All of the following parameters are valid for an operating temperature range of -40°C to 125°C and the supply voltage range, unless otherwise specified. Voltage reference is GND, if not otherwise specified. The current values are positive, if flowing into the circuit. 1.2.1 IC mounting notes The board layout has a huge effect on the thermal performance of this application. A sophisticated board layout can reduce the R down to 40K/W or lower! TJ-A This IC is delivered in a power package with fused leads. Pins 8, 9, 10, 26, 27 and 28 have direct metal connection to the lead paddle and that way to the silicon. These pins are the most efficient thermal bridges to ambient. For a good thermal performance it is strongly recommended to connect these pins to large copper areas on the board. Connecting all other pins to large copper areas will improve the thermal performance. One should leave as much copper as possible in the direct surrounding of the IC. Metal gaps on the board between pins on same potential enlarge the thermal impedance and should be avoided! Some pins are assembled in groups with same electrical potential. One should take care, that those pins (like GND pins 1-2-35-36, pins 17-18-19 or the NC with the VSUP pins 5-6, 13-14, 23-24 and 31-32) are connected each to a non-interrupted and gap-less copper area! For the VSUP – NC connection for instance this leads to a wider metal wire. Its width is two times the pin width plus the pin distance compared to a simple connection to a single pin. 4 ) According to description in chapter 2.1.1 and 3.2.5 Page 2 of E192.01 QM-No.: 18 DC Motor Full Bridge 1A 25DS0008E.00 DATA SHEET Jul 25, 2011 1.2.2 Load conditions and thermal requirements The IC E192.01 controls with its integrated H-Bridge a DC-Motor. This Motor moves a valve between two determined positions. The current draw during one motion period is shown in Figure 1.2.2-1. At the end of each motion period the valve is running in a soft mechanical blocking performed by a spring. In one type of application a Hall-Cell detects the end of the motion and sends a signal to the IC, which shuts down the H-Bridge as soon as the end position is reached. Another type of application works without a hall cell. In this application the IC will shut down the motor after a certain time. Figure 1.2.2-1 Current draw of the DC-Motor during one motion period The power dissipation peaks (under worst case conditions up to 6W) with the current draw since the on- resistance of the integrated H-bridge is independent on the current. So the short-term power dissipation can exceed the long-term power dissipation by a factor of ten or more. 5 The long-term thermal resistance R of the QSOP36 package is 55K/W ), a suitable PCB layout taken TJ-A for granted (refer to chapter 2.2.1). That means, that at 125°C for instance the long-term power dissipation should not exceed 450mW in order to prevent a silicon temperature above 150°C. An additional power dissipation of the voltage clamp for HALLSUP has to be taken into account. Since the power dissipation in case of continuously high duty-cycles is too large, it is necessary to limit the duty-cycle in order to reduce the average power dissipation in the IC. Referring to Figure 1.2.2-2 a higher power dissipation for short time periods the can be accepted. However, due to the limited average power dissipation there are cool–down periods with a low duty-cycle required. Table 1.2.2-1 lists the maximum duty-cycle for a certain condition. 5 ) A sophisticated board layout can reduce R down to 40K/W. TJ-A Page 3 of E192.01 QM-No.: 18 DC Motor Full Bridge 1A 25DS0008E.00 DATA SHEET Jul 25, 2011 Voltage Current Characteristics Ambient Duration Duty- [V] I I I temp. [sec] Cycle Peak Running Overtravel ΔT ΔT ΔT Peak Running Overtravel [A] [A] [A] [°C] [%] [msec] [msec] [msec] 13.5 2 0.30 0.65 5 500 60 105 1 time 100 5 50 10 50 Nominal 20 50 Continuous 25 16 2 0.75 0.75 5 500 60 105 1 time 100 5 50 10 40 Maximum ratings at Upper temperature range 20 25 Continuous 10 16 1.75 0.75 0.75 5 500 60 132 1 time 100 6 5 40 ) 10 6 25 ) Maximum ratings at Extreme temperature range 20 6 10 ) Continuous 6 10 ) 16 1.75 1.40 1.85 4 500 42 132 1 time 100 Extreme ratings at Extreme temperature range Table 2.2.2-1 List of allowed duty-cycles for various conditions. 60,0 50,0 40,0 30,0 20,0 10,0 0,0 0,001 0,01 0,1 1 10 100 1000 t [s] Figure 1.2.2-2 Thermal impedance between the silicon chip and the board environment of the QSOP36 2 package as a function of t. Pins 8 to 11 and 26 to 29 are connected to a 2inch on-board copper area. 6 ) Not recommended Page 4 of E192.01 QM-No.: 18 DC Motor Full Bridge 1A 25DS0008E.00 thermal Z(t) [K/W] DATA SHEET Jul 25, 2011 1.3 Package QSOP36 (fused) Package ELMOS packages meet the requirements of the latest JEDEC outline specification. All JEDEC outline specifications can be free downloaded from http://www.jedec.org or please contact your local ELMOS-Key- Account-Manager 1.4 Package Pin Out 1 36 NC NC 2 35 NC NC 3 34 INVDIR TESTIN 4 33 DIR RC 5 32 NC NC 6 31 VSUP VSUP 7 30 OUTA OUTB 8 29 GND GND 9 28 GND GND 10 27 GND GND 11 26 GND GND 12 25 OUTA OUTB 13 24 VSUP VSUP 14 23 NC NC 15 22 TRIGOUT MODE 16 21 TRIGIN HALLSUP 17 20 NC NC 18 19 NC NC 1.5 Pin Description Pin Number Pin name Function 8, 9, 10,11, GND Supply Ground 26, 27, 28, 29 3 INVDIR INVDIR = L ⇒ Inverts the meaning of DIR: Logic input, standard 5V logic level. 4 DIR Direction Command: HV Logic input, 16V logic level. 1, 2, 5, 14, 17, NC Not internally connected. Connect to anywhere. 18, 19, 20, 23, 32, 35, 36 6 VSUP Power supply voltage for the H-bridge (pin 7) and internal supply. 13, 24, 31 Power supply voltage for the H-bridge only. Internally connected via resistors. VSUP 7,12 OUTA DIMOS H-Bridge Output A. 15 TRIGOUT Buffered Shutdown Trigger: Open drain output for 50V max. 16 Shutdown Trigger: Logic input with internal pull up, standard 5V logic level. TRIGIN 21 Clamped supply voltage for external Hall-Cell. HALLSUP 22 MODE Logic input with internal pull up to 5V, connect not, to GND or HALLSUP 25, 30 OUTB DIMOS H-Bridge Output B. 33 Timing resistor for internal oscillator. RC 34 TESTIN Test mode enable input. Should be connected to GND. Page 5 of E192.01 QM-No.: 18 DC Motor Full Bridge 1A 25DS0008E.00 DATA SHEET Jul 25, 2011 2 Detailed Electrical Description The following parameters are valid for the operating conditions mentioned in Chapter 2.2 unless otherwise specified. 2.1 DC Characteristics 2.1.1 Supplies and Outputs Parameter VSUP # Conditions Symbol Min Typ Max Unit Supply voltage 06.01 VSUP 6.5 13.6 26.5 V 7 range 06.02 For the TRIGOUT function only ) VSUP 5.5 13.6 26.5 V 8 OVLO Enable 06.03 ) VthOVLO 16,1 17.6 19 V threshold OVLO Enable 06.04 VthOVHys 300 1200 mV hysteresis UVLO Enable 06.05 VthUVLO 7.3 7.6 V threshold 7 UVLO Enable 06.06 VthUVHys 80 600 mV hysteresis Power on reset 06.07 VSUP  VthPORH 3.9 5.5 V threshold Power off reset 06.08 VSUP  VthPORL 3.8 5.4 V threshold Power on/off reset 06.09 VhysPOR 0.1 1.7 V hysteresis Supply current 06.10 no load IBB 2 mA Parameter # Conditions Symbol Min Typ Max Unit OUTA/OUTB 9 Leakage current high 07.01 OUTA=Z or OUTB=Z ) IDSSH 60 μA side drivers Leakage current low 07.02 OUTA=Z or OUTB=Z IDSSL 60 μA side drivers Output on 07.03 RDSON_high 0.25 0.4 Ta≤25°C, VSUP≥10V Ω resistance 07.04 RDSON_low 0.25 0.4 Ta≤25°C, VSUP≥10V Ω 10 07.05 RDSON_high 0.6 0.8 Ta≤125°C, VSUP≥10V ) Ω 10 07.06 RDSON_low 0.6 0.8 Ta≤125°C, VSUP≥10V ) Ω 11 07.07 RDSON_high 0.35 0.55 Ta≤25°C, 7.1VVTRIGOUT>2V IscTRIGOUT 30 50 90 mA 15.06 2V>VTRIGOUT>1V 30 240 mA Clamping voltage 15.07 VclTRIGOUT 42 50 62 V ITRIGOUT = 200μA 2.1.2 Thermal shutdown Parameter # Conditions Symbol Min Typ Max Unit 13 Thermal shutdown 07.10 TSD 150 160 170 ) °C temperature Thermal shutdown hysteresis 07.11 5 15 ΔTSD °C 2.1.3 Inputs Parameter # Conditions Symbol Min Typ Max Unit 14 Thresholds of DIR 04.01 ) VthL 1.5 V 15 04.02 ) VthH 3.5 V 04.03 VHYS 0.6 1.3 1.8 V 16 03.01 VthL 0.8 V Thresholds of INVDIR, MODE and TRIGIN ) 17 03.02 ) VthH 2.4 V 03.03 VHYS 100 250 400 mV Pull up current of DIR, INVDIR, MODE and 03.04 IPU_MODE -60 -25 -10 VIN=2.4V μA TRIGIN Pull down current TESTIN 34.01 IpdTEST 10 30 60 1.5V≤ μA VTESTIN≤5V 12 ) Not tested in production, verified during prototyping. 13 ) TSD = Junction temperature. Guaranteed by design. 14 ) Voltages = 1.5V must be recognized as low level. 15 ) Voltages = 3.5V must be recognized as high level. 16 ) Voltages = 0.8V must be recognized as low level. 17 ) Voltages = 2.4V must be recognized as high level. Page 7 of E192.01 QM-No.: 18 DC Motor Full Bridge 1A 25DS0008E.00 DATA SHEET Jul 25, 2011 2.2 AC Characteristics 2.2.1 Motor Drivers Parameter # Conditions Symbol Min Typ Max Unit OUTA/OUTB Propagational delay 07.12 Switching delay to LS ON TLSON 10 μs 18 07.13 Switching delay to LS OFF TLSOFF 25 ) μs 07.14 Switching delay to HS ON THSON 25 μs 07.15 Switching delay to HS OFF THSOFF 25 μs Slew rate 07.16 12 36 Falling edge, R =24Ω V/μs LOAD 19 ) 07.17 1.5 15 Rising edge, R =24Ω V/μs LOAD 2.2.2 RC Timer function Parameter RC # Conditions Symbol Min Typ Max Unit Resistor value range 34.01 50 500 kΩ 20 One-shot Time-out 34.02 T1timed 0.86 1 1.14 s Rext = 200kΩ ) 21 period 34.03 T1timed Rext / Rext / Rext / s Rext = 50 … 500kΩ ) 232kΩ 200kΩ 175kΩ 22 34.04 T1triggered 1.72 2 2.28 s Rext = 200kΩ ) 17 34.05 T1triggered Rext / Rext / Rext / s Rext = 50 … 500kΩ ) 116kΩ 100kΩ 87.5kΩ 17 Delay time in case of 34.06 D1 Rext / Rext / Rext / s Rext = 50 … 500kΩ ) direction reversal 7.3MΩ 6.4MΩ 5.5MΩ operations 34.07 D1 31.25 ms Rext = 200kΩ 17 Fault condition 34.10 t Rext / Rext / Rext / ms bfault Rext = 50 … 500kΩ ) 300kΩ 200kΩ 100kΩ debouncing time 34.11 t 1 ms Rext = 200kΩ bfault 18 ) For information only. Guaranteed by design and verified during prototyping. The propagational delay is an internal delay, which cannot be measured in production. It ensures the break-before-make feature of the H- bridge. 19 ) Guaranteed by design, not tested in production and verified during prototyping. 20 ) Timed Shutdown Mode. 21 ) Tested on three points with 50kΩ, 200kΩ and 500kΩ. 22 ) Triggered Shutdown Mode. Page 8 of E192.01 QM-No.: 18 DC Motor Full Bridge 1A 25DS0008E.00 DATA SHEET Jul 25, 2011 3 Functional Description 3.1 Block Diagram VSUP C SUP Voltage HALLSUP Logic Level Clamp Supply 20mA 0.22uf/50V Charge Pump POR= Overvoltage Power-on Reset Shutdown/ Undervoltage Over Temperature Lockout Shutdown DIR Input Logic/ Fault control and Signal Conditioning: direction command Start- u p logic INVDIR OUTA DMOS Gate Drive H-Bridge OUTB Input Logic/ H-Bridge D.C.BRUSH MOTOR Signal TRIGIN Shutdown Conditioning: Shutdown Trigger Control Logic MODE RC Open Collector Buffer: Timer Module Position buffered TRIGOUT Shutdown Trigger VDO ASIC Ground Figure 3.1-1 Functional block diagram of the IC Page 9 of E192.01 QM-No.: 18 DC Motor Full Bridge 1A 25DS0008E.00 DATA SHEET Jul 25, 2011 3.2 Detailed Functional Description The IC contains a H-bridge for driving a DC motor bi-directionally. The internal support logic takes care that at each state change of the H-bridge the active output driver transistors get switched off first (break before make). As soon VSUP reaches VthPORH the IC awakes from reset. After reset the Motor is braked. Both low side drivers are switched on. The IC supports two modes of operations: Timed Shutdown and Triggered Shutdown. The mode of operation is selectable via a logic level input pin MODE on the IC. An internal 25μA pull-up pulls the MODE pin up to the internal 5V-supply voltage. 3.2.1 Timed Shutdown Mode of Operation: MODE=open (high) This mode of operation is selected by a logic high signal applied to the MODE pin. Due to the internal pull-up the Timed-Shutdown mode is selected simply by leaving the MODE pin open (nc). This mode of operation provides one-shot timed control of the H-bridge in response to a transition on the DIR input. In the steady state, the H-bridge will revert to a motor braking function, that is, both low-side drivers of the H-bridge will shunt the DC motor terminals to ground. Upon a valid transition of the DIR input, the 1-second one-shot Timer is activated, along with the H-bridge, to drive the DC motor in the specified direction (see table in the „Normal Operation“ section that follows). Assuming a stable DIR input, the Timer will timeout after the 1-second duration (T1) and the control logic will then revert to the steady-state condition of „braking“ the motor (low-side switches on). Should the DIR experience another state change midst the Timer operation (mid-travel reversal), the control logic brakes immediately the motor (both low-side drivers on) for a period of tdref (nominally 31ms) followed by a restart the one-shot Timer and H-bridge polarity reversal (to support mid-travel reversal DIR request). See state table Tab. 3.2.1-1 for details. After POR the IC enters its normal operation mode. The IC controls the H-bridge according to the DIR input, the current state of the H-bridge, and the state of the one-shot Timer. Transition on T0- State T1 State T2 State Comments DIR Pin One-shot (@T0+) Timed OUT A OUT B OUT A OUT B OUT A OUT B - - + - - -  Motor runs → - + + - - - Direction Reversal  - - - + - -  Motor runs ← + - - + - - Direction Reversal  Tab. 3.2.1-1: State table for the outputs OUTA and OUTB in Timed-Shutdown Mode. „-„ = GND-level, „+„ = VSUP-level T0+ represents the state at DIR transition. T0- represents the state prior to DIR transition. T1 represents One-shot timed H-bridge the state of nominal 1-second duration. T2 represents the post-Timer period and final stable state. Prior a direction reversal operation the delay time D1 (nominally 31ms) is added in order to prevent high peak currents. During D1 the IC breaks the motor (both low sides switches on). The One-shot Timer restarts after D1 on a reversal condition (new Timer event of 1s). A „-„ state for both OUTA and OUTB represent motor braking with both low sides of the H-bridge shorting the motor leads to ground. Page 10 of E192.01 QM-No.: 18 DC Motor Full Bridge 1A 25DS0008E.00 DATA SHEET Jul 25, 2011 3.2.2 Triggered Shutdown Mode of Operation: MODE=low This mode of operation is selected by a logic low signal applied to the MODE pin. This is accomplished by simply grounding the MODE pin. This mode of operation provides control of the H-bridge in response to a transition on the DIR input and feedback from the TRIGIN pin. In the steady state the H-bridge will revert to a motor braking function (both low-side drivers of the H-bridge shunts the DC motor terminals down to ground). Upon a valid transition of the DIR input, the H-bridge is activated to drive the DC motor in a specified direction (see the state table Figure 4.2.2-2) and the one-shot Timer is started. The H-bridge remains in this state until one of either two conditions are met: the appropriate Shutdown Trigger signal state is applied, or the one-shot Timer times out. After one of these conditions is met, the control logic brakes the motor by turning on both low-side drivers of the H-bridge. This is the steady-state condition. The one-shot Timer serves only as a safety function. In normal operation the Shutdown Trigger event on the TRIGIN pin occurs prior to a time out event. If for some reason the DC motor encounters a stall condition or the Shutdown Trigger signal faults, the one-shot timer will disable the drive stage (motor braking function), protecting the DC motor and the IC from excessive current. A rather immediate reversal is possible if the DIR transitions at the exact moment that the previous move terminates. This can result in excessive peak currents. In order to avoid high peak transients, the IC adds D1 (nominally 31ms) under this „transient“ reversal condition. Name Value Unit D1 31 ms T1 2000 ms Table 3.4.2-1 Delay times for the Flow Chart After POR the IC waits first 31ms (D1) before it enters its normal operation mode. The IC controls the H- bridge according to the DIR input, the current state of the H-bridge, and the state of the one-shot Timer (Figure 3.4.2-1) Page 11 of E192.01 QM-No.: 18 DC Motor Full Bridge 1A 25DS0008E.00 DATA SHEET Jul 25, 2011 START (Power On) Delay D1 INVDIR State N Y = HIGH CTRL = DIR CTRL ≠ DIR (Inverting control signal) (Non inverting control signal) Y CTRL State N = HIGH N N TRIGIN State TRIGIN State = = LOW HIGH Y Y Reset & Enable Timer Reset & Enable Timer OUT A = - OUT A = + OUT B = + OUT B = - OUT A = - OUT A = - OUT B = - OUT B = - Y Y Timer > T1 Timer > T1 Disable Timer Disable Timer N N N TRIGIN State N TRIGIN State = = N CTRL State N CTRL State LOW HIGH = = HIGH LOW Y Y Y Y N CTRL State N CTRL State = = HIGH LOW Y Y OUT A = - OUT B = - Disable Timer Delay D1 Figure 3.2.2-1 Control Flow Chart of normal operation in triggered shut down mode Page 12 of E192.01 QM-No.: 18 DC Motor Full Bridge 1A 25DS0008E.00 DATA SHEET Jul 25, 2011 One-Shot H-Bridge Comments INVDIR DIR TRIGIN Timer (T1) state state state state Current State Next State OUT A OUT B OUT A OUT B Example of normal run 0 0 1 0 - - - - Rest position 0 1 1 0 - - - + Start motion 0 1 1 0 - + - + Motion in progress 0 1 0 0 - + - - Brake DC motor, wait 31 ms Example of normal run with immediate reversal (DIR changes during motion) 0 0 1 0 - - - - Rest position 0 1 1 0 - - - + Start motion 0 0 1 0 - + - + Motion in progress 0 0 0 0 - + - - Brake DC motor, wait 31 ms 0 0 0 0 - - + - Starts motion 0 0 0 0 + - + - Motion in progress 0 0 1 0 + - - - Brake DC motor, wait 31 ms Example of Timeout with re-trial (and second timeout) 0 1 0 0 - - - - Rest position 0 0 0 0 - - - + Start motion 0 0 0 0 - + - + Motion in progress 0 0 0 1 - + - - Timeout - Break DC motor 0 0 0 0 - - - - Wait for DIR event (High) 0 1 0 0 - - - - Wait for DIR event (Low) 0 0 0 0 - - - + Re-Start motion 0 0 0 0 - + - + Motion in progress 0 0 0 1 - + - - Timeout - Brake DC motor Example of normal Initialization 0 0 0 0 - - - - Rest position 1 1 0 + - - - Break DC motor, wait 31 ms 0 0 0 1 - + - - Timeout - Brake DC motor 0 0 1 0 + - - - Brake DC motor, wait 31 ms 0 0 0 0 0 - + - - Brake DC motor, wait 31 ms Example of normal run with inverted DIR logic 1 0 0 0 - - - - Rest position 1 1 0 0 - - + - Start motion 1 1 0 0 + - + - Motion in progress 1 1 1 0 + - - - Brake DC motor, wait 31 ms LOW =0 LOW =0 LOW =0 0 = No HIGH = 1 HIGH = HIGH = 1 Timeout 1 1 = Timeout Note: OUT A = - and OUT B = - is called “braking” the DC motor Table 3.4.2-2 State Table for triggered Shutdown Mode Page 13 of E192.01 QM-No.: 18 DC Motor Full Bridge 1A 25DS0008E.00 DATA SHEET Jul 25, 2011 3.2.3 One-shot retriggerable Timer The pin RC provides a terminal for an external resistor that determines the frequency of an internal oscillator. The delay time T1 (1s or 2s) of the one-shot retriggerable Timer is generated digitally from its output frequency. Also the time D2 (31 ms) is generated from this oscillator output. 3.2.4 Voltage clamp for the Hall Cell HALLSUP The IC contains a clamped 12V voltage supply. It is used as the supply voltage source for an Allegro 3281 series Hall Cell for protecting it against voltages higher than 16V. 3.2.5 Buffered shutdown trigger output TRIGOUT In normal operation, a Hall Cell open-collector output feeds the pin TRIGIN. This Hall Cell is also responsible for providing position information to an external control module (customer interface). This externally reported position requires an open-collector output. In order to avoid contention at the Hall Cell’s open-collector output due to the interaction of the IC’s internal pull-up on the TRIGIN pin and the pull-up at the customer interface (for position reporting), a buffered/isolated Hall Cell output is provided by the pin TRIGOUT. 3.2.6 Over Temperature, Over Voltage and Under Voltage Shutdown The IC monitors the temperature and VSUP, the voltage on the VSUP pin and protects itself against conditions out of the normal operating limits. In particular the following three conditions are continuously monitored: Over-temperature, Under Voltage, and Over Voltage. The fault strategy includes non-latching and self-clearing strategy for recovery. The function of the TRIGOUT pin is not effected by any fault conditions. It remains valid. The response of all fault conditions is delayed by the debouncing time t , bfault so that short glitches have no impact on the application. In the event of an Over Temperature condition, the IC disables the four drivers of the H-bridge output to avoid damage due to excessive current. The control logic ignores processing of the DIR, TRIGIN, and One-shot Timer activity. Upon clearing of the fault condition, the IC carries out a Power-On-Reset and arm the One-shot Timer prior to any processing of the DIR or TRIGIN signals. The IC resumes immediately if the Tj is lower than TSD and the fault is clear. The Over Voltage event is detected, if the VSUP is higher than the VthOVLO. In order to protect the high side drivers the IC shuts down only these. That means if the IC is in „brake„-mode, nothing changes. If the IC is in „driving„-mode, one side of the H-bridge is high Z and the timer is frozen. This behavior reduces the effect of an Over Voltage event on the application to a minimum. The control logic ignores processing of the DIR, TRIGIN, and One-shot Timer activity. The IC resumes immediately if VSUP is lower than VthOVLO and the fault is cleared. The Under Voltage event is detected, if the VSUP is lower than the VthUVLO. The IC disables the high side drivers of the H-bridge and brakes the motor. The control logic ignores processing of the DIR, TRIGIN, and One-shot Timer activity. Upon clearing of the fault condition, the IC arms the One-shot Timer prior to any processing of the DIR or TRIGIN signals. The IC resumes immediately if VSUP is larger than VthUVLO and the fault is cleared. Page 14 of E192.01 QM-No.: 18 DC Motor Full Bridge 1A 25DS0008E.00 DATA SHEET Jul 25, 2011 Conditions H-bridge Comments Over Under Over State before trouble State after trouble Temperature Voltage Voltage OUTA OUTB Motor OUTA OUTB Motor - - - H L + H L + Motor runs positive - - - L H - L H - Motor runs negative L L Brake L L - - - Brake Motor is braked X X X Z Z + X X Z IC in RESET H L + L L - + - Brake Motor is braked - + - L H - L L Brake Motor is braked - + - L L Brake L L Brake Motor is braked - - + H L + Z L Z Motor is free - - + L H - L Z Z Motor is free L L Brake L L - - + Brake Motor is braked Tab. 3.2.6-1: Effect of trouble conditions on the motor. OUTX=H means VOUTX=VSUP, OUTX=L means VOUTX=GND, OUTX=Z means H-bridge in high Z. 3.2.7 Test modes The IC provides three test modes, which eases the test and measurement of the IC. The test modes are accessed by positive transitions on the TESTIN pin. Although there is a 30μA pull down integrated it is strongly recommended to connect the TESTIN pin in the final application to GND! Test mode Access code/ condition Description In this test mode TRIGOUT doesn’t show an image of TRIGIN, but is #1 One positive transition the output of an exor-chain. Connected to this exor-chain are all input on TESTIN Schmitt-triggers and the comparator outputs for under voltage, over voltage and over temperature monitoring. Thus all thresholds can be measured in this test mode. Staying in test mode #1 the threshold of the over temperature Thermal Force a current of 0 … monitoring can be reduced by forcing a current in the TESTIN pin. The shutdown 2mA in the TESTIN pin ratio between the pull down current and this forced current is a threshold measure for the shut down temperature. See description below. nd In this test mode one half of the H-bridge is disabled. Pin 12 and 25 #2 2 positive transition on remain in high-Z state and it is possible to use these pins as sense TESTIN connections to the driver transistor on pin 7 and 30 since internal resistors connect pin 7 to pin 12 and pin 25 to 30. Moreover there are resistors between the supply pins 13 and 7 as well as between 24 and 31. So by using pin 6 and 31 as supply pins only the pins 13 and 24 as sense pins, which make an accurate measurement of the high side driver on resistance possible. For the low side drivers one of the GND may be used as sense pin. The oscillator frequency (divided by 32) can be measured on the TRIGOUT pin. rd In this test mode the internal oscillator is disabled, a power on reset is #3 3 positive transition on performed (except for the test mode control logic) and the 32-bit TESTIN oscillator frequency divider is bypassed. The RC pin serves as input for the external clock. This test mode is designed for a fast digital pattern test. th The IC will return to normal mode. Normal 4 positive transition on TESTIN Tab. 3.2.7-1: Test mode functions and access pattern In test mode #1 the thermal shutdown threshold can be measured by forcing a certain current in the TESTIN pin. This current reduces the thermal shutdown threshold to the current test temperature T . test Page 15 of E192.01 QM-No.: 18 DC Motor Full Bridge 1A 25DS0008E.00 DATA SHEET Jul 25, 2011 With I = forced current for reducing the threshold, I = pull down current of the TESTIN pin, force pdTEST T = real thermal shut down temperature without a forced current and sdH T = real thermal recovery temperature without a forced current sdL I − I I − I force pdTEST force pdTEST T = X ⋅ T T = X ⋅ T sdH H test sdL L test I I pdTEST pdTEST The constants X and X are around 6°C and must be verified during qualification. H L 3.3 Application Circuit Off VBAT board D S C SUP ZD SUP 40V HALLSUP VSUP C HALLSUP Off R TRIGOUT board 220nF 10 TRIGOUT TRIGIN Hall Cell 100nF 40V INVDIR C TRIGOUT ZD TRIGOUT MODE OUTA Off R DIR Cmot board Dir 10k DIR 100nF Command OUTB RC R ext C DIR D.C.BRUSH MOTOR GND 200k Figure 3.3-1 Application diagram of the IC, CDIR is optional, for the protection circuitry refer to chapter 4.4. 3.3.1 Application notes This IC is designed for conditions described in chapter 2.1 and 2.2. If the electrical environment is rougher than specified in chapter 2.1 a sufficient protection circuitry is required to absorb destructive energies off the IC. Please refer to figure 4.3-1 and to chapter 4.4. For proper operation of the IC the use of the devices RDIR, ZDTRIGOUT and ZDSUP is strongly recommended. The capacitor across the DC motor is required. Page 16 of E192.01 QM-No.: 18 DC Motor Full Bridge 1A 25DS0008E.00 DATA SHEET Jul 25, 2011 3.4 Noise Immunity The application with the E192.01 is designed to meets the following requirements of ISO 7637: VSUP Parameter Condition Cycles Coupling Comment Pulse 1 t = 5s / U = -100V 100 pulses direct A serial (DS) protection diode is required. A 1 S parallel capacitor (CSUP) is recommended. Pulse 2 t = 0,5s / U = 100V 1000 pulses direct A Zener-Diode (ZDSUP) is required. 1 S 23 ) Pulse 3a/b ISO 7637 1000 Bursts direct A serial protection diode (DS) and a Zener- Diode (ZDSUP) is required. A parallel U = -150V / U = 100V S S capacitor (CSUP) is strongly recommended. 15 ) Pulse 4 U = -6V / U = -5V 10 pulses direct A serial protection diode (DS) is required s a t = 5s 8 Pulse 5 R = 2Ω, t = 250ms 10 pulses at direct A Zener-Diode (ZDSUP) is required. A i D t = 0,1ms U +U = 40V 1 minute parallel capacitor (CSUP) is recommended. r P S 15 intervals ) Tab. 3.4-1 Schaffner-Pulses 1, 2, 3, 4 and 5 applicable to battery lines DIR Parameter Condition Cycles Coupling Comment Pulse 3a/b ISO 7637 1000 Bursts resistive A serial protection resistor (RDIR≥10kΩ) is U = -150V / U = 100V required. S S 40V for 2min single pulses resistive A serial protection resistor (RDIR) is 50V for 500ms recommended. Tab. 3.4-2 Noise immunity of pin DIR TRIGOUT Parameter Condition Cycles Coupling Comment Pulse 3a/b DIN 40 839 Part 3 1000 Bursts capacitive, A serial protection resistor (RTRIGOUT) + a U = -150V / U = 100V via 4.7nF capacitor (CTRIGOUT=22nF for a couple S S capacitor of 4.7nF) is recommended. Alternatively a Zener-Diode (ZDTRIGOUT) is 15 24 recommended. ) ) 15 Pulse 3a/b DIN 40 839 Part 3 1000 Bursts direct A Zener-Diode (ZDTRIGOUT) is required. ) U = -150V / U = 100V S S 40V for 2min single resistive A serial protection resistor (RTRIGOUT) is 50V for 500ms pulses recommended. Tab. 3.4-3 Noise immunity of pin TRIGOUT 23 ) The Zener Diode should have a clamping voltage of about 30 to 45V. 24 ) The expenditure of external protection circuitry is depending on the size of the couple capacitor, thus on the energy reaching the IC. Page 17 of E192.01 QM-No.: 18 DC Motor Full Bridge 1A 25DS0008E.00 DATA SHEET Jul 25, 2011 3.5 ESD Protection VDD VSUP DIR VSUP TRIGOUT INVDIR OUTA HALLSUP RC OUTB TESTIN TRIGIN MODE Fig. 3.5-1 ESD-Structures Test Method: The ESD Protection circuitry is measured using „Human Body Model“ (JESD22A114A) and „Machine Model“ (JESD22A115A) with the following conditions: Human Body Model Machine Model Unit VIN 2000 200 V REXT 1500 0 Ω CEXT 100 200 pF Tab. 3.5-1 ESD-Test Models 4 Handling, Packing 4.1 Handling Devices are sensitive to damage by Electro- Static Discharge (ESD) and should only be handled at an ESD protected workstation. 4.2 Packing SMD devices are taped in acc. to DIN IEC 286 part3. JEDEC A112 Level 3 SMD devices are dry packed. Page 18 of E192.01 QM-No.: 18 DC Motor Full Bridge 1A 25DS0008E.00 WARNING – Life Support Applications Policy ELMOS Semiconductor AG is continually working to improve the quality and reliability of its products. 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