Board Type

VME

Counter/Timers/Interrupts

The BajaPPC-750 uses a programmable logic device (PLD) to implement two general purpose 31-bit counter/timers and an interrupt controller.

CPU

The CPU is an IBM PowerPC microprocessor running internally at 366 MHz or higher. The PPC750 has 32-kilobyte data and instruction caches, three instructions per clock cycle, and a 32/64-bit data bus mode.

EPROM

The BajaPPC-750 has a 32-pin PLCC socket with a 512-kilobyte EPROM or flash memory capacity. ROM access and control functions are provided by the Motorola MPC106 memory controller.

Ethernet

The BajaPPC-750 employs the Intel (formerly DEC) 21143 PCI/CardBus 10/100-Mb/s Ethernet LAN Controller, which interfaces directly to the PCI local bus. The 21143 is fully compliant with the IEEE 802.3 100BASET draft for Fast Ethernet.

L2 Cache

A 1-megabyte Level 2 cache is provided by two synchronous random access memory (SRAM) devices running at 122 MHz or higher. The cache has zero wait state performance (2-1-1-1 burst) with a two-way set associative cache design.

LED

The BajaPPC-750 features a 7-segment LED display on the front panel that is oriented so it can be read when the board is vertically mounted.

Mailbox Interrupts

Mailbox interrupts allow the BajaPPC-750 to be controlled remotely from specific VMEbus addresses. This feature supports CPU interrupt and VMEbus lock functions.

Parallel Port

The SMC FDC37C935 Ultra I/O chip also provides a parallel port for the BajaPPC-750 on row C of connector P2 (optional configuration only).

PMC Modules

PCI Mezzanine Card (PMC) interface is a 32-bit interface that allows you to customize the BajaPPC-750 by adding plugover modules. The plugover modules are based on the Peripheral Component Interconnect (PCI) standard. The BajaPPC-750 accepts two single-width or one doublewidth PMC modules with I/O on the front panel and connector P2.

Processor

IBM PowerPC PPC750

Rest/Interrupt Switch

The BajaPPC-750 has a two-position momentary toggle switch. In the reset position, this switch resets the board (and the VMEbus when the board is the system controller). In the interrupt position, it provides a user-definable debug tool.

SDRAM

The BajaPPC-750 may be populated with 32, 64, 128, or 256 megabytes of 64-bit wide synchronous DRAM. Refresh and other control functions are provided by the Motorola MPC106 “Grackle” memory controller.

Serial Interface

The BajaPPC-750 provides two 16C550-compatible serial ports by means of the SMC FDC37C935 Ultra I/O chip. This device is a versatile I/O controller that resides on the ISA bus. A Winbond Systems Laboratory W83C553F chip bridges the PCI and ISA busses.

User Flash

The BajaPPC-750 allows for 12 megabytes of user flash to support the PowerPC CPU. The MPC106 memory controller has four megabytes of paged flash (512 kilobytes per page) on its 8-bit ROM bus, as well as eight megabytes of flash on its 64-bit ROM bus.

VMEbus

The PCI to VME interface for the BajaPPC-750 is provided by a Tundra Universe II (CA91C142) chip, which has built-in FIFOs and full VME64 master/slave capability with DMA. The VMEbus has a 32-bit address bus with 16-, 24-, or 32-bit address modes (4-gigabyte range) and a 32-bit data bus with 8-, 16-, 24-, 32-, or 64-bit board compatibility. The board supports all seven VMEbus interrupts.