This product is obsolete. This information is available for your convenience only. For more information on Zarlink’s obsolete products and replacement product lists, please visit http://products.zarlink.com/obsolete_products/ Obsolescence Notice MH88435-P Data Access Arrangement Data Sheet August 2006 Features • FAX and Modem interface V.34(33k6) Ordering Information • Externally programmable line and network MH88435AD-P1 28 Pin DIL* Boxed balance impedances • Programmable DC termination characteristics *Pb Free Matte Tin • IEC950 recognised component 0°C to +70°C • Transformerless 2-4 Wire conversion Applications • Integral Loop Switch • Dial Pulse and DTMF operation Interface to Central Office or PABX line for: • Accommodates parallel phone detection • FAX/Modem (including software modems) • Line state detection outputs:- • Electronic Point of Sale loop current/ringing voltage/line voltage • Security System • Single +5 V operation, low on-hook power • Telemetry (35 mW) •Set Top Boxes • Full duplex voice and data transmission • On-Hook reception from the line • Approvable to UL1950 • Industrial temperature range available Isolation Barrier VCC VBIAS Opto- Logic Input AGND Isolation Buffer LC Input Buffer TIP VR+ & Analog Isolation Line Termination RING Buffer VR- NB1 NB2 THL cancellation VX and line Analog Isolation Buffer impedance ZA matching circuit VLOOP1 RV Ring & Loop VLOOP2 Isolation LCD Buffer LOOP RS Network Connections User Connections Figure 1 - Functional Block Diagram 1 Zarlink Semiconductor Inc. Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 2001-2006, Zarlink Semiconductor Inc. All Rights Reserved. MH88435-P Data Sheet Description The Zarlink MH88435 Data Access Arrangement (D.A.A.) provides a complete interface between audio or data transmission equipment and a telephone line. All functions are integrated into a single thick film hybrid module which provides high voltage isolation, very high reliability and optimum circuit design, needing a minimum of external components. The impedance and network balance are externally programmable, as are the DC termination characteristics, making the device suitable for most countries worldwide. NB1 1 TIP 28 2 NB2 27 RING VR+ IC 3 26 VR- 4 25 VLOOP1 VX 5 24 VLOOP2 LC 6 23 IC 7 22 SC ZA AGND 8 21 SC 9 VCC 20 IC 10 VBIAS 19 NP 11 18 NP LOOP 12 IC 17 IC RS 13 16 RV IC 14 15 LCD Figure 2 - Pin Connections Pin Description Pin # Name Description 1NB1 Network Balance 1. External passive components must be connected between this pin and NB2. 2NB2 Network Balance 2. External passive components must be connected between this pin and NB1. 3VR+ Differential Receive (Input). Analog input from modem/fax chip set. 4VR- Differential Receive (Input). Analog input from modem/fax chip set. 5VX Transmit (Output). Ground referenced (AGND) output to modem/fax chip set, biased at +2.0 V. 6LC Loop Control (Input). A logic 1 applied to this pin activates internal circuitry which provides a DC termination across Tip and Ring. This pin is also used for dial pulse application. 7ZA Line Impedance. Connect impedance matching components from this pin to Ground (AGND). 8 AGND Analog Ground. 4-Wire ground. Connect to earth. 9V Positive Supply Voltage. +5 V. CC 10 VBIAS Internal Reference Voltage. +2.0 V reference voltage. This pin should be decoupled externally to AGND, typically with a 10 µF 6.3 V capacitor. 11 LOOP Loop (Output). The output voltage on this pin is proportional to the line voltage across Tip - Ring, scaled down by a factor of 50. 2 Zarlink Semiconductor Inc. MH88435-P Data Sheet Pin Description (continued) 12, IC Internal Connection. No connection should be made to this pin externally. 14, 17, 20, 23, 26 13 RS Ringing Sensitivity. Connecting a link or resistor between this pin and LOOP (pin 11) will vary the ringing detection sensitivity of the module. 15 LCD Loop Condition Detect (Output). Indicates the status of loop current. 16 RV Ringing Voltage Detect (Output). The RV output indicates the presence of a ringing voltage applied across the Tip and Ring leads. 18, 19 NP No Pin. Isolation barrier, no pin fitted in this position. 21, 22 SC Short Circuit. These two pins should be connected to each other via a 0 Ω link. 24 VLOOP2 Loop Voltage Control Node 2. Used to set DC termination characteristics. 25 VLOOP1 Loop Voltage Control Node 1. Used to set DC termination characteristics. 27 RING Ring Lead. Connects to the “Ring” lead of the telephone line. 28 TIP Tip Lead. Connects to the “Tip” lead of the telephone line. Functional Description The device is a Data Access Arrangement (D.A.A.). It is used to correctly terminate a 2-Wire telephone line. It provides a signalling link and a 2-4 Wire line interface between an analog loop and subscriber data transmission equipment, such as Modems, Facsimiles (Fax’s), Remote Meters, Electronic Point of Sale equipment and Set Top Boxes. Isolation Barrier The device provides an isolation barrier capable of meeting the supplementary barrier requirements of the international standard IEC 950 and the national variants of this scheme such as EN 60950 for European applications and UL 1950 for North American applications and is classified as a Telecom Network Voltage (TNV) circuit. External Protection Circuit An External Protection Circuit assists in preventing damage to the device and the subscriber equipment, due to over-voltage conditions. See Application Note, MSAN-154 for recommendations. Suitable Markets The MH88435 has features such as programmable input and network balance impedance, programmable DC termination and a supplementary isolation barrier that makes it ideal for use throughout the world. There are a small number of countries with a 100 MW leakage requirement that this device does not meet. These are Belgium, Greece, Italy, Luxembourg and Spain. France’s current limit specification and Germany’s dial pulse requirements are met by the MH88437. This device is pin for pin compatible with the MH88435. 3 Zarlink Semiconductor Inc. MH88435-P Data Sheet Approval specifications are regularly changing and the relevant specification should always be consulted before commencing design. Line Termination When Loop Control (LC) is at a logic 1, a line termination is applied across Tip and Ring. The device is off-hook and DC loop current will flow. The line termination consists of both a DC line termination and an AC input impedance. It is used to terminate an incoming call, seize the line for an outgoing call, or if it is applied and disconnected at the required rate, can be used to generate dial pulses. The DC termination is approximately 300 Ω resistance, which is loop current dependent. It can be programmed to meet different national requirements. For normal operation Pin 22 and Pin 21 should be linked, and a resistor (R2) should be fitted between VLOOP1 and VLOOP2 as shown in Figure 5. The approval specification will give a DC mask characteristic that the equipment will need to comply to. The DC mask specifies the amount of current the DAA can source for a given voltage across tip and ring. Figure 3 shows how the voltage across tip and ring varies with different resistors (R2) for a given loop current. The AC input impedance should be set by the user to match the line impedance. 30 25 20 Iloop=26mA Iloop=20mA V(t-r) 15 Iloop=15mA 10 5 0 200 600 1000 1400 1800 2200 2600 3000 3400 3800 R2(kOhms) Figure 3 - DC Programming Capabilities Input Impedance The MH88435 has a programmable input impedance set by fitting external components between the ZA pin and AGND. For complex impedances the configuration shown in Figure is most commonly found. 4 Zarlink Semiconductor Inc. MH88435-P Data Sheet ZA R2 R1 C1 Figure 4 - Complex Impedances To find the external programming components for configuration 4, the following formula should be used: Zext = [(10 x R1)-1k3]+ [10 x R2)//(C1/10)] e.g., If the required input impedance = 220W + (820W//115nF), the external network to be connected to ZA will be: Zext = 900Ω + (8k2Ω//12nF) Where the input impedance (Z) = 600R the equation can be simplified to: Zext = (10 x Z) - 1k3Ω Zext = 4k7Ω Note: A table of commonly used impedances can be found in the DAA Application’s document MSAN-154. Zext = external network connected between ZA and AGND, Zint = 1.3kΩ (internal resistance). Network Balance The network balance impedance of the device can be programmed by adding external components between NB1 and NB2. For countries where the balance impedance matches the line impedance, a 15 kΩ resistor should be added between NB1 and NB2. Ringing Voltage Detection The sensitivity of the ringing voltage detection circuitry can be adjusted by applying an external resistor between the RS and LOOP pins. With a short circuit, the threshold sensitivity is ~10 Vrms R7 can be calculated using the equation: R7 = 30 kΩ x (Desired Threshold Voltage - 10Vrms) Therefore, 300k kΩ gives ~ 20Vrms and 600k kΩ gives ~ 30Vrms An AC ringing voltage across Tip and Ring will cause RV to output TTL pulses at the ringing frequency, with an envelope determined by the ringing cadence. 5 Zarlink Semiconductor Inc. MH88435-P Data Sheet Parallel Phone and Dummy Ringer An external parallel phone or dummy ringer circuit can be connected across Tip and Ring as shown in Figure 5. A dummy ringer is an AC load which represents a telephone’s mechanical ringer. In normal circumstances when a telephone is on-hook and connected to the PSTN, its AC (Ringer) load is permanently presented to the network. This condition is used by many PTT’s to test line continuity by placing a small AC current onto the line and measuring the voltage across tip (A) and ring (B). Today’s telecom equipment may not have an AC load present across tip and ring (e.g., modems), therefore any testing carried out by the PTT will see an open circuit across tip and ring. In this instance the PTT assumes that the line continuity has been damaged. To overcome this problem many PTT’s specify that a "Dummy Ringer" is presented to the network at all times. Ideally its impedance should be neglible in the audio band, and high at the ringing frequencies (e.g., 25Hz). Note that the requirement for the "Dummy Ringer" is country specific. Parallel phone detection is used mostly in set-top box applications. This is when a modem call will need to be disconnected from the central office by the equipment when the parallel phone is in the off-hook state. This is so that a call can be made to the emergency services. To detect this state, additional circuitry will be required and can be found in the application note, MSAN-154. 2-4 Wire Conversion The device converts the balanced 2-Wire input, presented by the line at Tip and Ring, to a ground referenced signal at VX, biased at 2.0 V. This simplifies the interface to a modem chip set. Conversely, the device converts the differential signal input at VR+ and VR- to a balanced 2-Wire signal across Tip and Ring. The device can also be used in a single ended mode at the receive input, by leaving VR+ open circuit and connecting the input signal to VR- only. Both inputs are biased at 2.0 V. During full duplex transmission, the signal at Tip and Ring consists of both the signal from the device to the line and the signal from the line to the device. The signal input at VR+ and VR- being sent to the line, must not appear at the output VX. In order to prevent this, the device has an internal cancellation circuit. The measure of this attenuation is Transhybrid Loss (THL). The MH88435 has the ability to transmit analog signals from Tip and Ring through to VX when on-hook. This can be used when receiving caller line identification information. Transmit Gain The Transmit Gain of the MH88435 is the gain from the differential signal across Tip and Ring to the ground referenced signal at VX. The internal Transmit Gain of the device is fixed as shown in the AC Electrical Characteristics table. For the correct gain, the Input Impedance of the MH88435, must match the specified line impedance. By adding an external potential divider to VX, it is possible to reduce the overall gain in the application. The output impedance of VX is approximately 10 Ω and the minimum resistance from VX to ground should be 2 kΩ. Example: If R3 = R4 = 2kΩ, in Figure 5, the overall gain would reduce by 6.0 dB. Receive Gain The Receive Gain of the MH88435 is the gain from the differential signal at VR+ and VR- to the differential signal across Tip and Ring. The internal Receive Gain of the device is fixed as shown in the AC Electrical Characteristics table. For the correct gain, the Input Impedance of the MH88435 must match the specified line impedance. 6 Zarlink Semiconductor Inc. MH88435-P Data Sheet With an internal series input resistance of 47 kΩ at the VR+ and VR- pins, external series resistors can be used to reduce the overall gain. Overall Receive Gain = 0dB + 20log (47kΩ / (47kΩ+R5)). For differential applications R6 must be equal to R5 in Figure 5. Example: If R5 = R6 = 47k in Figure 5, the overall gain would reduce by 6.0dB. Supervisory Features The device is capable of monitoring the line conditions across Tip and Ring, this is shown in Figure 5. The Loop Condition Detect pin (LCD), indicates the status of the line. The LCD output is at logic 1 when loop current flows, indicating that the MH88435 is in an off-hook state. LCD will also go high if a parallel phone goes off-hook while the DAA is on-hook. Therefore, line conditions can be determined with the LC and the LCD pins. The LOOP pin output voltage, VLoop, is proportional to the line voltage across Tip and Ring, V (t-r), scaled down by a factor of 50 and offset by VBias which is approximately 2V. With the aid of a simple external detector the LC, LCD and LOOP pins can be used to generate the signals necessary for parallel phone operation with a Set Top Box. Refer to MSAN-154. If Tip is more positive than ring VLoop < VBias If Tip is more negative than ring VLoop > VBias V (t-r) ª (VLoop - VBias) * 50 When the device is generating dial pulses, the LCD pin outputs TTL pulses at the same rate. The LCD output will also pulse if a parallel phone is used to pulse dial and also when ringing voltage is present at Tip and Ring. Mechanical Data See Figure 12 for details of the mechanical specification. 7 Zarlink Semiconductor Inc. MH88435-P Data Sheet +5V R7 R2 C2 + 11 9 25 24 22 21 13 R4 R3 C3 28 5 Analog TIP TIP VX Output R5 C4 4 Analog VR- L2 Input R1 3 R6 C5 MH88435 Analog VR+ Input D1 D2 16 RV Ringing Voltage Detect Output 15 LCD Loop Current Detect Output C1 6 C8 LC Loop Control Input L1 1 27 NB1 RING RING ZB 2 NB2 AGND VBIAS ZA 8 10 7 C7 Notes: 1) R1 & C1: Dummy Ringer, country specific typically 0.39 µF, 250 V & 3 kΩ C6 Zext + 2) R2: DC Mask Resistor typical 360 kΩ 3) R3 & R4: Transmit Gain Resistors ≥ 2k2 4) R5 = R6: Receive Gain Resistors typically 100 k 5) ZB: Network Balance Impedance 6) C2, C6 = 10 µF 6 V 7) C7 & C8 = 39 nF for 12 kHz filter and 22 nF for 16 KHz filter. These can be left off if meter pulse filtering not required. 8) Zext: External Impedance 9) D1 Zener Diode 6V2 10) L1, L2 = 4m7H 80 mA. These can be left off if = Ground (Earth) meter pulse filtering not required. 11) C3, C4 & C5 = 1 µF coupling capacitors 12) R7 = 620kΩ (30 V RMS ringing sensitivity) 13) D2 = Teccor P3100SB Figure 5 - Typical Application Circuit 8 Zarlink Semiconductor Inc. VCC VLOOP1 VLOOP2 RS LOOP MH88435-P Data Sheet . Absolute Maximum Ratings* - All voltages are with respect to AGND unless otherwise specified. Parameter Sym.Min.Max. Units Comments 1 DC Supply Voltage V -0.3 6 V CC 2 Storage Temperature T -55 +125 °C S 3 DC Loop Voltage V -110 +110 V BAT 4 Ringing Voltage V 150 Vrms VBAT = -56V R 5 Loop Current I 90 mA Loop 6 Ring Trip Current I 180 mA 250 ms 10% duty cycle or TRIP rms 500 ms single shot *Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied. Recommended Operating Conditions ‡ Parameter Sym. Min. Typ. Max. Units Test Conditions V 1 DC Supply Voltages V 4.75 5.0 5.25 CC 2 Operating Temperatures T 0 25 70 °C OP Industrial Temperature -40 +85 3 Ringing Voltage V 75 90 Vrms R ‡ Typical figures are at 25°C with nominal +5V supply and are for design aid only † - Loop Electrical Characteristics ‡ Characteristics Sym. Min. Typ. Max. Units Test Conditions 1 Ringing Voltage threshold VR Externally Adjustable 710 14 Vrms 2 Ringing Frequency 15 68 Hz 3 Operating Loop Current 15 80 mA Note 3 4 Off-Hook DC Voltage Test circuit as Fig. 4 Tip/Ring 6.0 V I =15mA )Note 1 Loop 6.0 V I =20mA )where R2 Loop 7.8 V =I =26mA ) 360kΩ Loop 5 Leakage Current 10 µA 100V DC Note 2. (Tip or Ring to AGND) 7 mA 1000V AC rms 6 Leakage Current on-hook 910 µAV = -50V BAT (Tip to Ring) 7 Dial Pulse Delay ON 0 +2 +4 ms OFF 0 +2 +4 ms 8 Loop Condition Detect Threshold 516 Voltage across tip and Off-Hook V ring † Electrical Characteristics are over Recommended Operating Conditions unless otherwise stated. ‡Typical figures are at 25°C with nominal + 5 V supplies and are for design aid only. Note 1: Refer to EIA/TIA 464 section 4.1.1.4.4. Note 2: This is equivalent to 10 MΩ leakage Tip/Ring to Ground. For countries requiring 100 MΩ leakage use the MH88436 with an enhanced leakage specification. Note 3: Operation at low loop currents depends on the DC programming resistor between VLoop1/2. The recommended 360K value will support V34 operation down to 20 mA. Voice operation is supported down to 15 mA. 9 Zarlink Semiconductor Inc. MH88435-P Data Sheet † DC Electrical Characteristics ‡ Characteristics Sym. Min. Typ. Max. Units Test Conditions 1 Supply Current I 7mAVCC = 5.0V, On-hook CC 2RV, Low Level Output Voltage V 0.4 V I = 4mA OL OL LCD High Level Output Voltage V 2.4 V I = 0.4mA OH OH 3 LC Low Level Input Voltage V 0.8 V IL 2.0 High Level Input Voltage V V IH Low Level Input Current I 0 10 µA V = 0.0V IL IL High Level Input Current I 350 400 µA V = 5.0V IH IH † Electrical Characteristics are over Recommended Operating Conditions unless otherwise stated. ‡Typical figures are at 25°C with nominal + 5V supplies and are for design aid only. † AC Electrical Characteristics ‡ Characteristics Sym. Min. Typ. Max. Units Test Conditions 1 Input Impedance VR- 47k Ω VR+ 94k Ω 2 Output Impedance at VX 10 Ω 3 Receive Gain (VR to 2-Wire) -1 0 1 dB Test circuit as Fig. 8 Input 0.5V at 1kHz 4 Frequency Response Gain -0.5 +0.4 +0.5 dB 300Hz (relative to Gain @ 1kHz) -0.5 0 +0.5 dB 3400Hz 5 Signal Output Overload Level THD < 5% @ 1kHz at 2-Wire 0 dBm I = 25-75mA LOOP at VX 0 dBm SINAD 6 Signal/Noise & Distortion Input 0.5V at 1kHz at 2-Wire 70 dB I = 25-75mA LOOP at VX 70 dB 300-3400Hz 7 Power Supply Rejection Ratio PSRR Ripple 0.1Vrms 1kHz on at 2-Wire 25 40 dB V CC at VX 25 40 dB 8 Transhybrid Loss THL 16 25 dB Test circuit as Fig.8 300-3400Hz at V R 9 2-Wire Input Impedance Zin Note 3 Ω @1kHz 10 Return Loss at 2-Wire RL Test circuit as Fig. 9 (Reference 600Ω) 14 20 dB 200-500Hz 20 24 dB 500-2500Hz 18 24 dB 2500-3400Hz 11 Longitudinal to Metallic Balance Test circuit as Fig. 10 46 65 dB 300-1000Hz 46 65 dB 1000-3400Hz Metallic to Longitudinal Balance Test circuit as Fig.11 60 68 dB 200-1000Hz 40 62 dB 1000-4000Hz 10 Zarlink Semiconductor Inc. MH88435-P Data Sheet † AC Electrical Characteristics ‡ Characteristics Sym. Min. Typ. Max. Units Test Conditions 12 Idle Channel Noise Nc at 2-Wire 10 20 dBrnC Cmess filter at VX 10 20 dBrnC at 2-Wire -80 dBm 300-3400Hz filter at VX -80 dBm 13 Transmit Gain (2-Wire to VX) Test circuit as Fig. 7 (Terminated gain) Off-Hook -1 0 +1 dB Input 0.5V @ 1kHz (Voltage gain) On-Hook 0 dB LC = 0V 14 Frequency Response Gain -1 +0.3 +1 dB 300Hz (relative to Gain @ 1kHz) -1 +0.2 +1 dB 3400Hz IMD 15 Intermodulation Distortion 60 dB I = 25-75mA LOOP products at VX and 2W F1 = 1kHz at -6dBm F2 = 800Hz at -6dBm Total signal power = -3dBm 16 Distortion at VX due to near end echo 75 dB I = 25-75mA LOOP (300Hz - 3400Hz bandwidth) F1 = 1kHz at -6dBm F2 = 800Hz at -6dBm Total signal power = -3dBm CMRR 17 Common Mode Rejection on 2 wire at 56 dB Test circuit as Fig. 10 VX 1-100Hz. Note 4 CMOL 18 Common Mode overload level 7 Vrms Test circuit as Fig. 10. Note 4 † Electrical Characteristics are over Recommended Operating Conditions unless otherwise stated. ‡Typical figures are at 25°C with nominal +5V and are for design aid only. Note 1: All of the above test conditions use a test source impedance which matches the device’s impedance. Note 2: dBm is referenced to 600Ω unless otherwise stated. Note 3: These parameters need to be taken into consideration when designing or specifying the power supply. 11 Zarlink Semiconductor Inc. MH88435-P Data Sheet 11 13 15 LOOP RS LCD ILOOP 3 28 VR+ TIP 4 1 VR- NB1 MH88435 5 VX 15K 21 2 SC NB2 22 SC 27 RING 360K 24 VLOOP2 10 25 VBIAS VLOOP1 10uF LC RV AGND VCC ZA 616 8 9 7 1K 4.7K 5V = Ground (Earth) 5V Figure 6 - Test Circuit 1 12 Zarlink Semiconductor Inc. MH88435-P Data Sheet -V 10H 500Ω 11 13 15 100uF LOOP RS LCD = Ground (Earth) 3 I=20mA 28 VR+ TIP + 4 1 VR- NB1 MH88435 5 VX 15K Vs 21 2 SC NB2 Impedance = Zin 22 SC 100uF 27 RING + 360K 24 10H 500Ω VLOOP2 10 25 VBIAS VLOOP1 10uF LC RV AGND VCC ZA 7 616 8 9 1K 4.7K 5V 5V Gain = [20 * Log (VX / Vs)] + 6.02 dB Figure 7 - Test Circuit 2 -V = Ground (Earth) 10H 500Ω 11 13 15 100uF LOOP RS LCD I=20mA 3 28 VR+ TIP + Vs 4 1 VR- NB1 MH88435 5 VX 15K Zin 21 2 NB2 SC 22 SC 100uF 27 RING + 360K 24 VLOOP2 10H 500Ω 10 25 VBIAS VLOOP1 10uF LC RV AGND VCC ZA 616 8 9 7 1K 4.7K 5V 5V Gain = 20 * Log (V(Zin) / Vs) Figure 8 - Test Circuit 3 13 Zarlink Semiconductor Inc. MH88435-P Data Sheet -V 10H 500Ω = Ground (Earth) 11 13 15 I=20mA 100uF LOOP RS LCD Zin 3 28 VR+ TIP + 4 1 VR- NB1 300Ω V1 MH88435 5 Vs = 0.5V VX 15K 21 2 NB2 SC 300Ω 22 SC 100uF 27 RING + 360K 10H 500Ω 24 VLOOP2 10 25 VBIAS VLOOP1 10uF LC RV AGND VCC ZA 616 8 9 7 1K 4.7K 5V 5V Return Loss = 20 * Log (2V1 / Vs) Figure 9 - Test Circuit 4 -V 10H 500Ω = Ground (Earth) 11 13 15 100uF I=20mA LOOP RS LCD 3 28 VR+ TIP + 4 1 VR- NB1 MH88435 300Ω 5 VX 15K V1 21 2 SC NB2 Vs = 0.5V 300Ω 22 SC 100uF 27 RING + 360K 24 10H 500Ω VLOOP2 V2 10 25 VBIAS VLOOP1 10uF LC RV AGND VCC ZA 9 616 8 7 1K 4.7K 5V 5V Long. to Met. Balance = 20 * Log (V1 / Vs) CMR = 20 * Log (VX / Vs) CMOL = V2 Figure 10 - Test Circuit 5 14 Zarlink Semiconductor Inc. MH88435-P Data Sheet -V = Ground (Earth) 10H 500Ω 13 15 11 100uF I=20mA LOOP RS LCD 3 28 VR+ TIP + 4 1 VR- NB1 MH88435 300Ω 5 VX 15K Vs 21 2 SC NB2 V1 300Ω 510Ω 22 SC 100uF 27 RING + 360K 24 10H 500Ω VLOOP2 10 25 VBIAS VLOOP1 10uF LC RV AGND VCC ZA 616 8 9 7 1K 4.7K 5V 5V Met. to Long. Balance = 20 * Log (V1 / Vs) Figure 11 - Test Circuit 6 0.162 Max (4.12 Max) 0.27 Max (6.9 Max) 0.063 Max (1.6 Max) 0.08 Typ (2 Typ) * 1.00 Typ 0.260+0.015 (6.6+0.38) (25.4 Typ) * 0.100+0.010 * 0.05 Typ (2.54+0.25) 1.05 Max (1.27 Typ) 0.020 + 0.005 (26.7 Max) (0.5 + 0.13) * 0.300+0.010 (7.62+0.25) Notes: 1) Not to scale 2) Dimensions in inches. (Dimensions in millimetres) 1 3) Pin tolerances are non-accumulative. 4) Recommended soldering conditions: Wave Soldering - Max temp at pins 260°C for 10 secs. 1.42 Max * Dimensions to centre of pin. (36.1 Max) Figure 12 - Mechanical Data for 28 Pin DIL Hybrid 15 Zarlink Semiconductor Inc. For more information about all Zarlink products visit our Web Site at www.zarlink.com Information relating to products and services furnished herein by Zarlink Semiconductor Inc. or its subsidiaries (collectively “Zarlink”) is believed to be reliable. However, Zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or use. Neither the supply of such information or purchase of product or service conveys any license, either express or implied, under patents or other intellectual property rights owned by Zarlink or licensed from third parties by Zarlink, whatsoever. Purchasers of products are also hereby notified that the use of product in certain ways or in combination with Zarlink, or non-Zarlink furnished goods or services may infringe patents or other intellectual property rights owned by Zarlink. This publication is issued to provide information only and (unless agreed by Zarlink in writing) may not be used, applied or reproduced for any purpose nor form part of any order or contract nor to be regarded as a representation relating to the products or services concerned. The products, their specifications, services and other information appearing in this publication are subject to change by Zarlink without notice. No warranty or guarantee express or implied is made regarding the capability, performance or suitability of any product or service. Information concerning possible methods of use is provided as a guide only and does not constitute any guarantee that such methods of use will be satisfactory in a specific piece of equipment. It is the user’s responsibility to fully determine the performance and suitability of any equipment using such information and to ensure that any publication or data used is up to date and has not been superseded. Manufacturing does not necessarily include testing of all functions or parameters. These products are not suitable for use in any medical products whose failure to perform may result in significant injury or death to the user. All products and materials are sold and services provided subject to Zarlink’s conditions of sale which are available on request. Purchase of Zarlink’s I2C components conveys a licence under the Philips I2C Patent rights to use these components in and I2C System, provided that the system conforms to the I2C Standard Specification as defined by Philips. Zarlink, ZL, the Zarlink Semiconductor logo and the Legerity logo and combinations thereof, VoiceEdge, VoicePort, SLAC, ISLIC, ISLAC and VoicePath are trademarks of Zarlink Semiconductor Inc. TECHNICAL DOCUMENTATION - NOT FOR RESALE