MH88422 Data Access Arrangement Data Sheet March 2008 Features • FAX and Modem interface (V29) Ordering Information • Variants available with different line MH88422-21 26 Pin DIL* Boxed impedances • Provides reinforced barrier to international PTT *Pb Free Matte Tin requirements 0°C to 70°C • Transformerless 2-4 Wire conversion. • Integral Loop Switch Description • Dial Pulse and DTMF operation • Line state detection outputs The Zarlink MH88422 Data Access Arrangement (D.A.A.) provides a complete interface between data • Loop current/ringing outputs transmission equipment and a telephone line. All • Single +5 V operation, low on-hook power functions are integrated into a single thick film hybrid (5 mW) module which provides high voltage isolation, very high • Full duplex data transmission reliability and optimum circuit design needing a minimum of external components. Applications A number of variants are available to meet particular country impedance requirements. The D.A.A. has been Interface to Central Office or PABX line for: designed to meet regulatory approvals requirements in • Modem these countries. •FAX • Telemetry Isolation Barrier VDD AGND Opto- Logic Input LC Input Buffer Isolation TIP Buffer & RING Line Termination Opto- Audio VR Buffer Isolation TXIN Transhybrid Opto- Audio VX loss Isolation Buffer cancellation TF circuit Opto- Ring & Loop RVLC RLS Buffer Isolation User Connections Network Connections Figure 1 - Functional Block Diagram 1 Zarlink Semiconductor Inc. Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 2001-2008, Zarlink Semiconductor Inc. All Rights Reserved. MH88422 Data Sheet Change Summary Changes from August 2006 Issue to August 2008 Issue. Page Item Change 1 Updated Ordering Information. VDD 1 26 TIP IC 2 25 IC 3 24 AGND RLS 23 IC 4 IC/NP LC 5 22 IC 6 21 IC IC/NP 20 RVLC 7 TF 19 IC 8 NP IC 9 18 TXIN 10 17 IC/NP IC 16 VX 11 RING 15 IC/NP 12 NP 13 14 VR IC Figure 2 - Pin Connections Pin Description Pin # Name Description 1 VDD Positive Supply Voltage. +5 V. 2, 4, 6, 8, IC Internal Connection. This pin is cropped short. 9 3 AGND Analog Ground. 4-Wire Ground. Normally connected to System Ground. 5LC Loop Control (Input). A logic 0 activates internal circuitry which provides a line termination across Tip and Ring. Used for seizing the line and dial pulsing. 7RVLC Ringing Voltage and Current Detect (Output). Indicates the status of loop current and ringing voltage. 10, 12 NP No Pin Fitted. 11 VX Transmit (Output). Analog output to modem/fax chip set. 13 VR Receive (Input). Analog input to modem/fax chip set. 14, 17 IC Internal Connection. This pin is cropped short. 15, 19 NP No Pin Fitted. 16 RING Ring Lead. Connects to the "Ring" lead of a telephone line. 18 TXIN Dummy Ringer Connection. Connects to the "Ring" lead of a telephone line through a dummy ringer capacitor. 20 TF Tip Feed. Connects externally to the RLS pin. 21 IC/NP No Pin Fitted. 2 Zarlink Semiconductor Inc. MH88422 Data Sheet Pin Description (continued) 23 NP Internal Connection. This pin is cropped short. 24 RLS Ringing Loop Sense. Connects externally to the TF pin. 25 IC Internal Connection. This pin is cropped short. 26 TIP Tip Lead. Connects to the "Tip" lead of a telephone line. Functional Description The device is a Data Access Arrangement (D.A.A.). It is used to correctly terminate a 2-Wire analog loop. It provides a signalling link and a 2-4 Wire line interface between an analog loop and the subscriber’s data transmission equipment such as Modems, Facsimiles (Fax’s), Remote Metering and Electronic Point of Sale equipment (EPOS). Isolation Barrier The device provides an isolation barrier implemented by using optocouplers. This is a reinforced barrier for an instantaneous power surge of up to 3kV r.m.s., for example a lightning strike. It also provides full isolation for a continuous AC voltage level of up to 250V r.m.s. External Protection Circuit Should the input voltage from the line exceed that isolated by the optocoupler, an External Protection Circuit assists in preventing damage to the device and the subscriber equipment. See Figure 3. Line Termination When Loop Control (LC) is at a logic 0, a line termination is applied across Tip and Ring. The device can be considered off-hook and DC loop current will flow. The line termination consists of both a DC line termination and an AC input impedance. When LC is at a logic 1, a Dummy Ringer is applied across Tip and Ring. The device can be considered on-hook and negligible DC current will flow. The dummy ringer is an AC load, which represents a telephone’s mechanical ringer. DC Line Termination When LC is at a logic 0, an active termination is applied across Tip and Ring, at which time it can be considered to be in an off-hook state. This is used to terminate an incoming call, seize the line for an outgoing call, or if it is applied and disconnected at the required rate, can be used to generate dial pulses. This termination resembles approximately 300Ω resistance, which is loop current dependent. Input Impedance The MH88422 has its own fixed Tip-Ring AC input impedance (Zin). Also shown are the countries whose PTT requirements match the impedances. MH88422-2 Zin = 600Ω North America 3 Zarlink Semiconductor Inc. MH88422 Data Sheet This country passes equipment approved to CTR21. The MH88422 will not meet this specification. See the MH88437 data sheet for a CTR21 Product. Dummy Ringer This device supports a dummy ringer option which can be configured by the inclusion of external components. Further details relating to component values and configuration can be obtained from MSAN-154. For example, Figure 3 shows capacitor C2 which if set to 1.8µF would meet the New Zealand dummy ringer requirements. MH88422 R2 11 R1 C3 26 Audio TIP TIP VX Output 24 RLS R3 13 C4 Audio VR Protection Input Circuit 20 TF 7 Ring Voltage & Loop C2 RVLC 18 Current Detect Output TXIN 5 16 RING LC Loop Control Input RING VDD AGND 1 3 Notes: 1) R1, R2: Transmit Gain Resistors 2) R3: Receive Gain Resistor C1 + 3) C1: 10µF 6V Tantalum 4) C2: Dummy Ringer Capacitor 250V 5) C3, C4: 10µF AC coupling Capacitors +5V Figure 3 - Typical Application Circuit 2-4 Wire Conversion The device converts the balanced 2-Wire input, presented by the line at Tip and Ring, to a ground referenced signal at VX, as required by modem/fax chip sets. Conversely the device converts the ground referenced signal input at VR, to a balanced 2-Wire signal across Tip and Ring. During full duplex transmission, the signal at Tip and Ring consists of both the signal from the device to the line and the signal from the line to the device. The signal input at VR, being sent to the line, must not appear at the output VX. In order to prevent this, the device has an internal cancellation circuit. The measure of attenuation is Transhybrid Loss (THL). The Transmit (VX) and Receive (VR) signals are ground referenced (AGND), and biased to 2.5V. The device must be in the off-hook condition for transmission or reception to take place. Transmit Gain The Transmit Gain of the MH88422 is the gain from the differential signal across Tip and Ring to the ground referenced signal at VX. The internal Transmit Gain of the device is fixed and depends on the variant as shown in the AC Electrical Characteristics table. For the correct gain, the Input Impedance of the MH88422 variant used, must match the specified line impedance. 4 Zarlink Semiconductor Inc. MH88422 Data Sheet By adding an external potential divider to VX, it is possible to reduce the overall gain in the application. The output impedance of VX is approximately 10Ω and the minimum resistance from VX to ground should be 2kΩ. Example: If R1 = R2 = 2kΩ, in Figure 3, the gain would reduce by 6.0dB. Receive Gain The Receive Gain of the MH88422 is the gain from the ground referenced signal at VR to the differential signal across Tip and Ring. The internal Receive Gain of the device is fixed as shown in the AC Electrical Characteristics table. For the correct gain, the Input Impedance of the MH88422 variant used, must match the specified line impedance. The input impedance to ground of VR is 47kΩ and this can be used with an external series resistor to form a potential divider and reduce the overall gain in the application. Example: If R3 = 100kΩ, in Figure 3, the Gain would reduce by 3.0dB. Supervisory Features The device is capable of monitoring the line conditions across Tip and Ring, this is shown in Figure 3. The Ringing Voltage Loop Current detect pin (RVLC), indicates the status of the device. The RVLC output is at logic 0 when loop current flows, indicating that the MH88422 is in an off hook state. When the device is generating dial pulses, the RVLC pin outputs a TTL pulse at the same rate. An AC ringing voltage across Tip and Ring will cause RVLC to output a TTL pulse at double the ringing frequency with an envelope determined by the ringing cadence. Mechanical Data See Figure 10, for details of the mechanical specification. 5 Zarlink Semiconductor Inc. MH88422 Data Sheet . Absolute Maximum Ratings* - All voltages are with respect to AGND unless otherwise specified. Parameter Symbol Min. Max. Units 1 DC Supply Voltage V -0.3 6 V DD 2 Storage Temperature T -55 +125 °C S 3 DC Loop Voltage V -110 +110 V BAT - 150 Vrms 4 Ringing Voltage V R 5 Loop Current I -90 mA Loop *Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied. Recommended Operating Conditions ‡ Parameter Sym. Min. Typ. Max. Units Test Conditions 1DC Supply Voltages V 4.75 5.0 5.25 V DD 2 Operating Temperatures T 025 70 °C OP 75 90 Vrms 150 Vrms for -2 variant 3 Ringing Voltage V R ‡ Typical figures are at 25°C with nominal +5V supply and are for design aid only † Loop Electrical Characteristics ‡ Characteristics Sym. Min. Typ. Max. Units Test Conditions 1 No Detect 7Vrms Externally Adjustable - See Detect 14 Vrms MSAN-154 2 Ringing Frequency 15 68 Hz 3 Operating Loop Current 15 80 mA 4 Off-Hook DC Voltage 6.0 V I =15mA Loop 2.4 6.0 V I =20mA (See Note 2) Loop 3.1 7.8 V I =26mA Loop 5 Leakage Current (Tip or 10 µA 100V DC Ring to AGND) 6 Leakage Current on-hook 910 µΑ V = -50V BAT (Tip to Ring) 7 DC Resistance during dialling 260 280 Ω 8 Dial Pulse Distortion ON 0 +2 +4 ms OFF 0 +2 +4 ms † Electrical Characteristics are over Recommended Operating Conditions unless otherwise stated. ‡Typical figures are at 25°C with nominal + 5V supplies and are for design aid only. Note 1: Refer to FTZ 1TR2 section 2.2 Note 2: Refer to EIA/TIA 464 section 4.1.1.4.4 Note 3: Refer to BS6305 section 4.3.1 Note 4: Refer to ZV5 Annex 1 6 Zarlink Semiconductor Inc. MH88422 Data Sheet † DC Electrical Characteristics ‡ Characteristics Sym. Min. Typ. Max. Units Test Conditions 1 Supply Current I 15 mA V = 5.0V, On-hook DD DD 2RVLC Low Level Output Voltage V 0.4 V I = 4mA OL OL High Level Output Voltage V 2.4 V I = 0.4mA OH OH 3LC Low Level Input Voltage V 0.8 V IL 2.0 High Level Input Voltage V V IH Low Level Input Current I -60 µA V = 0.0V IL IL High Level Input Current I 60 µA V = 5.0V IH IH † Electrical Characteristics are over Recommended Operating Conditions unless otherwise stated. ‡Typical figures are at 25°C with nominal + 5V supplies and are for design aid only. † AC Electrical Characteristics - MH88422-2 ‡ Characteristics Sym. Min. Typ. Max. Units Test Conditions 1 Return Loss at 2-Wire Test circuit as Fig 7 ERL (Reference 600Ω) 20 30 dB 500-2500Hz SFRL 14 19 dB 200-3200Hz 2 Longitudinal to Metallic Balance Test circuit as Fig 8 58 60 dB 200-1000Hz 53 55 dB 1000-3000Hz Metallic to Longitudinal Balance Test circuit as Fig 9 60 dB 200-1000Hz 40 dB 1000-4000Hz 3 Idle Channel Noise Nc at 2-Wire 13 20 dBrnC at VX 13 20 dBrnC 4 Transmit Gain (2-Wire to Vx) Test circuit as Fig 5 -1.4 -0.4 0.9 dB Input 0.5V @ 1kHz Off- Hook 5 Frequency Response Gain -1.6 -1.3 0.4 dB 200Hz (relative to Gain @ 1kHz) -2.1 -0.5 0.9 dB 3400Hz 6 Input Impedance VR 47k Ω 7 Output Impedance at VX 10 Ω 8 Receive Gain (VR to 2-Wire) 2.5 3.5 4.6 dB Test circuit as Fig 6 Input 0.5V at 1kHz 9 Frequency Response Gain (relative to Gain @ 1kHz) -1 0 +1 dB 300Hz -1 0 +1 dB 3400Hz 10 Signal Output Overload Level THD< 5% @1kHz at 2-Wire +2.0 +3.0 dBm I = 20 to 40mA Loop at Vx +2.0 +3.0 dBm THD 11 Total Harmonic Distortion Input -3.5dBm at 1kHz at 2-Wire 1.2 2.5 % at Vx 1.2 2.0 % 7 Zarlink Semiconductor Inc. MH88422 Data Sheet † AC Electrical Characteristics - MH88422-2 7 Power Supply Rejection Ratio PSRR Ripple 0.1 Vrms 1kHz at 2-Wire 12 20 dB at Vx 12 20 dB THL 8 Transhybrid Loss 6 20 dB Test circuit as Fig 6 Input -3.5dBm, 300-3400Hz at V R † Electrical Characteristics are over Recommended Operating Conditions unless otherwise stated. ‡ Typical figures are at 25×C with nominal +5V supply and are for design aid only Note 1: All of the above test conditions use a test source impedance which matches the device’s impedance. Note 2: dBm is referenced to 600Ω unless otherwise stated. +5V DUT 26 ILoop 1 TIP VDD 24 3 RLS AGND 5 22 IC LC/ 20 7 TF RVLC/ 470nF 9 18 TXIN IC 16 11 RING VX 1uF 13 14 NC VR Figure 4 - Test Circuit 1 -V +5v 10H 500Ω DUT 100uF I=20mA 1 26 VDD TIP + 24 3 RLS AGND 22 5 IC LC/ Vs Impedance = Zin 20 9 TF RVLC/ 470nF 9 20 NC TXIN 100uF 16 11 RING VX 1uF + 10H 500Ω 13 14 IC VR V Gain = 20 * Log (VX / Vs) Figure 5 - Test Circuit 2 8 Zarlink Semiconductor Inc. MH88422 Data Sheet -V 10H 500Ω +5v DUT 100uF I=20mA 1 26 VDD TIP + 24 3 RLS AGND 22 5 IC LC/ V (Zin) Zin 20 7 TF RVLC/ 470nF 9 18 NC TXIN 100uF 16 11 RING VX + 1uF 13 14 NC VR 10H 500Ω Vs Gain = 20 * Log (V(Zin) / Vs) Figure 6 - Test Circuit 3 9 Zarlink Semiconductor Inc. MH88422 Data Sheet -V 10H 500Ω +5v DUT I=20mA 100uF Zin 1 26 VDD TIP + 24 3 RLS AGND 300Ω 22 V1 5 IC LC/ Vs 20 7 TF RVLC/ 300Ω 470nF 9 18 TXIN IC 100uF 16 11 RING VX 1uF + 10H 500Ω 13 14 IC VR Return Loss = 20 x Log (V1 / Vs) Figure 7 - Test Circuit -V +5v 10H 500Ω DUT 100uF I=20mA 1 26 VDD TIP + 3 24 AGND RLS 300Ω 22 5 IC LC/ V1 20 7 TF Vs RVLC/ 470nF 300Ω 18 9 IC TXIN 100uF 16 11 RING VX + 1uF 10H 500Ω 13 14 IC VR Long. to Met. Balance = 20 * Log (V1 / Vs) Figure 8 - Test Circuit 5 10 Zarlink Semiconductor Inc. MH88422 Data Sheet -V +5v 10H 500Ω DUT 100uF I=20mA 1 26 VDD TIP + 3 24 RLS AGND 300Ω 22 5 IC LC/ Vs 20 7 TF RVLC/ 510Ω 300Ω V1 470nF 9 18 IC TXIN 100uF 16 11 RING VX + 1uF 10H 500Ω 13 14 IC VR Met. to Long. Balance = 20 * Log (V1 / Vs) Figure 9 - Test Circuit 6 11 Zarlink Semiconductor Inc. MH88422 Data Sheet 0.19 Max (4.8 Max) 0.27 Max (6.9 Max) 0.063 Max (1.6 Max) 0.08 Typ (2 Typ) * * 0.10 Typ 0.20+0.01 * 0.90 Typ 0.26+0.015 (6.6+0.4) (22.9 Typ) (5.08+0.25) (2.54 Typ) 0.020 + 0.005 0.95 Max (0.5 + 0.12) (24.2 Max) 1.42 Max (36.1 Max) Notes: 1) Not to scale 2) Dimensions in inches. (Dimensions in millimetres) 3) Pin tolerances are non-accumulative. 4) Recommended soldering conditions: Wave soldering - Max temp at pins 260°C for 10 secs. 1 * Dimensions to centre of pin. 5) Short-cropped pins. (see pin description) Figure 10 - Mechanical Data for 26-Pin DIL Hybrid 12 Zarlink Semiconductor Inc. For more information about all Zarlink products visit our Web Site at www.zarlink.com Information relating to products and services furnished herein by Zarlink Semiconductor Inc. or its subsidiaries (collectively “Zarlink”) is believed to be reliable. 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Manufacturing does not necessarily include testing of all functions or parameters. These products are not suitable for use in any medical products whose failure to perform may result in significant injury or death to the user. All products and materials are sold and services provided subject to Zarlink’s conditions of sale which are available on request. Purchase of Zarlink’s I2C components conveys a licence under the Philips I2C Patent rights to use these components in and I2C System, provided that the system conforms to the I2C Standard Specification as defined by Philips. Zarlink, ZL, the Zarlink Semiconductor logo and the Legerity logo and combinations thereof, VoiceEdge, VoicePort, SLAC, ISLIC, ISLAC and VoicePath are trademarks of Zarlink Semiconductor Inc. TECHNICAL DOCUMENTATION - NOT FOR RESALE