FEBRUARY 1994 DS3605-2.2 GP1020 SIX-CHANNEL PARALLEL CORRELATOR CIRCUIT FOR GPS OR GLONASS RECEIVERS The GP1020 is a six-channel CMOS digital correlator which 90 61 has been designed to work with the GP1010 L1-channel down- converter or other integrated circuits, and may be used to acquire and track the GPS C/A code or the GLONASS signals. For each of the six channels the GP1020 includes independ- 91 60 ent digital down-conversion to baseband, C/A code generation, correlation, and accumulate-and-dump registers. The GP1020 interfaces with a microprocessor via a 16-bit data bus to control the acquisition and tracking processes using the various registers on the chip. GP1020 FEATURES n Six Fully Independent Correlation Channels n Switchable to Receive GPS or GLONASS Codes n Input Multiplexer for Multiple GPS Front-Ends – Allows 120 31 Antenna Diversity n Input Multiplexer for GLONASS Multiple (Separate Channels) Front-Ends 1 30 GP120 n Digital Interface Compatible with Most 16 or 32-Bit Microprocessors Fig 1 Pin connections - top view n Fully Compatible with GP1010 GPS Receiver Front-End n Sideways Stackable to give Multiples of Six Channels ABSOLUTE MAXIMUM RATINGS n 120-pin Plastic Quad Flatpack These are not the operating conditions, but are the absolute limits which if exceeded, even momentarily, may cause perma- n Power Dissipation Less Than 500mW nent damage. To ensure sustained correct operation the device should be used within the limits given under Electrical Character- istics. APPLICATIONS n GPS or GLONASS Navigation Systems Supply voltage (V ) from ground (V ): 20·3V to16·0 V DD SS Input voltage (any input pin): V 20·3V to V 10·3 V n High Integrity Combined Receivers SS DD Output voltage (any output pin): V 20·3V to V 10·3 V SS DD n GPS Geodetic Receivers Storage temperature: 255°C to 1125°C n GPS Time Reference ORDERING INFORMATION The GP1020 is available in 120-pin Quad Flatpacks (Gullwing RELATED PRODUCTS formed leads) in both Commercial (0°C to 170°C) and Industrial (240°C to 185°C) grades. The ordering codes below are for Datasheet Part Description standard screened devices. Reference DW9255 35·42MHz SAW Filter DS3861 ORDERING CODES GP1020 CG GPKR Commercial - Plastic 120-pin QFP (GP120) GP1010 GPS Receiver Front-End DS3076 GP1020 IG GPKR Industrial - Plastic 120-pin QFP (GP120) MICROPROCESSOR MICROPROCESSOR SYSTEM SYSTEM SLAVECLK GP1020 TYPICAL GPS RECEIVER (Fig. 2) All satellites use the same L1 frequency of 1575·42MHz, but different Gold codes, so a single front-end may be used. To achieve better sky coverage it may be desirable to use more than one antenna, in which case separate front-ends will be needed. NAVIGATION GND 15V MASTERRESET SOLUTION MASTER CLK V V SS DD MASTER/SLAVE CS DECODE GP1010 SAMPLE CLK & SIGN SIGN 0 GP1020 DATA BUS (16) FILTER MAG MAG 0 (MASTER) ADDR BUS (8) SIGN 1 3 CONTROL MAG 1 TIC OUT INT OUT MULTIPLE ANTENNAS TO GIVE WIDER SKY COVERAGE TIC IN INT IN OPTIONAL CS DECODE SIGN 0 SECOND OPTIONAL SECOND GP1010 MAG 0 & GP1020 SIGN 1 FILTER MAG 1 (SLAVE) V MASTER/SLAVE V DD SS 15V MASTERRESET GND Fig. 2 GPS receiver simplified block diagram TYPICAL GLONASS RECEIVER (Fig. 3) Each satellite will use a different ‘L1’ carrier frequency, in the range 1602·5625 to 1615·500MHz, with 0·5625MHz spacing, but all with the same 511-bit spreading code. The normal method for receiving these signals is to use several front-ends, perhaps with the first LNA and mixer common, but certainly with different final local oscillators and mixers. 15V GND GLONASS FRONT-END FILTERS, AMPLIFIERS AND MIXERS V V DD SS MASTER/SLAVE NAVIGATION SOLUTION SAMPLE CLK SAMP CLK CHANNEL SIGN SELECTION SIGN 0 MASTERRESET L-BAND MAG AND ADC DOWN MAG 0 CONVERTER CHANNEL CHANNEL SIGN SELECTION SELECTION SIGN 1 MAG AND ADC AND ADC CS MAG 1 DECODE CHANNEL SIGN DATA BUS (16) SELECTION SIGN 2 MAG AND ADC MAG 2 ADDR BUS (8) GP1020 3 CONTROL CHANNEL SIGN SIGN 3 SELECTION MAG AND ADC MAG 3 INT OUT CHANNEL SIGN SIGN 4 SELECTION MAG AND ADC MAG 4 CHANNEL FREQUENCY SIGN SIGN 5 SELECTION GENERATOR MAG MASTER AND ADC MAG 5 CLOCK OSCILLATOR FREQUENCY SELECTION Fig. 3 GLONASS receiver simplified block diagram 2 GP1020 PIN DESCRIPTIONS (See Application Notes, p. 41) Pin Signal Type Description All V and all V pins must be used in order to ensure SS DD No. name reliable operation. Several pins, such as Satellite Inputs 2 to 9 Sign and Magnitudes are also used for device testing, but TICIN TIC input to slave 66 I only as a secondary function. TICOUT 67 O TIC output from Master D0 Data Bus, bit 0 68 I/O Pin Signal D1 69 I/O Data Bus, bit 1 Type Description No. name V Ground 70 2 SS V 71 1 Positive supply DD 1 A7 I Register Address, bit 7 D2 Data Bus, bit 2 72 I/O 2 A8 I Register Address, bit 8 D3 73 I/O Data Bus, bit 3 3 MASTER/ I Master or slave mode select TIME MARK One pulse per second output 74 O SLAVE RTCINT 75 I Real time clock interrupt input 4 TSCAN I Scan Test mode select MARKFB1 Timemark line driver feedback 76 I 5 TCKS I Test Clock select MARKFB2 77 I Timemark line driver feedback 6 TDI1 I Serial Test Data Input D4 Data Bus, bit 4 78 I/O 7 MASTER I Master Reset (active low) D5 79 I/O Data Bus, bit 5 RESET V Positive supply 80 1 DD 8 MOT/INTEL I Motorola (hi) or Intel (lo) bus select V 81 2 Ground SS 9 CS I Chip Select (active low) for bus D6 Data Bus, bit 6 82 I/O 10 V 2 Ground D7 SS 83 I/O Data Bus, bit 7 11 V 1 Positive supply WPROG Bus timing mode - see note 2 DD 84 I 12 WEN I Bus control - see note 1 NANDA 85 I Test Structure - see note 3 13 RW I Bus control - see note 1 NANDB Test Structure - see note 3 86 I 14 TMS2 Test Mode Select 2 I TDO 87 O Boundary Scan output 15 TMS1 I Test Mode Select 1 TCK Boundary Scan clock 88 I 16 TMAG Test PRN Pattern Magnitude o/p O TRST 89 I Boundary Scan reset 17 TSIGN O Test PRN Pattern Sign output NANDOP Test Structure - see note 3 90 O 18 MAG2 Satellite Input 2, Magnitude I/O TMS 91 I Boundary Scan control 19 100/219kHz O Programmable Interrupt Timer clock TDI Boundary Scan input 92 I 20 V Positive supply 1 MARKFB3 DD 93 I Timemark line driver feedback 21 V 2 Ground TDO7 Serial Test Data Output 7 SS 94 O 22 INTOUT Interrupt out to microprocessor O DISCOP 95 O On/Off control for LNA by GP1010 23 SIGN2 I/O Satellite Input 2, Sign TDO6 Serial Test Data Output 6 96 O 24 MAG3 Satellite Input 3, Magnitude I/O TDO5 97 O Serial Test Data Output 5 25 SIGN3 I/O Satellite Input 3, Sign D8 Data Bus, bit 8 98 I/O 26 MAG4 Satellite Input 4, Magnitude I/O D9 99 I/O Data Bus, bit 9 27 SIGN4 I/O Satellite Input 4, Sign V Ground 100 2 SS MAG5 Satellite Input 5, Magnitude 28 I/O V 101 1 Positive supply DD 29 SIGN5 I/O Satellite Input 5, Sign D10 Data Bus, bit 10 102 I/O MAG6 Satellite Input 6, Magnitude 30 I/O D11 103 I/O Data Bus, bit 11 31 SIGN6 I/O Satellite Input 6, Sign TDO4 Serial Test Data Output 4 104 O MAG7 Satellite Input 7, Magnitude 32 I/O TDO3 105 O Serial Test Data Output 3 33 SIGN7 I/O Satellite Input 7, Sign TDO2 Serial Test Data Output 2 106 O MAG8 Satellite Input 8, Magnitude 34 I/O TDO1 107 O Serial Test Data Output 1 35 SIGN8 I/O Satellite Input 8, Sign D12 Data Bus, bit 12 108 I/O MAG9 Satellite Input 9, Magnitude 36 I/O D13 109 I/O Data Bus, bit 13 37 SIGN9 I/O Satellite Input 9, Sign V Positive supply 110 1 DD MAG1 Satellite Input 1, Magnitude 38 I/O V 111 2 Ground SS 39 SIGN1 I/O Satellite Input 1, Sign D14 Data Bus, bit 14 112 I/O V Ground 40 2 D15 SS 113 I/O Data Bus, bit 15 41 V 1 Positive supply ALE Address Latch Enable, DD 114 I MAG0 Satellite Input 0, Magnitude 42 I bus control 43 SIGN0 I Satellite Input 0, Sign A1 Register Address, bit 1 (LSB) 115 I SAMPCLK Sampling clock to down-converter 44 O A2 116 I Register Address, bit 2 45 V 1 Positive supply A3 Register Address, bit 3 DD 117 I MASTERCLK 40MHz Master Clock 46 I A4 118 I Register Address, bit 4 47 V 2 Ground A5 SS 119 I Register Address, bit 5 Bias Bias for MASTERCLK in 600mV 48 O A6 120 I Register Address, bit 6 AC-coupled mode V Ground 49 2 SS NOTE 1. The functions of RW and WEN pins depend on whether the 50 V 1 Positive supply DD GP1020 is in Motorola™ (MOT/INTEL = ‘1’) or Intel™ mode (MOT/INTEL V Ground 51 2 SS = ‘0’). In Motorola mode, WEN is an enable (active high) and RW is Read/ 52 CLKSEL I Sets 100/219kHz to 100or 219kHz Write select (‘1’ = Read). In Intel mode RW is Read, active low, and WEN PLLLOCKIN PLL lock status from down-converter 53 I is Write, also active low. 54 BITECNTL O BITE control to down-converter GLONASSBIT I/P to monitor GLONASS front-end MOT/INTEL Mode WEN RW Function 55 I 56 SLAVECLK I/O 20MHz clock from Master to slave 1 Motorola 1 0 Write INTIN Interrupt to slave to sync to Master 57 I 1 Motorola 1 1 Read 58 TCK1 I/O Test Clock 1 0 Intel 1 0 Read TCK2 Test Clock 2 59 I/O 0 Intel 0 1 Write 60 TCK3 I/O Test Clock 3 TCK4 Test Clock 4 61 I/O NOTE 2. WPROG is used to modify the timing of bus operations; when it 62 TCK5 I/O Test Clock 5 is held HIGH the internal write signal is ORed with ALE to allow time for the TCK6 Test Clock 6 63 I/O internal address lines to stabilise; when it is held LOW there is no delay 64 TCK7 I/O Test Clock 7 added to write. NOTE 3. NANDOP (pin 90) is the output of a spare gate with TCK8 Test Clock 8 65 I inputs on NANDA (pin 85) and NANDB (pin 86). 3 GP1020 ELECTRICAL CHARACTERISTICS These characteristics are guaranteed over the following conditions (unless otherwise stated): Supply voltage, V = 5V ±10%; Ambient Temperature, T = 0°C to 170°C (CG grade),240°C to 185°C (IG grade). DD AMB DC CHARACTERISTICS Value Characteristic Units Conditions Min. Typ. Max. Supply current, I , chip fully active 100 mA DD CMOS inputs with pullup resistors to V : RTCINT, DD MASTER/SLAVE, MARKFB (3:1), NANDA, NANDB, WPROG, ALE Input voltage high 0·8V V DD Input voltage low 0·2V V DD Pullup resistor 20 75 250 kΩ CMOS inputs with pulldown resistors to V : MOT/INTEL, SS CLKSEL, INT IN, TIC IN Input voltage high 0·8V V DD Input voltage low 0·2V V DD Pulldown resistor 20 75 250 kΩ CMOS inputs without either pullup or pulldown resistors: MASTERRESET, CS, WEN, RW, MASTERCLK (note 1), SLAVECLK, A (8:1), D (15:0), TCK, TDI, TMS, TRST Input voltage high 0·8V V DD Input voltage low 0·2V V DD Input leakage current 1 10 μA V TIC period) before the measurement data specific sampled and latched on the positive edge of every INT OUT or to this channel was either read or the CHx_NEW_MEAS_DATA INT IN signal. They can also be sampled and latched on request bit was cleared. This bit is set on a TIC and latched until either by performing a write operation to STATUS_LATCH location. a master reset (hardware or software) or until a write operation BIT DESCRIPTION to CHx_MEAS_RST CHx_NEW_MEAS_DATA status bit active HIGH indicates if CHx_SLEW: Status indicating if the code phase counter was there is new measurement data available to be read. Each being slewed at time of TIC sampling. If such is the case, the individual bit can be cleared by a write operation with don’t care measurement data is not reliable. This bit is updated at each TIC data to CHx_MEAS_RST. This operation releases the overwrite when the overwrite protection is not active and is reset whenever protection. Each bit is also cleared on the trailing edge of a read CHx_MEAS_RST is written into with don’t care data or upon a of the associated CHx_CARR_CYCLE register. If new accumu- master reset (hardware or software). lated data becomes available after status bits have been latched, All status bits in this register will also be cleared when the the overwrite protection is not cleared while reading the clock phase propagation is disabled. CHx_CARR_CYCLE register and the CHx_NEW_MEAS_DATA bit will be set at the next MEAS_STATUS_A. A master reset PROP_DELAY_LO and PROP_DELAY_HI (hardware or software) and the inhibition of clock phases will also Read Addresses C3 and C4 H clear this status bit. RTC_TIC_ACK status bit is set whenever a Real Time Clock Register bit mapping, PROP_DELAY_LO interrupt has been received and the 100ms_TIC or 9ms_TIC following the interrupt has occured. It is reset by a read of Bit Description RTC_DELAY register or an ALL_MEAS_RST command. RTC_DELAY is overwrite protected by the measurement data 15 to 0 16 less significant bits of down counter protection mechanism. MARK_FB_ACK status bit is set whenever a Time Mark Register bit mapping, PROP_DELAY_HI feedback signal has been received on the selected pin, MARK_FB1, MARK_FB2 or MARK_FB3 or by the selected edge Bit Description of the TIC OUT signal. It is reset by a read of PROP_DELAY_LO register or a ALL_MEAS_RST command. MARK_FB_ACK is 4 to 0 5 more significant bits of down counter. overwrite protected by the measurement data protection mecha- nism. 15 to 5 Don’t care, held LOW. RTC_TIC_ACK and MARK_FB_ACK status bits are cleared 26 GP1020 PROP_DELAY_LO is a 16-bit register containing the 16 less RESET_CNTL Read/Write Address C0 H significant bits of an unsigned integer PROP_DELAY whose value is the number, minus one, of 50 nanosecond intervals Register bit mapping completed since the MARK output signal was generated. PROP_DELAY_HI is a 5-bit register containing the 5 more Bit Description significant bits of the same integer. This integer comes from the Mark Output programmable down counter and the 0 MRB (Chip MASTERRESET) DOWN_COUNT register as detailed below. If a read access is 1 CH1_RSTB performed when the programmable down counter is working the 2 CH2_RSTB data may be not stable. A MARK_FB_ACK status bit should be 3 CH3_RSTB acknowledged before performing a read access to the 4 CH4_RSTB PROP_DELAY registers. 5 CH5_RSTB 6 CH6_RSTB The programmable down counter operates as follows: 7 to 15 Not used Time Counter contents Remarks BIT DESCRIPTION ta DOWN_COUNT The counter is loaded by CHx_RSTB: When active LOW, the reset bit inhibits propa- Software with DOWN_COUNT gation of the clock phases to the tracking channel and resets the value. code generator, accumulated and measurement flags, CODE_DCO and CARRIER_DCO accumulators and their as- tb The one second time mark sociated INCR registers, the I&D accumulators, the code slew signal is issued and prop- counter and finally the code phase counter. This is required for agates through the output the search algorithm of one satellite signal using many channels driver. The Down counter wraps in order to start from a known relative code phase on all the round and continues to count channels. However, all of the registers in CHx can be pro- down. grammed and read as usual. To restart normal operation in the different channels at the same time, the corresponding tc PROP_DELAY When the feedback signal at CHx_RSTB bits should be set to HIGH during the same write input pin MARK FB1, MARK operation. All CHx_RSTB are set LOW by a master reset. FB2, MARK FB3 or Internal TIC MRB: When LOW (software reset), the effect is identical to signal, as selected by bits the hardware MASTERRESET except that the clock generator 7 to 5 of the TIMER_CNTL and the time base generator are not affected. It should be set to register, reaches the down HIGH to allow access to the different registers. MRB is set HIGH counter, its value is frozen by a hardware master reset. and can be read by the processor, (16 lower bits only) RTC_DELAY Read Address C2 H To get the correct number of 50 ns intervals, 1 should be added to the PROP_DELAY number. For example, if the feed- Register bit mapping back was so fast that the counter did not have time to count, the PROP_DELAY value will be 1F FFFF and by adding 1 the result Bit Description H becomes 00 0000 . H 15 to 0 Number of clock intervals counted from Other examples of delay counts: the occurrence of an RTC interrupt and the next TIC (TIC IN if the external source Real number of is selected). PROP_DELAY value 50 ns intervals Each count represents 2.275 microsecond. The register content is unsigned and 00 0000 1 the validity range is from 0 to TIC H 00 0001 2 period/2.275 microsecond. H 1F FFFC 2,097,150 H The error in RTC_DELAY is 6 2.275 microsecond as shown If there is no feedback coming from the external driver, a time- in Fig. 16. out function will stop the counter and no MARK_FB_ACK status RTC_DELAY is latched on a TIC and is overwrite protected bit will be asserted. The PROP_DELAY value will be 1F FFFD by its own measurement data overwrite protection mechanism. H (representing a propagation delay of 104.8575 ms). The RTC_TIC_ACK status bit of MEAS_STATUS_A register indicates if an RTC interrupt has been received. The The PROP_DELAY value can be used for: RTC_TIC_ACK status bit is cleared by writing to the ALL_MEAS_RST address and also by reading RTC_DELAY 1. Computation of DOWN_COUNT, to compensate for the register. propagation delay in the output driver circuit if this delay islarger than 50 nanoseconds. 2. As a BITE function, to check that the TIME_MARK output drivers work or to verify the TIC period. 27 GP1020 RTC_INT TIC NEXT 2·275μs CLOCK EDGE PREVIOUS 2·275μs (FREE RUNNING) CLOCK EDGE TIME UP TO 2·275μs UP TO 2·275μs DELAY DELAY MAKES MAKES COUNT TOO HIGH COUNT TOO SMALL Fig. 16 STAT_CHK_SEL Write Address C5 non valid data will be latched in STAT_CHK_SIGN and H STAT_CHK_MAG registers. For this reason perform a dummy read to STAT_CHK_MAG in order to clear the flag and wait for Register bit mapping the next time the flag is set to get valid data. Description NOTE: the STAT_CHK_MAG register contains the number of samples having the values 13 or23, and the STAT_CHK_SIGN Signal source register contains the number of positive samples (1 or 3) from the Bit selection with the selected input port. Selected input port following encoding: Bit 3 2 1 0 STATUS_LATCH WriteAddress 80 H A write to this location with don’t care data latches the state 3 to 0 0 0 0 0 0 of all status bits contained in ACCUM_STATUS_A, 0 0 0 1 1 ACCUM_STATUS_B, MEAS_STATUS_A and 0 0 1 0 2 MEAS_STATUS_B. Performing a write to STATUS_LATCH 0 0 1 1 3 prior to reading the status registers ensures reading of stable 0 1 0 0 4 status values. The latch takes effect within 200 nanoseconds of 0 1 0 1 5 the leading edge of the write pulse. The LOW to HIGH transition 0 1 1 0 6 of the INT signal will also latch the state of the status bit, thus it 0 1 1 1 7 is not necessary to write to STATUS_LATCH when the status 1 X 0 0 8 registers are to be read as a response to the INT signal in an 1 X 0 1 9 interrupt handling routine. The write to STATUS_LATCH is 1 X 1 0 Self test signal required only when the status registers are read at ‘random’ 1 X 1 1 Ground times, controlled by the microprocessor. These two mecha- nisms are mutually exclusive and should not be used in conjunc- 15 to 4 Not used, don’t care. tion - if they are both used (a write to STATUS_LATCH after the occurance of an INT signal) contentions and confusion will result. REGISTER DESCRIPTION To avoid this, make sure a read access does not take place at the same time as an interrupt rising edge. STAT_CHK_SEL can be written into at any time. The SELF If the INT_MASKB bit in TIMER_CNTL register is not set to TEST SIGNAL is both the sign and magnitude outputs (TSIGN HIGH, the interrupt will not latch the status bits in the status and TMAG output pins) of the SELF_TEST_GENERATOR registers ACCUM_STATUS_A, ACCUM_STATUS_B, block and are connected internally. MEAS_STATUS_A and MEAS_STATUS_B but a STATUS_LATCH write access will do so. Also, when a GP1020 STAT_CHK_SIGN and STAT_CHK_MAG is configured as a slave, it should have the INT_SOURCE and Read Addresses C5 and C6 H the INT_MASKB bits in the TIMER_CNTL register set to HIGH to get the status bits sampled at the same instant in both master Register bit mapping and slave GP1020s. Bit Description TDATA_DUTY_CYCLE Write Address C8 H This register is associated with the 13 to 0 Unsigned integer ranging from 0 to 16383 SELF_TEST_GENERATOR. It allows selection of the duty representing the number of sign or cycle of the data inversion function. magnitude bits sampled during two The time base period is 11 C/A code chips. The value of interrupt time base periods. TDATA_DUTY_CYCLE, valid from 0 to 10, determines the number of chips within the time base period where the data bit 15 to 14 Don’t care, held LOW. modulating the self test signal will be inverted. When the self test signal is fed back in a tracking channel, the inversion causes a These registers are overwrite protected. The overwrite slope reversal in the accumulator of the Accumulate and Dump protection is released and the NEW_STAT_DATA bit of the module and prevents the accumulator from saturating over a ACCUM_STATUS_A is reset on the trailing edge of a read to code epoch when TDATA_DUTY_CYCLE is properly set. This STAT_CHK_MAG or a write operation to ALL_ACCUM_RESET is the same effect as noise on a real satellite signal. location. Therefore, STAT_CHK_MAG should be read after REGISTER OPERATION STAT_CHK_SIGN. For the first time the flag NEW_STAT_DATA is set after a This register is a write only register and can be written into at master reset, if a write to the STAT_CHK_SEL register has not any time. At power up the register is reset, so it will always select been performed within two interrupt time base (INT) periods, the data inversion function. If the bits are all 1 the data inversion 28 ○○○○○○○○○ ○○○○○○○○○ ○○○○○○○○○ ○○○○○○○○○ ○○○○○○○○○ ○○○○○○○○○ ○○○○○○○○○ ○○○○○○○○○ ○○○○○○○○○ ○○○○○○○○○ ○○○○○○○○○ GP1020 function will never be selected. For standard operation a single Register bit mapping 0 is required and all the other bits must be at 1. The position of the 0 in the register allows the duty cycle of the data inversion Bit Name Description function to be set as shown below: 3 INT_SOURCE When LOW, the signal used to latch the state of status bits and Bits 10 9 8 7 6 5 4 3 2 1 0 Description the results of the STAT_CHECK block is the positive edge in Intel 0 0 0 0 0 0 0 0 0 0 0 Power up condition, the mode or the negative edge data inversion function in Motorola mode of the is always selected. INT signal generated on-chip. When HIGH, the edge 1 1 1 1 1 1 1 1 1 1 0 The data inversion of the INT signal provided on function is always INTIN pin of the device by a selected. companion GP1020 is used instead. INT_SOURCE is set 1 1 1 1 1 1 1 1 1 0 1 The data inversion LOW by reset. function is selected 10 times in 11. 4 TEST_OP/MARKB When LOW, the GP1020 MARK output pin will output 1 1 1 1 1 1 1 1 0 1 1 The data inversion the time MARK output. When function is selected 9 HIGH, the output will be driven times in 11. by a signal selected by the CH1_DUMP/OSC_CHECK bit (bit 8) of this TIMER_CNTL register. TEST_OP/MARKB is set LOW by reset. 0 1 1 1 1 1 1 1 1 1 1 The data inversion 7 to 5 Mark Feedback active edge function is selected 1 selection, with the following time in 11. encoding: 1 1 1 1 1 1 1 1 1 1 1 The data inversion Bit Selected function is never 7 6 5 function selected. 0 0 0 FB1↑ 0 0 1 FB1↓ TIMER_CNTL Write Address C2 H 0 1 0 FB2↑ 0 1 1 FB2↓ Register bit mapping 1 0 0 FB3↑ 1 0 1 FB3↓ Bit Name Description 1 1 0 TICOUT↑ 1 1 1 TICOUT↓ 0 TIC_PERIOD When LOW, the TIC period is 175 ns3571,428 = 99·9999ms. The FBx↑ (rising edge) and When HIGH, the TIC period is FBx ↓ (falling edge) signal edges 175 ns 3 51,948 = 9·0909ms. are used to calculate the TIC_PERIOD is set LOW by pulse width of the Mark reset. Feedback signal. This calcula- tion allows monitoring of the 1 INT_MASKB When LOW, the interrupt output pulse width and verification signal is disabled, the INT OUT that the result is in accordance pin is held LOW and the status with the 1 ms ± 0.01 ms bits are not sampled by an on- specification. The TIC OUT chip or an externally generated signal is also available as interrupt. When HIGH, the int- feedback for test purposes. errupt output signal is enabled Bits 7 to 5 are set LOW and the status bits will be by reset. sampled by an interrupt. INT_MASK is set LOW by reset. 2 TIC_SOURCE When LOW, TIC source is internal, when HIGH, TIC source is external (provided by a companion GP1020 through TICIN pin). TIC_SOURCE is set LOW by reset. 29 GP1020 Register bit mapping Bit Name Description 8 CH1_DUMP/OSC When LOW the GP1020 _CHECK MARK output pin will output a square wave with a period of 4·55 microseconds. (40MHz/182). Because this clock is derived from the TCXO, its stability and accuracy is representative of the TCXO stability and accuracy. When HIGH, the GP1020 MARK output pin will output a square-wave chang- ing its level at each DUMP event in channel 1. These features are used for test purposes during ATP of the GPS sensor unit and the TEST_OP/MARK bit (bit 4) must be set to HIGH to get either of these two test outputs.CH1_DUMP/ OSC_CHECK is set LOW by reset. 12 to 9 Interrupt time base selection with the encoding given in the following table. Bit 12 11 10 9 Selected interrupt High time Low time timebase period (μs) (μs) (μs) 0 0 X X 505.050 252.525 252.525 0100 420.875 84.175 336.700 0101 505.050 252.525 252.525 0110 589.225 336.700 252.525 0111 673.400 336.700 336.700 1000 757.575 420.875 336.700 1001 841.750 420.875 420.875 1010 925.925 505.050 420.875 1011 1010.100 84.175 925.925 1100 1094.275 168.350 925.925 1101 1178.450 84.175 1094.275 1110 1262.625 168.350 1094.275 1111 1346.800 420.875 925.925 Bits 12 to 9 are set LOW by reset. 30 GP1020 DETAILED OPERATION OF THE GP1020 1. MASTER RESET - Hardware or Software. programmed in sequence with the relevant data according to the At Master Reset, all registers, accumulators and counters are estimated DOPPLER shift. Given that the CHx_RSTB bit of the cleared except CHx_CNTL. In particular, this implies the follow- RESET_CNTL register is inactive, the programming is effective ing initial states: as soon as the write operation to CODE_INCR_LO is completed. If the content of CODE_INCR_HI does not need to be modified, All CHx_RSTB bits of the RESET_CNTL register are cleared. • it is not necessary to write into it. It is always necessary to write Thus all tracking channel clock phases are disabled. Program- into CODE_INCR_LO in order for the programming to be effec- ming registers can take place either before or after releasing the tive. CHx_RSTB bits. All the tracking channels are in UPDATE mode, the satellite CODE GENERATOR PROGRAMMING • code selected is GPS PRN No. 17 and the EARLY code is 1. Select in CHx_CNTL register the type of code to be used in selected on the dithering arm. All CHx_CNTL registers are in the dithering arm of the correlator; normally, for a search opera- MODE 1. tion, either an early or a late code is selected. The PRESET/ The TIC generator will be free running at start-up with a UPDB bit will be set LOW, for example, in UPDATE mode by • 100ms TIC period setting. The INT_MASKB bit of the master reset. TIMER_CNTL register is LOW, therefore the INT_OUT signal 2. Select in CHx_CNTL register the code to be generated among will be disabled and the output pin held LOW. The interrupt time the 45 possible C/A codes or the unique GLONASS code. base is set to 505.05μs. (Actually, all possible code combinations are programmable The BITECNTL bit of the BITE register is reset LOW (inactive even those not used by the GPS constellation and some • state). The associated BITECNTL output pin is also LOW. GLONASS-like codes are also available.) The selected code is The data bus is forced into input mode to avoid contention at applicable to both the prompt and the dithering arm. • power up. 3. Program each tracking channel CODE_SLEW register with the desired code phase. The slew operation will become effec- 2. SEARCH OPERATION at Power up, after a power tive at the first dump e.g. about 1 ms after CHx_RSTB release. glitch, or after losing satellite signals. The first dump will generate don’t care accumulated data and will set the associated CHx_NEW_ACCUM_DATA status bit. The REGISTER INITIALISATION second and the following dumps will generate useful data. For each channel, the proper GPS or GLONASS signal 4. Release the relevant CHx_RSTB bits of the RESET_CNTL source has to be selected by writing the proper code into register in order to start operation of the tracking channels. When CHx_SIG_SEL registers. The contents of these registers can be channels of more than one GP1020 are being used to search for changed at any time during the operation to change the signal the same code, consecutive write operations to each chip’s sources for any channels. RESET_CNTL register should ensure a startup with reasonably At power up, all CHx_RSTB bits of the RST_CNTL register well known relative code phases between the two chips. are in the reset LOW state. As stated above, in that state, all Whenever the code clock is being inhibited (to slew the code tracking channel control registers can be programmed. phase), the Accumulate & Dump module is held reset. It will start When it is required to perform a SEARCH for one satellite with to accumulate correlation results only after the slew operation is more than one channel, these channels are first reset if not completed. already in that state, with the corresponding CHx_RSTB bits, then the control registers are programmed. In particular, each 3. READING the ACCUMULATED Data CODE_SLEW register is programmed with a different value. Every time a DUMP occurs, the corresponding Then, the CHx_RSTB bits are released, causing the channels to CHx_NEW_ACCUM_DATA status bit is set in the start operating at the same time with the same code phase. One ACCUM_STATUS_A register. All In-phase and Quad-phase millisecond later, all channels will get the same accumulated registers together with ACCUM_STATUS_A and data and will be slewed with the pre-programmed values and will ACCUM_STATUS_B registers are mapped in consecutive ad- continue with a known relative code phase difference. Note that dresses so that they can be block-read after every timebase every time CHx_RSTB is set LOW, the code generator is reset. interrupt. Alternatively, a polling technique can be used by The following additional initialisation operations have to be periodically reading the ACCUM_STATUS_A register to find if performed. The block write addresses can be used whenever an interrupt or a write into STATUS_LATCH has been per- appropriate. formed. CARRIER_DCO PROGRAMMING The data contained in the IN_PHASE and QUAD_PHASE The CARR_INCR_HI and the CARR_INCR_LO registers are registers of the prompt and dithering arms will be protected from programmed in sequence with the relevant data according to the an overwrite due to consecutive DUMP events. The protection estimated DOPPLER shift for the frequency bin being looked at. mechanism is released on the trailing edge of a read operation The programming is effective as soon as the write operation to of the Q_PROMPT register. Thus the order of reading I_DITH, CARR_INCR_LO is completed (In fact, a small delay of 175 ns Q_DITH and I_PROMPT is optional but Q_PROMPT must maximum will occur to allow synchronisation of the processor always be read last to ensure coherence of the data set and to write operation to the chip operation). If the content of release the overwrite protection mechanism. CARR_INCR_HI does not need to be modified, it is not neces- The CHx_MISSED_ACCUM bit of the ACCUM_STATUS_B sary to write into it. It is always necessary to write into register indicates new accumulated data has been missed CARR_INCR_LO in order for the programming to be effective. because of a too long response time for reading the accumulated Note that, typically, the search algorithm would dwell on a given data. This status bit, when set, is latched until it is cleared by a frequency bin and perform a search over all code phases. Then write operation to CHx_ACCUM_RESET or by a master reset or it would repeat the process for the next frequency bin. by CHx_RSTB set to LOW. CODE_DCO PROGRAMMING The tracking channel being in UPDATE mode, the 4. SEARCH on other CODE PHASES PRESET_PHASE register does not need to be programmed. When it is desired to correlate on the next code phase, the The CODE_INCR_HI and the CODE_INCR_LO registers are CODE_SLEW has to be programmed with a value of 2 (in units 31 GP1020 of half code chips). The slew will be effective on the next dump. 4. Load the following PRESET registers: Thus this dump will generate don’t care accumulated data and as a minimum, the Q_PROMPT register will have to be read to PRESET_PHASE: Will set the code DCO phase. release the overwrite protection mechanism. CODE_SLEW: Will set the code phase. Note that it is only possible to delay the phase of the code. It 1MS_EPOCH: Will set the 1 ms epoch. cannot be advanced. 20MS_EPOCH:Will set the 20 ms epoch. 5. DATA BIT SYNCHRONISATION Related It is important to have the PRESET mode selected prior to Operations programming the CODE_SLEW and the EPOCH registers in order to have these new values effective on the next TIC as When the right code phase is found, the carrier loop is closed. opposed to immediately if they were programmed under UP- The CARR_INCR_HI and CARR_INCR_LO registers can be DATE mode.The PRESET_PHASE register can be programmed reprogrammed at any time to close the feedback loop and either before or after selecting the UPDATE mode. In PRESET resume code tracking. mode the value to program in the CODE_SLEW register repre- The Data Bit Sync algorithm should find the data bit transition sents the delay between the TIC and the first code chip. instant. The processor calculates the present one millisecond To ensure correct PRESET of EPOCH counters, the loading epoch and programs this value into the 1MS_EPOCH register. of PRESET registers has to be completed prior to the TIC relative The effect is immediate. to which the PRESET values are computed. Thus the operation After each DUMP, the epoch counter value can be read within has to take place within a TIC window. 1ms and preferably at the same time as the integrate and dump It is important to load the 20MS_EPOCH register last in the registers. This provides a means of verifying that the epoch loading sequence. The trailing edge of a write to this register counters are indeed properly programmed. Programming the enables the PRESET operation on the next TIC. epoch counter in the 500μs period following a valid 5. After the PRESET operation has taken place on a TIC, the CHx_NEW_ACCUM_DATA should ensure that the program- PRESET/UPDB bit of the CNTL register is reset and the channel ming becomes effective before the next DUMP. goes back to UPDATE mode. It is possible that the code phase Alternatively, the EPOCH registers can be left free-running has to be slewed so the CODE_SLEW register when loaded will and the delta-epoch can be added by the software each time it then cause a slew to start on the next DUMP. reads the EPOCH registers. However, the dithering between On the TIC, the measurement data saved for the signal being early and late code will be controlled by the actual contents of the tracked so far will be valid. The measurement data registers (or EPOCH registers, which will not necessarily be in phase with at least CHx_CARRIER_CYCLE register) must either be read or data bit boundaries. a write operation to CHx_MEAS_RESET must be made in order to clear the measurement status bits and allow measurement 6. READING the MEASUREMENT Data data acquisition on the next TIC for the new signal to be tracked At every occurrence of a TIC, the measurement data is under PRESET mode. latched in measurement data registers. The TIC does not generate any interrupt signal, however, it does set the 8. The TIC GENERATOR and the Interrupt Time CHx_NEW_MEAS_DATA status bits of the MEAS_STATUS_A Base register. This register is normally always read while collecting The interrupt time base consists of a free-running counter accumulated data once every 505.05 microseconds (The INT providing a pulse of constant period on a GP1020 output pin. The OUT signal rate). The software tests the frequency uncertainty on this time base will be identical to the CHx_NEW_MEAS_DATA status bits to determine if new meas- system oscillator drift. The interrupt time base shares some urement data is available to be read. For each channel, the last dividers with the TIC generator. The period of this time base is measurement data register to be read must be 175ns 3 2886 = 505.05μs at power up, but may be changed by CHx_CARR_CYCLE because the trailing edge of this read programming TIMER_CNTL register, and is always an exact releases the overwrite protection mechanism and clears the sub-multiple of the TIC time base. Every 198th (or 18th) interrupt corresponding CHx_NEW_MEAS_DATA bit. The software pulse at default rate will occur at the same time as a 100ms (or must also read the MEAS_STATUS_B register to determine if 9.0909ms) TIC, not taking into account propagation delays. there was any missed measurement data or if phase and epoch Either INT IN or INT OUT (as controlled by the INT_SOURCE bit counters were being slewed during the last TIC period, indicating of the TIMER_CNTL register) is used to sample and latch the invalid measurement data for the affected channel. status bits and statistics on incoming sign and magnitude bits. The interrupt is maskable. The INT_MASKB bit of the 7. The PRESET Mode TIMER_CNTL register when set LOW forces the logic level on Each tracking channel can be individually programmed to the output pin to LOW. A master reset will set this bit LOW. operate either in UPDATE or PRESET mode. A given channel is programmed in PRESET mode by writing a HIGH into the 9. SIGNAL PATH DELAY Introduced by Hardware PRESET/UPDB bit of the CHx_CNTL register. Signal Processing The sequence of operations is as follows: The signal path delay has two components as follows: 1. Write into CHx_CNTL to select the PRESET mode together with the appropriate code, code format on the dithering arm, etc. D = Total path delay = D + D t a d Since the PRESET mode is selected, the new selected code and D = Analogue path delay; varies with temperature and a code format will be effective on the next TIC. component tolerances. 2. Between the instant at which the PRESET mode is selected D = Digital path delay; constant if oscillator drift d and the next TIC, the tracking channel will continue to operate variations are neglected. normally, that is, it will provide accumulated data for the signal For GPS signals, D = 125ns. This delay is the time from the being tracked. d 3. The INCRement registers of the CODE and CARRIER DCO’S sampling edge of the SIGN and MAG bits in the GP1010 (SAMP CLK) to the performance of the correlation in the GP1020 on these have to be loaded with the appropriate frequencies for the new same SIGN and MAG bits (100ns) plus the delay between the signal to be tracked either immediately or only after the TIC has occured if it is desired not to disturb the tracking in effect. correlation and the TIC clock phases in the master GP1020 (25ns). 32 GP1020 10. Short Glitch Recovery Refer to the block diagram shown in Fig. 17 for the following If data bit synchronisation cannot be achieved on a given channel, discussion. but proper code and carrier lock are obtained, the software should It is assumed that the RTC selected provides an interrupt jump to the data bit synchronisation algorithm. If lock is not obtained, output signal which occurs periodically, every 100ms or every then the software should jump to the search algorithm. Given the second. The interrupt is sent to both the GP1020 and the magnitude of error terms (summed) and the worst case error allowed processor system. Within the GP1020, the interrupt is connected in order to keep data bit synchronisation, it is possible to calculate the to the RTC_INT input pin of the GP1020. Its edge enables the length of the longest permitted power glitch. See Fig. 20. RTC_DELAY counter. This counter is clocked by a signal with a period of 2.275μs and increments until the next TIC. The TIC 11. TIME MARK Generator causes the value of RTC_DELAY to be latched in order to be The Time Mark generator is designed to provide a one second read with the measurement data. Time Mark output signal which can be synchronised with a given time CLOCK (439·56kHz) RTC_INT AT 1 SEC RATE REAL TIME 100ms TIC COUNTER CLOCK ENABLE RESET RTC_DELAY MICROPROCESSOR NOTES SYSTEM 1. Latch counter value saved on TIC. 2. Register read with GP1020 measurement data. Fig. 17 RTC block diagram When the processor receives the RTC interrupt, it reads the RTC base, such as the receiver time base, the GPS time or UTC. The time. Alternatively, RTC_TIC may not be routed to the processor, but Time Mark is generated after a certain programmable delay relative instead, every time the RTC_TIC_ACK status bit of to the TIC. MEAS_STATUS_B is set in the GP1020, the software reads the The architecture chosen (see Fig. 19) involves minimal RTC time. With this information, together with the contents of hardware being clocked at a high rate and so gives low power RTC_DELAY, the software is able to determine first the delay consumption. between the RTC and the system clock and secondly, with consecu- As an example, to synchronise TIME MARK to UTC, the software tive readings, the RTC drift can be evaluated. These two pieces of could have the following sequence of operations (see Fig. 21): RTC TIME READ HERE POSITION FIX COMPUTED ON THIS TIC. BY PROCESSOR TIC IS GPS TIME TAGGED. 100ms TIC t s RTC_INT RTC_DELAY D NOTES 1. D = delay between RTC timebase and system time t . s 2. Consecutive measurements of D give an indication of RTC drift. 3. Resolution of D is a function of input clock to RTC_DELAY counter. Fig. 18 RTC timing diagram information are stored in non-volatile RAM every time they are 1. Acquire measurement data at time to (on an arbitrary TIC) calculated. After occurrence of a power glitch, the 100ms_TIC 2. Solve for UTC at measurement instant UTC (t ). Note that the 0 timebase restarts free running but with an arbitrary phase relation- solution can only be accurate to within the hardware propa- ship with respect to the TICs before the power glitch. The RTC gation delays in the receiver, typically a few microseconds, interrupt process occurs again as described above and it is possible unless these delays are calibrated and UTC solution is to relate the new system TIC time relative to the previous. Ideally, this corrected accordingly. process is precise enough such that the data bit sync is not lost and 3. Compute on which 100ms TIC, t , to take the next sample of m all the channel control registers can be reprogrammed with proper measurement data such that: values. Once the timing relationship is known, the PRESET mode UTC TIME MARK 2 t = d 1d m 1 2 can be used to resume tracking of the signals. 33 GP1020 Where UTCTIME MARK = Desired time mark synchronised to a UTC second. 40MHz MASTERCLOCK CLOCK 47 d = k 3 (time between TICS), 1 GENERATOR where k=INTEGER and d >Nav solution computation 1 delay. d = time offset (with 50 ns resolution) between time 2 20-BIT mark and 100ms_TIC labelled t 4571, 428 r COUNTER d < (time between TICS) 2 CLK 4. Acquire measurement data at t m • CNTL Compute Nav solution at t m • CONTROL Propagate Nav solution at UTC LOGIC • Given the oscillator drift, the delay of 25 ns added by • TIME_MARK_GEN block and the calibrated propagation 100ms TIC EXTERNAL delay, compute DOWN_COUNT, the value to program into LINE the programmable down counter to delay the time mark by d . 2 DRIVERS 20-BIT MARKFBx 5. Program down counter with DOWN_COUNT before the PROGRAMMABLE occurrence of t . r DOWN COUNTER 6. Output ARINC Data within 200ms after t (following ARINC r 743) 1 SEC. TIME MARK 7. Locate t 11 and go back to step 4. GP1020 m Fig. 19 Block diagram of TIME MARK generator t t t s1 s2 s3 100ms TIC RTC TIC D D 2 1 DRTC = (RTC 2RTC 2RTC ) 2 1 DRIFT RTC RTC 1 2 NOTES 1. t = t 2D 1DRTC1D (± error terms) s2 s1 1 2 2. ERROR TERMS: in ts : Equal to error terms of GPS time computation 1 while getting the NAV solution in D : Can be too long or too short by r, 1 where r = RTC_DELAY counter clock period in D : Same as D 2 1 in DRTC : Residual error in RTC drift estimate, = (effective RTC )2(estimated RTC ) DRIFT DRIFT Fig. 20 Timing diagram of a short glitch COMPUTE t m NAV SOLUTION COMPUTATION d d 1 2 DELAY 100ms TIC TIME t t t m r 0 TIME BETWEEN TICs OUTPUT IS CONSTANT UTC TIME MARK Fig. 21 TIME MARK timing diagram 34 GP1020 UTC ERROR BUDGET 4. Computation induced error: It is assumed that enough significant bits are retained such that this error approximates The following error budget is associated with the generation zero. of the Time Mark: Total Error = 5. TIME MARK transfer delay through drivers/cables: This TDOP1Clock Resolution1Oscillator Drift Residual Error. will be calibrated and compensated for up to the GPS receiver’s 1 Computation induced Error. output using the feedback to the down counter. There will be a 1 Time mark transfer delay through Drivers/cables. residual error due to: 1 Propagation delay in hardware, from antenna to correlator to measurement data sampler, where (a) Clock resolution = 50ns typical values are: (b) Feedback delay calibration = 25ns (estimated) 1. TDOP: estimated at 177ns with S/A ON (2 s number) 2. Clock Resolution: 50ns (in 21 bit programmable down 6. Propagation delays in the hardware: These are estimated counter). to be in the range of a few microseconds and are therefore the 3. Oscillator Drift Residual Error: major contributor to the TIME MARK synchronisation error. An (a) Due to temperature change on estimate could be included in the software to improve total TCXO since last oscillator drift accuracy when the total hardware design is complete. computation: about 50ns, computed with the following assumptions: TOTAL = 177ns150ns1100ns10175ns1hardware delays TOTAL = 402ns1hardware delays. (i) TCXO max slope is ± 1 ppm/°C (ii) Temperature max variation is 5 °C/minute 12. INTEGRATED CARRIER PHASE measurement (iii) The oscillator drift is computed every The GP1020 tracking channel hardware allows measure- second and is at most one second old at UTC ment of integrated carrier phase through CHx_CARR_CYCLE time mark. and CHx_CARR_DCO_PHASE registers. These two registers For example: are part of the measurement data sampled every TIC. The first 1ppm/°C 3 5°C/min 3 1sec one contains the 16 more significant bits of the number of full = 83ns for a temperature step change cycles elapsed and the second one contains the two remaining or 41.5 ns (rounded to 50ns) for a linear ramp less significant bits plus the cycle fraction (phase). Fig. 22 shows (b) Due to bias in drift estimation about 50ns max (rough how to add consecutive readings of these registers over several guess) TICs in order to get a consistent integrated carrier phase. TOTAL oscillator drift error = (a) 1 (b) ≈ 100ns. CARRIER CYCLES MEASUREMENT OVER MORE THAN ONE TIC PERIOD TIC TIC TIC 0 1 2 Y Y Y 1 2 0 2p2Y K CYCLES K CYCLES 0 1 2 DY DY 1 2 1. Reading at TIC : CHx_CARR_DCO_PHASE = Y 0 0 0 DY = 2p(K 11) 1Y 2Y 1 1 1 0 CHx_CARR_CYCLE CLEARED 0 = 2p (CHx_CARR_CYCLE )1CHx_CARR_DCO_PHASE 1 1 2CHx_CARR_DCO_PHASE 0 2. Reading at TIC : CHx_CARR_DCO_PHASE =Y 1 1 1 CHx_CARR_CYCLE = K 11 1 1 3. Reading at TIC : CHx_CARR_DCO_PHASE = Y 2 2 2 SDY = 2pS (CHx_CARR_CYCLE)1CHx_CARR_DCO_PHASE LAST CHx_CARR_CYCLE = K 11 2 2 2CHx_CARR_DCO_PHASE 0 Fig. 22 Integrated carrier phase measurement 35 GP1020 13. BUILT-IN TEST Functions The next table contains the truth table of the weight converter used in the SELF_TEST_GENERATOR : A. CHIP LEVEL Built-in Test Functions SELF_TEST_GENERATOR CARRIER_DCO bits MAG SIGN The GP1020 provides an on-chip self-test pattern generator (MSB-LSB) which is switched on under software control by setting SELF_TEST_EN bit of the BITE register. It uses tracking chan- 01011 1 MSB nel 1 or 2 according to the setting of SELF_TEST_SOURCE bit 011xx 1 MSB of the BITE register to generate SIGN and MAGNITUDE -like 100xx 1 MSB signals which can be fed back to any or all other channels by 10100 1 MSB selecting the self test signal source in CHx_SIG_SEL. The self- All other combinations 0 MSB test signal has a fixed data bit pattern of alternating one and zero every 20 milliseconds, the first bit being LOW. It has a fixed noise The design of the weight converter will drive a HIGH on the pattern which corresponds to particular In-phase and Quad- SIGN bit for 50% of the time and on the MAG bit for 31% of the phase accumulated values. The C/A code and the Doppler shift time. can be varied by programming the relevant registers of the Examples 1 and 2 show the results of the five first accumula- channel which has been selected by SELF_TEST_SOURCE. tions of the accumulated data for two different settings of the The standard software can then be used to acquire and track the SELF_TEST_GENERATOR and the channels. Because the self-test signal but it should take into account the fact that this channels had been started at the same time, they are practically self-test signal is not a real GPS signal. in phase with the incoming data (Sign and Mag outputs of the The SELF_TEST_GENERATOR output signal can also be SELF_TEST_GENERATOR). wrapped around externally by connecting the TSIGN and TMAG output pins to a GPS or GLONASS input port. Normally, the test source and tested channels will have the same DCO settings. Example 1: Value Register settings Comments (Hex) BITE 0020 STG on, CH1 as source TDATA_DUTY_CYCLE 0000 No noise (will cause an overflow condition in Q_PROMPT register if signals are in phase) CHx_SIG_SEL 000A Signal from the STG CHx_CODE_INCR_HI 016E CHx_CODE_INCR_LO A4A8 CHx_CARR_INCR_HI 01F5 CHx_CARR_INCR_LO C28F CHx_CNTL 0225 SV PRN 19, Dithering code RESET_CNTL 007F Start all channels at the same time First Second Third Fourth Fifth Results dump dump dump dump dump CHx_I_DITH 0388 0318 016C 04CC 02AC CHx_Q_DITH 3D28 3D98 3C34 3D78 3FE4 CHx_I_PROMPT 0A30 093C 0930 08F8 0978 CHx_Q_PROMPT 7FFC 7FFC 7FFC 7FFC 7FFC 36 GP1020 Example 2: Value Register settings Comments (Hex) BITE 0020 STG on, CH1 as source TDATA_DUTY_CYCLE 07F7 Invert the data 8 times in 11 CHx_SIG_SEL 000A Signal from the STG CHx_CODE_INCR_HI 016E CHx_CODE_INCR_LO A4A8 CHx_CARR_INCR_HI 01F5 CHx_CARR_INCR_LO B1B3 CHx_CNTL 0315 SV PRN 1, Early_Minus_Late code RESET_CNTL 007F Start all channels at the same time First Second Third Fourth Fifth Results dump dump dump dump dump CHx_I_DITH 2230 1EB8 2170 2030 1F00 CHx_Q_DITH 0598 0568 0374 078C 03CC CHx_I_PROMPT F8F4 0078 03E8 FF08 0590 CHx_Q_PROMPT 46D8 4798 4914 47B8 46D4 ADD_DAT_TST REGISTER Scan Loops and Internal Node Real-Time Observability The ADD_DAT_TST register allows the software and the ATE A number of registers are not connected to the data bus in any to verify the functionality of the data and address busses. For full way. These registers have two modes of operation: The normal details see ADD_DAT_TST section of DETAILED DESCRIP- mode and the SCAN LOOP mode in which the flip flops are cascaded TION OF REGISTERS. to form a shift register. There is one such scan loop per channel. Fig. 23 shows a block diagram of the Chip test functions. TDI1 B. SYSTEM-LEVEL Built-in Test Functions (Test Data In) is a serial input common to all scan loop shift registers. Each scan loop has a separate data O/P pin TDO (1:7) (Test Data GP1010 BITE interface: Out). The GP1020 BITE CNTL discrete output is provided to drive The control signal TSCAN (Test Scan) determines whether the the corresponding discrete input pin of the GP1010. When active, registers operate in normal mode (TSCAN LOW) or in scan loop this control unlocks the PLL and switches off the GP1010 front- mode (TSCAN HIGH). end amplifiers. As a result, the GP1020 should read an unlocked The Control Signal TCKS (Test Clock Select), when HIGH, status at its PLL LOCK discrete input. selects the 7 test clocks TCK(1:7) as a replacement for the seven The GP1020 includes Sign and Magnitude statistics checker clock phases provided by the clock generator in normal mode. This circuit. is intended for use only in the device factory and not in normal GLONASS IC BITE interface: operational use. TMS1 and TMS2 are Test Mode Select control pins. Uses the same BITE CNTL discrete output to put the GLONASS Their function is detailed in the following table: IC into test mode and one GP1020 discrete input pin, GLONASSBIT, for GLONASS IC go/nogo status. TMS2 TMS1 TIME MARK : LOW LOW Normal mode: SIGN (2:8) and Three MARK FEEDBACK input pins, selected by bits 7 to 5 of MAG (2:9) configured as inputs. TIMER_CNTL, are provided for testing the signal outputs of TDO (1:7) held LOW. TCK(1:7) TIME MARK line drivers. configured as inputs. SIGN (9) is Also, software selectable control bits (TIMER_CNTL bits 4 always used as a normal input. and 8) allow multiplexing of the normal 1 second period TIME MARK with one of two test signals, either 40MHz/91 = LOW HIGH Scan Loop mode: SIGN (2:8) 439.5604KHz intended for oscillator drift measurement or and MAG (2:9) onfigured as CH1_DUMP for system fault-finding purposes. inputs. TDO (1:7) output serial scan data. TCK (1:7) configured 14. CHIP MANUFACTURING-TEST Functions as inputs. HIGH X Channel 1 observability mode: The GP1020 design incorporates a series of features to SIGN (2:8), MAG (2:9) and TCK increase (a) the observability of internal nodes when working in (1:7) configured as outputs and the application and ( b) the observability and the controllability of together with TDO (1:7) allow the circuit during chip-level testing during manufacture. The real-time observability of internal following presents a summary of the chip test functions: nodes of channel 1 as listed TEST REGISTERS below. The internal TIC signal A number of registers have been added to improve the and the signal latching the status testability of the chip. They are not required for normal bits are also available on TDO4 operation : CHx_TST_CODE_PHASE, CHx_TST_CYCLE and and TDO7 pins. CHx_TST_CODE_SLEW. 37 GP1020 SIGN (2 : 8) MAG (2 : 9) TMS 2 SERIAL DATA TDI 1 MUX TCK 8 TDO (1) CHANNEL 1 CNTL TSCAN NODES MUX CHANNEL 2 TDO (2) CNTL MUX CHANNEL 3 TDO (3) CNTL MUX TDO (4) CHANNEL 4 CNTL MUX CHANNEL 5 TDO (5) CNTL MUX CHANNEL 6 TDO (6) CNTL OTHER CHIP MUX TDO (7) FUNCTIONS CNTL TMS1 CLK (1 : 7) TCKS TCKS CNTL MUX CLK (1 : 7) CLOCK TCK (1 : 7) GENERATOR Fig. 23 Chip test functions 38 GP1020 TABLE OF ACCESSIBLE CHANNEL INTERNAL NODES CNTL PIN: TMS1: LOW HIGH LOW LOW CNTL PIN: SIGN9 LOW LOW HIGH HIGH IN PHASE I & Q ACCUMULATOR ARM O/P pin Prompt Dithering Prompt Dithering SIGN 2 bit 13 13 12 12 MAG 2 bit 11 11 5 5 SIGN 3 bit 10 10 4 4 MAG 3 bit 9 9 3 3 SIGN4 bit 8 8 2 2 MAG 4 bit 7 7 1 1 SIGN 5 bit 6 6 0 0 QUAD-PHASE I & Q ACCUMULATOR ARM Prompt Dithering Prompt Dithering MAG 5 bit 13 13 12 12 SIGN 6 bit 11 11 5 5 MAG 6 bit 10 10 4 4 SIGN 7 bit 9 9 3 3 MAG 7 bit 8 8 2 2 SIGN 8 bit 7 7 1 1 MAG 8 bit 6 6 0 0 MAG 9 Dump Dump Dump Dump MIX_CORREL output In Phase ARM Quad Phase ARM Prompt Dithering Prompt Dithering TCK3 bit 0 0 0 0 TCK4 bit 1 1 1 1 TCK5 bit 2 2 2 2 TCK6 bit 3 3 3 3 LOW HIGH CNTL PIN: TMS1: X X CNTL PIN: SIGN9 CodeCLK Code CLK TDO1 Prompt C/A code Dithering C/A code TDO2 Preset load CARR DCO O/P bit 25 TDO3 TIC CARR DCO O/P bit 26 TDO4 CARR DCO O/P bit 27 CARR DCO O/P bit 27 TDO5 1ms epoch carry 1ms epoch carry TDO6 STATUS latch control STATUS latch control TDO7 X CNTL PIN: TMS1: X CNTL PIN: SIGN9 Sampled SIGN TCK1 Sampled MAG TCK2 RESCODEGEN TCK7 39 GP1020 15. BOUNDARY SCAN LOOP A boundary scan loop is implemented to allow the ATE to verify the connections of the chip at board level. The following pins are not included in Boundary Scan Loop : TDI1 100/219kHz SAMPCLK MASTERCLK BIAS PLLLOCKIN SLAVECLK TCK(1:8) MARK RTCINT MARKFB1 MARKFB2 MARKFB3 NANDA NANDB NANDOP The TAP controller has all functions necessary to be compatible with the JTAG standard (IEEE 1149.1-1990) with a few exceptions: All bidirectional pins are in input mode when the TRST signal is inactive (HIGH) so the chip cannot run freely when in bypass mode. The Capture-IR state loads the instruction 000 instead of x01. • The pins TMS, TCK and TRST do not have pull-up resistors. • This is the order of the pins in the loop (column by column): • A7 INTOUT* MAG9 D2 D15 A8 SIGN2 SIGN9 D3 ALE MASTER/SLAVE MAG3 MAG1 D4 A1 TCKS SIGN3 SIGN1 D5 A2 MASTERRESET MAG4 MAG0 D6 A3 MOT/INTEL SIGN4 SIGN0 D7 A4 CS MAG5 CLKSEL WPROG A5 WEN SIGN5 BITECNTL* D8 A6 RW MAG6 GLONASSBIT D9 TSCAN TMS2 SIGN6 INTIN D10 TMS1 MAG7 TICIN D11 TMAG* SIGN7 TICOUT* D12 TSIGN* MAG8 D0 D13 MAG2 SIGN8 D1 D14 NOTE: An asterisk in the above list indicates an output pin. 40 GP1020 APPLICATION NOTES PCB LAYOUT CONSIDERATIONS The GP1020 is a fast CMOS device so, although clock rates are low, the edge speeds can be very high. The board layout must, therefore, handle these edges on both output signals and on power supply current. SIMPLIFIED SYSTEM It is not always necessary to use all of the features of the GP1020 to make a good GPS receiver. The following pin connections show the minimum requirement and are given as a guide only. Unused inputs must be tied to V or V and not left floating. Failure to observe this may result in malfunction or damage to SS DD the device. Pin No. Signal name Description Connection 1 and 2 A7, A8 Address bus To microprocessor 3 MASTER/SLAVE Master or Slave mode select High, unless Slave 4 and 5 TSCAN, TCKS Control Test mode Both low 6 TDI1 Test Data serial input Low 7 MASTERRESET General reset, active low Power-on timer 8 MOT/INTEL Bus mode select High for Motorola, low for Intel 9 CS Chip Select, active low To microprocessor 10 V Ground 0V SS 11 V Positive supply 15V DD 12 WEN Write Enable - see mode table, page 3 To microprocessor 13 RW Read/Write - see mode table, page 3 To microprocessor 14 and 15 TMS2, TMS1 Test Mode Select 2 and 1 Both low 16 and17 TMAG, TSIGN Test PRN pattern output Leave open 18 MAG2 Source 2 MAG input Low 19 100/219kHz Clock output Leave open 20 V Positive supply 15V DD 21 V Ground 0V SS 22 INTOUT Interrupt output To microprocessor 23 to 39 SIGN and MAG 1 to 9 Source 1 to 9 SIGN and MAG inputs All low 40 V Ground 0V SS 41 V Positive supply 15V DD 42 and 43 MAG0, SIGN0 Source Mag and SIGN inputs To GP1010 44 SAMPCLK Sampling clock To GP1010 45 V Positive supply 15V DD 46 MASTERCLK 40MHz Master Clock To GP1010 47 V Ground 0V SS 48 BIAS Bias for Master Clock See Fig. 12 (page 8) 49 V Ground 0V SS 50 V Positive supply 15V DD 51 V Ground 0V SS 52 CLKSEL 100kHz (high)/219kHz (low) select High 53 PLLLOCKIN PLL Status input Low or GP1010 54 BITECNTL BITE control to Front-end Leave open 55 GLONASSBIT GLONASS BITE input Low 56 SLAVECLK Master to Slave clock Leave open 57 INTIN Interrupt input for Slave Low 58 to 65 TCK 1to 8 Test clocks or signals All low 66 TICIN TIC input to Slave Low 67 TICOUT TIC output from Master Leave open 68 and 69 D0 and D1 Data bus To microprocessor 70 V Ground 0V SS 71 V Positive supply 15V DD 72 and 73 D2 and D3 Data bus To microprocessor 74 TIMEMARK 1 PPS output Leave open 75 RTCINT Real Time Clock interrupt input Low 76 and 77 MARKFB 1 and 2 Time Mark driver feedback Both low 78 and 79 D4 and D5 Data bus To microprocessor 80 V Positive supply 15V DD Continued… 41 GP1020 PIN CONNECTIONS FOR A SIMPLIFIED SYSTEM (continued) Pin No. Signal name Description Connection 81 V Ground 0V SS 82 and 83 D6 and D7 Data bus To microprocessor 84 WPROG Bus timing mode select Low (see note 5) 85 and 86 NANDA and B Test/spare gate inputs Low 87 TDO Boundary Scan output Leave open 88 and 89 TCK and TRST Boundary Scan clock and Reset Both low 90 NANDOP Test/spare gate output Leave open 91 and 92 TMS and TDI Boundary Scan select and input Both low 93 MARKFB3 Time Mark driver feedback Low 94 TDO7 Test Data Output 7 Leave open 95 DISCOP General purpose output pin Leave open 96 and 97 TDO6 and TDO5 Test Data Outputs 6 and 5 Leave open 98 and 99 D8 and D9 Data bus To microprocessor 100 V Ground 0V SS 101 V Positive supply 15V DD 102 and 103 D10 and D11 Data bus To microprocessor 104 to 107 TDO4 to TDO1 Test Data Outputs 4 to 1 Leave open 108 and 109 D12 and D13 Data bus To microprocessor 110 V Positive supply 15V DD 111 V Ground 0V SS To microprocessor 112 and 113 D14 and D15 Data bus To microprocessor 114 ALE Address Latch Enable To microprocessor 115 to 120 A1 to A6 Address bus Notes 1. The action of WEN and RW is given in the table at the foot 5. WPROG is used to modify the Write timing. For most of page 3. applications, WPROG should be tied low. For use with an 2. In the above list, it is assumed that only one Front-end is Intel 486, it may be better to tie WPROG high to delay the being used and that it is connected to SIGN0 and MAG0. start of the Write operation until after the address decode Any other SIGN and MAG pair may be chosen if desired. in the GP1020 has settled. 3. Unused inputs are listed in the above table as tied low (to 6. ALE is listed as ‘To microprocessor’ but it is possible in ground) so that they are not left floating. systems with WPROG tied low to have ALE tied high to 4. Connections listed ‘To microprocessor’ may, in some make the latches in the GP1020 transparent if the address systems, be made via glue logic such as address latches. bus is externally latched for the write or read operation. 42 For more information about all Zarlink products visit our Web Site at www.zarlink.com Information relating to products and services furnished herein by Zarlink Semiconductor Inc. trading as Zarlink Semiconductor or its subsidiaries (collectively “Zarlink”) is believed to be reliable. However, Zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or use. 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