VMIPCI-5576 Fiber-Optic Reflective Memory with Interrupts • High-speed, easy-to-use fiber-optic network (170 Mbaud serially) • Data written to memory in one node is also written to memory in all nodes on the network • Up to 2,000 m between nodes and up to 256 nodes • Data transferred at 6.2 Mbyte/s without redundant transfer • Data transferred at 3.2 Mbyte/s with redundant transfer • Any node on the network can generate an interrupt in any other node on the network or in all network nodes with a single command • Error detection • Redundant transmission mode for suppressing errors • No processor overhead • No processor involvement in the operation of the network • Up to 1 Mbyte of Reflective Memory • D32:D16:D8 memory access • Single PCI 5 V slot, standard long card • PCI target data bursts supported with 44 Mbyte/s transfer rates • PCI master DMA controller. DMA transfer rates of 132 Mbyte/s maximum and 33 Mbyte/s sustained. • Configurable endian conversions for multiple CPU architectures on the network • Communication link compatible with VMIVME-5576 and VMIMB1-5576 • Software-addressable digital output bit available at output connector for use with optical switch board or any user-defined purpose • Windows NT® OS driver available which operates the VMIPCI-5576 as a network interface board. Allows TCP/IP and other protocol connectivity on a Ordering Options network of VMIPCI-5576 or VMIVME-5576 nodes. January 14, 1998 800-855576-000 B ABC – D E F INTRODUCTION — The VMIPCI-5576 is a PCI bus VMIPCI-5576 –1 – board which may be used with other VMIC 5576 family A = Memory Options boards to form a high-performance, daisy-chained, 0 = 256 Kbyte 1 = 512 Kbyte fiber-optic network. Data is transferred by writing to 2 = 1 Mbyte on-board global RAM. The data is automatically sent to the B = FIFO Option 0 = 512 Transfer FIFO same location in memory on all Reflective Memory boards on 1 = 4 K Transfer FIFO the network. The Reflective Memory network can include C = 1 (Option reserved for future use) PCI, VME, and Multibus systems. The network-compatible Connector Data members of the 5576 family include the VMIVME-5576 and Compatible Connector ST Connector VMIMB1-5576. PC Board Fiber-Optic Fiber-Optic Receiver HFBR-2100 Transmitter/Receiver (Hewlett-Packard) Fiber-Optic Transmitter HFBR-1100 PRODUCT OVERVIEW — The Reflective Memory (Hewlett-Packard) concept provides a very fast and efficient way of sharing data Cable Specifications across distributed computer systems. Fiber-Optic Cable – Multimode; 62.5 Micron core. Transmitters operate at 1,300 nm at 170 Mbaud. Maximum attenuation between nodes is 9 dB. VMIC’s VMIPCI-5576 Reflective Memory interface Minimum attenuation between nodes is .5 dB. allows data to be shared between up to 256 independent Fiber-Optic Cable Assemblies ABC – D E F systems (nodes) at rates up to 6.2 Mbyte/s. Each Reflective VMICBL-000-F3 – – Memory board may be configured with 256 Kbyte to 1 Mbyte A = Fiber-Optic Connector Type of on-board SRAM. The local SRAM provides fast Read 0 = Ceramic Ferrule ST Connector access times to stored data. Writes are stored in local SRAM 1 = Stainless Steel Ferrule ST Connector BC = Cable Lengths and broadcast over a high-speed fiber-optic data path to other 00 = Not Used 09 = 1,000 ft (304.8 m) 01 = 5 ft (1.5 m) 10 = 1,500 ft (457.3 m) Reflective Memory nodes. The transfer of data between 02 = 25 ft (7.6 m) 11 = 2,000 ft (609.7 m) nodes is software transparent, so no I/O overhead is required. 03 = 50 ft (15.2 m) 12 = 2,460 ft (750.0 m) 04 = 100 ft (30.4 m) 13 = 3,280 ft (1,000 m) Transmit and Receive FIFOs buffer data during peak data 05 = 150 ft (45.7 m) 14 = 4,100 ft (1,250 m) 06 = 200 ft (60.9 m) 15 = 4,920 ft (1,500 m) rates to optimize CPU and bus performance to maintain high 07 = 350 ft (106.7 m) 16 = 5,740 ft (1,750 m) data throughput. 08 = 500 ft (152.4 m) 17 = 6,560 ft (2,000 m) Note The Reflective Memory also allows interrupts to one or VMIC offers single fiber cable assemblies that are compatible with the VMIVME-5576 in length ranging from 1.5 to 2,000 m. These cable assemblies more nodes by writing to a byte register. Three separate, are U.L./NEC-rated OFNP and have a 2.5 mm ST-style bayonet connector user-definable interrupts may be used to synchronize a on each end. system process, or used to follow any data. The interrupt For Ordering Information, Call: 1-800-322-3616 or 1-256-880-0444 • FAX (256) 882-0859 always follows the data to ensure the reception of the data E-mail: info@vmic.com Web Address: www.vmic.com before the interrupt is acknowledged. Copyright © May 1996 by VMIC Specifications subject to change without notice. VMIC • 12090 South Memorial Parkway • Huntsville, Alabama 35803-3308 1 VMIPCI-5576 The VMIPCI-5576 requires no initialization unless bus as appropriate and move up to 1 Mbyte as a PCI initiator. interrupts are being used or endian byte swapping is desired. This capability removes the CPU from the responsibility of requesting the PCI bus and moving the data itself. This Each node on the system has a unique identification feature is very useful for moving large blocks of data. The number between 0 and 255. The node number is established PCI architecture ensures that the VMIPCI-5576 does not during hardware system integration by placement of jumpers monopolize the PCI bus during this process. Large DMA on the board. This node number can be read by software by blocks will automatically be split into smaller bursts on the accessing an on-board register. In some applications, this PCI bus by the DMA engine. The VMIPCI-5576 can be node number would be useful in establishing the function of programmed to issue a PCI interrupt at the conclusion of a the node. DMA transfer or the host can poll the status of the DMA process. The status of the DMA can be accessed from the In order to achieve an aggregate throughput of board, if required. Although the DMA engine can do both 6.2 Mbyte/s, nodes capable of writing to the Reflective DMA reads and DMA writes, they cannot occur Memory network at an aggregate rate of 6.2 Mbyte/s must be simultaneously. The VMIPCI-5576 can burst data onto the present. PCI bus at a maximum rate of 132 Mbyte/s and a sustained rate of 33 Mbyte/s. If the target operates at a slower rate, the LINK ARBITRATION — The VMIPCI-5576 system is PCI handshaking capabilities will throttle the data rate. a fiber-optic daisy chain ring as shown in Figure 1. Each transfer is passed from node-to-node until it has gone all the ERROR MANAGEMENT — Errors are detected by way around the ring and reaches the originating node. Each the VMIPCI-5576 with the use of the error detection facilities node retransmits all transfers that it receives except those that of the TAXI chipset and additional parity encoding and it originated. Nodes are allowed to insert transfers between checking. When a node detects an error, the erroneous transfers passing through. transfer is removed from the system and a PCI bus interrupt is generated, if enabled. The error rate of the VMIPCI-5576 INTERRUPT TRANSFERS — In addition to is a function of the rate of errors produced in the optical transferring data between nodes, the VMIPCI-5576 will portion of the system. This optical error rate depends on the allow any processor in any node to generate an interrupt on length and type of fiber-optic cable. Assuming an optical -12 -10 any other node. These interrupts would generally be used to , the error rate of the VMIPCI-5576 is 10 error rate of 10 indicate to the receiving node that new data has been sent and transfers/transfer. is ready for processing. These interrupts are also used to indicate that processing of old data is completed and the The VMIPCI-5576 can be operated in a redundant receiving node is ready for new data. transfer mode in which each transfer is transmitted twice. In this mode of operation, the first of the two transfers is used Three interrupts are available. The user may define the unless an error is detected in which case the second transfer function for each interrupt. Any processor can generate an is used. In the event that an error is detected in both transfers, interrupt on any other node on the network. In addition, any the node removes the transfer from the system. The -20 processor on the network can generate an interrupt on all probability of both transfers containing an error is 10 , or nodes on the network. Interrupts are generated by simply about one error every 3,731,000 years at maximum data rate. writing to a VMIPCI-5576 register. ENDIAN CONVERSIONS — Data lane steering can All data and interrupt command transfers contain the be configured in a Control Register to allow CPUs of different node number of the node that originated the transfer. This architectures to communicate. Byte swap, Word swap, and information is used primarily so the originating node can Byte-Word swap options are available. remove the transfer from the network after the transfer has traversed the ring. The node identification is also used by PROTECTION AGAINST LOST DATA — Data nodes receiving interrupt commands. When a node receives received by the node from the fiber-optic cable is error an interrupt command for itself, it places the identification checked and placed in a receive FIFO. Arbitration with number of the originating node in a FIFO. Up to 512 accesses from the PCI bus then takes place, and the data is interrupts can be stacked in the FIFO. During the interrupt written to the node’s SRAM and to the node’s transmit FIFO. service routine, the identification of the interrupting node can Data written to the board from the PCI bus is placed directly be read from the FIFO. into SRAM and into the transmit FIFO. Data in the transmit FIFO is transmitted by the node over the fiber-optic cable to PCI INITIATOR/DMA CAPABILITIES — The DMA the next node. Data could be lost if either FIFO were allowed capability is initiated by a PCI host. After the DMA engine is to become full. initialized by a host, the VMIPCI-5576 will request the PCI 2 For Ordering Information, Call: 1-800-322-3616 or 1-256-880-0444 • FAX (256) 882-0859 Artisan Scientific - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisan-scientific.com VMIPCI-5576 The product is designed to prevent either FIFO from Memory Size: 256 Kbyte, 512 Kbyte, or 1 Mbyte becoming full and overflowing. It is important to note the The 256 Kbyte, 512 Kbyte, and 1 Mbyte memory only way that data can start to accumulate in FIFOs is for data options of the VMIPCI-5576 all use 1 Mbyte of address to enter the node at a rate greater than 6.2 Mbyte/s or space to locate data in the local node. Since the PCI bus 3.2 Mbyte/s in redundant mode. Since data can enter from the is an automapped bus, all of these memory options must fiber and from the PCI bus, it is possible to exceed these rates. occupy 1 Mbyte of memory space on the PCI bus. This If the transmit FIFO becomes half-full, a bit in the Status mapping structure allows these options to be compatible Register is set. This is an indication to the node’s software with VMIVME-5576 Reflective Memories of size that subsequent WRITEs to the Reflective Memory should be 1 Mbyte and smaller. suspended until the FIFO is less than half-full. If the half-full indication is ignored and the transmit FIFO becomes full, INTERCONNECTION then writes to the Reflective Memory will be acknowledged with a STOP*. No data will be lost. Cable Requirements: Two fiber-optic cables If the receive FIFO is allowed to become over half-full, Cable Length: 2,000 m maximum between nodes there is a danger the receiver FIFO may overflow resulting in data loss. In order to prevent this situation, all PCI writes will Configuration: Daisy chain ring up to 256 nodes be acknowledged by a STOP* until the receive FIFO is less than half-full. Power Requirements: 5.0 A maximum at +5 VDC NETWORK MONITOR — There is a bit in a Status PHYSICAL/ENVIRONMENTAL Register that can be used to verify that data is traversing the ring (that is, the ring is not broken). This can also be used to Temperature Range: 0 to 65 °C, operating with measure network latency. forced air cooling. -40 to 85 °C, storage. VMIC offers single fiber cable assemblies that are Relative Humidity: 20 to 80 percent, noncondensing compatible with the VMIPCI-5576 in length ranging from 1.5 to 2,000 m. These cable assemblies are U.L./NEC-rated DATA TRANSFERS OFNP and have a 2.5 mm ST-style bayonet connector on each end. Data written into the Reflective Memory is broadcast to all nodes on the network without further involvement of SOFTWARE DRIVER — A Windows NT OS driver the sending or receiving nodes. Data is transferred from for the VMIPCI-5576 is available. The driver is NDIS memory locations on the sending nodes to corresponding compliant and supports the protocols configured into the memory locations on the receiving nodes. Windows NT OS including TCP/IP. The driver operates the VMIPCI-5576 as a network interface board. A portion of the A functional block diagram of the VMIPCI-5576 is Reflective Memory is reserved by the driver for network use, shown in Figure 2. and the remainder of memory is available as simple user-shared memory. When used as a network interface board, the VMIPCI-5576 has a dual role; the board provides TRADEMARKS both network connectivity as well as fast shared memory for distributed applications. The VMIC logo is a registered trademark of VMIC. Windows NT is a registered trademark of Microsoft Corporation. Other registered trademarks are the property of SPECIFICATIONS their respective owners. PCI Transfer Rate: 44 Mbyte/s as a Target, As DMA Initiator: 132 Mbyte/s maximum, 33 Mbyte/s sustained Network Transfer Rate: 6.2 Mbyte/s (longword accesses) without redundant transfer 3.2 Mbyte/s (longword accesses) with redundant transfer VMIC • 12090 South Memorial Parkway • Huntsville, Alabama 35803-3308 3 Artisan Scientific - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisan-scientific.com VMIPCI-5576 C 5 P 5 VMEbus CHASSIS U 7 NODE 0 WITH CPU AND 6 VMIVME-5576 C 5 P 5 U 7 Multibus CHASSIS NODE 1 6 WITH CPU AND VMIMB1-5576 VME COMPUTER NODES CAN BE VMEbus-BASED COMPUTERS OR COMPUTERS 5 WITH VMEbus I/O CHANNELS 5 SUCH AS SUN, HARRIS NIGHT NODE 2 7 HAWK, CONCURRENT, SILICON 6 GRAPHICS, DATA GENERAL, MOTOROLA DELTA SERIES, ENCORE 91 SERIES, ANY VMEbus CHASSIS, ETC. NODE 255 PCI bus PCI bus CHASSIS WORKSTATION WITH VMIPCI-5576 UP TO 2,000 m BETWEEN NODES Figure 1. Network Example Using Reflective Memory System FIBER-OPTIC FIBER-OPTIC CABLE CABLE FO FO REC'D TX TAXI TAXI RECEIVER TRANSMITTER INTERRUPT LOGIC TAXI INTERFACE 4 Kbyte/ 4 Kbyte/ CONTROL 512 DEEP 512 DEEP LOGIC IN FIFO OUT FIFO CTRL CTRL CS FIFO/RCV CTRL RAM CTRL WR RAM ADDRESS CONTROL PCI PCI bus I/F 1 Mbyte RAM MAXIMUM DATA ENDIAN SWAP BUFFER Figure 2. VMIPCI-5576 Functional Block Diagram 4 For Ordering Information, Call: 1-800-322-3616 or 1-256-880-0444 • FAX (256) 882-0859 Artisan Scientific - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisan-scientific.com Looking for more information? Visit us on the web at http://www.artisan-scientific.com for more information: • Price Quotations • Drivers· Technical Specifications. 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