97��&���% 3,3& 3&,�,QWHJUDWHG�3HULSKHUDO�&RQWUROOHU 3&���&RPSOLDQW�3&,�WR�,6$�%ULGJH ZLWK�$&3,��’LVWULEXWHG�’0$��3OXJ�DQG�3OD\� 0DVWHU�0RGH�3&,�,’(�&RQWUROOHU�ZLWK�8OWUD’0$��� 86%�&RQWUROOHU��.H\ERDUG�&RQWUROOHU��DQG�57& 5HYLVLRQ���� 0D\��������� 9,$�7(&+12/2*,(6��,1&� &RS\ULJKW�1RWLFH� &RS\ULJKW� 9,$7HFKQRORJLHV,QFRUSRUDWHG3ULQWHGLQWKH8QLWHG6WDWHV$//5,*+765(6(59(’ 1RSDUWRIWKLVGRFXPHQWPD\EHUHSURGXFHGWUDQVPLWWHGWUDQVFULEHGVWRUHGLQDUHWULHYDOV\VWHPRUWUDQVODWHGLQWR DQ\ODQJXDJHLQDQ\IRUPRUE\DQ\PHDQVHOHFWURQLFPHFKDQLFDOPDJQHWLFRSWLFDOFKHPLFDOPDQXDORURWKHUZLVH ZLWKRXWWKHSULRUZULWWHQSHUPLVVLRQRI9,$7HFKQRORJLHV,QFRUSRUDWHG 7KH97&97&$DQG97&%PD\RQO\EHXVHGWRLGHQWLI\SURGXFWVRI9,$7HFKQRORJLHV LVDUHJLVWHUHGWUDGHPDUNRI9,$7HFKQRORJLHV,QFRUSRUDWHG 70 36LVDUHJLVWHUHGWUDGHPDUNRI,QWHUQDWLRQDO%XVLQHVV0DFKLQHV&RUS 707070 3HQWLXP3UR*7/DQG$3,&DUHUHJLVWHUHGWUDGHPDUNVRI,QWHO&RUS 7070 :LQGRZVDQG3OXJDQG3OD\DUHUHJLVWHUHGWUDGHPDUNVRI0LFURVRIW&RUS 70 3&,LVDUHJLVWHUHGWUDGHPDUNRIWKH3&,6SHFLDO,QWHUHVW*URXS 9(6$LVDWUDGHPDUNRIWKH9LGHR(OHFWURQLFV6WDQGDUGV$VVRFLDWLRQ $OOWUDGHPDUNVDUHWKHSURSHUWLHVRIWKHLUUHVSHFWLYHRZQHUV ’LVFODLPHU�1RWLFH� 1ROLFHQVHLVJUDQWHGLPSOLHGRURWKHUZLVHXQGHUDQ\SDWHQWRUSDWHQWULJKWVRI9,$7HFKQRORJLHV9,$7HFKQRORJLHV PDNHVQRZDUUDQWLHVLPSOLHGRURWKHUZLVHLQUHJDUGWRWKLVGRFXPHQWDQGWRWKHSURGXFWVGHVFULEHGLQWKLVGRFXPHQW 7KHLQIRUPDWLRQSURYLGHGE\WKLVGRFXPHQWLVEHOLHYHGWREHDFFXUDWHDQGUHOLDEOHWRWKHSXEOLFDWLRQGDWHRIWKLV GRFXPHQW+RZHYHU9,$7HFKQRORJLHVDVVXPHVQRUHVSRQVLELOLW\IRUDQ\HUURUVLQWKLVGRFXPHQW)XUWKHUPRUH9,$ 7HFKQRORJLHVDVVXPHVQRUHVSRQVLELOLW\IRUWKHXVHRUPLVXVHRIWKHLQIRUPDWLRQLQWKLVGRFXPHQWDQGIRUDQ\SDWHQW LQIULQJHPHQWVWKDWPD\DULVHIURPWKHXVHRIWKLVGRFXPHQW7KHLQIRUPDWLRQDQGSURGXFWVSHFLILFDWLRQVZLWKLQWKLV GRFXPHQWDUHVXEMHFWWRFKDQJHDWDQ\WLPHZLWKRXWQRWLFHDQGZLWKRXWREOLJDWLRQWRQRWLI\DQ\SHUVRQRIVXFKFKDQJH 2IILFHV� 86$2IILFH7DLSHL2IILFH %UDQGLQ&RXUWWK)ORRU1R )UHPRQW&$&KXQJ&KHQJ5RDG+VLQ7LHQ 86$7DLSHL7DLZDQ52& 7HO7HO )D[)D[ 2QOLQH�6HUYLFHV� +RPH3DJHKWWSZZZYLDFRPWZ )736HUYHUIWSYLDFRPWZ %%6 �9,$�7HFKQRORJLHV��,QF� VT82C586B REVISION HISTORY Document Release Date Revision Initials Revision 0.1 10/13/96 Initial release for 586A DH Revision 0.5 12/23/96 Update to reflect 586B: DH • Updated pin definitions: reprinted Pins 18,31,33,58,60,131,133 (removed EXTSMI2-7 & DACEN) 1/8/97 Pins 77-78,80-83,85-86 (added GPI8-15 and GPO8-15) to fix Pins 94,87-88,92,136 (changed to GPIO0-4 and added alternate functions) Acrobat Pins 90,106,137 (added MIRQ0, MIRQ1, and MIRQ2 functions) PDF file Pins 91,93,103,107 (changed to PWRBTN#, RI#, VDD-5VSB, PWRON) size Pins 113-114,116-119,121-122 (added GPI, GPO, and EXTSMI functions) problem Fixed doc error DACK0-7 pin names changed to active low (DACK0-7#) Removed options: IRQ12 (pin 137), strap (pin 48), RTCAS (pin 94) • Updated register definitions Removed VIA-specific port A8/A9 registers Updated function 0 Rx5-4[3], Rx7-6[13], Rx41[0-4,6-7], Rx42[4-7], Rx44, Rx46[2-4], Rx47[3], Rx48[3], Rx4A[4-6], Removed Rx50 (MDRQ) Incorrect Rx55[7-4] change PIRQD# to MIRQ1, Rx56 swap A/B, Rx57 swap C/D Change Added 58-5B for PnP, XD, KBC/RTC config; added 60-6F for DDMA ctrl Removed power mgmt regs 80-94 & added function 3 ACPI Power Mgmt • Straps: moved 95-96 to 5A, allow RW after powerup, removed strap XD3 • Expanded CMOS RAM: added ports 72-75 & table 5 CMOS Reg Summary • Added Power Management Subsystem Overview • Incorporated App Note #53 APM-Compliant Pwr Mgmt Model of 82C586A • Added AC Timing Section with IDE Interface Timing Diagrams & Specs Revision 1.0 5/13/97 • Overview Changes: Added System Block Diagram DH • Pin Function Changes: Pin 90 added alternate function "POS" output (3040F and 3041 silicon) Pin 106 added alternate function "IRQ8#" input (3040F and 3041 silicon) Pin 137 added alternate function "SDDIR" output (3041 only silicon) • Register Definition Changes: Fixed typos: Port 75 note, Fn0 Rx48[3], Rx55-57[7:0]; Fn1 Rx4[7]; Fn2 Rx3C-3D; Fn3 Rx26[9], Rx2F, Rx62-63, Table 7 Added missing register: Function 0 Rx59[3] MIRQ Pin Config Register Function 0 PCI-to-ISA Bridge (3041 only silicon) Rx08[7:0] (changed) Revision Code Register Rx2C[31:0] (new) Subsystem ID Register (read) Rx41[0] (changed) ISA Test Mode Register Rx46[7:5] and Rx48[5:4] (new) Misc Control Registers 1 and 3 Rx5C[0] (new) DMA Control Register Rx70[31:0] (new) Subsystem ID Register (write) Function 1 IDE Controller (3041 only silicon) Rx43[7] (new) FIFO Configuration Register Rx44[1:0] (new) Misc Control Register 1 Function 3 Power Management (3040F and 3041 silicon) Rx04[0] (moved to Rx41[7]) Command Register Rx08[7:0] (changed) Revision ID Register Rx10[4:1], Rx14 (changed) Processor Control and Processor Level 2 Rx20[31:0] (moved to Rx48) I/O Base Address Register Power Management I/O(3040F and 3041 silicon) Rx40[6:5] (new) GPIO Direction Control Register • Electrical Spec Changes: Added PCI Cycle Timing • Mechanical Spec Changes: Added marking specs for 3040E/F, 3041 silicon Revision 1.0 May 13, 1997 -i- Revision History �9,$�7HFKQRORJLHV��,QF� VT82C586B TABLE OF CONTENTS REVISION HISTORY........................................................................................................................................................................I TABLE OF CONTENTS.................................................................................................................................................................. II LIST OF FIGURES..........................................................................................................................................................................III LIST OF TABLES ...........................................................................................................................................................................IV OVERVIEW ....................................................................................................................................................................................... 3 PINOUTS............................................................................................................................................................................................ 4 REGISTERS..................................................................................................................................................................................... 14 REGISTER OVERVIEW ................................................................................................................................................................. 14 CONFIGURATION SPACE I/O ....................................................................................................................................................... 20 REGISTER DESCRIPTIONS............................................................................................................................................................ 21 Legacy I/O Ports ................................................................................................................................................................... 21 Keyboard Controller Registers.............................................................................................................................................................. 22 DMA Controller I/O Registers.............................................................................................................................................................. 24 Interrupt Controller Registers ............................................................................................................................................................... 25 Timer / Counter Registers ..................................................................................................................................................................... 25 CMOS / RTC Registers......................................................................................................................................................................... 26 PCI to ISA Bridge Registers (Function 0) .......................................................................................................................... 27 PCI Configuration Space Header .......................................................................................................................................................... 27 ISA Bus Control.................................................................................................................................................................................... 27 Plug and Play Control ........................................................................................................................................................................... 30 Distributed DMA Control ..................................................................................................................................................................... 32 Miscellaneous ....................................................................................................................................................................................... 32 Enhanced IDE Controller Registers (Function 1).............................................................................................................. 33 PCI Configuration Space Header .......................................................................................................................................................... 33 IDE-Controller-Specific Confiiguration Registers................................................................................................................................ 35 IDE I/O Registers.................................................................................................................................................................................. 37 Universal Serial Bus Controller Registers (Function 2) .................................................................................................... 38 PCI Configuration Space Header .......................................................................................................................................................... 38 USB-Specific Configuration Registers.................................................................................................................................................. 39 USB I/O Registers................................................................................................................................................................................. 39 Power Management Registers (Function 3)........................................................................................................................ 40 PCI Configuration Space Header .......................................................................................................................................................... 40 Power Management-Specific PCI Configuration Registers .................................................................................................................. 41 Power Management Subsystem Overview ............................................................................................................................................ 43 Power Management I/O-Space Registers .............................................................................................................................................. 46 ELECTRICAL SPECIFICATIONS............................................................................................................................................... 55 ABSOLUTE MAXIMUM RATINGS ................................................................................................................................................. 55 DC CHARACTERISTICS................................................................................................................................................................ 55 AC TIMING SPECIFICATIONS...................................................................................................................................................... 56 PACKAGE MECHANICAL SPECIFICATIONS ........................................................................................................................ 63 Revision 1.0 May 13, 1997 -ii- Table of Contents �9,$�7HFKQRORJLHV��,QF� VT82C586B LIST OF FIGURES FIGURE 1. PC SYSTEM CONFIGURATION USING THE VT82C586B ................................................................................. 3 FIGURE 2. PIN DIAGRAM............................................................................................................................................................. 4 FIGURE 3. STRAP OPTION CIRCUIT....................................................................................................................................... 31 FIGURE 4. POWER MANAGEMENT SUBSYSTEM BLOCK DIAGRAM ........................................................................... 43 FIGURE 5. ULTRADMA-33 IDE TIMING - DRIVE INITIATING DMA BURST FOR READ COMMAND.................... 58 FIGURE 6. ULTRADMA-33 IDE TIMING - DRIVE INITIATING BURST FOR WRITE COMMAND............................ 58 FIGURE 7. ULTRADMA-33 IDE TIMING - PAUSING A DMA BURST ............................................................................... 59 FIGURE 8. ULTRADMA-33 IDE TIMING - DRIVE TERMINATING DMA BURST DURING READ COMMAND...... 60 FIGURE 9. ULTRADMA-33 IDE TIMING - DRIVE TERMINATING DMA BURST DURING WRITE COMMAND ... 60 FIGURE 10. ULTRADMA-33 IDE TIMING - HOST TERMINATING DMA BURST DURING READ COMMAND...... 61 FIGURE 11. ULTRADMA-33 IDE TIMING - HOST TERMINATING DMA BURST DURING WRITE COMMAND ... 61 FIGURE 12. ULTRADMA-33 IDE TIMING - PIO CYCLE...................................................................................................... 62 FIGURE 13. MECHANICAL SPECIFICATIONS - 208-PIN PLASTIC FLAT PACKAGE.................................................. 63 Revision 1.0 May 13, 1997 -iii- List of Figures �9,$�7HFKQRORJLHV��,QF� VT82C586B LIST OF TABLES TABLE 1. PIN DESCRIPTIONS..................................................................................................................................................... 5 TABLE 2. SYSTEM I/O MAP ....................................................................................................................................................... 14 TABLE 3. REGISTERS.................................................................................................................................................................. 14 TABLE 4. KEYBOARD CONTROLLER COMMAND CODES .............................................................................................. 23 TABLE 5. CMOS REGISTER SUMMARY................................................................................................................................. 26 TABLE 6. SCI/SMI/RESUME CONTROL FOR PM EVENTS................................................................................................. 44 TABLE 7. SUSPEND RESUME EVENTS AND CONDITIONS ............................................................................................... 44 TABLE 8. AC CHARACTERISTICS - PCI CYCLE TIMING.................................................................................................. 56 TABLE 9. AC CHARACTERISTICS - ULTRADMA-33 IDE BUS INTERFACE TIMING.................................................. 57 Revision 1.0 May 13, 1997 -iv- List of Tables �9,$�7HFKQRORJLHV��,QF� VT82C586B VT82C586B PIPC PCI INTEGRATED PERIPHERAL CONTROLLER PC97 COMPLIANT PCI-TO-ISA BRIDGE WITH ACPI, DISTRIBUTED DMA, PLUG AND PLAY, MASTER MODE PCI IDE CONTROLLER WITH ULTRADMA-33, USB CONTROLLER, KEYBOARD CONTROLLER, AND REAL TIME CLOCK • PC97 Compliant PCI to ISA Bridge − Integrated ISA Bus Controller with integrated DMA, timer, and interrupt controller − Integrated Keyboard Controller with PS2 mouse support − Integrated DS12885-style Real Time Clock with extended 256 byte CMOS RAM and Day/Month Alarm for ACPI − Integrated USB Controller with root hub and two function ports − Integrated master mode enhanced IDE controller with enhanced PCI bus commands and UltraDMA-33 extensions − PCI-2.1 compliant with delay transaction − Eight double-word line buffer between PCI and ISA bus − One level of PCI to ISA post-write buffer − Supports type F DMA transfers − Distributed DMA support for ISA legacy DMA across the PCI bus − Fast reset and Gate A20 operation − Edge trigger or level sensitive interrupt − Flash EPROM, 2MB EPROM and combined BIOS support − Programmable ISA bus clock − Supports external IOAPIC interface for symmetrical multiprocessor configurations • Inter-operable with VIA and other Host-to-PCI Bridges − Combine with VT82C585VPX/587VP for a complete 75MHz 6x86 / PCI / ISA system (Apollo VPX) − Combine with VT82C595 for a complete Pentium / PCI / ISA system (Apollo VP2) − Combine with VT82C685/687 for a complete Pentium-Pro /PCI / ISA system (Apollo P6) − Combine with VIA Apollo-AGP and Apollo Pro chipsets for new high-performance / enhanced-functionality systems − Inter-operable with other Intel or non-Intel Host-to-PCI bridges for a complete PC97 compliant PCI/ISA system • Enhanced Master Mode PCI IDE Controller with Extension to UltraDMA-33 − Dual channel master mode PCI supporting four Enhanced IDE devices − Transfer rate up to 33MB/sec to cover PIO mode 4, multi-word DMA mode 2 drives, and UltraDMA-33 interface − Sixteen levels (doublewords) of prefetch and write buffers − Interlaced commands between two channels − Bus master programming interface for SFF-8038i rev.1.0 and Windows-95 compliant − Full scatter gather capability − Support ATAPI compliant devices including DVD devices − Support PCI native and ATA compatibility modes − Complete software driver support Revision 1.0 May 13, 1997 -1- Features �9,$�7HFKQRORJLHV��,QF� VT82C586B Universal Serial Bus Controller • − USB v.1.0 and Intel Universal HCI v.1.1 compatible − Eighteen level (doublewords) data FIFO with full scatter and gather capability − Root hub and two function ports − Integrated physical layer transceivers with over-current detection status on USB inputs − Legacy keyboard and PS/2 mouse support • Sophisticated PC97-Compatible Power Management − Supports both ACPI (Advanced Configuration and Power Interface) and legacy (APM) power management − ACPI v1.0 Compliant (all required features plus extensions for most efficient desktop power management) − APM v1.2 Compliant − Supports soft-off (suspend to disk) and power-on suspend with hardware automatic wake-up − One idle timer, one peripheral timer and one general purpose timer, plus 24/32-bit ACPI compliant timer − Dedicated input pin for external modem ring indicator for system wake-up − Enhanced integrated real time clock (RTC) with date alarm, month alarm, and century field − Normal, doze, sleep, suspend and conserve modes − System event monitoring with two event classes − Five multi-purpose I/O pins plus support for up to 16 general purpose input ports and 16 output ports 2 − I C serial bus support for JEDEC-compatible DIMM identification and on-board-device power control − Seven external event input ports with programmable SMI condition − Primary and secondary interrupt differentiation for individual channels − Clock throttling control − Multiple internal and external SMI sources for flexible power management models • Plug and Play Controller − PCI interrupts steerable to any interrupt channel − Three steerable interrupt channels for on-board plug and play devices TM − Microsoft Windows 95 and plug and play BIOS compliant • Pin-compatible upgrade from VT82C586 and VT82C586A for existing designs • Built-in Nand-tree pin scan test capability • 0.5um mixed voltage, high speed and low power CMOS process • Single chip 208 pin PQFP Revision 1.0 May 13, 1997 -2- Features �9,$�7HFKQRORJLHV��,QF� VT82C586B OVERVIEW The VT82C586B PIPC (PCI Integrated Peripheral Controller) is a high integration, high performance and high compatibility device that supports Intel and non-Intel based processor to PCI bus bridge functionality to make a complete Microsoft PC97- compliant PCI/ISA system. In addition to complete ISA extension bus functionality, the VT82C586B includes standard intelligent peripheral controllers: a) Master mode enhanced IDE controller with dual channel DMA engine and interlaced dual channel commands. Dedicated FIFO coupled with scatter and gather master mode operation allows high performance transfers between PCI and IDE devices. In addition to standard PIO and DMA mode operation, the VT82C586B also supports the emerging UltraDMA-33 standard to allow reliable data transfer rates up to 33MB/sec throughput. The IDE controller is SFF-8038i v1.0 and Microsoft Windows-95 compliant. b) Universal Serial Bus controller that is USB v1.0 and Universal HCI v1.1 compliant. The VT82C586B includes the root hub with two function ports with integrated physical layer transceivers. The USB controller allows hot plug and play and isochronous peripherals to be inserted into the system with universal driver support. The controller also implements legacy keyboard and mouse support so that legacy software can run transparently in a non-USB-aware operating system environment. c) Keyboard controller with PS2 mouse support. d) Real Time Clock with 256 byte extended CMOS. In addition to the standard ISA RTC functionality, the integrated RTC also includes the date alarm and other enhancements for compatibility with the ACPI standard. e) Notebook-class power management functionality that is compliant with ACPI and legacy APM requirements. Two types of sleep states (soft-off and power-on-suspend) are supported with hardware automatic wake-up. Additional functionality includes event monitoring, CPU clock throttling (Intel processor protocol), modular power control, hardware- and software- based event handling, general purpose IO, chip select and external SMI. f) Distributed DMA capability for support of ISA legacy DMA over the PCI bus. g) Plug and Play controller that allows complete steerability of all PCI interrupts to any interrupt channel. Three additional steerable interrupt channels are provided to allow plug and play and reconfigurability of on-board peripherals for Windows 95 compliance. h) External IOAPIC support for Intel-compliant symmetrical multiprocessor systems. The VT82C586B also enhances the functionality of the standard ISA peripherals. The integrated interrupt controller supports both edge and level triggered interrupts channel by channel. The integrated DMA controller supports type F DMA in addition to standard ISA DMA modes. Compliant with the PCI-2.1 specification, the VT82C586B supports delayed transactions so that slower ISA peripherals do not block the traffic of the PCI bus. Special circuitry is built in to allow concurrent operation without causing dead lock even in a PCI-to-PCI bridge environment The chip also includes eight levels (doublewords) of line buffers from the PCI bus to the ISA bus to further enhance overall system performance. CA MA/RAS/CAS CPU / Cache North Bridge System Memory CD MD PCI Sideband Signals: Init / CPUreset I2C (Module ID) IRQ / NMI USB SMI / StopClk Expansion VT82C586B KBC FERR / IGNNE Cards RTC 208PQFP IDE Crystal GPIO, Power Control, Reset Boot ROM ISA Figure 1. PC System Configuration Using the VT82C586B Revision 1.0 May 13, 1997 -3- Overview �9,$�7HFKQRORJLHV��,QF� VT82C586B PINOUTS Figure 2. Pin Diagram VDD-PCI 157 (IRQ8#) I 104 RTCX1 AD4 158 IO 103 VDD-5VSB AD5 159 IO I 102 VBAT AD6 160 IO 101 AGND AD7 161 IO 100 AVDD CBE0# 162 IO I 99 USBCLK AD8 163 IO IO 98 USBDATA1- AD9 164 IO IO 97 USBDATA1+ AD10 165 IO IO 96 USBDATA0- GND 166 IO 95 USBDATA0+ AD11 167 IO (EXTSMI0#) O 94 GPIO0 AD12 168 IO I 93 RI# AD13 169 IO (GPI_RE#) (EXTSMI3#) IO 92 GPIO3 AD14 IO I PWRBTN# 170 91 VDD-PCI 171 ‡ (POS) (MIRQ0) IO 90 APICCS# AD15 172 IO I 89 DRDYB# CBE1# 173 IO (Data) (I2CD2) (EXTSMI2#) IO 88 GPIO2 PAR 174 IO (Clock) (I2CD1) (EXTSMI1#) IO 87 GPIO1 SERR# 175 I (GPI15) (GPO15) IO 86 SD15 STOP# 176 IO (GPI14) (GPO14) IO 85 SD14 GND 177 84 GND DEVSEL# 178 IO (GPI13) (GPO13) IO 83 SD13 TRDY# 179 IO (GPI12) (GPO12) IO 82 SD12 97��&���% IRDY# 180 IO (GPI11) (GPO11) IO 81 SD11 FRAME# 181 IO (GPI10) (GPO10) IO 80 SD10 CBE2# 182 IO 79 VDD5 AD16 183 IO (GPI9) (GPO9) IO 78 SD9 IO SD8 VDD-PCI 184 (GPI8) (GPO8) 77 AD17 185 IO I 76 MEMCS16# 3&,�,QWHJUDWHG AD18 186 IO I 75 IRQ3 AD19 187 IO I 74 IRQ4 188 I 73 IRQ5 GND AD20 189 IO I 72 IRQ6 AD21 190 IO I 71 IRQ7 3HULSKHUDO�&RQWUROOHU AD22 191 IO IO 70 LA17/DA0 AD23 192 IO IO 69 LA18/DA1 IDSEL 193 I 68 GND34)3 CBE3# 194 IO IO 67 LA19/DA2 AD24 195 IO IO 66 LA20/DCS1A# AD25 196 IO IO 65 LA21/DCS3A# GND 197 IO 64 LA22/DCS1B# VDD-PCI 198 Note: Pin names in parentheses (...) indicate alternate function IO 63 LA23/DCS3B# AD26 199 IO IO 62 SBHE# AD27 200 IO I 61 IRQ9 AD28 201 IO ‡ 3040 Rev F and Later Revisions O 60 DACK0# AD29 202 IO I 59 DRQ0 † 3041 Rev A and Later Revisions AD30 203 IO O 58 DACK5# AD31 204 IO I 57 DRQ5 PIRQD# 205 I O 56 SOE# PIRQC# 206 I O 55 DIOWB# PIRQB# 207 I O 54 DIORB# GND 208 53 VDD5 Revision 1.0 May 13, 1997 -4- Pinouts PIRQA# 1 I 156 GND PCICLK 2 I IO 155 AD3 PCIRST# 3 O IO 154 AD2 RSTDRV 4 O IO 153 AD1 IOCHCK# 5 I IO 152 AD0 OSC 6 I O 151 PREQ# DRQ2 7 I I 150 PGNT# IOCHRDY 8 I O 149 SMI# SMEMW# 9 O O 148 STPCLK# SMEMR# 10 O O 147 A20M IOW# 11 IO O 146 NMI IOR# 12 IO O 145 INTR GND 13 144 VDD3 BCLK 14 O O 143 INIT AEN 15 O O 142 CPURST DRQ1 16 I O 141 FERR# VDD5 17 140 GND DACK1# 18 O O 139 IGNNE# SA16 19 IO I 138 PWRGD DD15/SA15 20 IO † (SDDIR) IO 137 MASTER# (MIRQ2) DD14/SA14 21 IO (GPO_WE) IO 136 GPIO4 (EXTSMI4#) DD13/SA13 22 IO O 135 ROMCS# (KBCS#) DD12/SA12 23 IO IO 134 SPKR (Strap) DD11/SA11 24 IO O 133 DACK7# DD10/SA10 25 IO I 132 DRQ7 O GND 26 131 DACK6# DD9/SA9 27 IO I 130 DRQ6 DD8/SA8 28 IO I 129 IRQ14 REFRESH# 29 IO I 128 IRQ15 DRQ3 30 I I 127 IRQ11 DACK3# 31 O I 126 IRQ10 TC 32 O I 125 IOCS16# DACK2# 33 O IO 124 MEMW# VDD5 34 IO 123 MEMR# BALE 35 O (GPI7) (GPO7) IO 122 XD7 (Strap) (EXTSMI7#) DD7/SA7 36 IO (GPI6) (GPO6) IO 121 XD6 (Strap) (EXTSMI6#) DD6/SA6 37 IO 120 GND DD5/SA5 38 IO (GPI5) (GPO5) IO 119 XD5 (Strap) (EXTSMI5#) GND 39 (GPI4) (GPO4) IO 118 XD4 (Strap) (EXTSMI4#) DD4/SA4 40 IO (GPI3) (GPO3) IO 117 XD3 (EXTSMI3#) DD3/SA3 41 IO (GPI2) (GPO2) IO 116 XD2 (Strap) DD2/SA2 42 IO 115 VDD5 DD1/SA1 43 IO IO 114 XD1 (Strap) (GPI1) (GPO1) DD0/SA0 44 IO IO 113 XD0 (Strap) (GPI0) (GPO0) DDRQA 45 I O 112 XDIR DDRQB 46 I IO 111 MSDT (IRQ12) DDACKA# 47 O IO 110 MSCK (KA20G) DDACKB# 48 O IO 109 KBDT (KBRC#) DRDYA# 49 I IO 108 KBCK (IRQ1) DIORA# 50 O O 107 PWRON DIOWA# 51 O I 106 KEYLOCK (MIRQ1) (IRQ8#) ‡ GND 52 O 105 RTCX2 (RTCCS#) �9,$�7HFKQRORJLHV��,QF� VT82C586B Table 1. Pin Descriptions CPU Interface Signal Name Pin No. I/O Signal Description CPURST 142 O CPU Reset. The VT82C586B asserts CPURST to reset the CPU during power-up. INTR 145 O INTR is driven by the VT82C586B to signal the CPU that an CPU Interrupt. interrupt request is pending and needs service. NMI 146 O Non-Maskable Interrupt. NMI is used to force a non-maskable interrupt to the CPU. The VT82C586B generates an NMI when either SERR# or IOCHK# is asserted. INIT 143 O Initialization. The VT82C586B asserts INIT if it detects a shut-down special cycle on the PCI bus or if a soft reset is initiated by the register STPCLK# 148 O Stop Clock. STPCLK# is asserted by the VT82C586B to the CPU in response to different Power-Management events. SMI# 149 O System Management Interrupt. SMI# is asserted by the VT82C586B to the CPU in response to different Power-Management events. FERR# 141 O Numerical Coprocessor Error. This signal is tied to the coprocessor error signal on the CPU. IGNNE# 139 O Ignore Numeric Error. This pin is connected to the “ignore error” pin on the CPU. Revision 1.0 May 13, 1997 -5- Pinouts �9,$�7HFKQRORJLHV��,QF� VT82C586B PCI Bus Interface Signal Name Pin No. I/O Signal Description PCLK 2 I PCI Clock. PCLK provides timing for all transactions on the PCI Bus. FRAME# 181 B Frame. Assertion indicates the address phase of a PCI transfer. Negation indicates that one more data transfer is desired by the cycle initiator. AD[31:0] 204-199, 196- B Address/Data Bus. The standard PCI address and data lines. The address is driven 195, 192-189, with FRAME# assertion and data is driven or received in following cycles. 187-185, 183, 172, 170-167, 165-163, 161- 158, 155-152 C/BE[3:0]# 194, 182, 173, B Command/Byte Enable. The command is driven with FRAME# assertion. Byte 162 enables corresponding to supplied or requested data are driven on following clocks. IRDY# 180 B Initiator Ready. Asserted when the initiator is ready for data transfer. TRDY# 179 B Target Ready. Asserted when the target is ready for data transfer. STOP# 176 B Asserted by the target to request the master to stop the current transaction. Stop. DEVSEL# 178 B Device Select. The VT82C586B asserts this signal to claim PCI transactions through positive or subtractive decoding. PAR 174 B Parity. A single parity bit is provided over AD[31:0] and C/BE[3:0]#. SERR# 175 I System Error. SERR# can be pulsed active by any PCI device that detects a system error condition. Upon sampling SERR# active, the VT82C586B can be programmed to generate an NMI to the CPU. IDSEL 193 I Initialization Device Select. IDSEL is used as a chip select during configuration read and write cycles. PIRQA-D# 1, 207-205 I . These pins are typically connected to the PCI bus INTA#- PCI Interrupt Request INTD# pins as follows: PIRQA# PIRQB# PIRQC# PIRQD# PCI Slot 1 INTA# INTB# INTC# INTD# PCI Slot 2 INTB# INTC# INTD# INTA# PCI Slot 3 INTC# INTD# INTA# INTB# PCI Slot 4 INTD# INTA# INTB# INTC# PREQ# 151 O PCI Request. This signal goes to the North Bridge to request the PCI bus. PGNT# 150 I PCI Grant. This signal is driven by the North Bridge to grant PCI access to the VT82C586B. Revision 1.0 May 13, 1997 -6- Pinouts �9,$�7HFKQRORJLHV��,QF� VT82C586B ISA Bus Control Signal Name Pin No. I/O Signal Description SA[15:0] / 20-25, 27-28, B System Address Bus / IDE Data Bus DD[15:0] 36-38, 40-44 SA16 19 B System Address Bus LA23/DCS3B#, 63-67, 69-70 B Multifunction Pins LA22/DCS1B#, ISA Bus Cycles: LA21/DCS3A#, Address: The LA[23:17] address lines are bi-directional. These address lines allow accesses to physical memory on the ISA bus up to 16MBytes. LA20/DCS1A#, LA[19:17] / PCI IDE Cycles: DA[2:0] Chip Select: DCS1A# is for the ATA command register block and corresponds to CS1FX# on the primary IDE connector. DCS3A# is for the ATA command register block and corresponds to CS3FX# on the primary IDE connector. DCS1B# is for the ATA command register block and corresponds to CS17X# on the primary IDE connector. DCS3B# is for the ATA command register block and corresponds to CS37X# on the primary IDE connector. Disk Address: DA[2:0] are used to indicate which byte in either the ATA command block or control block is being accessed. SD[15:8] / 86-85, 83-80, B System Data. SD[15:8] provide the high order byte data path for devices residing on GPI[15:8] / 78-77 the ISA bus. These pins also function as 15-8 if the General Purpose Inputs GPO[15:8] GPIO3_CFG bit is low (pin 92 becomes GPI_RE# for enabling external inputs onto the SD pins using an external buffer). These pins also function as General Purpose Outputs 15-8 if the GPIO4_CFG bit is low (pin 136 becomes GPO_WE for control of an external latch). SBHE# 62 B System Byte High Enable. SBHE# indicates, when asserted, that a byte is being transferred on the upper byte (SD[15:8]) of the data bus. SBHE# is negated during refresh cycles. IOR# 12 B IOR# is the command to an ISA I/O slave device that the slave may drive I/O Read. data on to the ISA data bus. IOW# 11 B I/O Write. IOW# is the command to an ISA I/O slave device that the slave may latch data from the ISA data bus. MEMR# 123 B Memory Read. MEMR# is the command to a memory slave that it may drive data onto the ISA data bus. MEMW# 124 B Memory Write. MEMW# is the command to a memory slave that it may latch data from the ISA data bus. SMEMR# 10 O Standard Memory Read. SMEMR# is the command to a memory slave, under 1MB, which indicates that it may drive data onto the ISA data bus SMEMW# 9 O Standard Memory Write. SMEMW# is the command to a memory slave, under 1MB, which indicates that it may latch data from the ISA data bus. BALE 35 O Bus Address Latch Enable. BALE is an active high signal asserted by the VT82C586B to indicate that the address (SA[19:0], LA[23:17] and the SBHE# signal) is valid IOCS16# 125 I 16-Bit I/O Chip Select. This signal is driven by I/O devices on the ISA Bus to indicate that they support 16-bit I/O bus cycles. MEMCS16# 76 I Memory Chip Select 16. ISA slaves that are 16-bit memory devices drive this line low to indicate they support 16-bit memory bus cycles. IOCHCK# 5 I When this signal is asserted, it indicates that a parity or an I/O Channel Check. uncorrectable error has occurred for a device or memory on the ISA Bus. IOCHRDY 8 I I/O Channel Ready. Devices on the ISA Bus negate IOCHRDY to indicate that additional time (wait states) is required to complete the cycle. Revision 1.0 May 13, 1997 -7- Pinouts �9,$�7HFKQRORJLHV��,QF� VT82C586B ISA Bus Control (continued) Signal Name Pin No. I/O Signal Description REFRESH# 29 B Refresh. As an output REFRESH# indicates when a refresh cycle is in progress. As an input REFRESH# is driven by 16-bit ISA Bus masters to indicate refresh cycle. AEN 15 O Address Enable. AEN is asserted during DMA cycles to prevent I/O slaves from misinterpreting DMA cycles as valid I/O cycles. IRQ15, 14, 11- 128-129, 127- I Interrupt Request. The IRQ signals provide both system board components and 9, 7-3 126, 61, 71-75 ISA Bus I/O devices with a mechanism for asynchronously interrupting the CPU. DRQ7-5, 3-0 132, 130, 57, I DMA Request. The DRQ lines are used to request DMA services from the 30, 7, 16, 59 VT82C586B’s DMA controller. DACK7:5, 3-0# 133, 131, 58, O Acknowledge. The DACK# output lines indicate a request for DMA service has 31, 33, 18, 60 been granted. TC 32 O Terminal Count. The VT82C586B asserts TC to DMA slaves as a terminal count indicator. MASTER# (see below) I ISA Master Request. (see below pin 137) SPKR / 134 B Multifunction Pin Power-up Strap Normal Operation: Speaker Drive. The SPKR signal is the output of counter 2. Power-up Strapping: 0/1 = Fixed/flexible IDE I/O base Revision 1.0 May 13, 1997 -8- Pinouts �9,$�7HFKQRORJLHV��,QF� VT82C586B On Board Plug and Play Signal Name Pin No. I/O Signal Description MIRQ0 / 90 I Multifunction Pin (see PCI Configuration Register Function 0 Rx59[3,0]) APICCS# / O MIRQ0. Steerable interrupt request input for on-board devices. POS (3040F) O . Chip select for external IOAPIC chip for symmetric multiprocessor APICCS# implementations. POS. Power-On Suspend Status Output (see Function 0 Rx59 bit-3). This function was introduced in rev F of the 3040 silicon and is not available in earlier chips. Rx59[3] Rx59[0] Pin Function 0 0 MIRQ0 (input) 0 1 APICCS# (output) 1 0 -illegal- 1 1 POS (output) MIRQ1 / 106 I Multifunction Pin (see PCI Configuration Register Function 0 Rx59[1] & Rx48[4]) KEYLOCK / I MIRQ1. Steerable interrupt request input for on-board devices. IRQ8# (3040F) I KEYLOCK. Keyboard lock input. IRQ8#. Interrupt input for external RTC. This function was introduced in revision F of the 3040 silicon and is not available in earlier chips. Rx48[4] Rx59[1] Pin Function 0 0 MIRQ1 (input) 0 1 KEYLOCK (input) 1 0 -illegal- 1 1 IRQ8# (input) (see also Rx5A[2] and table below). With this setting, Rx57[3:0] must be set to 0 (MIRQ1 routing) Rx5A[2] Rx48[4] Pin Function 0 0 External RTC - IRQ8# input on pin 104 0 1 External RTC - IRQ8# input on pin 106 1 x Internal RTC - IRQ8# input not required MIRQ2 / 137 I Multifunction Pin (see PCI Configuration Register Function 0 Rx59[2] & Rx48[5]) MASTER# / I MIRQ2. Steerable interrupt request input for on-board devices. SDDIR (3041A) O ISA Master Request indicator. This pin also serves as the direction MASTER#. control for the IDE interface DD / SA transceivers (see SOE#). SDDIR. This pin may be programmed to serve as a direction control for the IDE interface DD / SA transceivers (see SOE#) separate from MASTER#. This function was introduced in revision A of the 3041 silicon and not available in earlier chips. Rx48[5] Rx59[2] Pin Function 0 0 MASTER# (input) 0 1 MIRQ2 (input) 1 0 -illegal- 1 1 SDDIR (output) Revision 1.0 May 13, 1997 -9- Pinouts �9,$�7HFKQRORJLHV��,QF� VT82C586B UltraDMA-33 Enhanced IDE Interface Signal Name Pin No. I/O Signal Description DRDYA# / 49 I EIDE Mode: I/O Channel Ready A. Primary channel device ready indicator DDMARDYA# UltraDMA Mode: Device DMA Ready A. Primary channel output flow control / DSTROBEA The device may assert DDMARDY# to pause output transfers Device Strobe A. Primary channel input data strobe (both edges) The device may stop DSTROBE to pause input data transfers DRDYB# / 89 I EIDE Mode: I/O Channel Ready B. Secondary channel device ready DDMARDYB# UltraDMA Mode: Device DMA Ready B. Secondary channel output flow control / DSTROBEB The device may assert DDMARDY# to pause output transfers Device Strobe B. Secondary channel input strobe (both edges) The device may stop DSTROBE to pause input data transfers DIORA# / 50 O EIDE Mode: Device I/O Read A. Primary channel device read strobe HDMARDYA# UltraDMA Mode: Host DMA Ready A. Primary channel input flow control / HSTROBEA The host may assert HDMARDY# to pause input transfers Host Strobe A. Primary channel output data strobe (both edges) The host may stop HSTROBE to pause output data transfers DIORB# / 54 O EIDE Mode: Device I/O Read B. Secondary channel device read strobe HDMARDYB# UltraDMA Mode: Host DMA Ready B. Secondary channel input flow control / HSTROBEB The host may assert HDMARDY# to pause input transfers Host Strobe B. Secondary channel output strobe (both edges) The host may stop HSTROBE to pause output data transfers DIOWA# / 51 O EIDE Mode: Device I/O Write A. Primary channel device write strobe STOPA UltraDMA Mode: Stop A. Primary channel stop transfer: asserted by the host prior to initiation of an UltraDMA burst; negated by the host before data is transferred in an UltraDMA burst. Assertion of STOP by the host during or after data transfer in UltraDMA mode signals the termination of the burst. DIOWB# / 55 O EIDE Mode: Device I/O Write B. Secondary channel device write strobe STOPB UltraDMA Mode: Stop B. Secondary channel stop transfer: asserted by the host prior to initiation of an UltraDMA burst; negated by the host before data is transferred in an UltraDMA burst. Assertion of STOP by the host during or after data transfer in UltraDMA mode signals the termination of the burst. SOE# 56 O System Address Transceiver Output Enable. This signal controls the output enables of the 245 transceivers that interface the DD[15:0] signals to SA[15:0]. The transceiver direction controls are driven by MASTER# with DD[15-0] connected to the “A” side of the transceivers and SA[15-0] connected to the “B” side. DDRQA 45 I Device DMA Request A. Primary channel DMA request DDRQB 46 I Device DMA Request B. Secondary channel DMA request DDACKA# 47 O Device DMA Acknowledge A. Primary channel DMA acknowledge DDACKB# 48 O Device DMA Acknowledge B. Secondary channel DMA acknowledge Note: Refer to the ISA bus interface pin descriptions for remaining IDE interface pin descriptions (the IDE address, data, and drive select pins are multiplexed with the ISA bus LA and SA pins). Also, the MASTER# pin description may be found in the "On Board Plug and Play" pin group (DD / SA transceiver direction control). Revision 1.0 May 13, 1997 -10- Pinouts �9,$�7HFKQRORJLHV��,QF� VT82C586B XD Interface Signal Name Pin No. I/O Signal Description XD7-0, 122 B Multifunction Pins EXTSMI7-3#, 121 X-bus Data Bus. For connection to external X-Bus devices (e.g. BIOS ROM) GPI7-0, 119 External SMI Inputs. External SCI/SMI ports. GPO7-0, 118 General Purpose Inputs. GPIO3_CFG bit low (pin 92 = GPI_RE#) Power-up Straps 117 General Purpose Outputs. GPIO4_CFG bit low (pin 136 = GPO_WE) 116 Power-up Strap Option Inputs. (see Configuration Register Offset 5Ah) 114 XD0: 0/1 - Disable/enable internal KBC 113 XD1: 0/1 - Disable/enable internal PS/2 Mouse XD2: 0/1 - Disable/enable internal RTC XD4~XD7: RP13~RP16 for internal KBC XDIR 112 O XDIR is tied directly to the direction control of a 74F245 X-Bus Data Direction. transceiver that buffers the X-Bus data and ISA-Bus data (the output enable of the transceiver should be grounded). SD0-7 connect to the “A” side of the transceiver and XD0-7 connect to the “B” side. XDIR high indicates that SD0-7 drives XD0-7. ROMCS# / 135 O Multifunction Pin. ROM Chip Select / Keyboard Controller Chip Select. KBCS# ISA memory cycle: ROMCS#. Chip Select to the BIOS ROM. ISA I/O cycle: KBCS#. Chip Select to the external keyboard controller. General Purpose I/O Signal Name Pin No. I/O Signal Description GPIO0 / 94 B : General Purpose I/O with external SCI/SMI capability. General Purpose I/O 0 EXTSMI0# This pin sits on the VDD-5VSB power plane and is available even under soft-off state. GPIO1 / 87 B General Purpose I/O 1: General Purpose I/O with external SCI/SMI capability. 2 EXTSMI1# / Can be used along with pin 88 as an I C pair (by software convention this pin is I2CD1 (Clock) defined as clock). GPIO2 / 88 B General Purpose I/O 2: General Purpose I/O with external SCI/SMI capability. 2 EXTSMI2# / Can be used along with pin 87 as an I C pair (by software convention this pin is I2CD2 (Data) defined as data). GPIO3 / 92 B Multifunction Pin (per GPIO3 Configuration Bit: Function 3 Rx40 bit-6) EXTSMI3# / GPIO3 Configuration bit high: General Purpose I/O 3: General Purpose I/O with GPI_RE# external SCI/SMI capability. GPIO3 Configuration bit low: Read Enable for General Purpose Inputs: Connects to the output enable (OE# pin) of the external 244 buffers whose data pins connect to SD15-8 and XD7-0 for GPI15-0. GPIO4 / 136 B (per GPIO4 Configuration Bit: Function 3 Rx40 bit-7) Multifunction Pin EXTSMI4# / GPIO4 Configuration bit high: General Purpose I/O 4: General Purpose I/O with GPO_WE external SCI/SMI capability. GPIO4 Configuration bit low: Write Enable for General Purpose Outputs: Connects to the latch enable (LE pin) of the external 373 latches whose data pins connect to SD15-8 and XD7-0 for GPO15-0. Revision 1.0 May 13, 1997 -11- Pinouts �9,$�7HFKQRORJLHV��,QF� VT82C586B Universal Serial Bus Interface Signal Name Pin No. I/O Signal Description USBDATA0+ 95 B USB Port 0 Data + USBDATA0- 96 B USB Port 0 Data - USBDATA1+ 97 B USB Port 1 Data + USBDATA1- 98 B USB Port 1 Data - USBCLK 99 I USB Clock. Clock input for Universal Serial Bus interface Keyboard Interface Signal Name Pin No. I/O Signal Description KBCK / 108 B Multifunction Pin. Function depends on enable/disable of internal KBC. KA20G Internal KBC enabled: Keyboard Clock. Clock to keyboard interface. Internal KBC disabled: Gate A20: Gate A20 output from external KBC KBDT / 109 B Multifunction Pin. Function depends on enable/disable of internal KBC. KBRC# Internal KBC enabled: Data to keyboard interface. Keyboard Data. Internal KBC disabled: Keyboard Reset: Reset input from external KBC. MSCK / IRQ1 110 B Multifunction Pin. Function depends on enable/disable of internal KBC. PS/2 mouse enabled: Mouse Clock. Clock to PS/2 mouse interface. PS/2 mouse disabled and internal KBC disabled: Interrupt Request 1. IRQ 1 input from external KBC. MSDT / IRQ12 111 B Multifunction Pin. Function depends on enable/disable of internal KBC. PS/2 mouse enabled: Mouse Data. Data to PS/2 mouse interface. PS/2 mouse disabled: Interrupt Request 12. IRQ 12 input from external KBC A20M 147 O A20 Mask. Direct connect A20 mask on CPU. KEYLOCK / 106 I Keyboard Lock. Keyboard lock signal for internal keyboard controller. MIRQ1 / (For reference only - see pin 106 description in "Onboard Plug and Play" section) IRQ8# Internal Real Time Clock Signal Name Pin No. I/O Signal Description RTCX1 / 104 I Multifunction Pin IRQ8# Internal RTC enabled: RTC Crystal Input: 32.768Khz crystal or oscillator input. Internal RTC disabled: Interrupt Request 8: IRQ8 input from external RTC Rx5A[2] Rx48[4] Pin Function 0 0 External RTC - IRQ8# input on pin 104 0 1 External RTC - IRQ8# input on pin 106 1 x Internal RTC - IRQ8# input not required RTCX2 / 105 O Multifunction Pin RTCCS# Internal RTC enabled: RTC Crystal Output: 32.768Khz crystal output Internal RTC disabled: External RTC Chip Select VBAT 102 I RTC Battery. Battery input for internal RTC Revision 1.0 May 13, 1997 -12- Pinouts �9,$�7HFKQRORJLHV��,QF� VT82C586B Resets and Clocks Signal Name Pin No. I/O Signal Description PWRGD 138 I Power Good. Connected to the POWERGOOD signal on the Power Supply. PCIRST# 3 O PCI Reset. An active low reset signal for the PCI bus. The VT82C586B will generate PCIRST# during power-up or from the control register. RSTDRV 4 O Reset Drive. RSTDRV is the reset signal to the ISA bus. BCLK 14 O Bus Clock. ISA bus clock. OSC 6 I Oscillator. OSC is the 14.31818 MHz clock signal. It is used by the internal Timer. Power Management Signal Name Pin No. I/O Signal Description PWRBTN# 91 I Referenced to VDD-5VSB. Power Button. PWRON 107 O Power Supply Control. Powered by VDD-5VSB. RI# 93 I Ring Indicator. May be connected to external modem circuitry to allow the system to be re-activated by a received phone call. Input referenced to VDD-5VSB. Power and Ground Signal Name Pin No. I/O Signal Description VDD5 17, 34, 53, 79, P Power Supply. 4.75 to 5.25V. This supply is turned on only when the mechanical 115 switch on the power supply is turned on and the PWRON signal is conditioned high. VDD-5VSB 103 P Power Supply. Always available unless the mechanical switch of the power supply is turned off. If the "soft-off" state is not implemented, then this pin can be connected to VDD5. VDD3 144 P Power Supply. This pin should be connected to the same voltage as the CPU I/O circuitry. VDD_PCI 157, 171, 184, P PCI Voltage. 3.3 or 5V. 198 AVDD 100 P USB Differential Output Power Source AGND 101 P USB Differential Output Ground GND 13, 26, 39, 52, P Ground 68, 84, 120, 140, 156, 166, 177, 188, 197, 208 Revision 1.0 May 13, 1997 -13- Pinouts �9,$�7HFKQRORJLHV��,QF� VT82C586B Table 3. Registers REGISTERS Legacy I/O Registers Register Overview Port Master DMA Controller Registers Default Acc 00 Channel 0 Base & Current Address RW The following tables summarize the configuration and I/O 01 Channel 0 Base & Current Count RW registers of the VT82C586B. These tables also document the 02 Channel 1 Base & Current Address RW power-on default value (“Default”) and access type (“Acc”) for 03 Channel 1 Base & Current Count RW each register. Access type definitions used are RW 04 Channel 2 Base & Current Address RW (Read/Write), RO (Read/Only), “—” for reserved / used 05 Channel 2 Base & Current Count RW (essentially the same as RO), and RWC (or just WC) (Read / 06 Channel 3 Base & Current Address RW Write 1’s to Clear individual bits). Registers indicated as RW 07 Channel 3 Base & Current Count RW may have some read/only bits that always read back a fixed value (usually 0 if unused); registers designated as RWC or 08 Status / Command RW WC may have some read-only or read write bits (see individual 09 Write Request WO register descriptions for details). 0A Write Single Mask WO 0B Write Mode WO Detailed register descriptions are provided in the following 0C Clear Byte Pointer FF WO section of this document. All offset and default values are 0D Master Clear WO shown in hexadecimal unless otherwise indicated 0E Clear Mask WO 0F Read / Write Mask RW Table 2. System I/O Map Port Function Actual Port Decoding Port Master Interrupt Controller Regs Default Acc 00-1F Master DMA Controller 0000 0000 000x nnnn 20 Master Interrupt Control — * 20-3F Master Interrupt Controller 0000 0000 001x xxxn 21 Master Interrupt Mask — * 20 Master Interrupt Control Shadow — RW 40-5F Timer / Counter 0000 0000 010x xxnn 21 Master Interrupt Mask Shadow — RW 60-6F Keyboard Controller 0000 0000 0110 xnxn * RW if shadow registers are disabled (60h) KBC Data 0000 0000 0110 x0x0 (61h) Misc Functions & Spkr Ctrl 0000 0000 0110 xxx1 Port Timer/Counter Registers Default Acc (64h) KBC Command / Status 0000 0000 0110 x1x0 40 Timer / Counter 0 Count RW 70-77 RTC/CMOS/NMI-Disable 0000 0000 0111 0nnn 41 Timer / Counter 1 Count RW 78-7F -available for system use- 0000 0000 0111 1xxx 42 Timer / Counter 2 Count RW 80 -reserved- (debug port) 0000 0000 1000 0000 43 Timer / Counter Control WO 81-8F DMA Page Registers 0000 0000 1000 nnnn Port Keyboard Controller Registers Default Acc 90-91 -available for system use- 0000 0000 1001 000x 60 Keyboard Controller Data RW 92 System Control 0000 0000 1001 0010 61 Misc Functions & Speaker Control RW 93-9F -available for system use- 0000 0000 1001 nnnn 64 Keyboard Ctrlr Command / Status RW A0-BF Slave Interrupt Controller 0000 0000 101x xxxn C0-DF Slave DMA Controller 0000 0000 110n nnnx Port CMOS / RTC / NMI Registers Default Acc E0-FF -available for system use- 0000 0000 111x xxxx 70 CMOS Memory Address & NMI Disa WO 71 CMOS Memory Data (128 bytes) RW 100-CF7 -available for system use- 72 CMOS Memory Address RW CF8-CFB PCI Configuration Address 0000 1100 1111 10xx 73 CMOS Memory Data (256 bytes) RW CFC-CFF PCI Configuration Data 0000 1100 1111 11xx 74 CMOS Memory Address RW D00-FFFF -available for system use- 75 CMOS Memory Data (256 bytes) RW NMI Disable is port 70h (CMOS Memory Address) bit-7. RTC control occurs via specific CMOS data locations (0-0Dh). Ports 72-73 may be used to access all 256 locations of CMOS. Ports 74-75 may be used to access CMOS if the internal RTC is disabled. Revision 1.0 May 13, 1997 -14- Register Overview �9,$�7HFKQRORJLHV��,QF� VT82C586B Port DMA Page Registers Default Acc Port Slave DMA Controller Registers Default Acc 87 DMA Page - DMA Channel 0 RW C0 Channel 0 Base & Current Address RW 83 DMA Page - DMA Channel 1 RW C2 Channel 0 Base & Current Count RW 81 DMA Page - DMA Channel 2 RW C4 Channel 1 Base & Current Address RW 82 DMA Page - DMA Channel 3 RW C6 Channel 1 Base & Current Count RW 8F DMA Page - DMA Channel 4 RW C8 Channel 2 Base & Current Address RW 8B DMA Page - DMA Channel 5 RW CA Channel 2 Base & Current Count RW 89 DMA Page - DMA Channel 6 RW CC Channel 3 Base & Current Address RW 8A DMA Page - DMA Channel 7 RW CE Channel 3 Base & Current Count RW D0 Status / Command RW Port System Control Registers Default Acc D2 Write Request WO 92 System Control RW D4 Write Single Mask WO D6 Write Mode WO Port Slave Interrupt Controller Regs Default Acc D8 Clear Byte Pointer FF WO A0 Slave Interrupt Control — * DA Master Clear WO A1 Slave Interrupt Mask — * DC Clear Mask WO A0 Slave Interrupt Control Shadow — RW DE Read / Write Mask RW A1 Slave Interrupt Mask Shadow — RW * RW accessible if shadow registers are disabled Revision 1.0 May 13, 1997 -15- Register Overview �9,$�7HFKQRORJLHV��,QF� VT82C586B PCI Function 0 Registers - PCI-to-ISA Bridge Offset Plug and Play Control Default Acc 50 -reserved- (do not program) 24 RW Configuration Space PCI-to-ISA Bridge Header Registers 51-53 -reserved- 00 — Offset PCI Configuration Space Header Default Acc 54 PCI IRQ Edge / Level Selection 00 RW 1-0 Vendor ID 1106 RO 55 PnP Routing for External MIRQ0-1 00 RW 3-2 Device ID 0586 RO 56 PnP Routing for PCI INTB-A 00 RW 5-4 Command 000F RW 57 PnP Routing for PCI INTD-C 00 RW 7-6 Status 0200 WC 58 PnP Routing for External MIRQ2 00 RW 8 Revision ID nn RO 59 MIRQ Pin Configuration 04 RW 9 Programming Interface 00 RO 5A XD Power-On Strap Options † RW A Sub Class Code 01 RO 5B Internal RTC Test Mode 00 RW B Base Class Code 06 RO 5C DMA Control 00 RW C -reserved- (cache line size) 00 — 5F-5D -reserved- 00 — D -reserved- (latency timer) 00 — † Power-up default value depends on external strapping E Header Type 80 RO F Built In Self Test (BIST) 00 RO Offset Distributed DMA Default Acc 10-27 -reserved- (base address registers) 00 — 61-60 Channel 0 Base Address / Enable 0000 RW 28-2B -reserved- (unassigned) 00 — 63-62 Channel 1 Base Address / Enable 0000 RW 2F-2C Subsystem ID Read 00 RO 65-64 Channel 2 Base Address / Enable 0000 RW 30-33 -reserved- (expan. ROM base addr) 00 — 67-66 Channel 3 Base Address / Enable 0000 RW 34-3B -reserved- (unassigned) 00 — 69-68 -reserved- 0000 — 3C -reserved- (interrupt line) 00 — 6B-6A Channel 5 Base Address / Enable 0000 RW 3D -reserved- (interrupt pin) 00 — 6D-6C Channel 6 Base Address / Enable 0000 RW 3E -reserved- (min gnt) 00 — 6F-6E Channel 7 Base Address / Enable 0000 RW 3F -reserved- (max lat) 00 — Offset Miscellaneous Default Acc Configuration Space PCI-to-ISA Bridge-Specific Registers 70 Subsystem ID Write 00 WO 71-7F -reserved- 00 — Offset ISA Bus Control Default Acc 40 ISA Bus Control 00 RW 41 ISA Test Mode 00 RW 42 ISA Clock Control 00 RW 43 ROM Decode Control 00 RW 44 Keyboard Controller Control 00 RW 45 Type F DMA Control 00 RW 46 Miscellaneous Control 1 00 RW 47 Miscellaneous Control 2 00 RW 48 Miscellaneous Control 3 01 RW 49 -reserved- 00 — 4A IDE Interrupt Routing 04 RW 4B -reserved- 00 — 4C DMA / Master Mem Access Control 1 00 RW 4D DMA / Master Mem Access Control 2 00 RW 4F-4E DMA / Master Mem Access Control 3 0300 RW Revision 1.0 May 13, 1997 -16- Register Overview �9,$�7HFKQRORJLHV��,QF� VT82C586B PCI Function 1 Registers - IDE Controller Configuration Space IDE-Specific Registers Offset Configuration Space IDE Registers Default Acc Configuration Space IDE Header Registers 40 Chip Enable 08 RW 41 IDE Configuration 02 RW Offset PCI Configuration Space Header Default Acc 42 -reserved- (do not program) 09 RW 1-0 Vendor ID 1106 RO 43 FIFO Configuration 3A RW 3-2 Device ID 0571 RO 44 Miscellaneous Control 1 68 RW 5-4 Command 0080 RO 45 Miscellaneous Control 2 00 RW 7-6 Status 0280 RW 46 Miscellaneous Control 3 C0 RW 8 Revision ID nn RO A8A8A8A8 4B-48 Drive Timing Control RW 9 Programming Interface 85 RW 4C Address Setup Time FF RW A Sub Class Code 01 RO 4D -reserved- (do not program) 00 RW B Base Class Code 01 RO 4E Sec Non-1F0 Port Access Timing FF RW C -reserved- (cache line size) 00 — 4F Pri Non-1F0 Port Access Timing FF RW D Latency Timer 00 RW 53-50 UltraDMA33 Extd Timing Control 03030303 RW E Header Type 00 RO 54-5F -reserved- 00 — F Built In Self Test (BIST) 00 RO 61-60 Primary Sector Size 0200 RW 13-10 Base Address - Pri Data / Command 000001F0 RO 62-67 -reserved- 00 — 17-14 Base Address - Pri Control / Status 000003F4 RO 69-68 Secondary Sector Size 0200 RW 1B-18 Base Address - Sec Data / Command 00000170 RO 70-FF -reserved- 00 — 1F-1C Base Address - Sec Control / Status 00000374 RO 23-20 Base Address - Bus Master Control 0000CC01 RW I/O Registers - IDE Controller 24-2F -reserved- (unassigned) 00 — 30-33 -reserved- (expan ROM base addr) 00 — These registers are compliant with the SFF 8038 v1.0 standard. Refer to that specification for additional information. 34-3B -reserved- (unassigned) 00 — 3C Interrupt Line 0E RW Offset IDE I/O Registers Default Acc 3D Interrupt Pin 00 RO 0 Primary Channel Command 00 RW 3E Minimum Grant 00 RO 1 -reserved- 00 — 3F Maximum Latency 00 RO 2 Primary Channel Status 00 WC 3 -reserved- 00 — 4-7 Primary Channel PRD Table Addr 00 RW 8 Secondary Channel Command 00 RW 9 -reserved- 00 — A Secondary Channel Status 00 WC B -reserved- 00 — C-F Secondary Channel PRD Table Addr 00 RW Revision 1.0 May 13, 1997 -17- Register Overview �9,$�7HFKQRORJLHV��,QF� VT82C586B PCI Function 2 Registers - USB Controller I/O Registers - USB Controller Offset USB I/O Registers Default Acc Configuration Space USB Header Registers 1-0 USB Command 0000 RW 3-2 USB Status 0000 WC Offset PCI Configuration Space Header Default Acc 5-4 USB Interrupt Enable 0000 RW 1-0 Vendor ID 1106 RO 7-6 Frame Number 0000 RW 3-2 Device ID 3038 RO B-8 Frame List Base Address 00000000 RW 5-4 Command 0000 RW C Start Of Frame Modify 40 RW 7-6 Status 0200 WC 11-10 Port 1 Status / Control 0080 WC 8 Revision ID nn RO 13-12 Port 2 Status / Control 0080 WC 9 Programming Interface 00 RO A Sub Class Code 03 RO B Base Class Code 0C RO C Cache Line Size 00 RO D Latency Timer 16 RW E Header Type 00 RO F BIST 00 RO 10-1F -reserved- 00 — 23-20 Base Address 00000301 RW 24-3B -reserved- 00 — 3C Interrupt Line 00 RW 3D Interrupt Pin 04 RO 3E-3F -reserved- 00 — Configuration Space USB-Specific Registers Offset USB Control Default Acc 40 Miscellaneous Control 1 00 RW 41 Miscellaneous Control 2 00 RW 42-43 -reserved- 00 RO 44-45 -reserved- (test only, do not program) RW 46-47 -reserved- (test) RO 48-5F -reserved- 00 — 60 Serial Bus Release Number 10 RO 61-BF -reserved- 00 — C1-C0 Legacy Support 2000 RW C2-FF -reserved- 00 — Revision 1.0 May 13, 1997 -18- Register Overview �9,$�7HFKQRORJLHV��,QF� VT82C586B PCI Function 3 Registers - Power Management I/O Space Power Management- Registers Offset Basic Control / Status Registers Default Acc Configuration Space Power Management Header Registers 1-0 Power Management Status 0000 WC 3-2 Power Management Enable 0000 RW Offset PCI Configuration Space Header Default Acc 5-4 Power Management Control 0000 RW 1-0 Vendor ID 1106 RO 7-6 -reserved- 00 — 3-2 Device ID 3040 RO 5-4 Command 0000 RO B-8 Power Management Timer 0000 0000 RW 7-6 Status 0280 WC F-C -reserved- 00 — 8 Revision ID nn RO Offset Processor Registers Default Acc 9 Programming Interface RO 00† 13-10 Processor Control 0000 0000 RW A Sub Class Code RO 00† 14 Processor LVL2 00 RO B Base Class Code RO 00† 15 Processor LVL3 00 RO C Cache Line Size 00 RO 1F-16 -reserved- 00 — D Latency Timer 00 RO Offset General Purpose Registers Default Acc E Header Type00RO F BIST 00 RO 21-20 General Purpose Status 0000 WC 10-3F -reserved- 00 — 23-22 General Purpose SCI Enable 0000 RW † The default values for these registers may be changed by 25-24 General Purpose SMI Enable 0000 RW writing to offsets 61-63h (see below). 27-26 General Purpose Power Supply Ctrl 0200 RW Offset Generic Registers Default Acc Configuration Space Power Management-Specific Registers 29-28 Global Status 0000 WC 2B-2A Global Enable 0000 RW Offset Power Management Default Acc 2D-2C Global Control 00 RW 40 Pin Configuration 00 RW 2E -reserved- 00 — 41 General Configuration 00 RW 2F SMI Command 00 RW 42 SCI Interrupt Configuration 00 RW 33-30 Primary Activity Detect Status 0000 0000 WC 43 -reserved- 00 — 37-34 Primary Activity Detect Enable 0000 0000 RW 45-44 Primary Interrupt Channel 0000 RW 3B-38 GP Timer Reload Enable 0000 0000 RW 47-46 Secondary Interrupt Channel 0000 RW 3F-3C -reserved- 00 — 4B-48 I/O Base Address (256 Bytes) 0000 0001 RW Offset General Purpose I/O Registers Default Acc 4F-4C -reserved- 00 — 41-40 GPIO Direction Control 0000 RW 53-50 GP Timer Control 0000 0000 RW 43-42 GPIO Port Output Value 0000 RW 54-60 -reserved- 00 — 45-44 GPIO Port Input Value input RO 61 Write value for Offset 9 (Prog Intfc) 00 WO 47-46 GPO Port Output Value 0000 RW 62 Write value for Offset A (Sub Class) 00 WO 49-48 GPI Port Input Value input RO 63 Write value for Offset B (Base Class) 00 WO FF-4A -reserved- 00 — 64-FF -reserved- 00 — Revision 1.0 May 13, 1997 -19- Register Overview �9,$�7HFKQRORJLHV��,QF� VT82C586B Configuration Space I/O Mechanism #1 These ports respond only to double-word accesses. Byte or word accesses will be passed on unchanged. Port CFB-CF8 - Configuration Address ......................... RW 31 Configuration Space Enable 0 Disabled .................................................default 1 Convert configuration data port writes to configuration cycles on the PCI bus 30-24 Reserved ........................................ always reads 0 23-16 PCI Bus Number Used to choose a specific PCI bus in the system 15-11 Device Number Used to choose a specific device in the system 10-8 Function Number Used to choose a specific function if the selected device supports multiple functions 7-2 Register Number Used to select a specific DWORD in the device’s configuration space 1-0 Fixed ........................................ always reads 0 Port CFF-CFC - Configuration Data .............................. RW Refer to PCI Bus Specification Version 2.1 for further details on operation of the above configuration registers. Revision 1.0 May 13, 1997 -20- Configuration Space I/O �9,$�7HFKQRORJLHV��,QF� VT82C586B Port 92h - System Control ................................................ RW Register Descriptions 7-6 Hard Disk Activity LED Status 0 Off .................................................... default Legacy I/O Ports 1-3 On 5-4 Reserved ........................................always reads 0 This group of registers includes the DMA Controllers, Interrupt Controllers, and Timer/Counters as well as a number 3 Power-On Password Bytes Inaccessable ..default=0 of miscellaneous ports originally implemented using discrete 2 Reserved ........................................always reads 0 logic on original PC/AT motherboards. All of the registers 1 A20 Address Line Enable 0 A20 disabled / forced 0 (real mode) ...... default listed are integrated on-chip. These registers are implemented 1 A20 address line enabled in a precise manner for backwards compatibility with previous generations of PC hardware. These registers are listed for 0 High Speed Reset 0 Normal information purposes only. Detailed descriptions of the 1 Briefly pulse system reset to switch from actions and programming of these registers are included in protected mode to real mode numerous industry publications (duplication of that information here is beyond the scope of this document). All of these registers reside in I/O space. Port 61 - Misc Functions & Speaker Control ................. RW 7 Reserved ........................................ always reads 0 6 IOCHCK# Active................................................. RO This bit is set when the ISA bus IOCHCK# signal is asserted. Once set, this bit may be cleared by setting bit-3 of this register. Bit-3 should be cleared to enable recording of the next IOCHCK#. IOCHCK# generates NMI to the CPU if NMI is enabled. 5 Timer/Counter 2 Output ..................................... RO This bit reflects the output of Timer/Counter 2 without any synchronization. 4 Refresh Detected .................................................. RO This bit toggles on every rising edge of the ISA bus REFRESH# signal. 3 IOCHCK# Disable .............................................. RW 0 Enable IOCHCK# assertions..................default 1 Force IOCHCK# inactive and clear any “IOCHCK# Active” condition in bit-6 2 Reserved ........................................RW, default=0 1 Speaker Enable.................................................... RW 0 Disable ...................................................default 1 Enable Timer/Ctr 2 output to drive SPKR pin 0 Timer/Counter 2 Enable..................................... RW 0 Disable ...................................................default 1 Enable Timer/Counter 2 Revision 1.0 May 13, 1997 -21- Register Descriptions �9,$�7HFKQRORJLHV��,QF� VT82C586B Keyboard Controller Registers Port 64 - Keyboard / Mouse Status .................................. RO 0 Keyboard Output Buffer Full The keyboard controller handles the keyboard and mouse 0 Keyboard Output Buffer Empty............. default interfaces. Two ports are used: port 60 and port 64. Reads 1 Keyboard Output Buffer Full from port 64 return a status byte. Writes to port 64h are 1 Input Buffer Full command codes (see command code list following the register 0 Input Buffer Empty................................ default descriptions). Input and output data is transferred via port 60. 1 Input Buffer Full A “Control” register is also available. It is accessable by 2 System Flag writing commands 20h / 60h to the command port (port 64h); 0 Power-On Default.................................. default The control byte is written by first sending 60h to the 1 Self Test Successful command port, then sending the control byte value. The 3 Command / Data control register may be read by sending a command of 20h to 0 Last write was data write ....................... default port 64h, waiting for “Output Buffer Full” status = 1, then 1 Last write was command write reading the control byte value from port 60h. 4 Keylock Status 0 Locked Traditional (non-integrated) keyboard controllers have an “Input Port” and an “Output Port” with specific pins dedicated 1Free to certain functions and other pins available for general 5 Mouse Output Buffer Full 0 Mouse output buffer empty.................... default purpose I/O. Specific commands are provided to set these pins 1 Mouse output buffer holds mouse data high and low. All outputs are “open-collector” so to allow input on one of these pins, the output value for that pin would 6 General Receive / Transmit Timeout 0 No error ................................................. default be set high (non-driving) and the desired input value read on 1 Error the input port. These ports are defined as follows: 7 Parity Error Bit Input Port Lo Code Hi Code 0 No parity error (odd parity received)..... default 0 P10 - Keyboard Data In B0 B8 1 Even parity occurred on last byte received 1 P11 - Mouse Data In B1 B9 from keyboard / mouse 2 P12 - Turbo Pin (PS/2 mode only) B2 BA 3 P13 - user-defined B3 BB KBC Control Register .......... (R/W via Commands 20h/60h) 4 P14 - user-defined B6 BE ........................................always reads 0 7 Reserved 5 P15 - user-defined B7 BF 6 PC Compatibility 6 P16 - user-defined – – 0 Disable scan conversion 7 P17 - undefined – – 1 Convert scan codes to PC format; convert 2- Bit Output Port Lo Code Hi Code byte break sequences to 1-byte PC-compatible 0 P20 - SYSRST (1=execute reset) – – break codes ............................................ default 1 P21 - GATEA20 (1=A20 enabled) – – 5 Mouse Disable 2 P22 - Mouse Data Out B4 BC 0 Enable Mouse Interface ......................... default 3 P23 - Mouse Clock Out B5 BD 1 Disable Mouse Interface 4 P24 - Keyboard OBF Interrupt (IRQ1) – – 4 Keyboard Disable 5 P25 - Mouse OBF Interrupt (IRQ 12) – – 0 Enable Keyboard Interface .................... default 6 P26 - Keyboard Clock Out – – 1 Disable Keyboard Interface 7 P27 - Keyboard Data Out – – 3 Keyboard Lock Disable 0 Enable Keyboard Inhibit Function......... default Bit Test Port Lo Code Hi Code 1 Disable Keyboard Inhibit Function 0 T0 - Keyboard Clock In – – 2 System Flag ................................................default=0 1 T1 - Mouse Clock In – – This bit may be read back as status register bit-2 Note: Command code C0h transfers input port data to the 1 Mouse Interrupt Enable output buffer. Command code D0h copies output port values 0 Disable mouse interrupts ....................... default to the output buffer. Command code E0h transfers test input 1 Generate interrupt on IRQ12 when mouse data port data to the output buffer. comes in output bufer Port 60 - Keyboard Controller Input Buffer ................. WO 0 Keyboard Interrupt Enable Only write to port 60h if port 64h bit-1 = 0 (1=full). 0 Disable Keyboard Interrupts.................. default 1 Generate interrupt on IRQ1 when output buffer Port 60 - Keyboard Controller Output Buffer ................ RO has been written. Only read from port 60h if port 64h bit-0 = 1 (0=empty). Revision 1.0 May 13, 1997 -22- Register Descriptions �9,$�7HFKQRORJLHV��,QF� VT82C586B Port 64 - Keyboard / Mouse Command .......................... WO This port is used to send commands to the keyboard / mouse controller. The command codes recognized by the VT82C586B are listed n the table below. Note: The VT82C586B Keyboard Controller is compatible with the VIA VT82C42 Industry-Standard Keyboard Controller except that due to its integrated nature, many of the input and output port pins are not available externally for use as general purpose I/O pins (even though P13-P16 are set on power-up as strapping options). In other words, many of the commands below are provided and “work”, but otherwise perform no useful function (e.g., commands that set P12-P17 high or low). Also note that setting P10-11, P22-23, P26-27, and T0-1 high or low directly serves no useful purpose, since these bits are used to implement the keyboard and mouse ports and are directly controlled by keyboard controller logic. Table 4. Keyboard Controller Command Codes Code Keyboard Command Code Description Code Keyboard Command Code Description 20h Read Control Byte (next byte is Control Byte) C0h Read input port (read P10-17 input data to 60h Write Control Byte (next byte is Control Byte) the output buffer) C1h Poll input port low (read input data on P11-13 9xh Write low nibble (bits 0-3) to P10-P13 repeatably & put in bits 5-7 of status A1h Output Keyboard Controller Version # C2h Poll input port high (same except P15-17) A4h Test if Password is installed (always returns F1h to indicate not installed) C8h Unblock P22-23 (use before D1 to change A7h Disable Mouse Interface active mode) A8h Enable Mouse Interface C9h Reblock P22-23 (protection mechanism for D1) A9h Mouse Interface Test (puts test results in port 60h) CAh Read mode (output KBC mode info to port 60 (value: 0=OK, 1=clk stuck low, 2=clk stuck high, output buffer (bit-0=0 if ISA, 1 if PS/2) 3=data stuck lo, 4=data stuck hi, FF=general error) AAh KBC self test (returns 55h if OK, FCh if not) D0h Read Output Port (copy P10-17 output port values ABh Keyboard Interface Test (see A9h Mouse Test) to port 60) ADh Disable Keyboard Interface D1h Write Output Port (data byte following is written to AEh Enable Keyboard Interface keyboard output port as if it came from keyboard) AFh Return Version # D2h Write Keyboard Output Buffer & clear status bit-5 (write following byte to keyboard) B0h Set P10 low D3h Write Mouse Output Buffer & set status bit-5 (write B1h Set P11 low following byte to mouse; put value in mouse input B2h Set P12 low buffer so it appears to have come from the mouse) B3h Set P13 low D4h Write Mouse (write following byte to mouse) B4h Set P22 low B5h Set P23 low E0h Read test inputs (T0-1 read to bits 0-1 of resp byte) B6h Set P14 low Exh Set P23-P21 per command bits 3-1 B7h Set P15 low Fxh Pulse P23-P20 low for 6usec per command bits 3-0 B8h Set P10 high B9h Set P11 high All other codes not listed are undefined. BAh Set P12 high BBh Set P13 high BCh Set P22 high BDh Set P23 high BEh Set P14 high BFh Set P15 high Revision 1.0 May 13, 1997 -23- Register Descriptions �9,$�7HFKQRORJLHV��,QF� VT82C586B DMA Controller I/O Registers Ports C0-DF - Slave DMA Controller Channels 0-3 of the Slave DMA Controller control System DMA Channels 4-7. There are 16 Slave DMA Controller Ports 00-0F - Master DMA Controller registers: Channels 0-3 of the Master DMA Controller control System DMA Channels 0-3. There are 16 Master DMA Controller registers: I/O Address Bits 15-0 Register Name 0000 0000 1100 000x Ch 0 Base / Current Address RW I/O Address Bits 15-0 Register Name 0000 0000 1100 001x Ch 0 Base / Current Count RW 0000 0000 000x 0000 Ch 0 Base / Current Address RW 0000 0000 1100 010x Ch 1 Base / Current Address RW 0000 0000 000x 0001 Ch 0 Base / Current Count RW 0000 0000 1100 011x Ch 1 Base / Current Count RW 0000 0000 000x 0010 Ch 1 Base / Current Address RW 0000 0000 1100 100x Ch 2 Base / Current Address RW 0000 0000 000x 0011 Ch 1 Base / Current Count RW 0000 0000 1100 101x Ch 2 Base / Current Count RW 0000 0000 000x 0100 Ch 2 Base / Current Address RW 0000 0000 1100 110x Ch 3 Base / Current Address RW 0000 0000 000x 0101 Ch 2 Base / Current Count RW 0000 0000 1100 111x Ch 3 Base / Current Count RW 0000 0000 000x 0110 Ch 3 Base / Current Address RW 0000 0000 1101 000x Status / Command RW 0000 0000 000x 0111 Ch 3 Base / Current Count RW 0000 0000 1101 001x Write Request WO 0000 0000 000x 1000 Status / Command RW 0000 0000 1101 010x Write Single Mask WO 0000 0000 000x 1001 Write Request WO 0000 0000 1101 011x Write Mode WO 0000 0000 000x 1010 Write Single Mask WO 0000 0000 1101 100x Clear Byte Pointer F/F WO 0000 0000 000x 1011 Write Mode WO 0000 0000 1101 101x Master Clear WO 0000 0000 000x 1100 Clear Byte Pointer F/F WO 0000 0000 1101 110x Clear Mask WO 0000 0000 000x 1101 Master Clear WO 0000 0000 1101 111x Read/Write All Mask Bits WO 0000 0000 000x 1110 Clear Mask WO 0000 0000 000x 1111 R/W All Mask Bits RW Note that not all bits of the address are decoded. The Slave DMA Controller is compatible with the Intel 8237 Note that not all bits of the address are decoded. DMA Controller chip. Detailed description of 8237 DMA The Master DMA Controller is compatible with the Intel 8237 controller operation can be obtained from the Intel Peripheral DMA Controller chip. Detailed descriptions of 8237 DMA Components Data Book and numerous other industry Controller operation can be obtained from the Intel Peripheral publications. Components Data Book and numerous other industry publications. Ports 80-8F - DMA Page Registers There are eight DMA Page Registers, one for each DMA channel. These registers provide bits 16-23 of the 24-bit address for each DMA channel (bits 0-15 are stored in registers in the Master and Slave DMA Controllers). They are located at the following I/O Port addresses: I/O Address Bits 15-0 Register Name 0000 0000 1000 0111 Channel 0 DMA Page (M-0).........RW 0000 0000 1000 0011 Channel 1 DMA Page (M-1).........RW 0000 0000 1000 0001 Channel 2 DMA Page (M-2).........RW 0000 0000 1000 0010 Channel 3 DMA Page (M-3).........RW 0000 0000 1000 1111 Channel 4 DMA Page (S-0) ..........RW 0000 0000 1000 1011 Channel 5 DMA Page (S-1) ..........RW 0000 0000 1000 1001 Channel 6 DMA Page (S-2) ..........RW 0000 0000 1000 1010 Channel 7 DMA Page (S-3) .........RW Revision 1.0 May 13, 1997 -24- Register Descriptions �9,$�7HFKQRORJLHV��,QF� VT82C586B Interrupt Controller Registers Interrupt Controller Shadow Registers The following shadow registers are enabled by setting bit 4 of Ports 20-21 - Master Interrupt Controller Rx47 to 1 (offset 47h in the PCI-ISA Bridge function 0 The Master Interrupt Controller controls system interrupt register group). If the shadow registers are enabled, they are channels 0-7. Two registers control the Master Interrupt read back at the indicated I/O port instead of the standard Controller. They are: interrupt controller registers (writes to the interrupt controller register ports are directed to the standard interrupt controller I/O Address Bits 15-0 Register Name registers). 0000 0000 001x xxx0 Master Interrupt Control RW 0000 0000 001x xxx1 Master Interrupt Mask RW Port 20 - Master Interrupt Control Shadow ................... RO Note that not all bits of the address are decoded. 7-5 Reserved ........................................always reads 0 4 OCW3 bit 5 The Master Interrupt Controller is compatible with the Intel 3 OCW2 bit 7 8259 Interrupt Controller chip. Detailed descriptions of 8259 2 ICW4 bit 4 Interrupt Controller operation can be obtained from the Intel 1 ICW4 bit 1 Peripheral Components Data Book and numerous other 0 ICW1 bit 3 industry publications. Port 21 - Master Interrupt Mask Shadow ....................... RO 7-5 Reserved ........................................always reads 0 Ports A0-A1 - Slave Interrupt Controller 4-0 T7-T3 of Interrupt Vector Address The Slave Interrupt Controller controls system interrupt channels 8-15. The slave system interrupt controller also Port A0 - Slave Interrupt Control Shadow ..................... RO occupies two register locations: 7-5 Reserved ........................................always reads 0 I/O Address Bits 15-0 Register Name 4 OCW3 bit 5 0000 0000 101x xxx0 Slave Interrupt Control RW 3 OCW2 bit 7 0000 0000 101x xxx1 Slave Interrupt Mask RW 2 ICW4 bit 4 1 ICW4 bit 1 Note that not all address bits are decoded. 0 ICW1 bit 3 The Slave Interrupt Controller is compatible with the Intel Port A1 - Slave Interrupt Mask Shadow ........................ RO 8259 Interrupt Controller chip. Detailed descriptions of 8259 7-5 Reserved ........................................always reads 0 Interrupt Controller operation can be obtained from the Intel 4-0 T7-T3 of Interrupt Vector Address Peripheral Components Data Book and numerous other industry publications. Timer / Counter Registers Ports 40-43 - Timer / Counter Registers There are 4 Timer / Counter registers: I/O Address Bits 15-0 Register Name 0000 0000 010x xx00 Timer / Counter 0 Count RW 0000 0000 010x xx01 Timer / Counter 1 Count RW 0000 0000 010x xx10 Timer / Counter 2 Count RW 0000 0000 010x xx11 Timer / Counter Cmd Mode WO Note that not all bits of the address are decoded. The Timer / Counters are compatible with the Intel 8254 Timer / Counter chip. Detailed descriptions of 8254 Timer / Counter operation can be obtained from the Intel Peripheral Components Data Book and numerous other industry publications. Revision 1.0 May 13, 1997 -25- Register Descriptions �9,$�7HFKQRORJLHV��,QF� VT82C586B CMOS / RTC Registers Offset Description Binary Range BCD Range 00 Seconds 00-3Bh 00-59h Port 70 - CMOS Address ................................................. WO 00-3Bh 00-59h 01 Seconds Alarm 7 NMI Disable.........................................................WO 02 Minutes 00-3Bh 00-59h 0 Enable NMI Generation. NMI is asserted on 03 Minutes Alarm 00-3Bh 00-59h encountering IOCHCK# on the ISA bus or 04 Hours am 12hr: 01-1Ch 01-12h SERR# on the PCI bus. pm 12hr: 81-8Ch 81-92h 1 Disable NMI Generation ........................default 24hr: 00-17h 00-23h 6-0 CMOS Address (lower 128 bytes).......................WO am 12hr: 01-1Ch 01-12h 05 Hours Alarm Port 71 - CMOS Data........................................................ RW pm 12hr: 81-8Ch 81-92h 24hr: 00-17h 00-23h 7-0 CMOS Data (128 bytes) 06 Day of the Week Sun=1: 01-07h 01-07h Note: Ports 70-71 may be accessed if Rx5A bit-2 is set to 07 Day of the Month 01-1Fh 01-31h one to select the internal RTC. If Rx5A bit-2 is set to 08 Month 01-0Ch 01-12h zero, accesses to ports 70-71 will be directed to an 09 Year 00-63h 00-99h external RTC. 0A Register A Port 72 - CMOS Address .................................................. RW 7 UIP Update In Progress 7-0 CMOS Address (256 bytes)................................. RW 6-4 DV2-0 Divide (010=ena osc & keep time) 3-0 RS3-0 Rate Select for Periodic Interrupt Port 73 - CMOS Data........................................................ RW 7-0 CMOS Data (256 bytes) 0B Register B Note: Ports 72-73 may be accessed if Rx5A bit-2 is set to 7 SET Inhibit Update Transfers one to select the internal RTC. If Rx5A bit-2 is set to 6PIE Periodic Interrupt Enable zero, accesses to ports 72-73 will be directed to an 5 AIE Alarm Interrupt Enable external RTC. 4 UIE Update Ended Interrupt Enable 3 SQWE No function (read/write bit) Port 74 - CMOS Address .................................................. RW 2DM Data Mode (0=BCD, 1=binary) 7-0 CMOS Address (256 bytes)................................. RW 1 24/12 Hours Byte Format (0=12, 1=24) 0 DSE Daylight Savings Enable Port 75 - CMOS Data........................................................ RW 7-0 CMOS Data (256 bytes) 0C Register C Interrupt Request Flag 7 IRQF Note: Ports 74-75 may be accessed only if Function 0 Rx5B Periodic Interrupt Flag 6PF bit-1 is set to one to enable the internal RTC SRAM Alarm Interrupt Flag 5AF and if Rx48 bit-3 (Port 74/75 Access Enable) is set to 4UF Update Ended Flag one to enable port 74/75 access. 3-0 0 Unused (always read 0) Note: Ports 70-71 are compatible with PC industry- standards and may be used to access the lower 128 0D Register D bytes of the 256-byte on-chip CMOS RAM. Ports 7 VRT Reads 1 if VBAT voltage is OK 72-73 may be used to access the full extended 256- 6-0 0 Unused (always read 0) byte space. Ports 74-75 may be used to access the (111 Bytes) full on-chip extended 256-byte space in cases where 0E-7C Software-Defined Storage Registers the on-chip RTC is disabled. Offset Extended Functions Binary Range BCD Range Note: The system Real Time Clock (RTC) is part of the 7D Date Alarm 01-1Fh01-31h “CMOS” block. The RTC control registers are 7E Month Alarm 01-0Ch 01-12h located at specific offsets in the CMOS data area (0- 7F Century Field 13-14h 19-20h 0Dh and 7D-7Fh). Detailed descriptions of CMOS / RTC operation and programming can be obtained 80-FF Software-Defined Storage Registers (128 Bytes) from the VIA VT82887 Data Book or numerous other industry publications. For reference, the definition of the RTC register locations and bits are Table 5. CMOS Register Summary summarized in the following table: Revision 1.0 May 13, 1997 -26- Register Descriptions �9,$�7HFKQRORJLHV��,QF� VT82C586B PCI to ISA Bridge Registers (Function 0) ISA Bus Control All registers are located in the function 0 PCI configuration Offset 40 - ISA Bus Control ............................................. RW space of the VT82C586B. These registers are accessed through PCI configuration mechanism #1 via I/O address 7 ISA Command Delay CF8/CFC. 0 Normal................................................... default 1 Extra 6 Extended ISA Bus Ready PCI Configuration Space Header 0 Disable................................................... default 1 Enable Offset 1-0 - Vendor ID = 1106h ......................................... RO 5 ISA Slave Wait States 0 4 Wait States.......................................... default Offset 3-2 - Device ID = 0586h .......................................... RO 1 5 Wait States 4 Chipset I/O Wait States Offset 5-4 - Command ....................................................... RW 0 2 Wait States.......................................... default ........................................ always reads 0 15-4 Reserved 1 4 Wait States 3 Special Cycle Enable .....Normally RW†, default = 1 3 I/O Recovery Time 2 Bus Master ........................................ always reads 1 0 Disable................................................... default 1 Memory Space.................. Normally RO†, reads as 1 1 Enable 0 I/O Space ...................... Normally RO†, reads as 1 2 Extend-ALE † If the test bit at offset 46 bit-4 is set, access to the above 0 Disable................................................... default indicated bits is reversed: bit-3 above becomes read only 1 Enable (reading back 1) and bits 0-1 above become read / write (with 1 ROM Wait States a default of 1). 0 1 Wait State ........................................... default 1 0 Wait States Offset 7-6 - Status ........................................................... RWC 0 ROM Write 15 Detected Parity Error....................write one to clear 0 Disable................................................... default ...................... always reads 0 14 Signalled System Error 1 Enable 13 Signalled Master Abort .................write one to clear Offset 41 - ISA Test Mode ................................................ RW 12 Received Target Abort ..................write one to clear 7 Bus Refresh Arbitration (do not program) default=0 11 Signalled Target Abort...................... always reads 0 6 XRDY Test Mode (do not program) ...........default=0 10-9 DEVSEL# Timing .................... fixed at 01 (medium) 5 Port 92 Fast Reset 8 Data Parity Detected.......................... always reads 0 0 Disable................................................... default 7 Fast Back-to-Back.............................. always reads 0 1 Enable 6-0 Reserved ........................................ always reads 0 4 A20G Emulation (do not program).............default=0 Offset 8 - Revision ID = nn ................................................ RO 3 Double DMA Clock 7-0 ID for VT82C586 = 0xh 0 Disable (DMA Clock = ½ ISA Clock)... default ID for VT82C586A = 2xh 1 Enable (DMA Clock = ISA Clock) ID for VT82C586B = 3xh (3040 OEM Silicon) 2 SHOLD Lock During INTA (do not program) def=0 ID for VT82C586B = 4xh (3041 Production Sil.) 1 Refresh Request Test Mode (do not program).def=0 0 Refresh Test Mode ..................... (3041 silicon only) Offset 9 - Program Interface = 00h ................................... RO 0 Disable ISA Refresh .............................. default 1 Enable ISA Refresh Offset A - Sub Class Code = 01h ....................................... RO Note: This bit should always be set to one in the OEM 3040 silicon. Offset B - Class Code = 06h ............................................... RO Offset E - Header Type = 80h ............................................ RO 7-0 Header Type Code .........80h (Multifunction Device) Offset F - BIST = 00h ......................................................... RO Offset 2F-2C - Subsystem ID ............................................. RO Revision 1.0 May 13, 1997 -27- Register Descriptions �9,$�7HFKQRORJLHV��,QF� VT82C586B Offset 42 - ISA Clock Control. ......................................... RW Offset 46 - Miscellaneous Control 1 ................................ RW 7 Latch IO16# 7 PCI Master Write Wait States .(3041 Silicon Only) 0 Enable (recommended setting) ...............default 0 0 Wait States.......................................... default 1 Disable 1 1 Wait State 6 Reserved (no defined function) ................. default = 0 6 Gate INTRQ...............................(3041 Silicon Only) 0 Disable................................................... default 5 Master Request Test Mode (do not program) . def=0 1 Enable 4 Reserved (no defined function) ................. default = 0 5 Flush Line Buffer for Int or DMA IOR Cycle ........ 3 ISA CLOCK Select Enable 0 ISA Clock = PCICLK/4 .........................default ...............................(3041 Silicon Only) 0 Disable................................................... default 1 ISA Clock selected per bits 2-0 1 Enable 2-0 ISA Bus Clock Select (if bit-3 = 1) 000 PCICLK/3 ..............................................default 4 Config Command Reg Rx04 Access (Test Only) 0 Normal: Bits 0-1=RO, Bit 3=RW......... default 001 PCICLK/2 1 Test Mode: Bits 0-1=RW, Bit-3=RO 010 PCICLK/4 3 Reserved (do not program)........................default = 0 011 PCICLK/6 2 Reserved (no function) ..............................default = 0 100 PCICLK/5 101 PCICLK/10 1 PCI Burst Read Interruptability 0 Allow burst reads to be interrupted........ default 110 PCICLK/12 1 Don’t allow PCI burst reads to be interrupted 111 OSC/2 0 Post Memory Write Enable Note: Procedure for ISA CLOCK switching: 0 Disable................................................... default 1) Set bit 3 to 0; 2) Change value of bit 2-0; 3) Set bit 3 to 1 1 Enable The Post Memory Write function is automatically Offset 43 - ROM Decode Control .................................... RW enabled when Delay Transaction (see Rx47 bit-6 Setting these bits enables the indicated address range to be below) is enabled, independent of the state of this bit. included in the ROMCS# decode: Offset 47 - Miscellaneous Control 2 ................................ RW .......................... default=0 7 FFFE0000h-FFFEFFFFh 6 FFF80000h-FFFDFFFFh .........................default=0 7 CPU Reset Source 5 000E8000h-000EFFFFh ............................ default=0 0 Use CPURST as CPU Reset .................. default 1 Use INIT as CPU Reset 4 000E0000h-000E7FFFh ............................ default=0 6 PCI Delay Transaction Enable 3 000D8000h-000DFFFFh ........................... default=0 0 Disable................................................... default 2 000D0000h-000D7FFFh ............................ default=0 1 Enable 1 000C8000h-000CFFFFh ........................... default=0 The "Post Memory Write" function is automatically 0 000C0000h-000C7FFFh............................. default=0 enabled when this bit is enabled, independent of the Offset 44 - Keyboard Controller Control ........................ RW state of Rx46 bit-0 above. 7 KBC Timeout Test (do not program) ....... default = 0 5 EISA 4D0/4D1 Port Enable 6-4 Reserved (do not program)........................ default = 0 0 Disable (ignore ports 4D0-1)................. default 3 Mouse Lock Enable 1 Enable (ports 4D0-1 per EISA specification) 0 Disabled .................................................default 4 Interrupt Controller Shadow Register Enable 1 Enabled 0 Disable................................................... default 2-1 Reserved (do not program)........................ default = 0 1 Enable 0 Reserved (no function).............................. default = 0 3 Reserved (always program to 0)..............default = 0 Note: Always mask this bit. This bit may read back Offset 45 - Type F DMA Control ..................................... RW as either 0 or 1 but must always be 7 ISA Master / DMA to PCI Line Buffer .... default=0 programmed with 0. ........... default=0 6 DMA type F Timing on Channel 7 2 Write Delay Transaction Time-Out Timer Enable 5 DMA type F Timing on Channel 6 ........... default=0 0 Disable................................................... default 4 DMA type F Timing on Channel 5 ........... default=0 1 Enable 3 DMA type F Timing on Channel 3 ........... default=0 1 Read Delay Transaction Time-Out Timer Enable 2 DMA type F Timing on Channel 2 ........... default=0 0 Disable................................................... default 1 DMA type F Timing on Channel 1 ........... default=0 1 Enable 0 DMA type F Timing on Channel 0 ........... default=0 0 Software PCI Reset ......write 1 to generate PCI reset Revision 1.0 May 13, 1997 -28- Register Descriptions �9,$�7HFKQRORJLHV��,QF� VT82C586B Offset 48 - Miscellaneous Control 3 ................................. RW 4C - ISA DMA/Master Memory Access Control 1 ........ RW 7-6 Reserved ........................................ always reads 0 7-0 PCI Memory Hole Bottom Address These bits correspond to HA[23:16] ............default=0 5 MASTER# Pin Function (Pin 137)... (3041 Silicon) 0 "Input" Mode (Pin 137 = MASTER#) ...default 4D - ISA DMA/Master Memory Access Control 2 ........ RW 1 "Output" Mode (Pin 137 = SDDIR) 7-0 PCI Memory Hole Top Address (HA[23:16]) 4 IRQ8# Input Source.........(3040F and 3041 Silicon) These bits correspond to HA[23:16] ............default=0 0 IRQ8# input on RTCX1 pin 104 ............default 1 IRQ8# input on KEYLOCK pin 106 Note: Access to the memory defined in the PCI memory See also Rx5A[2] - internal/external RTC: hole will not be forwarded to PCI. This function is Rx5A[2] Rx48[4] Pin Function disabled if the top address less than or equal to the 0 0 Ext RTC, IRQ8# in pin 104 bottom address. 0 1 Ext RTC, IRQ8# in pin 106 4F-4E - ISA DMA/Master Memory Access Control 3 ... RW 1 x Int RTC, no IRQ8# in req'd 3 Extra RTC Port 74/75 Enable 15-12 Top of PCI Memory for ISA DMA/Master accesses 0 Disable ...................................................default 0000 1M .................................................... default 1 Enable 0001 2M 2 Integrated USB Controller Disable ... ... 0 Enable.....................................................default 1111 16M 1 Disable Note: All ISA DMA / Masters that access addresses higher 1 Integrated IDE Controller Disable than the top of PCI memory will not be directed to the 0 Enable.....................................................default PCI bus. 1 Disable 11 Forward E0000-EFFFF Accesses to PCI........def=0 0 512K PCI Memory Decode 10 Forward A0000-BFFFF Accesses to PCI .......def=0 0 Use Rx4E[15-12] to select top of PCI memory 9 Forward 80000-9FFFF Accesses to PCI ........def=1 1 Use contents of Rx4E[15-12] plus 512K as top 8 Forward 00000-7FFFF Accesses to PCI ........def=1 of PCI memory .......................................default 7 Forward DC000-DFFFF Accesses to PCI ......def=0 ......def=0 6 Forward D8000-DBFFF Accesses to PCI Offset 4A - IDE Interrupt Routing .................................. RW 5 Forward D4000-D7FFF Accesses to PCI .......def=0 7 Wait for PGNT Before Grant to ISA Master / 4 Forward D0000-D3FFF Accesses to PCI .......def=0 DMA 3 Forward CC000-CFFFF Accesses to PCI .....def=0 0 Disable...................................................default 2 Forward C8000-CBFFF Accesses to PCI ......def=0 1 Enable (must be set to 1) 1 Forward C4000-C7FFF Accesses to PCI .......def=0 6 Bus Select for Access to I/O Devices Below 100h 0 Forward C0000-C3FFF Accesses to PCI .......def=0 0 Access ports 00-FFh via XD bus............default 1 Access ports 00-FFh via SD bus (applies to external devices only; internal devices such as the mouse controller are not effected) ..................... default = 0 5-4 Reserved (do not program) 3-2 IDE Second Channel IRQ Routing 00 IRQ14 01 IRQ15.....................................................default 10 IRQ10 11 IRQ11 1-0 IDE Primary Channel IRQ Routing 00 IRQ14.....................................................default 01 IRQ15 10 IRQ10 11 IRQ11 Revision 1.0 May 13, 1997 -29- Register Descriptions �9,$�7HFKQRORJLHV��,QF� VT82C586B Plug and Play Control Offset 50 - Reserved (Do Not Program) .......................... RW Offset 58 - PNP IRQ Routing 4 ....................................... RW 7-0 Reserved .......................................... default = 04h These bits control routing for external IRQ input MIRQ2. 7-4 Reserved ........................................always reads 0 Offset 54 - PCI IRQ Edge / Level Select .......................... RW 3-0 MIRQ2 Routing (see PnP IRQ routing table) 7-4 Reserved ........................................ always reads 0 PnP IRQ Routing Table The following bits all default to “level” triggered (0) 0000 Disabled................................................. default 3 PIRQA# Invert (edge) / Non-invert (level).......(1/0) 0001 IRQ1 2 PIRQB# Invert (edge) / Non-invert (level).......(1/0) 0010 Reserved .......(1/0) 1 PIRQC# Invert (edge) / Non-invert (level) 0011 IRQ3 0 PIRQD# Invert (edge) / Non-invert (level).......(1/0) 0100 IRQ4 Note: PIRQA-D# normally connect to PCI interrupt pins 0101 IRQ5 INTA-D# (see pin definitions for more information). 0110 IRQ6 0111 IRQ7 Note: The definitions of the fields of the following three 1000 Reserved registers were incorrectly documented in some earlier 1001 IRQ9 revisions of this document. The silicon has not changed 1010 IRQ10 and the following definition should be used for all silicon 1011 IRQ11 revisions: 1100 IRQ12 1101 Reserved Offset 55 - PNP IRQ Routing 1 ........................................ RW 1110 IRQ14 These bits control routing for external IRQ inputs MIRQ0-1. 1111 IRQ15 7-4 PIRQD# Routing (see PnP IRQ routing table) 3-0 MIRQ0 Routing (see PnP IRQ routing table) Offset 59 - MIRQ Pin Configuration .............................. RW 7-4 Reserved ........................................always reads 0 Offset 56 - PNP IRQ Routing 2 ........................................ RW 3 Power-On Suspend Status Output Enable (Pin 90) 7-4 PIRQA# Routing (see PnP IRQ routing table) ..(3040 Rev F and 3041 Silicon Only)) 3-0 PIRQB# Routing (see PnP IRQ routing table) 0 Disable POS Status Output.................... default 1 Enable POS Status output on pin 90. Alternate Offset 57 - PNP IRQ Routing 3 ........................................ RW functions of pin 90 are APICCS# and MIRQ0 7-4 PIRQC# Routing (see PnP IRQ routing table) if this bit is not set (see bit-0 below). 3-0 MIRQ1 Routing (see PnP IRQ routing table) 2 MIRQ2 / MASTER# Selection (Pin 137) Note: these bits must be set to 0 if Rx48[4]=1 and 0 MIRQ2................................................... default Rx59[1]=1 (input IRQ8# on MIRQ1 pin 106) 1 MASTER# 1 MIRQ1 / KEYLOCK Selection (Pin 106) 0 MIRQ1................................................... default 1 KEYLOCK 0 MIRQ0 / APICCS# Selection (Pin 90) 0 MIRQ0................................................... default 1 APICCS# Revision 1.0 May 13, 1997 -30- Register Descriptions �9,$�7HFKQRORJLHV��,QF� VT82C586B Offset 5A - XD Power-On Strap Options ........................ RW Offset 5B - Internal RTC Test Mode .............................. RW The bits in this register are latched from pins XD7-0 at power- 7-3 Reserved ........................................always reads 0 up but are read/write accessible so may be changed after 2 RTC Reset Enable (do not program) ..........default=0 power-up to change the default strap setting: 1 RTC SRAM Access Enable 0 Disable................................................... default 7 Keyboard RP16.............................latched from XD7 1 Enable 6 Keyboard RP15 ............................latched from XD6 This bit is set if the internal RTC is disabled but it is 5 Keyboard RP14 ............................latched from XD5 desired to still be able to access the internal RTC 4 Keyboard RP13 ............................latched from XD4 SRAM via ports 74-75. If the internal RTC is 3 Reserved ....................................... always reads 0 enabled, setting this bit does nothing (the internal ....................latched from XD2 2 Internal RTC Enable RTC SRAM should be accessed at either ports 70/71 0 Disable or 72/73. 1 Enable 0 RTC Test Mode Enable (do not program) .default=0 1 Internal PS2 Mouse Enable..........latched from XD1 0 Disable Offset 5C - DMA Control (3041 Silicon Only) ............... RW 1 Enable 7-1 Reserved ........................................always reads 0 0 Internal KBC Enable....................latched from XD0 0 DMA Line Buffer Disable 0 Disable 0 DMA cycles can be to/from line buffer ....... def 1 Enable 1 Disable DMA Line Buffer Note: External strap option values may be set by connecting the indicated external pin to a 4.7K ohm pullup (for 1) or driving it low during reset with a 7407 TTL open collector buffer (for 0) as shown in the suggested circuit below: 9&&9&& . 5(6(7;’ Figure 3. Strap Option Circuit Revision 1.0 May 13, 1997 -31- Register Descriptions �9,$�7HFKQRORJLHV��,QF� VT82C586B Distributed DMA Control Miscellaneous Offset 61-60 - Distributed DMA Ch 0 Base / Enable ...... RW Offset 73-70 - Subsystem ID (3041 Silicon Only) ........... WO 15-4 Channel 0 Base Address Bits 15-4 .......... default = 0 31-0 Subsystem ID and Subsystem Vendor ID 3 Channel 0 Enable Write Only. Always reads back 0. 0 Disable ...................................................default Contents may be read at offset 2C. 1 Enable ........................................ always reads 0 2-0 Reserved Offset 63-62 - Distributed DMA Ch 1 Base / Enable ...... RW 15-4 Channel 1 Base Address Bits 15-4 .......... default = 0 3 Channel 1 Enable 0 Disable ...................................................default 1 Enable 2-0 Reserved ........................................ always reads 0 Offset 65-64 - Distributed DMA Ch 2 Base / Enable ...... RW 15-4 Channel 2 Base Address Bits 15-4 .......... default = 0 3 Channel 2 Enable 0 Disable ...................................................default 1 Enable 2-0 Reserved ........................................ always reads 0 Offset 67-66 - Distributed DMA Ch 3 Base / Enable ...... RW 15-4 Channel 3 Base Address Bits 15-4 .......... default = 0 3 Channel 3 Enable 0 Disable ...................................................default 1 Enable 2-0 Reserved ........................................ always reads 0 Offset 6B-6A - Distributed DMA Ch 5 Base / Enable .... RW 15-4 Channel 5 Base Address Bits 15-4 .......... default = 0 3 Channel 5 Enable 0 Disable ...................................................default 1 Enable 2-0 Reserved ........................................ always reads 0 Offset 6D-6C - Distributed DMA Ch 6 Base / Enable .... RW 15-4 Channel 6 Base Address Bits 15-4 .......... default = 0 3 Channel 6 Enable 0 Disable ...................................................default 1 Enable 2-0 Reserved ........................................ always reads 0 Offset 6F-6E - Distributed DMA Ch 7 Base / Enable ..... RW 15-4 Channel 7 Base Address Bits 15-4 .......... default = 0 3 Channel 7 Enable 0 Disable ...................................................default 1 Enable 2-0 Reserved ........................................ always reads 0 Revision 1.0 May 13, 1997 -32- Register Descriptions �9,$�7HFKQRORJLHV��,QF� VT82C586B Enhanced IDE Controller Registers (Function 1) Offset 9 - Programming Interface ................................... RW 7 Master IDE Capability........... fixed at 1 (Supported) This Enhanced IDE controller interface is fully compatible 6-4 Reserved ........................................always reads 0 with the SFF 8038i v.1.0 specification. There are two sets of ...... fixed at 1 3 Programmable Indicator - Secondary software accessible registers -- PCI configuration registers and 0 Fixed (mode is determined by bit-2) Bus Master IDE I/O registers. The PCI configuration registers 1 Supports both modes (may be set to either are located in the function 1 PCI configuration space of the mode by writing bit-2) VT82C586B. The Bus Master IDE I/O registers are defined in 2 Channel Operating Mode - Secondary the SFF8038i v1.0 specification. 0 Compatibility Mode ............default if SPKR=0 1 Native PCI Mode ................default if SPKR=1 PCI Configuration Space Header The default value for this bit is determined at power- up as strapped by the SPKR pin (pin 134) ): 0 = Offset 1-0 - Vendor ID (1106h=VIA) ................................ RO fixed IDE addressing, 1 = flexible IDE addressing. See figure 2 for strap circuit. Offset 3-2 - Device ID (0571h=IDE Controller) ............... RO 1 Programmable Indicator - Primary.......... fixed at 1 0 Fixed (mode is determined by bit-2) Offset 5-4 - Command ....................................................... RW 1 Supports both modes (may be set to either 15-10 Reserved ........................................ always reads 0 mode by writing bit-0) 9 Fast Back to Back Cycles ..........fixed at 0 (disabled) 0 Channel Operating Mode - Primary 8 SERR# Enable............................fixed at 0 (disabled) 0 Compatibility Mode.............default if SPKR=0 7 Address Stepping ...................... default=1 (enabled) 1 Native PCI Mode ................default if SPKR=1 VIA recommends that this bit always be set to 1 to The default value for this bit is determined at power- provide additional address decode time to IDE up as strapped by the SPKR pin (pin 134) ): 0 = devices. fixed IDE addressing, 1 = flexible IDE addressing. 6 Parity Error Response...............fixed at 0 (disabled) See figure 2 for strap circuit. ....................fixed at 0 (disabled) 5 VGA Palette Snoop Compatibility Mode (fixed IRQs and I/O addresses): 4 Memory Write & Invalidate .....fixed at 0 (disabled) 3 Special Cycles .............................fixed at 0 (disabled) Command Block Control Block 2 Bus Master ............................... default=0 (disabled) Channel Registers Registers IRQ S/G operation can be issued only when the “Bus Pri 1F0-1F7 3F6 14 Master” bit is enabled. Sec 170-177 376 15 ............................fixed at 0 (disabled) 1 Memory Space Native PCI Mode (registers are programmable in I/O space) 0 I/O Space ............................... default=0 (disabled) Command Block Control Block When the “I/O Space” bit is disabled, the device will Channel Registers Registers not respond to any I/O addresses for both compatible Pri BA @offset 10h BA @offset 14h and native mode. Sec BA @offset 18h BA @offset 1Ch Offset 7-6 - Status ........................................................... RWC Command register blocks are 8 bytes of I/O space 15 Detected Parity Error................................ default=0 Control registers are 4 bytes of I/O space (only byte 2 is used) 14 Signalled System Error.............................. default=0 13 Received Master Abort.............................. default=0 Offset A - Sub Class Code (01h) ....................................... RO 12 Received Target Abort .............................. default=0 Offset B - Base Class Code (01h) ...................................... RO 11 Signalled Target Abort..............................Fixed at 0 10-9 DEVSEL# Timing ..................default = 01 (medium) Offset D - Latency Timer (Default=0) ............................. RW 8 Data Parity Detected.................................. default=0 ......................................Fixed at 1 7 Fast Back to Back Offset E - Header Type (00h) ............................................ RO 6-0 Reserved ........................................ always reads 0 Offset F - BIST (00h) ......................................................... RO Offset 8 - Revision ID ......................................................... RO 0-7 Revision Code for IDE Controller Logic Block Revision 1.0 May 13, 1997 -33- Register Descriptions �9,$�7HFKQRORJLHV��,QF� VT82C586B Offset 13-10 - Pri Data / Command Base Address.......... RW Offset 3C - Interrupt Line (0Eh) ..................................... RW Specifies an 8 byte I/O address space. Offset 3D - Interrupt Pin (00h) ......................................... RO 31-16 Reserved ..........................................always read 0 7-0 Interrupt Routing Mode ....................................... default=01F0h 15-3 Port Address 00h Legacy mode interrupt routing............... default 2-0 Fixed at 001b ..................................................... fixed 01h Native mode interrupt routing Offset 17-14 - Pri Control / Status Base Address............ RW Offset 3E - Min Gnt (00h) ................................................. RO Specifies a 4 byte I/O address space of which only the third Offset 3F - Max Latency (00h).......................................... RO byte is active (i.e., 3F6h for the default base address of 3F4h). ..........................................always read 0 31-16 Reserved 15-2 Port Address....................................... default=03F4h 1-0 Fixed at 01b ....................................................... fixed Offset 1B-18 - Sec Data / Command Base Address ........ RW Specifies an 8 byte I/O address space. 31-16 Reserved ..........................................always read 0 15-3 Port Address ...................................... default=0170h ..................................................... fixed 2-0 Fixed at 001b Offset 1F-1C - Sec Control / Status Base Address .......... RW Specifies a 4 byte I/O address space of which only the third byte is active (i.e., 376h for the default base address of 374h). 31-16 Reserved ..........................................always read 0 ...................................... default=0374h 15-2 Port Address 1-0 Fixed at 01b ....................................................... fixed Offset 23-20 - Bus Master Control Regs Base Address .. RW Specifies a 16 byte I/O address space compliant with the SFF- 8038i rev 1.0 specification. 31-16 Reserved ..........................................always read 0 15-4 Port Address .......................................default=CC0h .................................................. fixed 3-0 Fixed at 0001b Revision 1.0 May 13, 1997 -34- Register Descriptions �9,$�7HFKQRORJLHV��,QF� VT82C586B IDE-Controller-Specific Confiiguration Registers Offset 44 - Miscellaneous Control 1 ................................ RW 7 Reserved ........................................always reads 0 Offset 40 - Chip Enable ..................................................... RW 6 Master Read Cycle IRDY# Wait States 0 0 wait states 7-2 Reserved ............................ always reads 000001b 1 1 wait state............................................. default 1 Primary Channel Enable........ default = 0 (disabled) 5 Master Write Cycle IRDY# Wait States 0 Secondary Channel Enable .... default = 0 (disabled) 0 0 wait states Offset 41 - IDE Configuration .......................................... RW 1 1 wait state............................................. default 4 FIFO Output Data 1/2 Clock Advance 7 Primary IDE Read Prefetch Buffer 0 Disabled................................................. default 0 Disable ...................................................default 1 Enabled 1 Enable 3 Bus Master IDE Status Register Read Retry 6 Primary IDE Post Write Buffer 0 Disable ...................................................default Retry bus master IDE status register read when master write operation for DMA read is not complete 1 Enable 0 Disabled 5 Secondary IDE Read Prefetch Buffer 1 Enabled.................................................. default 0 Disable ...................................................default 1 Enable 2 Reserved ........................................always reads 0 4 Secondary IDE Post Write Buffer 1 B-Channel Threshold Value 0 (3041 Silicon Only) 0 Disabled................................................. default 0 Disable ...................................................default 1 Enabled 1 Enable ....... , default=0 0 A-Channel Threshold Value 0 (3041 Silicon Only) 3 Reserved (read write) do not change 0 Disabled................................................. default 2 Reserved (read write) .......do not change, default=1 1 Enabled 1 Reserved (read write) .......do not change, default=1 0 Reserved (read write) .......do not change, default=0 Offset 45 - Miscellaneous Control 2 ................................ RW Offset 42 - Reserved (Do Not Program) .......................... RW 7 Reserved ........................................always reads 0 6 Interrupt Steering Swap Offset 43 - FIFO Configuration ....................................... RW 0 Don’t swap channel interrupts ............... default 7 PREQ# Asserted Till DDACK# De-Asserted .......... 1 Swap interrupts between the two channels .............................. (3041 Silicon Only) 5-0 Reserved ........................................always reads 0 0 Disabled .................................................default Offset 46 - Miscellaneous Control 3 ................................ RW 1 Enabled 7 Primary Channel Read DMA FIFO Flush 6-5 FIFO Configuration Between the Two Channels 1 = Enable FIFO flush for read DMA when interrupt Primary Secondary 00 16 0 asserts primary channel. ...............default=1 (enabled) 01 8 8......................................default 6 Secondary Channel Read DMA FIFO Flush 1 = Enable FIFO flush for Read DMA when interrupt 10 8 8 asserts secondary channel............ Default=1 (enabled) 11 0 16 5 Primary Channel End-of-Sector FIFO Flush 4 Reserved ........................................ always reads 1 1 = Enable FIFO flush at the end of each sector for 3-2 Threshold for Primary Channel the primary channel. ................... Default=0 (disabled) 00 1 4 Secondary Channel End-of-Sector FIFO Flush 01 3/4 1 = Enable FIFO flush at the end of each sector for 10 1/2 .....................................................default the secondary channel................. Default=0 (disabled) 11 1/4 3-2 Reserved ........................................always reads 0 1-0 Threshold for Secondary Channel 1-0 Max DRDY Pulse Width 00 1 Maximum DRDY# pulse width after the cycle count. 01 3/4 Command will deassert in spite of DRDY# status to 10 1/2 .....................................................default avoid system ready hang. 11 1/4 00 No limitation.......................................... default 01 64 PCI clocks 10 128 PCI clocks 11 192 PCI clocks Revision 1.0 May 13, 1997 -35- Register Descriptions �9,$�7HFKQRORJLHV��,QF� VT82C586B Offset 4B-48 - Drive Timing Control ............................... RW Offset 53-50 - UltraDMA33 Extended Timing Control . RW The following fields define the Active Pulse Width and 31 Pri Drive 0 UltraDMA33-Mode Enable Method Recovery Time for the IDE DIOR# and DIOW# signals: 0 Enable by using “Set Feature” command..... def 1 Enable by setting bit-6 of this register 31-28 Primary Drive 0 Active Pulse Width...... def=1010b 30 Pri Drive 0 UltraDMA33-Mode Enable 27-24 Primary Drive 0 Recovery Time............. def=1000b 0 Disable................................................... default 23-20 Primary Drive 1 Active Pulse Width...... def=1010b 1 Enable UltraDMA33-Mode Operation 19-16 Primary Drive 1 Recovery Time............. def=1000b 29 Pri Drive 0 Transfer Mode ........................ read only 15-12 Secondary Drive 0 Active Pulse Width .. def=1010b 0 Based on UltraDMA33 DMA mode...... default 11-8 Secondary Drive 0 Recovery Time ......... def=1000b 1 Based on UltraDMA33 PIO Mode .. def=1010b 7-4 Secondary Drive 1 Active Pulse Width ........................................always reads 0 28-26 Reserved 3-0 Secondary Drive 1 Recovery Time ......... def=1000b 25-24 Pri Drive 0 Cycle Time The actual value for each field is the encoded value in the field 02T plus one and indicates the number of PCI clocks. 13T 24T Offset 4C - Address Setup Time ....................................... RW 3 5T .................................................... default 7-6 Primary Drive 0 Address Setup Time 5-4 Primary Drive 1 Address Setup Time 23 Pri Drive 1 UltraDMA33-Mode Enable Method 3-2 Secondary Drive 0 Address Setup Time 22 Pri Drive 1 UltraDMA33-Mode Enable 1-0 Secondary Drive 1 Address Setup Time ........................ read only 21 Pri Drive 1 Transfer Mode For each field above: 20-18 Reserved ........................................always reads 0 00 1T 17-16 Pri Drive 1 Cycle Time 01 2T 15 Sec Drive 0 UltraDMA33-Mode Enable Method 10 3T 14 Sec Drive 0 UltraDMA33-Mode Enable 11 4T .....................................................default 13 Sec Drive 0 Transfer Mode........................ read only 12-10 Reserved ........................................always reads 0 Offset 4E - Secondary Non-1F0 Port Access Timing ...... RW 9-8 Sec Drive 0 Cycle Time 7-4 DIOR#/DIOW# Active Pulse Width....... def=1111b 3-0 DIOR#/DIOW# Recovery Time.............. def=1111b 7 Sec Drive 1 UltraDMA33-Mode Enable Method The actual value for each field is the encoded value in 6 Sec Drive 1 UltraDMA33-Mode Enable the field plus one and indicates the number of PCI 5 Sec Drive 1 Transfer Mode........................ read only clocks. 4-2 Reserved ........................................always reads 0 1-0 Sec Drive 1 Cycle Time Offset 4F - Primary Non-1F0 Port Access Timing` ........ RW Each byte defines UltraDMA33 operation for the indicated 7-4 DIOR#/DIOW# Active Pulse Width....... def=1111b drive. The bit definitions are the same within each byte. 3-0 DIOR#/DIOW# Recovery Time.............. def=1111b The actual value for each field is the encoded value in Offset 61-60 - Primary Sector Size .................................. RW the field plus one and indicates the number of PCI clocks. ........................................always reads 0 15-12 Reserved 11-0 Number of Bytes Per Sector ................default=200h Offset 69-68 - Secondary Sector Size .............................. RW 15-12 Reserved ........................................always reads 0 11-0 Number of Bytes Per Sector ................default=200h Revision 1.0 May 13, 1997 -36- Register Descriptions �9,$�7HFKQRORJLHV��,QF� VT82C586B IDE I/O Registers These registers are compliant with the SFF 8038I v1.0 standard. Refer to the SFF 8038I v1.0 specification for further details. Offset 0 - Primary Channel Command Offset 2 - Primary Channel Status Offset 4-7 - Primary Channel PRD Table Address Offset 8 - Secondary Channel Command Offset A - Secondary Channel Status Offset C-F - Secondary Channel PRD Table Address Revision 1.0 May 13, 1997 -37- Register Descriptions �9,$�7HFKQRORJLHV��,QF� VT82C586B Universal Serial Bus Controller Registers (Function 2) Offset 8 - Revision ID (nnh) .............................................. RO 7-0 Silicon Revision Code (0 indicates first silicon) This USB host controller interface is fully compatible with UHCI specification v1.1. There are two sets of software Offset 9 - Programming Interface (00h) .......................... RO accessible registers: PCI configuration registers and USB I/O registers. The PCI configuration registers are located in the Offset A - Sub Class Code (03h) ....................................... RO function 2 PCI configuration space of the VT82C586B. The USB I/O registers are defined in the UHCI v1.1 specification. Offset B - Base Class Code (0Ch) ..................................... RO Offset 0D - Latency Timer ............................................... RW PCI Configuration Space Header 7-0 Timer Value ..........................................default = 16h Offset 1-0 - Vendor ID ....................................................... RO Offset 0E - Header Type (00h) .......................................... RO 0-7 Vendor ID ................. (1106h = VIA Technologies) Offset 23-20 - USB I/O Register Base Address ............... RW Offset 3-2 - Device ID ......................................................... RO 31-16 Reserved ........................................always reads 0 0-7 Device ID (3038h = VT82C586B USB Controller) 15-5 USB I/O Register Base Address. Port Address for the base of the 32-byte USB I/O Register block, Offset 5-4 - Command ....................................................... RW corresponding to AD[15:5] 15-8 Reserved ........................................ always reads 0 4-0 00001b 7 Address Stepping ...................... default=0 (disabled) 6 Reserved (parity error response) ..................fixed at 0 Offset 3C - Interrupt Line (00h) ...................................... RW 5 Reserved (VGA palette snoop) ....................fixed at 0 7-4 Reserved ........................................always reads 0 4 Memory Write and Invalidate . default=0 (disabled) 3-0 USB Interrupt Routing ........................default = 16h 3 Reserved (special cycle monitoring) ............fixed at 0 0000 Disabled................................................. default 2 Bus Master ............................... default=0 (disabled) 0001 IRQ1 1 Memory Space........................... default=0 (disabled) 0010 Reserved 0 I/O Space ............................... default=0 (disabled) 0011 IRQ3 0100 IRQ4 Offset 7-6 - Status ........................................................... RWC 0101 IRQ5 15 Reserved (detected parity error).......... always reads 0 0110 IRQ6 14 Signalled System Error.............................. default=0 0111 IRQ7 13 Received Master Abort.............................. default=0 1000 IRQ8 12 Received Target Abort .............................. default=0 1001 IRQ9 11 Signalled Target Abort.............................. default=0 1010 IRQ10 10-9 DEVSEL# Timing 1011 IRQ11 00 Fast 1100 IRQ12 01 Medium ......................................default (fixed) 1101 IRQ13 10 Slow 1110 IRQ14 11 Reserved 1111 IRQ15 (see note below) ........................................ always reads 0 8-0 Reserved Note: Some software incorrectly sets this register to 0FFh to disable USB interrupts. A value of 0FFh will program the USB interrupt to interrupt controller channel 15 and cause the secondary IDE channel to work improperly. Offset 3D - Interrupt Pin (04h) ......................................... RO Revision 1.0 May 13, 1997 -38- Register Descriptions �9,$�7HFKQRORJLHV��,QF� VT82C586B USB-Specific Configuration Registers USB I/O Registers These registers are compliant with the UHCI v1.1 standard. Offset 40 - Miscellaneous Control 1 ................................. RW Refer to the UHCI v1.1 specification for further details. 7 PCI Memory Command Option 0 Support Memory-Read-Line, Memory-Read- Offset 1-0 - USB Command Multiple, and Memory-Write-and-Invalidate .... .....................................................default Offset 3-2 - USB Status 1 Only support Memory Read, Memory Write Commands Offset 5-4 - USB Interrupt Enable 6 Babble Option Offset 7-6 - Frame Number 0 Automatically disable babbled port when EOF babble occurs..........................................default Offset B-8 - Frame List Base Address 1 Don’t disable babbled port 5 PCI Parity Check Option Offset 0C - Start Of Frame Modify 0 Disable PERR# generation.....................default 1 Enable parity check and PERR# generation Offset 11-10 - Port 1 Status / Control 4 Reserved ........................................ always reads 0 3 USB Data Length Option Offset 13-12 - Port 2 Status / Control 0 Support TD length up to 1280................default 1 Support TD length up to 1023 Offset 1F-14 - Reserved 2 USB Power Management 0 Disable USB power management...........default 1 Enable USB power management 1 DMA Option 0 16 DW burst access................................default 1 8 DW burst access 0 PCI Wait States 0 Zero wait ................................................default 1 One wait Offset 41 - Miscellaneous Control 2 ................................. RW 7-3 Reserved ........................................ always reads 0 2 Trap Option 0 Set trap 60/64 status bits without checking enable bits ..............................................default 1 Set trap 60/64 status bits only when trap 60/64 enable bits are set. 1 A20gate Pass Through Option 0 Pass through A20GATE command sequence defined in UHCI.....................................default 1 Don’t pass through Write I/O port 64 (ff) 0 Reserved ........................................ always reads 0 Offset 60 - Serial Bus Release Number ............................. RO 7-0 Release Number.............................. always reads 10h Offset C1-C0 - Legacy Support ......................................... RO 15-0 UHCI v1.1 Compliant................ always reads 2000h Revision 1.0 May 13, 1997 -39- Register Descriptions �9,$�7HFKQRORJLHV��,QF� VT82C586B Power Management Registers (Function 3) This section describes the ACPI (Advanced Configuration and Power Interface) Power Management system of the VT82C586B. This system supports both ACPI and legacy power management functions and is compatible with the APM v1.2 and ACPI v0.9 specifications. PCI Configuration Space Header Offset 1-0 - Vendor ID ....................................................... RO Offset 8 - Revision ID (nnh) .............................................. RO 0-7 Vendor ID ................. (1106h = VIA Technologies) 7-4 Silicon Version Code 0 OEM Version ("3040 Silicon") Offset 3-2 - Device ID ......................................................... RO 1 Production Version ("3041 Silicon") 0-7 Device ID ................(3040h = ACPI Power Mgmt) 2-F -reserved for future use- 3-0 Silicon Revision Code Offset 5-4 - Command ....................................................... RW OEM Version 15-8 Reserved ........................................ always reads 0 0 Revision E ("3040E") 7 Address Stepping ........................................fixed at 0 1 Revision F ("3040F") 6 Reserved (parity error response) ..................fixed at 0 2-F -reserved for future use- 5 Reserved (VGA palette snoop) ....................fixed at 0 Production Version 4 Memory Write and Invalidate ...................fixed at 0 0 Revision A ("3041" or "3041A") (special cycle monitoring) ............fixed at 0 3 Reserved 1-F -reserved for future use- 2 Bus Master .................................................fixed at 0 Programming and pin differences between the above silicon 1 Memory Space.............................................fixed at 0 versions and revisions are indicated in this document in the 0 I/O Space .................................................fixed at 0 appropriate section. Marking specifications corresponding to 0 Disable ........ always reads 0 in 3040F and later the above versions and revisions are also included in the 1 Enable Mechanical Specifications section of this document. Note: In 3040E and earlier silicon, this bit could be set to 1 to allow access to the Power Management I/O Offset 9 - Programming Interface (00h) .......................... RO Register Block (the quadword at offset 20 was used in The value returned by this register may be changed by writing that silicon to set the base address for this register the desired value to PCI Configuration Function 3 offset 61h. block). Beginning with 3040F silicon, the function of this bit was moved to offset 41 bit-7 and the base Offset A - Sub Class Code (00h) ....................................... RO address register for the PM I/O register block was The value returned by this register may be changed by writing moved from to offset 48. the desired value to PCI Configuration Function 3 offset 62h. Offset 7-6 - Status ........................................................... RWC Offset B - Base Class Code (00h) ...................................... RO 15 Detected Parity Error........................ always reads 0 The value returned by this register may be changed by writing 14 Signalled System Error...................... always reads 0 the desired value to PCI Configuration Function 3 offset 63h. 13 Received Master Abort...................... always reads 0 12 Received Target Abort ...................... always reads 0 Offset 0D - Latency Timer ............................................... RW 11 Signalled Target Abort...................... always reads 0 10-9 DEVSEL# Timing 7-0 Timer Value ..........................................default = 16h 00 Fast Offset 0E - Header Type (00h) .......................................... RO 01 Medium .....................................default (fixed) 10 Slow Offset 23-20 - I/O Register Base Address (3040E only) . RW 11 Reserved 31-16 Reserved ........................................always reads 0 8 Data Parity Detected.......................... always reads 0 15-8 Power Management I/O Register Base Address. 7 Fast Back to Back .............................. always reads 1 Port Address for the base of the 256-byte Power 6-0 Reserved ........................................ always reads 0 Management I/O Register block, corresponding to AD[15:8]. The "I/O Space" bit at offset 5-4 bit-0 enables access to this register block. 7-0 00000001b Revision 1.0 May 13, 1997 -40- Register Descriptions �9,$�7HFKQRORJLHV��,QF� VT82C586B Power Management-Specific PCI Configuration Registers Offset 45-44 - Primary Interrupt Channel (0000h) ....... RW 15 1/0 = Ena/Disa IRQ15 as Primary Intrpt Channel 14 1/0 = Ena/Disa IRQ14 as Primary Intrpt Channel Offset 40 - Pin Configuration (C0h) ................................ RW 13 1/0 = Ena/Disa IRQ13 as Primary Intrpt Channel 7 GPIO4 Configuration 12 1/0 = Ena/Disa IRQ12 as Primary Intrpt Channel 0 Define pin 136 as GPO_WE 11 1/0 = Ena/Disa IRQ11 as Primary Intrpt Channel 1 Define pin 136 as GPIO4 .......................default 10 1/0 = Ena/Disa IRQ10 as Primary Intrpt Channel 6 GPIO3 Configuration 9 1/0 = Ena/Disa IRQ9 as Primary Intrpt Channel 0 Define pin 92 as GPI_RE# 8 1/0 = Ena/Disa IRQ8 as Primary Intrpt Channel 1 Define pin 92 as GPIO4 .........................default 7 1/0 = Ena/Disa IRQ7 as Primary Intrpt Channel 5-0 Reserved ........................................ always reads 0 6 1/0 = Ena/Disa IRQ6 as Primary Intrpt Channel Offset 41 - General Configuration (00h) ......................... RW 5 1/0 = Ena/Disa IRQ5 as Primary Intrpt Channel 4 1/0 = Ena/Disa IRQ4 as Primary Intrpt Channel 7 3040E and earlier: Reserved 3 1/0 = Ena/Disa IRQ3 as Primary Intrpt Channel 7 3040F and later: I/O Enable for ACPI I/O Base 2 Reserved ........................................always reads 0 0 Disable access to ACPI I/O block ..........default 1 1/0 = Ena/Disa IRQ1 as Primary Intrpt Channel 1 Allow access to Power Management I/O 0 1/0 = Ena/Disa IRQ0 as Primary Intrpt Channel Register Block (see offset 4B-48 to set the base address for this register block). The Offset 47-46 - Secondary Interrupt Channel (0000h) .... RW definitions of the registers in the Power 15 1/0 = Ena/Disa IRQ15 as Secondary Intr Channel Management I/O Register Block are included 14 1/0 = Ena/Disa IRQ14 as Secondary Intr Channel later in this document, following the Power 13 1/0 = Ena/Disa IRQ13 as Secondary Intr Channel Management Subsystem overview. 12 1/0 = Ena/Disa IRQ12 as Secondary Intr Channel 6 ACPI Timer Reset 11 1/0 = Ena/Disa IRQ11 as Secondary Intr Channel 0 Disable ...................................................default 10 1/0 = Ena/Disa IRQ10 as Secondary Intr Channel 1 Enable 9 1/0 = Ena/Disa IRQ9 as Secondary Intr Channel 5-4 Reserved (Do Not Program)...................... default = 0 8 1/0 = Ena/Disa IRQ8 as Secondary Intr Channel 3 ACPI Timer Count Select 7 1/0 = Ena/Disa IRQ7 as Secondary Intr Channel 0 24-bit Timer ...........................................default 6 1/0 = Ena/Disa IRQ6 as Secondary Intr Channel 1 32-bit Timer 5 1/0 = Ena/Disa IRQ5 as Secondary Intr Channel 2 PCI Frame Activation in C2 as Resume Event 4 1/0 = Ena/Disa IRQ4 as Secondary Intr Channel 0 Disable ...................................................default 3 1/0 = Ena/Disa IRQ3 as Secondary Intr Channel 1 Enable 2 Reserved ........................................always reads 0 1 Clock Throttling Clock Selection 1 1/0 = Ena/Disa IRQ1 as Secondary Intr Channel 0 32 usec (512 usec cycle time).................default 0 1/0 = Ena/Disa IRQ0 as Secondary Intr Channel 1 1 msec (16 msec cycle time) 0 Reserved (Do Not Program)...................... default = 0 Offset 4B-48 - I/O Register Base Address (3040F and later silicon; see Offset 23-20 for 3040E and earlier) ............ RW Offset 42 - SCI Interrupt Configuration (00h) ............... RW 31-16 Reserved ........................................always reads 0 7-4 Reserved ........................................ always reads 0 15-8 Power Management I/O Register Base Address. 3-0 SCI Interrupt Assignment Port Address for the base of the 256-byte Power 0000 Disabled .................................................default Management I/O Register block, corresponding to 0001 IRQ1 AD[15:8]. The "I/O Space" bit at offset 41 bit-7 0010 Reserved (offset 5-4 bit-0 in 3040E and earlier silicon) enables 0011 IRQ3 access to this register block. The definitions of the 0100 IRQ4 registers in the Power Management I/O Register 0101 IRQ5 Block are included later in this document, following 0110 IRQ6 the Power-Management-Specific PCI Configuration 0111 IRQ7 register descriptions and the Power Management 1000 IRQ8 Subsystem overview. 1001 IRQ9 7-0 00000001b 1010 IRQ10 1011 IRQ11 1100 IRQ12 1101 IRQ13 1110 IRQ14 1111 IRQ15 Revision 1.0 May 13, 1997 -41- Register Descriptions �9,$�7HFKQRORJLHV��,QF� VT82C586B Offset 53-50 - GP Timer Control (0000 0000h) .............. RW 3 GP0 Timer Start On setting this bit to 1, the GP0 timer loads the value 31-30 Conserve Mode Timer Count Value defined by bits 15-8 of this register and starts 00 1/16 second ............................................default counting down. The GP0 timer is reloaded at the 01 1/8 second occurrence of certain peripheral events enabled in the 10 1 second GP Timer Reload Enable Register (Power 11 1 minute Management I/O Space Offset 38h). If no such event 29 Conserve Mode Status occurs and the GP0 timer counts down to zero, then This bit reads 1 when in Conserve Mode the GP0 Timer Timeout Status bit is set to one (bit-2 28 Conserve Mode Enable of the Global Status register at Power Management Set to 1 to enable Conserve Mode (not used in Register I/O Space Offset 28h). Additionally, if the desktop applications). GP0 Timer Timeout Enable bit is set (bit-2 of the Global Enable register at Power Management 27-26 Secondary Event Timer Count Value Register I/O Space Offset 2Ah), then an SMI is 00 2 milliseconds.........................................default generated. 01 64 milliseconds 2 GP0 Timer Automatic Reload 10 ½ second This bit is set to one to enable the GP0 timer to reload 11 by EOI + 0.25 milliseconds automatically after counting down to 0. 25 Secondary Event Occurred Status 1-0 GP0 Timer Base This bit reads 1 to indicate that a secondary event has 00 Disable................................................... default occurred (to resume the system from suspend) and the 01 1/16 second secondary event timer is counting down. 10 1 second 24 Secondary Event Timer Enable 11 1 minute 0 Disable ...................................................default 1 Enable Offset 61 - Programming Interface Read Value ............ WO 7-0 Rx09 Read Value 23-16 GP1 Timer Count Value (base defined by bits 5-4) The value returned by the register at offset 9h (Programming Interface) may be changed by writing the desired value to this 15-8 GP0 Timer Count Value (base defined by bits 1-0) location. 7 GP1 Timer Start Offset 62 - Sub Class Read Value .................................... WO On setting this bit to 1, the GP1 timer loads the value 7-0 Rx0A Read Value defined by bits 23-16 of this register and starts The value returned by the register at offset 0Ah (Sub Class counting down. The GP1 timer is reloaded at the Code) may be changed by writing the desired value to this occurrence of certain peripheral events enabled in the location. GP Timer Reload Enable Register (Power Management I/O Space Offset 38h). If no such event Offset 63 - Base Class Read Value ................................... WO occurs and the GP1 timer counts down to zero, then the GP1 Timer Timeout Status bit is set to one (bit-3 7-0 Rx0B Read Value of the Global Status register at Power Management The value returned by the register at offset 0Bh (Base Class Register I/O Space Offset 28h). Additionally, if the Code) may be changed by writing the desired value to this GP1 Timer Timeout Enable bit is set (bit-3 of the location. Global Enable register at Power Management Register I/O Space Offset 2Ah), then an SMI is generated. 6 GP1 Timer Automatic Reload This bit is set to one to enable the GP1 timer to reload automatically after counting down to 0. 5-4 GP1 Timer Base 00 Disable ...................................................default 01 32 usec 10 1 second 11 1 minute Revision 1.0 May 13, 1997 -42- Register Descriptions �9,$�7HFKQRORJLHV��,QF� VT82C586B Power Management Subsystem Overview Power Plane Management The power management function of the VT82C586B is There are three power planes inside the VT82C586B. The indicated in the following block diagram: scheme is optimal for systems with ATX power supplies, although it also works using non-ATX power supplies. The *3 key feature of the ATX power supply is that two sets of power ’HYLFH 60,(YHQWV sources are available: the first set is always on unless turned,GOH 6&,60,(YHQWV 7LPHUoff by the mechanical switch. Only one voltage (5V) is :DNHXS(YHQWV available for this set. The second set includes the normal 5V3ULPDU\ (YHQWVand 12V and is controlled by an input signal PWRON as well as the mechanical switch. This set of voltages is available only *3 when both the mechanical switch is on and the PWRON signal *OREDO is high. The power planes powered by the above two sets of6WDQGE\ 6&,B(160,$UELWHU60, 7LPHUsupplies are referred to as VDD-5VSB and VDD-5V (also called VDD5), respectively. In addition to the two power 3:5%718VHU’HF planes, a third plane is powered by the combination of 5VSB,QWHUIDFH6&,$UELWHU*3,26&, and VBAT for the integrated real time clock. Most of the 6OHHS:DNHcircuitry inside the VT82C586B is powered by VDD-5V. The%XV 6WDWH 0DVWHUamount of logic powered by VDD-5VSB is very small and 0DFKLQH remains functional as long as the mechanical switch of the 5, &38+DUGZDUHpower supply is turned on. The main function of this logic is 673&/.(YHQWV86%to control the power supply of the VDD-5V plane. &RQWUROUHVXPH 57& 3RZHU General Purpose I/O Ports 3ODQH307LPHU &RQWUROAs ACPI compliant hardware, the VT82C586B includes /HJDF\2QO\(YHQW/RJLFPWRBTN# (pin 91) and RI# (pin 93) pins to implement power $&3,/HJDF\(YHQW/RJLFbutton and ring indicator functionality. In addition, a PWRON $&3,/HJDF\*HQHULF&RQWURO)HDWXUHVpin (pin 107) is also available to control the VDD-5V power $&3,/HJDF\)L[HG&RQWURO)HDWXUHVplane by VDD-5VSB powered logic. Furthermore, the $&3,2QO\(YHQW/RJLFVT82C586B offers many general purpose I/O ports with the following capabilities: 2 • I C support Figure 4. Power Management Subsystem Block Diagram • Three GPIO ports without external logic in addition to 2 2 the I C port. Five GPIO ports are available if I C Refer to ACPI Specification v0.9 and APM specification v1.2 functionality is not used. Every port can be used inputs, for additional information. outputs or I/O with external SCI/SMI capabilities. • Sixteen GPI and sixteen GPO pins using external buffers (244 buffers for input and 373 latches for output). Pins 87, 88 and 94 of the VT82C586B are dedicated general purpose I/O pins that can be used as inputs, outputs or I/O with external SMI capability. In particular, pins 87 and 88 can be 2 used to implement a software-implemented I C port for system configuration and general purpose peripheral communication. Pins 92 and 136 can be configured either as dedicated general purpose I/O pins or as control signals for external buffers for implementing up to sixteen GPI and sixteen GPO ports. The GPI and GPO ports are connected to the SD15-8 and XD7-0. The configuration is determined in the GPIO4_CFG and CPIO3_CFG bits of the PIN_CFG register: GPIO4_CFG: default to 1 to define pin 136 as GPIO4; set to 0 to redefine the pin as GPO_WE latch enable. GPIO3_CFG: default to 1 to define pin 92 as GPIO3; set to 0 to redefine the pin as GPI_RE# buffer enable. Revision 1.0 May 13, 1997 -43- Register Descriptions �9,$�7HFKQRORJLHV��,QF� VT82C586B Power Management Events Three types of power management events are supported: The VT82C586B allows the following events to wake up the system from the two suspend states and from the C2 state to 1) ACPI-required Fixed Events defined in the PM1a_STS the normal working state (processor in C0 state): and PM1a_EN registers. These events can trigger either SCI or SMI depending on the SCI_EN bit: • Activation of External Inputs: PWRBTN#, RI#, GPIO0 and other EXTSMI pins (see table below) • PWRBTN# Triggering • RTC Alarm and ACPI Power Management Timer (see • RTC Alarm table below) • ACPI Power Management Timer Carry (always SCI) • (see table below) USB Resume Event • BIOS Release (always SCI) • Interrupt Events (always resume independent of any 2) ACPI-aware General Purpose Function Events defined register setting) in the GP_STS and GP_SCI_EN, and GP_SMI_EN • ISA Master or DMA Events (always resume registers. These events can trigger either SCI or SMI independent of any register setting) depending on the setting of individual SMI and SCI enable bits: The VT82C586B also provides very flexible SCI/SMI steering and the PWRON control for these events: • EXTSMI triggering (refer to Table 2) • USB Resume Table 6. SCI/SMI/Resume Control for PM Events • RI# Indicator 3) defined in the GBL_STS and Event Global Individual Separate Generic Global Events SCI/SMI Enable Bits Control for GBL_EN registers. These registers are mainly used for Control for SCI & PWRON SMI: SMI Resume • GP0 and GP1 Timer Time Out PWRBTN# SCI_EN bit N Y • Secondary Event Timer Time Out RI# N YY • Occurrence of Primary Events RTC Alarm N Y N (defined in register PACT_STS and PACT_EN) GPIO0 N YY • Legacy USB accesses (keyboard and mouse). (EXTSMI0) Once enabled, each of the EXTSMI inputs triggers an SCI or External SCI/SMI N Y N SMI at either the rising or the falling transition of the (non-GPIO0) corresponding input pin signal. Software can check the status ACPI PM Timer Always SCI N N of the input pins via register EXTSMI_VAL and take proper USB Resume N N Y actions. Please refer to the table below on the availability of resume Among many possible actions, the SCI and SMI routine can events in each type of suspend state. change the processor state by programming the P_BLK registers. The routine can also set the SLP_EN bit to put the Table 7. Suspend Resume Events and Conditions system into one of the two suspend states: Input Trigger Power Plane Soft Off Power-On 1) Suspend to Disk (or Soft-Off): The VDD-5V power Suspend plane is turned off while VDD-5VSB and VDD-RTC PWRBTN# VDD-5VSB Y Y planes remain on. RI# VDD-5VSB Y Y 2) Power-On-Suspend: All power planes remain on but the RTC Alarm VBAT Y Y processor is put in the C3 state. GPIO0 VDD-5VSB Y Y In either suspend state, there is minimal interface between (EXTSMI0) powered and non-powered planes. External SCI/SMI VDD-5V N Y (non-GPIO0) ACPI PM Timer VDD-5V N Y USB Resume VDD-5V N Y PCI/ISA VDD-5V NN Interrupts PCI/ISA VDD-5V NN Master/DMA Revision 1.0 May 13, 1997 -44- Register Descriptions �9,$�7HFKQRORJLHV��,QF� VT82C586B Legacy Power Management Timers enabled, the occurrence of the primary event reloads the GP0 timer if the PACT_GP0_EN bit is also set to 1. The cause of In addition to the ACPI power management timer, the the timer reload is recorded in the corresponding bit of VT82C586B includes the following four legacy power PRI_ACT_STS register while the timer is reloaded. If no management timers: enabled primary event occurs during the count down, the GP0 GP0 Timer: general purpose timer with primary event timer will time out (count down to 0) and the system can be GP1 Timer: general purpose timer with peripheral event programmed (setting the GP0TO_EN bit in the GBL_EN register to one) to trigger an SMI to switch the system to a reload power down mode. Secondary Event Timer: to monitor secondary events : not used in desktop applications The VT82C586B distinguishes two kinds of interrupt requests Conserve Mode Timer as far as power management is concerned: the primary and The normal sequence of operations for a general purpose timer secondary interrupts. Like other primary events, the (GP0 or GP1) is to occurrence of a primary interrupt demands that the system be 1) First program the time base and timer value of the initial restored to full processing capability. Secondary interrupts, count (register GP_TIM_CNT). however, are typically used for housekeeping tasks in the 2) Then activate counting by setting the GP0_START or background unnoticeable to the user. The VT82C586B allows GP1_START bit to one: the timer will start with the each channel of interrupt request to be declared as either initial count and count down towards 0. primary, secondary, or ignorable in the PIRQ_CH and 3) When the timer counts down to zero, an SMI will be SIRQ_CH registers. Secondary interrupts are the only system generated if enabled (GP0TO_EN and GP1TO_EN in the secondary events defined in the VT82C586B. GBL_EN register) with status recorded (GP0TO_STS and Like primary events, primary interrupts can be made to reload GP1TO_STS in the GBL_STS register). the GP0 timer by setting the PIRQ_EN bit to 1. Secondary 4) Each timer can also be programmed to reload the initial interrupts do not reload the GP0 timer. Therefore the GP0 count and restart counting automatically after counting timer will time out and the SMI routine can put the system into down to 0. This feature is not used in standard VIA power down mode if no events other than secondary interrupts BIOS. are happening periodically in the background. The GP0 and GP1 timers can be used just as the general Primary events can be programmed to trigger an SMI (setting purpose timers described above. However, they can also be of the PACT_EN bit). Typically, this SMI triggering is turned programmed to reload the initial count by system primary off during normal system operation to avoid degrading system events or peripheral events thus used as primary event (global performance. Triggering is turned on by the SMI routine standby) timer and peripheral timer, respectively. The before entering the power down mode so that the system may secondary event timer is solely used to monitor secondary be returned to normal operation at the occurrence of primary events. events. At the same time, the GP0 timer is reloaded and the count down process is restarted. System Primary and Secondary Events Peripheral Events Primary system events are distinguished in the PRI_ACT_STS and PRI_ACT_EN registers: Primary and secondary events define system events in general Bit Event Trigger and the response is typically expressed in terms of system 7 Keyboard Access I/O port 60h events. Individual peripheral events can also be monitored by 6 Serial Port Access I/O ports 3F8h-3FFh, 2F8h-2FFh, the VT82C586B through the GP1 timer. The following four 3E8h-3EFh, or 2E8h-2EFh categories of peripheral events are distinguished (via register 5 Parallel Port Access I/O ports 378h-37Fh or 278h-27Fh GP_RLD_EN): 4 I/O ports 3B0h-3DFh or memory Video Access Bit-7 Keyboard Access A/B segments Bit-6 Serial Port Access 3 IDE/Floppy Access I/O ports 1F0h-1F7h, 170h-177h, Bit-4 Video Access or 3F5h Bit-3 IDE/Floppy Access 2 Reserved The four categories are subsets of the primary events as 1 Primary Interrupts Each channel of the interrupt defined in PRI_ACT_EN and the occurrence of these events controller can be programmed to can be checked through a common register PRI_ACT_STS. be a primary or secondary As a peripheral timer, GP1 can be used to monitor one (or interrupt more than one) of the above four device types by programming 0 ISA Master/DMA Activity the corresponding bit to one and the other bits to zero. Time Each category can be enabled as a primary event by setting the out of the GP1 timer indicates no activity of the corresponding corresponding bit of the PRI_ACT_EN register to 1. If device type and appropriate action can be taken as a result. Revision 1.0 May 13, 1997 -45- Register Descriptions �9,$�7HFKQRORJLHV��,QF� VT82C586B Power Management I/O-Space Registers Basic Power Management Control and Status Offset 1-0 - Power Management Status ........................ RWC Offset 3-2 - Power Management Enable ......................... RW The bits in this register are set only by hardware and can be The bits in this register correspond to the bits in the Power reset by software by writing a one to the desired bit position. Management Status Register at offset 1-0. (WAK_STS) ................... default = 0 ........................................always reads 0 15 Wakeup Status 15 Reserved This bit is set when the system is in the suspend state and an enabled resume event occurs. Upon setting this bit, the system automatically transitions from the suspend state to the normal working state (from C3 to C0 for the processor). 14-12 Reserved ........................................ always reads 0 14-12 Reserved ........................................always reads 0 11 Power Button Override Status (PBOR_STS). def=0 11 Reserved ........................................always reads 0 This bit is set when the PWRBTN# input pin is continuously asserted for more than 4 seconds. The setting of this bit will reset the PB_STS bit and transition the system into the soft off state. 10 RTC Status (RTC_STS) ........................... default = 0 10 RTC Enable (RTC_EN)............................default = 0 This bit is set when the RTC generates an alarm (on This bit may be set to trigger either an SCI or an SMI (depending on the setting of the SCI_EN bit) to be assertion of the RTC IRQ signal). generated when the RTC_STS bit is set. 9 Reserved ........................................ always reads 0 9 Reserved ........................................always reads 0 8 Power Button Status (PB_STS)............... default = 0 8 Power Button Enable (PB_EN) ...............default = 0 This bit is set when the PWRBTN# signal is asserted This bit may be set to trigger either an SCI or an SMI LOW. If the PWRBTN# signal is held LOW for (depending on the setting of the SCI_EN bit) to be more than four seconds, this bit is cleared, the generated when the PB_STS bit is set. PBOR_STS bit is set, and the system will transition into the soft off state. ........................................always reads 0 7-6 Reserved ........................................ always reads 0 7-6 Reserved (GBL_STS)........................ default = 0 5 Global Enable (GBL_EN).........................default = 0 5 Global Status This bit is set by hardware when BIOS_RLS is set This bit may be set to trigger either an SCI or an SMI (typically by an SMI routine to release control of the (depending on the setting of the SCI_EN bit) to be SCI/SMI lock). When this bit is cleared by software generated when the GBL_STS bit is set. (by writing a one to this bit position) the BIOS_RLS bit is also cleared at the same time by hardware. 4 Bus Master Status (BM_STS) ................. default = 0 4 Reserved ........................................always reads 0 This bit is set when a system bus master requests the system bus. All PCI master, ISA master and ISA DMA devices are included. 3-1 Reserved ........................................ always reads 0 3-1 Reserved ........................................always reads 0 (TMR_EN) ..............default = 0 0 Timer Carry Status (TMR_STS)............. default = 0 0 ACPI Timer Enable rd This bit may be set to trigger either an SCI or an SMI The bit is set when the 23 (31st) bit of the 24 (32) (depending on the setting of the SCI_EN bit) to be bit ACPI power management timer changes. generated when the TMR_STS bit is set. Revision 1.0 May 13, 1997 -46- Register Descriptions �9,$�7HFKQRORJLHV��,QF� VT82C586B Offset 5-4 - Power Management Control ........................ RW Offset 0B-08 - Power Management Timer ...................... RW 15-14 Reserved ........................................ always reads 0 31-24 Extended Timer Value (ETM_VAL) This field reads back 0 if the 24-bit timer option is 13 Sleep Enable (SLP_EN)...................... always reads 0 This is a write-only bit; reads from this bit always selected (Rx41 bit-3). return zero. Writing a one to this bit causes the 23-0 Timer Value (TMR_VAL) This read-only field returns the running count of the system to sequence into the sleep (suspend) state power management timer. This is a 24/32-bit counter defined by the SLP_TYP field. that runs off a 3.579545 MHz clock, and counts while 12-10 Sleep Type (SLP_TYP) 000 Soft Off (also called Suspend to Disk). The in the S0 (working) system state. The timer is reset to an initial value of zero during a reset, and then VDD5 power plane is turned off while the continues counting until the 14.31818 MHz input to VDD-5VSB and VDD-RTC (VBAT) planes the chip is stopped. If the clock is restarted without a remain on. 010 Power On Suspend. All power planes remain reset, then the counter will continue counting from where it stopped. on but the processor is put into the C3 state. 0x1 Reserved 1xx Reserved In either sleep state, there is minimal interface between powered and non-powered planes so that the effort for hardware design may be well managed. 9-3 Reserved ........................................ always reads 0 2 Global Release (GBL_RLS) ..................... default = 0 This bit is set by ACPI software to indicate the release of the SCI / SMI lock. Upon setting of this bit, the hardware automatically sets the BIOS_STS bit. The bit is cleared by hardware when the BIOS_STS bit is cleared by software. Note that the setting of this bit will cause an SMI to be generated if the BIOS_EN bit is set (bit-5 of the Global Enable register at offset 2Ah). 1 Bus Master Reload (BMS_RLD)............. default = 0 This bit is used to enable the occurrence of a bus master request to transition the processor from the C3 state to the C0 state. 0 SCI Enable (SCI_EN)............................... default = 0 Selects the power management event to generate either an SCI or SMI: 0 Generate SMI 1 Generate SCI Note that certain power management events can be programmed individually to generate an SCI or SMI independent of the setting of this bit (refer to the General Purpose SCI Enable and General Purpose SMI Enable registers at offsets 22 and 24). Also, TMR_STS & GBL_STS always generate SCI and BIOS_STS always generates SMI. Revision 1.0 May 13, 1997 -47- Register Descriptions �9,$�7HFKQRORJLHV��,QF� VT82C586B Processor Power Management Registers Offset 13-10 - Processor Control ...................................... RW Offset 14 - Processor Level 2 (P_LVL2) .......................... RO 31-5 Reserved ........................................ always reads 0 7-0 Level 2 ........................................always reads 0 4 Throttling Enable (THT_EN). 3040 Silicon: Reads from this register put the 3040 Silicon: This bit determines the effect of processor in the C2 clock state if the Throttling reading the "Processor Level 2" (P_LVL2) port: Enable bit (Function 3 Rx10 bit-4) is set. 0 No clock throttling. Reads from the Processor 3041 Silicon: Reads from this register put the Level 2 register are ignored. processor into the Stop Clock state (the VT82C586B 1 Reading the "Processor Level 2" port enables asserts STPCLK# to suspend the processor). Wake clock throttling by modulating the STPCLK# up from Stop Clock state is by interrupt (INTR, SMI, signal with a duty cycle determined bits 3-1 of PWRBTN#, RTC wakeup, or pin toggle SCI). this register. Reads from this register return all zeros; writes to this register 3041 Silicon: Setting this bit starts clock throttling have no effect. (modulating the STPCLK# signal) regardless of the CPU state (i.e., it is not necessary to Offset 15 - Processor Level 3 (P_LVL3) .......................... RO read the "Processor Level 2" port to start clock 7-0 Level 3 ........................................always reads 0 throttling). The throttling duty cycle is Reads from this register put the processor in the C3 determined by bits 3-1 of this register. clock state with the STPCLK# signal asserted. 3041 3-1 Throttling Duty Cycle (THT_DTY) silicon: wake up from Stop Clock state is by This 3-bit field determines the duty cycle of the interrupt (INTR, SMI, PWRBTN#, RTC wakeup, or STPCLK# signal when the system is in throttling pin toggle SCI). mode (the "Throttling Enable" bit is set to one and, in Reads from this register return all zeros; writes to this register 3040 silicon, the "Processor Level 2" register is have no effect. read). The duty cycle indicates the percentage of time the STPCLK# signal is asserted while the Throttling Enable bit is set. The field is decoded as follows: 000 Reserved 001 0-12.5% 010 12.5-25% 011 25-37.5% 100 37.5-50% 101 50-62.5% 110 62.5-75% 111 75-87.5% 0 Reserved ........................................ always reads 0 Revision 1.0 May 13, 1997 -48- Register Descriptions �9,$�7HFKQRORJLHV��,QF� VT82C586B General Purpose Power Management Registers Offset 21-20 - General Purpose Status (GP_STS) ....... RWC Offset 23-22 - General Purpose SCI Enable ................... RW 15-10 Reserved ........................................ always reads 0 15-10 Reserved ........................................always reads 0 9 USB Resume Status (USB_STS) 9 Enable SCI on setting of the USB_STS bit ....def=0 This bit is set when a USB peripheral generates a 8 Enable SCI on setting of the RI_STS bit .......def=0 resume event. 7 Enable SCI on setting of the EXT7_STS bit ..def=0 8 Ring Status (RI_STS) 6 Enable SCI on setting of the EXT6_STS bit ..def=0 This bit is set when the RI# input is asserted low. 5 Enable SCI on setting of the EXT5_STS bit ..def=0 7 EXTSMI7 Toggle Status (EXT7_STS) 4 Enable SCI on setting of the EXT4_STS bit ..def=0 This bit is set when the EXTSMI7# pin is toggled. 3 Enable SCI on setting of the EXT3_STS bit ..def=0 6 EXTSMI6 Toggle Status (EXT6_STS) ..def=0 2 Enable SCI on setting of the EXT2_STS bit This bit is set when the EXTSMI6# pin is toggled. 1 Enable SCI on setting of the EXT1_STS bit ..def=0 5 EXTSMI5 Toggle Status (EXT5_STS) 0 Enable SCI on setting of the EXT0_STS bit ..def=0 This bit is set when the EXTSMI5# pin is toggled. These bits allow generation of an SCI using a separate set of 4 EXTSMI4 Toggle Status (EXT4_STS) conditions from those used for generating an SMI. This bit is set when the EXTSMI4# pin is toggled. 3 EXTSMI3 Toggle Status (EXT3_STS) Offset 25-24 - General Purpose SMI Enable .................. RW This bit is set when the EXTSMI3# pin is toggled. 15-10 Reserved ........................................always reads 0 2 EXTSMI2 Toggle Status (EXT2_STS) 9 Enable SMI on setting of the USB_STS bit ...def=0 This bit is set when the EXTSMI2# pin is toggled. 8 Enable SMI on setting of the RI_STS bit ......def=0 1 EXTSMI1 Toggle Status (EXT1_STS) 7 Enable SMI on setting of the EXT7_STS bit..def=0 This bit is set when the EXTSMI1# pin is toggled. 6 Enable SMI on setting of the EXT6_STS bit..def=0 0 EXTSMI0 Toggle Status (EXT0_STS) 5 Enable SMI on setting of the EXT5_STS bit..def=0 This bit is set when the EXTSMI0# pin is toggled. 4 Enable SMI on setting of the EXT4_STS bit..def=0 ..def=0 3 Enable SMI on setting of the EXT3_STS bit Note that the above bits correspond one for one with the bits 2 Enable SMI on setting of the EXT2_STS bit..def=0 of the General Purpose SCI Enable and General Purpose SMI 1 Enable SMI on setting of the EXT1_STS bit..def=0 Enable registers at offsets 22 and 24: an SCI or SMI is 0 Enable SMI on setting of the EXT0_STS bit..def=0 generated if the corresponding bit of the General Purpose SCI These bits allow generation of an SMI using a separate set of or SMI Enable registers, respectively, is set to one. conditions from those used for generating an SCI. The above bits are set by hardware only and can only be Offset 27-26 - Power Supply Control .............................. RW cleared by writing a one to the desired bit. 15-11 Reserved ........................................always reads 0 10 Ring PS Control (RI_PS_CTL) ......................def=0 This bit enables the setting of the RI_STS bit to turn on the VDD_5V power plane by setting PWRON = 1. ..................def=1 9 Power Button Control (PB_CTL) This bit is used to control the setting of the PB_STS bit to resume the system from suspend (turn on the VDD_5V power plane by setting PWRON = 1). 8 RTC PS Control (RTC_PS_CTL) ..................def=0 This bit enables the setting of the RTC_STS bit to resume the system from suspend (turn on the VDD_5V power plane by setting PWRON = 1). 7-1 Reserved ........................................always reads 0 0 EXTSMI0 Toggle PS Control (E0_PS_CTL) def=0 This bit enables the setting of the EXT0_STS bit to resume the system from suspend (turn on the VDD_5V power plane by setting PWRON = 1). Revision 1.0 May 13, 1997 -49- Register Descriptions �9,$�7HFKQRORJLHV��,QF� VT82C586B Generic Power Management Registers Offset 29-28 - Global Status .......................................... RWC Offset 2B-2A - Global Enable .......................................... RW 15-7 Reserved ........................................ always reads 0 15-7 Reserved ........................................always reads 0 6 Software SMI Status (SW_SMI_STS)............ def=0 6 Software SMI Enable (SW_SMI_EN) ............def=0 This bit is set when the SMI_CMD port (offset 2F) is This bit may be set to trigger an SMI to be generated written. when the SW_SMI_STS bit is set. 5 BIOS Status (BIOS_STS) ................................ def=0 5 BIOS Enable (BIOS_EN).................................def=0 This bit is set when the GBL_RLS bit is set to one This bit may be set to trigger an SMI to be generated (typically by the ACPI software to release control of when the BIOS_STS bit is set. the SCI/SMI lock). When this bit is reset (by writing a one to this bit position) the GBL_RLS bit is reset at the same time by hardware. 4 Legacy USB Status (LEG_USB_STS) ............ def=0 4 Legacy USB Enable (LEG_USB_EN).............def=0 This bit is set when a legacy USB event occurs. This bit may be set to trigger an SMI to be generated when the LEG_USB_STS bit is set. 3 GP1 Timer Time Out Status (GP1TO_STS).. def=0 3 GP1 Timer Time Out Enable (GP1TO_EN) ..def=0 This bit is set when the GP1 timer times out. This bit may be set to trigger an SMI to be generated when the GP1TO_STS bit is set. 2 GP0 Timer Time Out Status (GP0TO_STS).. def=0 2 GP0 Timer Time Out Enable (GP0TO_EN) ..def=0 This bit is set when the GP0 timer times out. This bit may be set to trigger an SMI to be generated when the GP0TO_STS bit is set. 1 Secondary Event Timer Time Out Status 1 Secondary Event Timer Time Out Enable (STTO_STS).....................................................def=0 (STTO_EN)......................................................def=0 This bit is set when the secondary event timer times This bit may be set to trigger an SMI to be generated out. when the STTO_STS bit is set. 0 Primary Activity Status (PACT_STS)............ def=0 0 Primary Activity Enable (PACT_EN) ............def=0 This bit is set at the occurrence of any enabled This bit may be set to trigger an SMI to be generated primary system activity (see the Primary Activity when the PACT_STS bit is set. Detect Status register at offset 30h and the Primary Activity Detect Enable register at offset 34h). After checking this bit, software can check the status bits in the Primary Activity Detect Status register at offset 30h to identify the specific source of the primary event. Note that setting this bit can be enabled to reload the GP0 timer (see bit-0 of the GP Timer Reload Enable register at offset 38). Note that SMI can be generated based on the setting of any of the above bits (see the offset 2Ah Global Enable register bit descriptions in the right hand column of this page). The bits in this register are set by hardware only and can only be cleared by writing a one to the desired bit position. Revision 1.0 May 13, 1997 -50- Register Descriptions �9,$�7HFKQRORJLHV��,QF� VT82C586B Offset 2D-2C - Global Control (GBL_CTL) ................... RW Offset 2F - SMI Command (SMI_CMD) ............. 3041: RW 15-9 Reserved ........................................ always reads 0 ............... 3040: WO, always reads 0 (Read at Func 3 Rx47) 8 SMI Active (INSMI) 7-0 SMI Command 0 SMI Inactive...........................................default Writing to this port sets the SW_SMI_STS bit. Note 1 SMI Active. If the SMIIG bit is set, this bit that if the SW_SMI_EN bit is set (see bit-6 of the needs to be written with a 1 to clear it before Global Enable register at offset 2Ah), then an SMI is the next SMI can be generated. generated. 7-5 Reserved ........................................ always reads 0 4 SMI Lock (SMIIG) 0 Disable SMI Lock ..................................default 1 Enable SMI Lock (SMI low to gate for the next SMI). 3 Reserved ........................................ always reads 0 2 Power Button Triggering 0 SCI/SMI generated by PWRBTN# low level 1 SCI/SMI generated by PWRBTN# rising edge Set to one to avoid the situation where PB_STS is set to wake up the system then reset again by PBOR_STS to switch the system into the soft-off state. Must be set to 0 for ACPI v0.9 compliance. 1 BIOS Release (BIOS_RLS) This bit is set by legacy software to indicate release of the SCI/SMI lock. Upon setting of this bit, hardware automatically sets the GBL_STS bit. This bit is cleared by hardware when the GBL_STS bit cleared by software. Note that if the GBL_EN bit is set (bit-5 of the Power Management Enable register at offset 2), then setting this bit causes an SCI to be generated (because setting this bit causes the GBL_STS bit to be set). 0 SMI Enable (SMI_EN) 0 Disable all SMI generation 1 Enable SMI generation Revision 1.0 May 13, 1997 -51- Register Descriptions �9,$�7HFKQRORJLHV��,QF� VT82C586B Offset 33-30 - Primary Activity Detect Status ............. RWC Offset 37-34 - Primary Activity Detect Enable............... RW These bits correspond to the Primary Activity Detect Enable These bits correspond to the Primary Activity Detect Status bits in offset 37-34. bits in offset 33-30. 31-8 Reserved ..........................................always read 0 31-8 Reserved ......................................... always read 0 7 Keyboard Controller Access Status..... (KBC_STS) 7 Keyboard Controller Status Enable ..... (KBC_EN) Set if the keyboard controller is accessed via I/O port 0 Don't set PACT_STS if KBC_STS is set..... def 60h. 1 Set PACT_STS if KBC_STS is set 6 Serial Port Access Status ....................... (SER_STS) 6 Serial Port Status Enable........................ (SER_EN) Set if the serial port is accessed via I/O ports 3F8- 0 Don't set PACT_STS if SER_STS is set...... def 3FFh, 2F8-2FFh, 3E8-3EFh, or 2E8-2Efh (COM1-4, 1 Set PACT_STS if SER_STS is set respectively). 5 Parallel Port Access Status....................(PAR_STS) 5 Parallel Port Status Enable ....................(PAR_EN) Set if the parallel port is accessed via I/.O ports 278- 0 Don't set PACT_STS if PAR_STS is set ..... def 27Fh or 378-37Fh (LPT2 or LPT1). 1 Set PACT_STS if PAR_STS is set 4 Video Access Status.................................(VID_STS) 4 Video Status Enable .................................(VID_EN) Set if the video port is accessed via I/O ports 3B0- 0 Don't set PACT_STS if VID_STS is set...... def 3DFh or memory space A0000-BFFFFh. 1 Set PACT_STS if VID_STS is set 3 IDE / Floppy Access Status ....................(IDE_STS) 3 IDE / Floppy Status Enable .....................(IDE_EN) Set if the IDE or floppy devices are accessed via I/O 0 Don't set PACT_STS if IDE_STS is set ...... def ports 1F0-1F7h, 170-177h or 3F5h. 1 Set PACT_STS if IDE_STS is set 2 Reserved ............................................... default=0 2 Reserved .................................................... default 1 Primary Interrupt Activity Status......(PIRQ_STS) 1 Primary INTR Status Enable ............... (PIRQ_EN) Set on the occurrence of a primary interrupt (enabled 0 Don't set PACT_STS if PIRQ_STS is set.... def via the "Primary Interrupt Channel" register at 1 Set PACT_STS if PIRQ_STS is set Function 3 PCI configuration register offset 44h). 0 ISA Master / DMA Activity Status...... (DRQ_STS) 0 ISA Master / DMA Status Enable......... (DRQ_EN) Set on the occurrence of ISA master or DMA activity. 0 Don't set PACT_STS if DRQ_STS is set .... def 1 Set PACT_STS if DRQ_STS is set Note: The bits above correspond to the bits of the Primary Note: Setting of any of the above bits also sets the Activity Detect Enable register at offset 34 (see right PACT_STS bit (bit-0 of offset 28) which causes the hand column of this page): if the corresponding bit is GP0 timer to be reloaded (if PACT_GP0_EN is set) set in that register, setting of the above bits will cause or generates an SMI (if PACT_EN is set). the PACT_STS bit to be set (bit-0 of the Global Offset 3B-38 - GP Timer Reload Enable ......................... RW Status register at offset 28). Setting of PACT_STS All bits in this register default to 0 on power up. may be set up to enable a "Primary Activity Event": 31-8 Reserved ......................................... always read 0 an SMI will be generated if PACT_EN is set (bit-0 of 7 Enable GP1 Timer Reload on KBC Access the Global Enable register at offset 2Ah) and/or the 1 = setting of KBC_STS causes GP1 timer to reload. GP0 timer will be reloaded if the "GP0 Timer Reload 6 Enable GP1 Timer Reload on Serial Port Access on Primary Activity" bit is set (bit-0 of the GP Timer 1 = setting of SER_STS causes GP1 timer to reload. Reload Enable register at offset 38 on this page). 5 Reserved ......................................... always read 0 4 Enable GP1 Timer Reload on Video Access Note: Bits 3-7 above also correspond to bits 3-7 of the GP 1 = setting of VID_STS causes GP1 timer to reload. Timer Reload Enable register at offset 38 (see right 3 Enable GP1 Timer Reload on IDE/Floppy Access hand column of this page): if the corresponding bit is 1 = setting of IDE_STS causes GP1 timer to reload. set in that register, setting the bit in this register will 2-1 Reserved ......................................... always read 0 cause the GP1 timer to be reloaded. 0 Enable GP0 Timer Reload on Primary Activity 1 = setting of PACT_STS causes GP0 timer to reload. All bits of this register are set by hardware only and may only Primary activities are enabled via the Primary be cleared by writing a one to the desired bit. All bits default Activity Detect Enable register (offset 37-34) with to 0. status recorded in the Primary Activity Detect Status register (offset 33-30). Revision 1.0 May 13, 1997 -52- Register Descriptions �9,$�7HFKQRORJLHV��,QF� VT82C586B General Purpose I/O Registers Offset 40 - GPIO Direction Control (GPIO_DIR) .......... RW Offset 42 - GPIO Port Output Value (GPIO_VAL) ...... RW 7 Reserved ..........................................always read 0 7-5 Reserved ........................................always reads 0 6 SMI/SCI Event Disable on GPIO3/GPIO4 4 GPIO4_VAL 0 Enable GPIO3/GPIO4 to cause SCI/SMI Write output value for the GPIO4 pin if the port is Events.....................................................default available (GPIO4_CFG = 1 in PCI Config Register 1 GPIO3/GPIO4 will only cause SCI/SMI function 3 offset 40h). The input state of the GPIO4 Events during Power-On-Suspend (POS) mode pin may be read from register EXTSMI_VAL bit-4. 5 Interrupt Resume from Power-On Suspend 3 GPIO3_VAL 0 Enable (resume on interrupt from POS) ...... def Write output value for the GPIO3 pin if the port is 1 Disable (ignore interrupts during POS) available (GPIO3_CFG = 1 in PCI Config Register 4 GPIO4_DIR function 3 offset 40h). The input state of the GPIO3 0 Pin 136 is GPIO4 input ..........................default pin may be read from register EXTSMI_VAL bit-3. 1 Pin 136 is GPIO4 output (if Rx40 bit-7 = 1) 2 GPIO2_VAL If Rx40[7]=0 (PCI Configuration function 3 offset Write output value for the GPIO2 (I2CD2) pin. The 40h GPIO4_CFG bit), pin 136 is the GPO_WE input state of the GPIO2 pin may be read from output, independent of the state of this bit. register EXTSMI_VAL bit-2. 3 GPIO3_DIR 1 GPIO1_VAL 0 Pin 92 is GPIO3 input ............................default Write output value for the GPIO1 (I2CD1) pin. The 1 Pin 92 is GPIO3 output (if Rx40 bit-6 = 1) input state of the GPIO1 pin may be read from If Rx40[6]=0 (PCI Configuration function 3 offset register EXTSMI_VAL bit-1. 40h GPIO3_CFG bit), pin 92 is the GPI_RE# output, 0 GPIO0_VAL independent of the state of this bit. Write output value for the GPIO0 pin. The input 2 GPIO2_DIR state of the GPIO0 pin may be read from register 0 Pin 88 is GPIO2 / I2CD1 input ..............default EXTSMI_VAL bit-0. 1 Pin 88 is GPIO2 / I2CD1 output Offset 44 - GPIO Port Input Value (EXTSMI_VAL) ..... RO 1 GPIO1_DIR Depending on the configuration, up to 8 external SCI/SMI 0 Pin 87 is GPIO1 / I2CD2 input ..............default ports are available as indicated below. The state of these 1 Pin 87 is GPIO1 / I2CD2 output inputs may be read in this register. 0 GPIO0_DIR 0 Pin 94 is GPIO0 input ............................default 7 EXTSMI7# Input Value 1 Pin 94 is GPIO0 output GPIO3_CFG=0: EXTSMI7# on XD7 (pin 122) GPIO3_CFG=1: EXTSMI7# function not available 6 EXTSMI6# Input Value GPIO3_CFG=0: EXTSMI6# on XD6 (pin 121) GPIO3_CFG=1: EXTSMI6# function not available 5 EXTSMI5# Input Value GPIO3_CFG=0: EXTSMI5# on XD5 (pin 119) GPIO3_CFG=1: EXTSMI5# function not available 4 EXTSMI4# Input Value GPIO4_CFG=0: GPIO3_CFG=0: EXTSMI4# on XD4 (pin 118) GPIO3_CFG=1: EXTSMI4# function not avail GPIO4_CFG=1: EXTSMI4# on GPIO4 (pin 136) 3 EXTSMI3# Input Value GPIO3_CFG=0: EXTSMI3# on XD3 (pin 117) GPIO3_CFG=1: EXTSMI3# on GPIO3 (pin 92) 2 EXTSMI2# Input Value (on GPIO2 pin 88) 1 EXTSMI1# Input Value (on GPIO1 pin 87) (on GPIO0 pin 94) 0 EXTSMI0# Input Value Note: GPIO3_CFG and GPIO4_CFG are located in PCI Configuration Register function 3 offset 40h. Revision 1.0 May 13, 1997 -53- Register Descriptions �9,$�7HFKQRORJLHV��,QF� VT82C586B Offset 47-46 - GPO Port Output Value (GPO_VAL) ..... RW Offset 49-48 - GPI Port Input Value (GPI_VAL) ........... RO Reads from this register return the last value written (held on Reads from this register are ignored (and return a value of 0). chip). Input port value for the external 15-8 GPI15-8 Value. GPI port connected to SD15-8. This port is available 15-8 GPO15-8 Value. Output port value for the external only if the GPIO3_CFG bit is zero to define pin 92 as GPO port connected to SD15-8. This port is GPI_RE#. available only if the GPIO4_CFG bit is zero to define 7-0 GPI7-0 Value. Input port value for the external GPI pin 136 as GPO_WE. port connected to XD7-0. This port is available only 7-0 GPO7-0 Value. Output port value for the external if the GPIO3_CFG bit is zero to define pin 92 as GPO port connected to XD7-0. This port is available GPI_RE#. only if the GPIO4_CFG bit is zero to define pin 136 GPIO3_CFG is in PCI Config Register function 3 offset 40h. as GPO_WE. GPIO4_CFG is in PCI Config Register function 3 offset 40h. Revision 1.0 May 13, 1997 -54- Register Descriptions �9,$�7HFKQRORJLHV��,QF� VT82C586B ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings Parameter Min Max Unit o Ambient operating temperature 0 70 C o Storage temperature -55 125 C Input voltage -0.5 5.5 Volts Output voltage (V = 5V) -0.5 5.5 Volts DD Output voltage (V = 3.1 - 3.6V) -0.5 V + 0.5 Volts DD DD Note: Stress above the conditions listed may cause permanent damage to the device. Functional operation of this device should be restricted to the conditions described under operating conditions. DC Characteristics o TA-0-70 C, V =5V+/-5%, GND=0V DD Symbol Parameter Min Max Unit Condition V Input low voltage -0.50 0.8 V IL V Input high voltage 2.0 V +0.5 V IH DD V Output low voltage - 0.45 V I =4.0mA OL OL V Output high voltage 2.4 - V I =-1.0mA OH OH I Input leakage current - +/-10 uA 0