T4I 6053-xxx No. 87-006056-000 Revision A TECHNICAL REFERENCE ® Pentium 4 PROCESSOR-BASED SBC WARRANTY The product is warranted against material and manufacturing defects for two years from date of delivery. Buyer agrees that if this product proves defective Trenton Technology Inc. is only obligated to repair, replace or refund the purchase price of this product at Trenton Technology’s discretion. The warranty is void if the product has been subjected to alteration, neglect, misuse or abuse; if any repairs have been attempted by anyone other than Trenton Technology Inc.; or if failure is caused by accident, acts of God, or other causes beyond the control of Trenton Technology Inc. Trenton Technology Inc. reserves the right to make changes or improvements in any product without incurring any obligation to similarly alter products previously purchased. In no event shall Trenton Technology Inc. be liable for any defect in hardware or software or loss or inadequacy of data of any kind, or for any direct, indirect, incidental or consequential damages arising out of or in connection with the performance or use of the product or information provided. Trenton Technology Inc.’s liability shall in no event exceed the purchase price of the product purchased hereunder. The foregoing limitation of liability shall be equally applicable to any service provided by Trenton Technology Inc. RETURN POLICY Products returned for repair must be accompanied by a Return Material Authorization (RMA) number, obtained from Trenton Technology prior to return. Freight on all returned items must be prepaid by the customer, and the customer is responsible for any loss or damage caused by common carrier in transit. Items will be returned from Trenton Technology via Ground, unless prior arrangements are made by the customer for an alter- native shipping method To obtain an RMA number, call us at (800) 875-6031 or (770) 287-3100. We will need the following information: Return company address and contact Model name and model # from the label on the back of the board Serial number from the label on the back of the board Description of the failure An RMA number will be issued. Mark the RMA number clearly on the outside of each box, include a failure report for each board and return the product(s) to our Utica, NY facility: TRENTON Technology Inc. 1001 Broad Street Utica, NY 13501 Attn: Repair Department TRADEMARKS IBM, PC, VGA, EGA, OS/2 and PS/2 are trademarks or registered trademarks of International Business Machines Corp. AMI and AMIBIOS are trademarks of American Megatrends Inc. Intel and Pentium are registered trademarks of Intel Corporation. MS-DOS and Microsoft are registered trademarks of Microsoft Corp. PICMG and the PICMG logo are registered trademarks of the PCI Industrial Computer Manufacturers Group. SCSISelect is a trademark of Adaptec, Inc. All other brand and product names may be trademarks or registered trademarks of their respective companies. LIABILITY This manual is as complete and factual as possible at the time of printing; however, the DISCLAIMER information in this manual may have been updated since that time. Trenton Technology Inc. reserves the right to change the functions, features or specifications of their products at any time, without notice. Copyright © 2002 by Trenton Technology Inc. All rights reserved. E-mail: Support@TrentonProcessors.com Web: www.TrentonProcessors.com TRENTON Technology Inc. 2350 Centennial Drive • Gainesville, Georgia 30504 Sales: (800) 875-6031 • Phone: (770) 287-3100 • Fax: (770) 287-3150 T4I Technical Reference Table of Contents Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 SBC Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3 SBC Board Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4 Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5 Bus Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5 Data Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5 Bus Speed - ISA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5 Bus Speed - PCI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5 Bus Speed - System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5 Memory Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5 System Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5 DMA Channels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5 BIOS (Flash). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5 Cache Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5 NetBurst Micro-Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6 DDR Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6 Error Checking and Correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7 PCI Local Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7 Universal Serial Bus (USB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7 Super XGA Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7 System Hardware Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7 PCI Ethernet Interfaces (Dual). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8 Hub Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9 PCI SCSI Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9 PCI Enhanced IDE Interfaces (Dual) . . . . . . . . . . . . . . . . . . . . . . . 1-10 Floppy Drive Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-10 Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-10 Enhanced Parallel Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-10 PS/2 Mouse Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-10 Keyboard Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-10 Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-10 Thermal Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-11 TRENTON Technology Inc. i T4I Technical Reference Table of Contents Specifications (continued) Power Fail Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-11 Battery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-12 Temperature/Environment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-12 UL Recognition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-12 Configuration Jumpers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-13 Ethernet LEDs and Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-15 System BIOS Setup Utility. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-16 Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-17 ISA/PCI Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 ISA Bus Pin Numbering. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 ISA Bus Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 ISA Bus Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 I/O Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7 Interrupt Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7 PCI Local Bus Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8 PCI Local Bus Signal Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9 PCI Local Bus Pin Numbering. . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10 PCI Local Bus Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11 PCI Local Bus Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . 2-14 PICMG Edge Connector Pin Assignments . . . . . . . . . . . . . . . . . . 2-18 System BIOS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 BIOS Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 Password Entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 BIOS Errors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 Running AMIBIOS Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5 BIOS Setup Utility Main Menu . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6 BIOS Setup Utility Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7 Security Setup. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11 Change Supervisor Password . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11 Disabling Supervisor Password. . . . . . . . . . . . . . . . . . . . . . . . . 3-14 Change User Password . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-14 Clear User Password . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-14 Boot Sector Virus Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . 3-14 Exit Menu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-17 ii TRENTON Technology Inc. T4I Technical Reference Table of Contents Advanced Setup. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 CPU Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5 IDE Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7 IDE Device Setup. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-11 Floppy Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-15 SuperIO Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-17 DMI Event Logging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-21 Remote Access Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-23 USB Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-25 PCI Plug and Play Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 Chipset Setup. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1 Intel ICH4 SouthBridge Configuration . . . . . . . . . . . . . . . . . . . . . . 6-3 Boot Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1 Boot Settings Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-5 Boot Device Priority. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-9 Hard Disk Drives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-11 Removable Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-13 ATAPI CDROM Drives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-15 Appendix A - BIOS Messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-1 BIOS Beep Codes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-1 BIOS Error Messages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-2 Bootblock Initialization Code Checkpoints . . . . . . . . . . . . . . . . . . A-6 Bootblock Recovery Code Checkpoints. . . . . . . . . . . . . . . . . . . . . A-7 Post Code Checkpoints. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-8 DIM Code Checkpoints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-10 Additional Checkpoints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-11 Declaration of Conformity TRENTON Technology Inc. iii T4I Technical Reference This page intentionally left blank. Copyright 2002 by Trenton Technology Inc. All rights reserved. iv TRENTON Technology Inc. T4I Technical Reference HANDLING _______________________________________________________________________ PRECAUTIONS WARNING: This product has components which may be damaged by electrostatic discharge. _______________________________________________________________________ To protect your single board computer (SBC) from electrostatic damage, be sure to observe the following precautions when handling or storing the board: Keep the SBC in its static-shielded bag until you are ready to perform your installation. Handle the SBC by its edges. Do not touch the I/O connector pins. Do not apply pressure or attach labels to the SBC. Use a grounded wrist strap at your workstation or ground yourself frequently by touching the metal chassis of the system before handling any components. The system must be plugged into an outlet that is connected to an earth ground. Use antistatic padding on all work surfaces. Avoid static-inducing carpeted areas. SOLDER-SIDE This SBC has components on both sides of the PCB. It is important for you to observe COMPONENTS the following precautions when handling or storing the board to prevent solder-side components from being damaged or broken off: Handle the board only by its edges. Store the board in padded shipping material or in an anti-static board rack. Do not place an unprotected board on a flat surface. TRENTON Technology Inc. v T4I Technical Reference This page intentionally left blank. Copyright 2002 by Trenton Technology Inc. All rights reserved. vi TRENTON Technology Inc. T4I Technical Reference Specifications Chapter 1 Specifications INTRODUCTION The T4I full-featured PCI/ISA processors are single board computers (SBCs) which ® ® feature the Intel Pentium 4 microprocessor, 400/533MHz system bus, Intel 69030 video interface, 2GB DDR memory, PCI Local Bus, cache memory, floppy controller, dual EIDE (Ultra ATA/100) interfaces, Ultra160 SCSI controller, dual Ethernet inter- faces, two serial ports, parallel port, speaker port, mouse port and keyboard port on a ® single ISA-size card. These single-slot, high performance SBCs plug into PICMG PCI/ISA passive backplanes and provide full PC compatibility for the system expansion slots. MODELS Model # Model Name Speed Pentium 4 Processor - 533MHz FSB/512K cache: 6053-107-xM T4I/2.8 2.8GHz 6053-106-xM T4I/2.66 2.66GHz 6053-105-xM T4I/2.53 2.53GHz 6053-104-xM T4I/2.4 2.4GHz 6053-103-xM T4I/2.26 2.26GHz Pentium 4 Processor - 400MHz FSB/512K cache: 6053-006-xM T4I/2.6 2.6GHz 6053-005-xM T4I/2.5 2.5GHz 6053-004-xM T4I/2.4A 2.4GHz 6053-003-xM T4I/2.2 2.2GHz 6053-002-xM T4I/2.0A 2.0GHz 6053-001-xM T4I/1.8A 1.8GHz where xM indicates memory size (0M = 0MB memory, 8M =8MB memory, etc.) ® ® FEATURESIntel Pentium 4 microprocessor 2.8GHz, 2.66GHz, 2.53GHz, 2.4GHz or 2.26GHz with 512K cache and a 533MHz Front Side Bus (FSB) 2.6GHz, 2.5GHz, 2.4GHz, 2.2GHz, 2.0GHz or 1.8GHz with 512K cache and a 400MHz FSB Intel 845-E chipset with 400/533MHz system bus PCI Local Bus operating in 32-bit/33MHz mode Super XGA on-board video interface (Intel 69030) PCI Local Bus supports off-board PCI option cards, PCI 10/100Base-T and PCI 10/100/1000Base-T Ethernet controllers and on-board PCI Ultra160 SCSI controller - Adaptec AIC-7892 Memory error checking and correction (ECC) support Compatible with PCI Industrial Computer Manufacturers Group (PICMG) 1.0 Specification TRENTON Technology Inc. 1-1 Specifications T4I Technical Reference FEATURES Supports up to 2GB of Double Data Rate (DDR) on-board memory (CONTINUED) Floppy drive and dual PCI EIDE Ultra ATA/100 drive interfaces Two serial ports and one parallel port Dual Universal Serial Bus (USB 2.0) support Automatic or manual peripheral configuration Watchdog timer System hardware monitor Full PC compatibility 1-2 TRENTON Technology Inc. T4I Technical Reference Specifications SBC BLOCK DIAGRAM TRENTON Technology Inc. 1-3 Specifications T4I Technical Reference SBC BOARD LAYOUT 1-4 TRENTON Technology Inc. T4I Technical Reference Specifications ® ® PROCESSORIntel Pentium 4 microprocessor 2.8GHz, 2.66GHz, 2.53GHz, 2.4GHz or 2.26GHz with 512K cache and a 533MHz Front Side Bus (FSB) 2.6GHz, 2.5GHz, 2.4GHz, 2.2GHz, 2.0GHz or 1.8GHz with 512K cache and a 400MHz FSB Processor uses the mPGA 478 packaging BUS INTERFACES ISA and PCI Local Bus compatible DATA PATH DDR Memory - 64-bit ISA Bus - 16-bit PCI Bus - 32-bit Video - 32-bit BUS SPEED - ISA 8.33MHz BUS SPEED - PCI 33MHz BUS SPEED - 400/533MHz Front Side Bus SYSTEM MEMORY Double Data Rate (DDR) memory for 1600MB/s or 2100MB/s memory bandwidth INTERFACE SYSTEM BUS The Intel 845-E chipset supports the system bus at 400MHz or 533MHz, which provides a higher bandwidth path for transferring data between main memory/chipset and the processor. DMA CHANNELS The SBC is fully PC compatible with seven DMA channels, each supporting type F transfers. INTERRUPTS The SBC is fully PC compatible with interrupt steering for PCI plug and play compati- bility. BIOS (FLASH) The BIOS is an AMIBIOS with built-in advanced CMOS setup for system parameters, peripheral management for configuring on-board peripherals, PCI-to-PCI bridge support and PCI interrupt steering. The Flash BIOS resides in the Intel 82802 Firmware Hub (FWH). The BIOS may be upgraded from floppy disk by pressing + immediately after reset or power-up with the floppy disk in drive A:. Custom BIOSs are available. CACHE MEMORY The processor includes integrated on-die, 512K 8-way set associative level two (L2) cache, which implements the Advanced Transfer Cache architecture. The processor also includes a 12K level one (L1) Execution Trace Cache and 8K L1 data cache. These cache arrays run at the full speed of the processor core. TRENTON Technology Inc. 1-5 Specifications T4I Technical Reference NETBURST™ NetBurst micro-architecture defines the techniques Intel uses to enhance the processor’s MICRO- execution of the BIOS, operating system and application software. These techniques ARCHITECTURE include hyper pipelined technology, a rapid execution engine, advanced dynamic execution, enhanced floating point and multimedia unit and Streaming SIMD Extensions 2 (SSE2). The processor’s system bus speed and memory cache are also part of the NetBurst microarchitecture. Hyper pipelined technology doubles the pipeline depth inside the processor, which enables more instructions to be loaded, resulting in higher core frequencies. Advanced dynamic execution includes an improved speculative execution algorithm that minimizes processor instruction misdirects and results in faster instruction execution. The rapid execution engine enables the two arithmetic logic units (ALUs) of the processor to operate at twice the core frequency. Many integer instructions can now execute in half the internal core clock period, resulting in improved software execution speeds. NetBurst micro-architecture improvements in the floating point and multimedia unit include making the registers 128 bits wide and adding a separate register for moving data. The SSE2 has 144 instructions which improve performance in secure transactions and multimedia processing. These instructions are used for double-precision floating point, SIMD integer and memory management improvements. DDR MEMORY The Double Data Rate (DDR) memory interface consists of a single channel which terminates in two dual in-line memory module (DIMM) sockets and supports auto detection of up to 2GB of memory. The System BIOS automatically detects memory type, size and speed. The SBC uses industry standard 72-bit wide gold finger PC1600 or PC2100 memory modules in two 184-pin sockets. ______________________________________________________________________ NOTE: Memory modules can be installed in one or both DIMM sockets. If only one DIMM module is used, it should be populated in the top DIMM socket (Bank 2 - BK2). If two modules are used, they must be the same DIMM speed (PC1600 or PC2100), but may be different sizes (see table below). Registered DIMMs are not supported. All memory modules must have gold contacts. ______________________________________________________________________ The SBC supports DIMMs which are PC1600/PC2100 compliant and have the following features: 184-pin with gold-plated contacts ECC (72-bit) memory Unbuffered configuration 1-6 TRENTON Technology Inc. T4I Technical Reference Specifications The following DIMM sizes are supported: DIMM Size DIMM Type ECC 64MB Unbuffered 8M x 72 128MB Unbuffered 16M x 72 256MB Unbuffered 32M x 72 512MB Unbuffered 64M x 72 1GB Unbuffered 128M x 72 ERROR CHECKING The memory interface supports ECC modes via BIOS setting for multiple-bit error AND CORRECTION detection and correction of all errors confined to a single nibble. PCI LOCAL BUS The SBC is fully compliant with the PCI Local Bus 2.2 Specification. The PCI Local INTERFACE Bus is 32 bits wide and runs at 33MHz. It interfaces to standard PCI option cards in the backplane and to the on-board video, Ultra160 SCSI, 10/100/1000Base-T Ethernet and PCI-to-ISA bridge interfaces. The SBC’s high-speed hub interface and PCI Local Bus interface combination increases the connection speeds of Ethernet LANs and off-board PCI, ISA and SCSI devices. The PCI Local Bus interface to the backplane is compliant with the PCI Industrial Computer Manufacturers Group (PICMG) 1.0 Specification. UNIVERSAL SERIAL The SBC supports two high-speed USB 2.0 ports for data transfers up to 480Mbit/sec. It BUS (USB) also supports USB 1.1 devices for data transfers at 12 or 1.5Mbit/sec. The Universal Serial Bus (USB) is an interface allowing for connectivity to many standard PC periph- erals via an external port. SUPER XGA The Intel 69030 video interface integrates 4MB of high-speed memory into the chip. I NTERFACE By embedding memory and graphics controller logic on the same die, the 69030 delivers uncompromised performance. The increase in the frame buffer bandwidth enables the 69030 to support high-color, high-resolution graphics modes and real-time video acceler- ation. The interface supports pixel resolutions up to 1280 x 1024 non-interlaced. Software drivers for enhanced performance and resolution are available for most popular operating systems. SYSTEM The system hardware monitoring system monitors system voltages, temperature and fan HARDWARE speeds. MONITOR The circuitry is based on Winbond’s W83783S hardware monitoring IC that is interfaced via the system’s SMBus. System voltages of +12V, +5V, +3.3V, +2.5V, VCCORE (processor voltage) and -12V are monitored. Each of these six voltages has program- mable “high” and “low” watchdog limits. Also monitored are the processor die temper- ature and the fan speed associated with the processor’s active heatsink thermal solution. Programmable watchdog limits are also associated with fan speed RPMs. When any of these programmed limits are exceeded, monitor software can be used to report the out- of-limit condition. TRENTON Technology Inc. 1-7 Specifications T4I Technical Reference The System Hardware Monitor connector (P18) provides an external interface for user functionality. Pin assignments for this connector are as follows: Pin #/Definition Description Pin 1 - GND System Ground Pin 2 - GPO General Purpose Output Active low open drain output. This multi- function output is controlled by the W38383S’s configuration register at offset 40(h) and the control register at 4D(h). It can be used as a general-purpose output or programmed to provide a beep function that can be used as a watchdog warning signal. This output is open drain. Pin 3 - CI Chassis Intrusion Input Active low input from an external circuit, which can be used to indicate a chassis intrusion event. This input line is connected directly to the ICH’s System Management Interface’s INTRUDER# input. It can be set to disable the system if the chassis is open or can be used as a general-purpose input if intruder detection is not used. Pin 4 - OVT Over Temperature This active low, open drain output can be used to indicate that an over-temperature condition exists. PCI ETHERNET The SBC supports two Ethernet interfaces as described below. Both of these interfaces INTERFACES are compliant with IEEE 802.3 and PCI Local Bus 2.2 Specifications. Software drivers (DUAL) are supplied for most popular operating systems. LAN 1 - 10/100Base-T LAN 1 (P16) is implemented using the integrated LAN controller in the Intel 82801DB (ICH4) and its companion Intel 82562ET 10/100Base-T Ethernet PHY which supports 10Base-T and 100Base-TX Fast Ethernet modes. The main components of this interface are: Intel 82801DB for 10/100-Mb/s media access control (MAC), a serial ROM port and a PCI Bus Master interface Intel 82562ET 10/100-Mb/s PHY Serial ROM for storing the Ethernet address and the interface configuration and control data 1-8 TRENTON Technology Inc. T4I Technical Reference Specifications Integrated RJ-45/Magnetics module connector on the SBC's I/O bracket for direct connection to the network. The connector requires a category 5 (CAT5) unshielded twisted-pair (UTP) 2-pair cable for a 100-Mb/s network connection or a category3 (CAT3) or higher UTP 2-pair cable for a 10-Mb/s network connection. Link status and activity LEDs on the I/O bracket for status indication (See Ethernet LEDs and Connectors later in this chapter.) LAN 2 - 10/100/1000Base-T LAN 2 (P1) is implemented using an Intel 82540 10/100/1000Base-T Ethernet contoller which supports Gigabit, 10Base-T and 100Base-TX Fast Ethernet modes. The main components of this interface are: Intel 82540 for 10/100/1000-Mb/s media access control (MAC) with PHY, a serial ROM port and a PCI Bus Master interface Serial ROM for storing the Ethernet address and the interface configuration and control data Integrated RJ-45/Magnetics module connector on the SBC's I/O bracket for direct connection to the network. The connector requires a category 5 (CAT5) unshielded twisted-pair (UTP) 2-pair cable for a 100-Mb/s network connection or a category3 (CAT3) or higher UTP 2-pair cable for a 10-Mb/s network connection. A category 5e (CAT5e) or higher UTP 2-pair cable is recommended for a 1000-Mb/s (Gigabit) network connection. Link status and activity LEDs on the I/O bracket for status indication (See Ethernet LEDs and Connectors later in this chapter.) HUB INTERFACE The 845-E chipset utilizes a dedicated hub interface connection between the 845-E memory controller hub (MCH) and the I/O controller hub (ICH4). The purpose of the 845-E hub interface is to provide efficient, high-speed communication between chipset components in order to support high-speed I/O applications. It is a parity-protected, 266MB/s point-to-point hub interface and uses an 8-bit 66MHz base clock running at 4x. PCI SCSI The SCSI interface supports Ultra160 SCSI data transfer using Adaptec’s AIC-7892 INTERFACE SCSI controller, which supports SCSI data transfer up to 160MB per second. The interface supports up to 15 SCSI devices, complies with the SPI-3 standard and is compatible with both single-ended and Low Voltage Differential (LVD) SCSI I/O. The Ultra160 features of this channel include double-edge clocking, domain validation and cyclical redundancy checking. Active termination is provided with terminator voltage protected by a self-resetting fuse. A jumper (JU9) is provided to disable the termination (see the Configuration Jumpers section later in this chapter). Software drivers are available for most popular operating systems. The Adaptec SCSISelect Configuration Utility allows you to view and/or change the default configuration settings for the Ultra160 SCSI adapter. You may press + to invoke the configuration utility. TRENTON Technology Inc. 1-9 Specifications T4I Technical Reference PCI ENHANCED Dual high performance PCI Bus Master EIDE interfaces are capable of supporting two IDE INTERFACES IDE disk drives each in a master/slave configuration. The interfaces support Ultra (DUAL) ATA/100 with synchronous ATA mode transfers up to 100MB per second. Ultra ATA/100 cables must be used with Ultra ATA/100 drives. FLOPPY DRIVE The SBC supports two floppy disk drives. Drives can be 360K to 2.88MB, in any INTERFACE combination. SERIAL INTERFACE Two high-speed FIFO (16C550) serial ports with independently programmable baud rates are supported. The IRQ for each serial port has BIOS selectable addressing. ENHANCED The SBC provides a PC/AT compatible bidirectional parallel port and supports enhanced PARALLEL parallel port (EPP) mode and extended capabilities port (ECP) mode. The ECP mode is INTERFACE IEEE 1284 compliant. The IRQ for the parallel port has BIOS selectable addressing. PS/2 MOUSE The SBC is compatible with a PS/2-type mouse. The mouse connection can be made by INTERFACE using either the PS/2 mouse header or the bracket mounted mouse/keyboard mini DIN connector. The mouse may be connected directly to the mini DIN connector or to the "mouse" side of the "Y" adapter. Mouse voltage is protected by a self-resetting fuse. KEYBOARD The SBC is compatible with an AT-type keyboard. The keyboard connection can be INTERFACE made by using either the keyboard header or the "keyboard" side of the "Y" adapter plugged into the bracket mounted mouse/keyboard mini DIN connector. Keyboard voltage is protected by a self-resetting fuse. WATCHDOG TIMER The watchdog timer is a hardware timer which resets the SBC if the timer is not refreshed by software periodically. The timer is typically used to restart a system in which an application becomes hung on an external event. When the application is hung, it no longer refreshes the timer. The watchdog timer then times out and resets the SBC. The watchdog timer has programmable timeout periods of 30 mseconds, 10 seconds or 60 seconds. When enabled, the watchdog timer generates a system reset by deactivating the Power Good signal. Watchdog timer control is supplied via the ICH4 General Purpose I/O pins. The state of these GPIO signals are controlled by the GPIO Level Input or Output Register (GP_LVL). This 32-bit register is located at offset 0C(h) in the General Purpose I/O space at base address 500(h). Bits 19, 20 and 23 of this register are used for watchdog timer control. The register can also be accessed in byte mode; bits 23-16 reside at I/O address 50E(h). The GP_LVL bit definitions are as follows: Bit 19 - Watchdog Input (WDI) When the watchdog timer is enabled, this bit must be toggled (0 to 1 or 1 to 0) within the selected watchdog timeout period. Failure to do so results in a system reset. This function is controlled by bit 19 of the GP_LVL register. Bits 20 and 23 - Watchdog Select 0/Watchdog Select 1 (WDS0/WDS1) These two bits of the GP_LVL register select the watchdog timeout period. 1-10 TRENTON Technology Inc. T4I Technical Reference Specifications Timeout period options are as follows: WDS1 WDS0 Timeout Period 0 0 30 mseconds 0 1 Disabled (power-on default) 1 0 10 seconds 1 1 60 seconds The Watchdog Input (WDI) bit should be toggled immediately prior to changing the timeout period. Once the WDS1 and WDS0 bits have been set to select the desired timeout period, the WDI bit must be toggled within the selected period. A set of watchdog timer software code and sample programs are available from Technical Support. THERMAL MONITOR The SBC’s processor has a built-in thermal monitor feature designed to prevent processor failure at elevated operating temperature. The thermal monitor consists of an on-die temperature sensor and a fast-acting thermal control circuit (TCC). The temperature sensor is precision-tuned to activate the TCC when the processor’s internal die temperature nears the temperature limits of the processor. During a high temperature situation, the TCC activates to modulate the processor’s internal clocks down to a duty-cycle of 30% to 50%, causing processor performance to throttle down by approximately 50%. Near the temperature activation point, a small amount of hysteresis prevents rapid active-to-inactive TCC transitions. During TCC activation, the processor continues to function, but at a reduced rate of instruction execution. Once the processor’s temperature returns to a non-critical level and the hysteresis timer expires, the TCC deactivates and returns the processor clocks to normal duty cycles and the processor execution speeds to normal. A case temperature of approximately 65º C. causes the TCC to activate; processor temperatures above 135º C. cause the processor to automatically shut down. The actual TCC activation point in a specific SBC application may vary as a function of processor loading, system case design, SBC location within a case and other factors. When the TCC activates, the SBC’s Thermal Throttling Activity LED turns on. Depending on the setting of the Thermal Throttling Activity LED jumper (JU6), the LED either goes off after the processor returns to normal temperature or remains on in a latched state to indicate that the processor’s TCC has activated at least once. (See the Configuration Jumpers section later in this chapter for further explanation of the Thermal Throttling Activity LED jumper.) Under normal operating conditions, the SBC’s active cooling system generally prevents the TCC from activating. POWER FAIL A hardware reset is issued when any of the monitored voltages drops below its specified DETECTION nominal low voltage limit. The monitored voltages and their nominal low limits are listed on the following page. TRENTON Technology Inc. 1-11 Specifications T4I Technical Reference Monitored Nominal Voltage Low Limit Voltage Source +5V 4.5 volts System Power Supply +3.3V 2.97 volts System Power Supply +1.2V 1.056 volts On-Board Regulator +1.25V 1.1 volt On-Board Regulator +2.5V 2.452 volts On-Board Regulator BATTERY A built-in lithium battery is provided, for ten years of data retention for CMOS memory. ______________________________________________________________________ CAUTION: There is a danger of explosion if the battery is incorrectly replaced. Replace it only with the same or equivalent type recommended by the manufacturer. Dispose of used batteries according to the manufacturer's instructions. ______________________________________________________________________ TEMPERATURE/ Operating Temperature: 0º C. to 45º C. ENVIRONMENT Storage Temperature: - 40º C. to 70º C. Humidity: 5% to 90% non-condensing UL RECOGNITION This SBC is a UL recognized product listed in file #E208896. This board was investigated and determined to be in compliance under the Bi-National Standard for Information Technology Equipment. This included the Electrical Business Equipment, UL 1950, Third Edition, and CAN/CSA C22.22 No. 950-95. 1-12 TRENTON Technology Inc. T4I Technical Reference Specifications CONFIGURATION The setup of the configuration jumpers on the SBC is described below. * indicates the JUMPERS default value of each jumper. ______________________________________________________________________ NOTE: For two-position jumpers (3-post), "TOP" is toward the memory sockets; "BOTTOM" is toward the edge fingers. ______________________________________________________________________ Jumper Description JU6 Thermal Throttling Activity LED If the processor core gets to a critical temperature, it slows itself down to half its normal speed. This jumper sets the way in which the LED displays in response to this self-limiting mode. Install for real-time activity. The LED lights only when the processor is operating in slow-power mode. * Remove for latched activity. The LED lights and stays on once the processor has gone into slow-power mode. JU7 Speed LED This jumper is used in conjunction with the Link/Speed LED for the 10/100/1000Base-T Ethernet interface. The LED is located on the SBC’s Gigabit LAN connector (LAN2/P1). For further information, see the Ethernet LEDs and Connectors section below. Install to use the Link/Speed LED to indicate that the Ethernet interface has a valid link at either 1000-Mb/s or 100-Mb/s. Green = valid link at 1000-Mb/s * Orange = valid link at 100-Mb/s Remove to use the Link/Speed LED to indicate that the Ethernet interface has a valid link at either 100-Mb/s or 10-Mb/s . Orange = valid link at 100-Mb/s Green = valid link at 10-Mb/s JU8 Password Clear Install for one power-up cycle to reset the password to the default (null password). Remove for normal operation. * TRENTON Technology Inc. 1-13 Specifications T4I Technical Reference CONFIGURATION JUMPERS Jumper Description (CONTINUED) JU9 SCSI Termination This jumper may be used to enable or disable on-board active termination for the Ultra160 SCSI interface. Install on the TOP to enable active temination. * Install on the BOTTOM to allow the AIC-7892 to control termination. Remove to disable active termination. JU10/JU11 System Flash ROM Operational Modes The Flash ROM has two programmable sections: the Boot Block for “flashing” in the BIOS and the Main Block for the executable BIOS and PnP parameters. Normally only the Main Block is updated when a new BIOS is flashed into the system. JU10 JU11 All Blocks Write Enabled Remove * Remove * Boot Block Write Protected Install Remove Block 2-16 Write Protected Remove Install JU12 CMOS Clear Install on the TOP to operate. * Install on the BOTTOM to clear. __________________________________________________ NOTE: The CMOS Clear jumper works on power-up. To clear the CMOS, power down the system, install the jumper, then turn the power back on. CMOS is cleared during the POST routines. Wait for AMIBIOS to display a "CMOS Settings Wrong" message; then power down the system again and remove the jumper before the next power-up. __________________________________________________ JU19 SCSI Activity LED Install to light the hard drive LED for SCSI drive activity. * Remove if you do not have a SCSI drive (i.e., the SCSI controller is not being used). 1-14 TRENTON Technology Inc. T4I Technical Reference Specifications ETHERNET LEDS LAN 1 - 10/100Base-T AND CONNECTORS LAN 1 (P16) is implemented using the integrated LAN controller in the Intel 82801DB (ICH4) and its companion Intel 82562ET 10/100Base-T Ethernet PHY which supports 10Base-T and 100Base-TX Fast Ethernet modes. The interface has two LEDs for status indication and an RJ-45 network connector.. LED/Connector Description Link/Activity LED Green LED which indicates the link status. Off The Ethernet interface did not find a valid link on the network connection. Transmit and receive are not possible. On (solid) The Ethernet interface has a valid link on the network connection and is ready for normal operation. The Speed LED identifies connection speed. On (flashing) Indicates network transmit or receive activity. Speed LED Amber LED which identifies connection speed. Off Indicates a 10-Mb/s connection. On Indicates a 100-Mb/s connection. RJ-45 Network The RJ-45 network connector requires a category 5 Connector (CAT5) unshielded twisted-pair (UTP) 2-pair cable for a 100-Mb/s network connection or a category 3 (CAT3) or higher UTP 2-pair cable for a 10-Mb/s network connection. LAN 2 - 10/100/1000Base-T LAN 2 (P1) is implemented using an Intel 82540 10/100/1000Base-T Ethernet contoller which supports Gigabit, 10Base-T and 100Base-TX Fast Ethernet modes. It has two LEDs for status indication and an RJ-45 network connector.. LED/Connector Description Activity LED Orange LED which indicates network activity. This is the upper LED on the LAN connector (i.e., toward the memory sockets). Off Indicates there is no current network transmit or receive activity. On (flashing) Indicates network transmit or receive activity. TRENTON Technology Inc. 1-15 Specifications T4I Technical Reference ETHERNET LEDS AND CONNECTORS LED/Connector Description (CONTINUED) Link/Speed LED Bi-color (green/orange) LED which identifies the link status and connection speed. This is the lower LED on the LAN connector (i.e., toward the edge connectors). Green Indicates a valid link at either 1000-Mb/s or 10-Mb/s, depending on the setting of the associated Speed LED jumper (JU7). Orange Indicates a valid link at 100-Mb/s, regardless of the setting of the associated Speed LED jumper. ______________________________________________ NOTE: For further information on the Speed LED jumper, see the Configuration Jumpers section earlier in this chapter. ______________________________________________ RJ-45 Network The RJ-45 network connector requires a category 5 Connector (CAT5) unshielded twisted-pair (UTP) 2-pair cable for a 100-Mb/s network connection or a category 3 (CAT3) or higher UTP 2-pair cable for a 10-Mb/s network connection. A category 5e (CAT5e) or higher UTP 2-pair cable is recommended for a 1000-Mb/s (Gigabit) network connection. SYSTEM BIOS The System BIOS is an AMIBIOS with a ROM-resident setup utility. The BIOS Setup SETUP UTILITY Utility allows you to select to the following categories of options: Main Menu Advanced Setup PCIPnP Setup Chipset Setup Boot Setup Security Setup Exit Each of these options allows you to review and/or change various setup features of your system. Details are provided in the following chapters of this manual. 1-16 TRENTON Technology Inc. T4I Technical Reference Specifications CONNECTORS ______________________________________________________________________ NOTE: Pin 1 on the connectors is indicated by the square pad on the PCB. ______________________________________________________________________ P1 - 10/100/1000Base-T Ethernet Connector 8 pin shielded RJ-45 connector, Belfuse #0826-1X1T-23 Pin Signal 1 TRP1+ 2 TRP1- 3 TRP2+ 4 TRP3+ 5 TRP3- 6 TRP2- 7 TRP4+ 8 TRP4- P3 - Floppy Drive Connector 34 pin dual row header, Amp #103308-7 Pin Signal Pin Signal 1 Gnd 2 N-RPM 3 Gnd 4 NC 5 Gnd 6 D-Rate0 7 Gnd 8 P-Index 9 Gnd 10 N-Motoron 1 11 Gnd 12 N-Drive Sel2 13 Gnd 14 N-Drive Sel1 15 Gnd 16 N-Motoron 2 17 Gnd 18 N-Dir 19 Gnd 20 N-Stop Step 21 Gnd 22 N-Write Data 23 Gnd 24 N-Write Gate 25 Gnd 26 P-Track 0 27 Gnd 28 P-Write Protect 29 Gnd 30 N-Read Data 31 Gnd 32 N-Side Select 33 Gnd 34 Disk Chng P4A - Keyboard Header 5 pin single row header, Amp #640456-5 Pin Signal 1 Kbd Clock 2 Kbd Data 3 Key 4 Kbd Gnd 5 Kbd Power (+5V fused) with self-resetting fuse TRENTON Technology Inc. 1-17 Specifications T4I Technical Reference CONNECTORS (CONTINUED) P5 - Speaker Port Connector 4 pin single row header, Amp #640456-4 Pin Signal 1 Speaker Data 2 Key 3 Gnd 4 +5V P6 - Serial Port 1 Connector 10 pin dual row header, Amp #103308-1 Pin Signal Pin Signal 1 Carrier Detect 2 Data Set Ready-I 3 Receive Data-I 4 Request to Send-O 5 Transmit Data-O 6 Clear to Send-I 7 Data Terminal Ready-O 8 Ring Indicator-I 9 Signal Gnd 10 NC P7 - Serial Port 2 Connector 10 pin dual row header, Amp #103308-1 Pin Signal Pin Signal 1 Carrier Detect 2 Data Set Ready-I 3 Receive Data-I 4 Request to Send-O 5 Transmit Data-O 6 Clear to Send-I 7 Data Terminal Ready-O 8 Ring Indicator-I 9 Signal Gnd 10 NC P8 - Parallel Port Connector 26 pin dual row header, Amp #103308-6 Pin Signal Pin Signal 1 Strobe 2 Auto Feed XT 3 Data Bit 0 4 Error 5 Data Bit 1 6 Init 7 Data Bit 2 8 Slct In 9 Data Bit 3 10 Gnd 11 Data Bit 4 12 Gnd 13 Data Bit 5 14 Gnd 15 Data Bit 6 16 Gnd 17 Data Bit 7 18 Gnd 19 ACK 20 Gnd 21 Busy 22 Gnd 23 Paper End 24 Gnd 25 Slct 26 NC 1-18 TRENTON Technology Inc. T4I Technical Reference Specifications CONNECTORS (CONTINUED) P9 - PS/2 Mouse and Keyboard Connector 6 pin mini DIN, Kycon #KMDG-6S-B4T Pin Signal 1 Ms Data 2 Kbd Data 3 Gnd 4 Power (+5V fused) with self-resetting fuse 5 Ms Clock 6 Kbd Clock P9A - PS/2 Mouse Header 6 pin single row header, Amp #640456-6 Pin Signal 1 Ms Data 2 Reserved 3 Gnd 4 Power (+5V fused) with self-resetting fuse 5 Ms Clock 6 Reserved P10 - External Reset Connector 2 pin single row header, Amp #640456-2 Pin Signal 1 External Reset In (Low Active) 2 Gnd P11 - Primary IDE Hard Drive Connector 40 pin dual row header, 3M #30340-6002HB Pin Signal Pin Signal 1 Reset 2 Gnd 3 Data 7 4 Data 8 5 Data 6 6 Data 9 7 Data 5 8 Data 10 9 Data 4 10 Data 11 11 Data 3 12 Data 12 13 Data 2 14 Data 13 15 Data 1 16 Data 14 17 Data 0 18 Data 15 19 Gnd 20 NC 21 DRQ 0 22 Gnd 23 IOW 24 Gnd 25 IOR 26 Gnd 27 IORDY 28 SELPDP 29 DACK 0 30 Gnd TRENTON Technology Inc. 1-19 Specifications T4I Technical Reference CONNECTORS (CONTINUED) P11 - Primary IDE Hard Drive Connector (continued) Pin Signal Pin Signal 31 IRQ 14 32 NC 33 Add 1 34 PCBL DET * 35 Add 0 36 Add 2 37 CS 1P 38 CS 3P 39 IDEACTP 40 Gnd P11A - Secondary IDE Hard Drive Connector 40 pin dual row header, 3M #30340-6002HB Pin Signal Pin Signal 1 Reset 2 Gnd 3 Data 7 4 Data 8 5 Data 6 6 Data 9 7 Data 5 8 Data 10 9 Data 4 10 Data 11 11 Data 3 12 Data 12 13 Data 2 14 Data 13 15 Data 1 16 Data 14 17 Data 0 18 Data 15 19 Gnd 20 NC 21 DRQ 1 22 Gnd 23 IOW 24 Gnd 25 IOR 26 Gnd 27 IORDY 28 SELPDS 29 DACK 1 30 Gnd 31 IRQ 15 32 NC 33 Add 1 34 SCBL DET * 35 Add 0 36 Add 2 37 CS 1S 38 CS 3S 39 IDEACTS 40 Gnd * For ATA/66 and ATA/100 drives, which should be set for Cable Select for proper speed operation. If other drives are detected, pin definition is Gnd. P12 - Hard Drive LED Connector 4 pin single row header, Amp #640456-4 Pin Signal 1 LED + 2 LED - 3 LED - 4 LED + 1-20 TRENTON Technology Inc. T4I Technical Reference Specifications CONNECTORS (CONTINUED) P13 - Ultra160 SCSI Connector 68 pin high density connector, Amp #749069-7 Pin Signal Pin Signal 1 SCD12 35 SCD#12 2 SCD13 36 SCD#13 3 SCD14 37 SCD#14 4 SCD15 38 SCD#15 5 SCDPH 39 SCDPH# 6 SCD0 40 SCD#0 7 SCD1 41 SCD#1 8 SCD2 42 SCD#2 9 SCD3 43 SCD#3 10 SCD4 44 SCD#4 11 SCD5 45 SCD#5 12 SCD6 46 SCD#6 13 SCD7 47 SCD#7 14 SCDPL 48 SCDPL# 15 Gnd 49 Gnd 16 DIFSENSE 50 Gnd 17 TERMPWR 51 TERMPWR 18 TERMPWR 52 TERMPWR 19 NC 53 NC 20 Gnd 54 Gnd 21 SCATN 55 SCATN# 22 Gnd 56 Gnd 23 SCBSY 57 SCBSY# 24 SCACK 58 SCACK# 25 SCRST 59 SCRST# 26 SCMSG 60 SCMSG# 27 SCSEL 61 SCSEL# 28 SCCD 62 SCCD# 29 SCREQ 63 SCREQ# 30 SCIO 64 SCIO# 31 SCD8 65 SCD#8 32 SCD9 66 SCD#9 33 SCD10 67 SCD#10 34 SCD11 68 SCD#11 TRENTON Technology Inc. 1-21 Specifications T4I Technical Reference CONNECTORS (CONTINUED) P15 - PCI SXGA Interface Connector 15 pin VGA Ultra Compact connector, Amp #788574-1 Pin Signal Pin Pin Signal Signal 6Gnd 1Red 11 NC 7Gnd 2 Green 12 EEDI 8Gnd 3Blue 13 HSYNC 9+5V 4NC 14 VSYNC 10 Gnd 5Gnd 15 EECS P16 - 10/100Base-T Ethernet Connector 8 pin shielded RJ-45 connector, Pulse #J0035D21B Pin Signal 1 TD+ 2 TD- 3 RX+ 4 NC 5 NC 6 RX- 7 NC 8 NC P17 - Universal Serial Bus (USB) Connector 8 pin dual row header, Molex #702-46-0821 (+5V fused with self-resetting fuses) Pin Signal Pin Signal 1 +5V-USB0 2 +5V-USB1 3 USB0- 4 USB1- 5 USB0+ 6 USB1+ 7 Gnd-USB0 8 Gnd-USB1 P18 - System Hardware Monitor Connector 4 pin single row header, Amp #640456-4 Pin Signal 1 Gnd 2 GPO (General Purpose Output) 3 CI (Chassis Intrusion Input) 4 OVT (Over Temperature) 1-22 TRENTON Technology Inc. T4I Technical Reference Specifications CONNECTORS (CONTINUED) P19 - CPU Fan 1 3 pin single row header, Molex #22-23-2031 Pin Signal 1 Gnd 2 +12V 3 FanTach P21 - Power Good LED 2 pin single row header, Amp #640456-2 Pin Signal 1 LED - 2 LED + P22 - System Management Bus Connector 2 pin single row header, Amp #640456-2 Pin Signal 1 SMB Clock 2 SMB Data P23 - +5V VRM Supply 2 pin header, Molex #39-29-3026 Pin Signal 1 +5V 2 +5V P24 - CPU VRM Power Input 4 pin header, Molex #39-29-3046 Pin Signal 1 Gnd 2 Gnd 3 +12V 4 +12V TRENTON Technology Inc. 1-23 Specifications T4I Technical Reference This page intentionally left blank. Copyright 2002 by Trenton Technology Inc. All rights reserved. 1-24 TRENTON Technology Inc. T4I Technical Reference ISA/PCI Reference Chapter 2 ISA/PCI Reference ISA BUS PIN NUMBERING 62-pin ISA Bus Connector Component Side of Board 36-pin ISA Bus Connector TRENTON Technology Inc. 2-1 ISA/PCI Reference T4I Technical Reference ISA BUS PIN The following tables summarize pin assignments for the Industry Standard Architecture ASSIGNMENTS (ISA) Bus connectors. I/O Pin Signal Name I/O I/O Pin Signal Name I/O A1 IOCHK# I B1 Gnd Ground A2 D7 I/O B2 RESDRV O A3 D6 I/O B3 +5V Power A4 D5 I/O B4 IRQ9 I A5 D4 I/O B5 -5V Power A6 D3 I/O B6 DRQ2 I A7 D2 I/O B7 -12V Power A8 D1 I/O B8 NOWS# I A9 D0 I/O B9 +12V Power A10 CHRDY I B10 Gnd SMWTC# Ground A11 AEN O B11 SMRDC# O A12 SA19 I/O B12 IOWC# O A13 SA18 I/O B13 IORC# I/O A14 SA17 I/O B14 DAK3# I/O A15 SA16 I/O B15 DRQ3 O A16 SA15 I/O B16 DAK1# I A17 SA14 I/O B17 DRQ1 O A18 SA13 I/O B18 REFRESH# I A19 SA12 I/O B19 BCLK I/O A20 SA11 I/O B20 IRQ7 O A21 SA10 I/O B21 IRQ6 I A22 SA9 I/O B22 IRQ5 I A23 SA8 I/O B23 IRQ4 I A24 SA7 I/O B24 IRQ3 I A25 SA6 I/O B25 DAK2# I A26 SA5 I/O B26 T-C O A27 SA4 I/O B27 BALE O A28 SA3 I/O B28 +5V O A29 SA2 I/O B29 OSC Power A30 SA1 I/O B30 Gnd O A31 SA0 I/O B31 Ground I/O Pin Signal Name I/O I/O Pin Signal Name I/O C1 SBHE# I/O D1 M16# I C2 LA23 I/O D2 IO16# I C3 LA22 I/O D3 IRQ10 I C4 LA21 I/O D4 IRQ11 I C5 LA20 I/O D5 IRQ12 I C6 LA19 I/O D6 IRQ15 I C7 LA18 I/O D7 IRQ14 I C8 LA17 I/O D8 DAK0# O C9 MRDC# I/O D9 DRQ0 I C10 MWTC# I/O D10 DAK5# O C11 D8 I/O D11 DRQ5 I C12 D9 I/O D12 DAK6# O C13 D10 I/O D13 DRQ6 I C14 D11 I/O D14 DAK7# O C15 D12 I/O D15 DRQ7 I C16 D13 I/O D16 +5V Power C17 D14 I/O D17 Master16# I C18 D15 I/O D18 Gnd Ground 2-2 TRENTON Technology Inc. T4I Technical Reference ISA/PCI Reference ISA BUS SIGNAL The following is a description of the ISA Bus signals. All signal lines are TTL- DESCRIPTIONS compatible. AEN (O) Address Enable (AEN) is used to degate the microprocessor and other devices from the I/O channel to allow DMA transfers to take place. When this line is active, the DMA controller has control of the address bus, the data-bus Read command lines (memory and I/O), and the Write command lines (memory and I/O). BALE (O) (Buffered) Address Latch Enable (BALE) is provided by the bus controller and is used on the system board to latch valid addresses and memory decodes from the microprocessor. It is available to the I/O channel as an indicator of a valid microprocessor or DMA address (when used with AEN). Microprocessor addresses SA[19::0] are latched with the falling edge of BALE. BALE is forced high during DMA cycles. BCLK (O) BCLK is the system clock. The clock has a 50% duty cycle. This signal should only be used for synchronization. It is not intended for uses requiring a fixed frequency. CHRDY (I) I/O Channel Ready (CHRDY) is pulled low (not ready) by a memory or I/O device to lengthen I/ O or memory cycles. Any slow device using this line should drive it low immediately upon detecting its valid address and a Read or Write command. Machine cycles are extended by an integral number of clock cycles. This signal should be held low for no more than 2.5 micro- seconds. D[15::0] (I/O) Data signals D[15::0] provide bus bits 15 through 0 for the microprocessor, memory, and I/O devices. D15 is the most-significant bit and D0 is the least-significant bit. All 8-bit devices on the I/O channel should use D[7::0] for communications to the microprocessor. The 16-bit devices will use D[15::0]. To support 8-bit devices, the data on D[15::8] will be gated to D[7::0] during 8-bit transfers to these devices. 16-bit microprocessor transfers to 8-bit devices will be converted to two 8-bit transfers. DAK[7::5]#, DAK[3::0]# (O) DMA Acknowledge DAK[7::5]# and DAK[3::0]# are used to acknowledge DMA requests DRQ[7::5] and DRQ[3::0]. They are active low. DRQ[7::5], DRQ[3::0] (I) DMA Requests DRQ[7::5] and DRQ[3::0] are asynchronous channel requests used by peripheral devices and the I/O channel microprocessors to gain DMA service (or control of the system). They are prioritized, with DRQ0 having the highest priority and DRQ7 having the lowest. A request is generated by bringing a DRQ line to an active level. A DRQ line must be held high until the corresponding DMA Request Acknowledge (DAK) line goes active. DRQ[3::0] will perform 8-bit DMA transfers; DRQ[7::5] will perform 16-bit transfers. TRENTON Technology Inc. 2-3 ISA/PCI Reference T4I Technical Reference IO16# (I) I/O 16-bit Chip Select (IO16#) signals the system board that the present data transfer is a 16-bit, 1 wait-state, I/O cycle. It is derived from an address decode. IO16# is active low and should be driven with an open collector or tri-state driver capable of sinking 20 mAmps. IOCHK# (I) I/O Channel Check (IOCHK#) provides the system board with parity (error) information about memory or devices on the I/O channel. When this signal is active, it indicates an uncorrectable system error. IORC# (I/O) I/O Read (IORC#) instructs an I/O device to drive its data onto the data bus. It may be driven by the system microprocessor or DMA controller, or by a microprocessor or DMA controller resident on the I/O channel. This signal is active low. IOWC# (I/O) I/O Write (IOWC#) instructs an I/O device to read the data on the data bus. It may be driven by any microprocessor or DMA controller in the system. This signal is active low. IRQ[15::14], IRQ[12::9], IRQ[7::3] (I) Interrupt Requests IRQ[15::14], IRQ[12::9] and IRQ[7::3] are used to signal the microprocessor that an I/O device needs attention. The interrupt requests are prioritized, with IRQ[15::14] and IRQ[12::9] having the highest priority (IRQ9 is the highest) and IRQ[7::3] having the lowest priority (IRQ7 is the lowest). An interrupt request is generated when an IRQ line is raised from low to high. The line must be held high until the microprocessor acknowledges the interrupt request (Interrupt Service routine). LA[23::17] (I/O) These signals (unlatched) are used to address memory and I/O devices within the system. They give the system up to 16MB of addressability. These signals are valid when BALE is high. LA[23::17] are not latched during microprocessor cycles and therefore do not stay valid for the whole cycle. Their purpose is to generate memory decodes for 1 wait-state memory cycles. These decodes should be latched by I/O adapters on the falling edge of BALE. These signals also may be driven by other microprocessors or DMA controllers that reside on the I/O channel. M16# (I) M16# Chip Select signals the system board if the present data transfer is a 1wait-state, 16- bit, memory cycle. It must be derived from the decode of LA[23::17]. M16# should be driven with an open collector or tri-state driver capable of sinking 20 mAmps. Master16# (I) Master16# is used with a DRQ line to gain control of the system. A processor or DMA controller on the I/O channel may issue a DRQ to a DMA channel in cascade mode and receive a DAK#. Upon receiving the DAK#, an I/O microprocessor may pull Master16# low, which will allow it to control the system address, data, and control lines (a condition known as tri-state). After Master16# is low, the I/O microprocessor must wait one system clock period before driving the address and data lines, and two clock periods before issuing a Read or Write command. If this signal is held low for more than 15microseconds, system memory may be lost because of a lack of refresh. 2-4 TRENTON Technology Inc. T4I Technical Reference ISA/PCI Reference NOWS# (I) The No Wait State (NOWS#) signal tells the microprocessor that it can complete the present bus cycle without inserting any additional wait cycles. In order to run a memory cycle to a 16-bit device without wait cycles, NOWS# is derived from an address decode gated with a Read or Write command. In order to run a memory cycle to an 8-bit device with a minimum of two wait states, NOWS# should be driven active on system clock after the Read or Write command is active gated with the address decode for the device. Memory Read and Write commands to a 8-bit device are active on the falling edge of the system clock. NOWS# is active low and should be driven with an open collector or tri-state driver capable of sinking 20 mAmps. OSC (O) Oscillator (OSC) is a high-speed clock with a 70-nanosecond period (14.31818 MHz). This signal is not synchronous with the system clock. It has a 50% duty cycle. REFRESH# (I/O) The REFRESH# signal is used to indicate a refresh cycle and can be driven by a micropro- cessor on the I/O channel. RESDRV (O) Reset Drive (RESDRV) is used to reset or initialize system logic at power-up time or during a low line-voltage outage. This signal is active high. SA[19::0] (I/O) Address bits SA[19::0] are used to address memory and I/O devices within the system. These twenty address lines, in addition to LA[23::17], allow access of up to 16MB of memory. SA[19::0] are gated on the system bus when BALE is high and are latched on the falling edge of BALE. These signals are generated by the microprocessor or DMA Controller. They also may be driven by other microprocessors or DMA controllers that reside on the I/O channel. SBHE# (I/O) System Bus High Enable (SBHE#) indicates a transfer of data on the upper byte of the data bus, D[15::8]. 16-bit devices use SBHE# to condition data bus buffers tied to D[15::8]. SMRDC# (O), MRDC# (I/O) These signals instruct the memory devices to drive data onto the data bus. SMRDC# is active only when the memory decode is within the low 1MB of memory space. MRDC# is active on all memory read cycles. MRDC# may be driven by any microprocessor or DMA controller in the system. SMRDC is derived from MRDC# and the decode of the low 1MB of memory. When a microprocessor on the I/O channel wishes to drive MRDC#, it must have the address lines valid on the bus for one system clock period before driving MRDC# active. Both signals are active low. SMWTC# (O), MWTC# (I/O) These signals instruct the memory devices to store the data present on the data bus. SMWTC# is active only when the memory decode is within the low 1MB of the memory space. MWTC# is active on all memory write cycles. MWTC# may be driven by any microprocessor or DMA controller in the system. SMWTC# is derived from MWTC# and the decode of the low 1MB of memory. When a microprocessor on the I/O channel wishes to drive MWTC#, it must have the address lines valid on the bus for one system clock period before driving MWTC# active. Both signals are active low. TRENTON Technology Inc. 2-5 ISA/PCI Reference T4I Technical Reference T-C (O) Terminal Count (T-C) provides a pulse when the terminal count for any DMA channel is reached. 2-6 TRENTON Technology Inc. T4I Technical Reference ISA/PCI Reference I/O ADDRESS MAP* Hex Range Device 000-01F DMA Controller 1 020-03F Interrupt Controller 1, Master 040-05F Timer 060-06F 8042 (Keyboard) 070-07F Realtime Clock, NMI (non-maskable interrupt) Mask 080-09F DMA Page Register 0A0-0BF Interrupt Controller 2 0C0-0DF DMA Controller 2 0F0 Clear Math Coprocessor Busy 0F1 Reset Math Coprocessor 0F8-0FF Math Coprocessor 1F0-1F8 Fixed Disk 200-207 Game I/O 278-27F Parallel Printer Port 2 2F8-2FF Serial Port 2 300-31F Prototype Card 360-36F Reserved 378-37F Parallel Printer Port 1 380-38F SDLC, Bisynchronous 2 3A0-3AF Bisynchronous 1 3B0-3BF Monochrome Display and Printer Adapter 3C0-3CF Reserved 3D0-3DF Color/Graphics Monitor Adapter 3F0-3F7 Diskette Controller 3F8-3FF Serial Port 1 INTERRUPT A * SSIGNMENTS Interrupt Description IRQ0 Timer Output 0 IRQ1 Keyboard (Output Buffer Full) IRQ2 Interrupt 8 through 15 IRQ3 erial Port 2 IRQ4 Serial Port 1 IRQ5 Parallel Port 2 IRQ6 Diskette Controller IRQ7 Parallel Port 1 IRQ8 Realtime Clock Interrupt IRQ9 Software Redirected to INT 0AH (IRQ2) IRQ10 Unassigned IRQ11 Unassigned IRQ12 PS/2 Mouse IRQ13 Coprocessor IRQ14 Fixed Disk Controller IRQ15 Unassigned (may be assigned by the system to the secondary IDE) * These are typical parameters, which may not reflect your current system. TRENTON Technology Inc. 2-7 ISA/PCI Reference T4I Technical Reference PCI LOCAL BUS The PCI (Peripheral Component Interconnect) Local Bus is a high performance, 32-bit or OVERVIEW 64-bit bus with multiplexed address and data lines. It is intended for use as an inter- connect mechanism between highly integrated peripheral controller components, peripheral add-in boards and processor/memory systems. The "local bus" moves peripheral functions with high bandwidth requirements closer to the system’s processor bus and can produce substantial performance gains with graphical user interfaces (GUI’s) and other high bandwidth functions (i.e., full motion video, SCSI, LAN’s, etc.). The PCI Local Bus accommodates future system requirements and is applicable across multiple platforms and architectures. The PCI component and add-in card interface is processor independent, enabling an efficient transition to future processor generations, by bridges or by direct integration, and use with multiple processor architectures. Processor independence allows the PCI Local Bus to be optimized for I/O functions, enables concurrent operation of the local bus with the processor/memory subsystem, and accommodates multiple high perfor- mance peripherals in addition to graphics. Movement to enhanced video and multimedia displays and other high bandwidth I/O will continue to increase local bus bandwidth requirements. A transparent 64-bit extension of the 32-bit data and address buses is defined, doubling the bus bandwidth and offering forward and backward compatibility of 32-bit (132MB/s peak) and 64-bit (264MB/s peak) PCI Local Bus peripherals. 2-8 TRENTON Technology Inc. T4I Technical Reference ISA/PCI Reference PCI LOCAL BUS The PCI interface requires a minimum of 47 pins for a target-only device and 49 pins for SIGNAL DEFINITION a master to handle data and addressing, interface control, arbitration and system functions. The diagram below shows the pins in functional groups, with required pins on the left side and optional pins on the right side. Required Pins: Optional Pins: Address & Data: 64-bit Extension AD[31::00] AD[63::32] C/BE[3::0]# C/BE[7::4]# PAR PAR64 REQ64# Interface Control: ACK64# PCI FRAME# Interface Control: TRDY# COMPLIANT IRDY# LOCK# DEVICE STOP# INTA# DEVSEL# INTB# IDSEL INTC# INTD# Error Reporting: PERR# Cache Support: SERR# SBO# SDONE Arbitration JTAG (IEEE 1149.1): (masters only): TDI REQ# TDO GNT# TCK System: TMS CLK TRST# RST# PCI Pin List TRENTON Technology Inc. 2-9 ISA/PCI Reference T4I Technical Reference PCI LOCAL BUS PIN NUMBERING Component Side of Board 5-volt/32-bit PCI Connector 2-10 TRENTON Technology Inc. T4I Technical Reference ISA/PCI Reference PCI LOCAL BUS The PCI Local Bus pin assignments shown below are for the PCI option slots on the PIN ASSIGNMENTS backplane. The PCI Local Bus specifies both 5-volt and 3.3-volt signaling environments. The following bus pin assignments are for the 5-volt connector. The 3.3-volt connector bus pin assignments are the same with the following exceptions: * The pins noted as +V (I/O) are +5 volts or +3.3 volts, depending on which connector is being used. † Pins B12, B13, A12 and A13 are Gnd (ground) on the 5-volt connector, but are Connector Keys on the 3.3-volt connector. †† Pin B49 is Gnd (ground) on the 5-volt connector, but is M66EN on the 3.3- volt connector. ††† Pins B50, B51, A50 and A51 are Connectors Keys on the 5-volt connector, but are Gnd (ground) on the 3.3-volt connector. I/O Pin Signal Name I/O Pin Signal Name B1 -12V A1 TRST# 32-bit connector B2 TCK A2 +12V B3 Gnd A3 TMS B4 TDO A4 TDI B5 +5V A5 +5V B6 +5V A6 INTA# B7 INTB# A7 INTC# B8 INTD# A8 +5V B9 PRSNT1# A9 Reserved B10 Reserved A10 +V (I/O) * B11 PRSNT2# A11 Reserved B12 Gnd † A12 Gnd † B13 Gnd † A13 Gnd † B14 Reserved A14 Reserved B15 Gnd A15 RST# B16 CLK A16 +V (I/O) * B17 Gnd A17 GNT# B18 REQ# A18 Gnd B19 +V (I/O) * A19 Reserved B20 AD31 A20 AD30 B21 AD29 A21 +3.3V B22 Gnd A22 AD28 B23 AD27 A23 AD26 B24 AD25 A24 Gnd B25 +3.3V A25 AD24 B26 C/BE3# A26 IDSEL B27 AD23 A27 +3.3V B28 Gnd A28 AD22 B29 AD21 A29 AD20 B30 AD19 A30 Gnd B31 +3.3V A31 AD18 B32 AD17 A32 AD16 B33 C/BE2# A33 +3.3V B34 Gnd A34 FRAME# B35 IRDY# A35 Gnd TRENTON Technology Inc. 2-11 ISA/PCI Reference T4I Technical Reference PCI LOCAL BUS PIN ASSIGNMENTS (CONTINUED) I/O Pin Signal Name I/O Pin Signal Name B36 +3.3V A36 TRDY# B37 DEVSEL# A37 Gnd B38 Gnd A38 STOP# B39 LOCK# A39 +3.3V B40 PERR# A40 SDONE B41 +3.3V A41 SBO# B42 SERR# A42 Gnd B43 +3.3V A43 PAR B44 C/BE1# A44 AD15 B45 AD14 A45 +3.3V B46 Gnd A46 AD13 B47 AD12 A47 AD11 B48 AD10 A48 Gnd B49 Gnd †† A49 AD9 B50 Connector Key ††† A50 Connector Key ††† 5-volt key B51 Connector Key ††† A51 Connector Key ††† 5-volt key B52 AD8 A52 C/BE0# B53 AD7 A53 +3.3V B54 +3.3V A54 AD6 B55 AD5 A55 AD4 B56 AD3 A56 Gnd B57 Gnd A57 AD2 B58 AD1 A58 AD0 B59 +V (I/O) * A59 +V (I/O) * B60 ACK64# A60 REQ64# B61 +5V A61 +5V B62 +5V A62 +5V 32-bit connector end 2-12 TRENTON Technology Inc. T4I Technical Reference ISA/PCI Reference PCI LOCAL BUS The following pin assignments apply only to backplanes with 64-bit PCI option slots. PIN ASSIGNMENTS (CONTINUED) I/O Pin Signal Name I/O Pin Signal Name Connector Key Connector Key 64-bit spacer Connector Key Connector Key 64-bit spacer B63 Reserved A63 Gnd 64-bit connector start B64 Gnd A64 C/BE7# B65 C/BE6# A65 C/BE5# B66 C/BE4# A66 +V (I/O) * B67 Gnd A67 PAR64 B68 AD63 A68 AD62 B69 AD61 A69 Gnd B70 +V (I/O) * A70 AD60 B71 AD59 A71 AD58 B72 AD57 A72 Gnd B73 Gnd A73 AD56 B74 AD55 A74 AD54 B75 AD53 A75 +V (I/O) * B76 Gnd A76 AD52 B77 AD51 A77 AD50 B78 AD49 A78 Gnd B79 +V (I/O) * A79 AD48 B80 AD47 A80 AD46 B81 AD45 A81 Gnd B82 Gnd A82 AD44 B83 AD43 A83 AD42 B84 AD41 A84 +V (I/O) * B85 Gnd A85 AD40 B86 AD39 A86 AD38 B87 AD37 A87 Gnd B88 +V (I/O) * A88 AD36 B89 AD35 A89 AD34 B90 AD33 A90 Gnd B91 Gnd A91 AD32 B92 Reserved A92 Reserved B93 Reserved A93 Gnd 64-bit connector end B94 Gnd A94 Reserved TRENTON Technology Inc. 2-13 ISA/PCI Reference T4I Technical Reference PCI LOCAL BUS The PCI Local Bus signals are described below and may be categorized into the SIGNAL following functional groups: DESCRIPTIONS System Pins Address and Data Pins Interface Control Pins Arbitration Pins (Bus Masters Only) Error Reporting Pins Interrupt Pins (Optional) Cache Support Pins (Optional) 64-Bit Bus Extension Pins (Optional) JTAG/Boundary Scan Pins (Optional) A # symbol at the end of a signal name indicates that the active state occurs when the signal is at a low voltage. When the # symbol is absent, the signal is active at a high voltage. The following are descriptions of the PCI Local Bus signals. ACK64# (optional) Acknowledge 64-bit Transfer, when actively driven by the device that has positively decoded its address as the target of the current access, indicates the target is willing to transfer data using 64bits. ACK64# has the same timing as DEVSEL#. AD[31::00] Address and Data are multiplexed on the same PCI pins. A bus transaction consists of an address phase followed by one or more data phases. During the address phase, AD[31::00] contain a physical address (32 bits). During data phases, AD[07::00] contain the least signif- icant byte (lsb) and AD[31::24] contain the most signficant byte (msb). AD[63::32] (optional) Address and Data are multiplexed on the same pins and provide 32additional bits. During an address phase (when using the DAC command and when REQ64# is asserted), the upper 32bits of a 64-bit address are transferred; otherwise, these bits are reserved but are stable and indeterminate. During a data phase, an additional 32bits of data are transferred when REQ64# and ACK64# are both asserted. C/BE[3::0]# Bus Command and Byte Enables are multiplexed on the same PCI pins. During the address phase of a transaction, these pins define the bus command; during the data phase they are used as byte enables. The byte enables are valid for the entire data phase and determine which byte lanes carry meaningful data. C/BE0# applies to byte0 (lsb) and C/BE3# applies to byte 3 (msb). 2-14 TRENTON Technology Inc. T4I Technical Reference ISA/PCI Reference C/BE[7::4]# (optional) Bus Command and Byte Enables are multiplexed on the same pins. During an address phase (when using the DAC command and when REQ64# is asserted), the actual bus command is transferred on C/BE[7::4]#; otherwise, these bits are reserved and indeterminate. During a data phase, C/BE[7::4]# are byte enables indicating which byte lanes carry meaningful data when REQ64# and ACK64# are both asserted. C/BE4# applies to byte4 and C/BE7# applies to byte7. CLK Clock provides timing for all transactions on PCI and is an input to every PCI device. DEVSEL# Device Select, when actively driven, indicates that the driving device has decoded its address as the target of the current access. As an input, DEVSEL# indicates whether any device on the bus has been selected. FRAME# Cycle Frame is an interface control pin which is driven by the current master to indicate the beginning and duration of an access. When FRAME# is asserted, data transfers continue; when it is deasserted, the transaction is in the final data phase. GNT# Grant indicates to the agent that access to the bus has been granted. This is a point to point signal. Every master has its own GNT#. IDSEL Initialization Device Select is used as a chip select during configuration read and write transac- tions. INTA#, INTB#, INTC#, INTD# (optional) Interrupts on PCI are optional and defined as "level sensitive," asserted low (negative true), using open drain output drivers. PCI defines one interrupt for a single function and up to four interrupt lines for a multi-function device or connector. Interrupt A is used to request an interrupt. For a single function device, only INTA# may be used, while the other three interrupt lines have no meaning. Interrupt B, Interrupt C and Interrupt D are used to request additional interrupts and only have meaning on a multi-function device. IRDY# Initiator Ready indicates the initiating agent’s (bus master’s) ability to complete the current data phase of the transaction. IRDY# is used in conjunction with TRDY#. During a write, IRDY# indicates that valid data is present on AD[31::0]. During a read, it indicates that the master is prepared to accept data. LOCK# Lock indicates an operation that may require multiple transactions to complete. When LOCK# is asserted, non-exclusive transactions may proceed to an address that is not currently locked. TRENTON Technology Inc. 2-15 ISA/PCI Reference T4I Technical Reference PAR Parity is even parity across AD[31::00] and C/BE[3::0]#. Parity generation is required by all PCI agents. The master drives PAR for address and write data phases; the target drives PAR for read data phases. PAR64 (optional) Parity Upper DWORD is the even parity bit that protects AD[63::32] and C/BE[7::4]#. The master drives PAR64 for address and write data phases; the target drives PAR64 for read data phases. PERR# Parity Error is for the reporting of data parity errors during all PCI transactions except a Special Cycle. There are no special conditions when a data parity error may be lost or when reporting of an error may be delayed. PRSNT1# and PRSNT2# PRSNT1# and PRSNT2# are related to the connector only, not to other PCI components. They are used for two purposes: indicating that a board is physically present in the slot and providing information about the total power requirements of the board. REQ# Request indicates to the arbiter that this agent desires use of the bus. This is a point to point signal. Every master has its own REQ#. REQ64# (optional) Request 64-bit Transfer, when actively driven by the current bus master, indicates it desires to transfer data using 64 bits. REQ64# has the same timing as FRAME#. REQ64# has meaning at the end of reset. RST# Reset is used to bring PCI-specific registers, sequencers and signals to a consistent state. SBO# (optional) Snoop Backoff is an optional cache support pin which indicates a hit to a modified line when asserted. When SBO# is deasserted and SDONE is asserted, it indicates a "clean" snoop result. SDONE (optional) Snoop Done is an optional cache support pin which indicates the status of the snoop for the current access. When deasserted, it indicates the result of the snoop is still pending. When asserted, it indicates the snoop is complete. SERR# System Error is for reporting address parity errors, data parity errors on the Special Cycle command, or any other system error where the result will be catastrophic. If an agent does not want a non-maskable interrupt (NMI) to be generated, a different reporting mechanism is required. 2-16 TRENTON Technology Inc. T4I Technical Reference ISA/PCI Reference STOP# Stop indicates that the current target is requesting the master to stop the current transaction. TCK (optional) Test Clock is used to clock state information and test data into and out of the device during operation of the TAP (Test Access Port). TDI (optional) Test Data Input is used to serially shift test data and test instructions into the device during TAP (Test Access Port) operation. TDO (optional) Test Data Output is used to serially shift test data and test instructions out of the device during TAP (Test Access Port) operation. TMS (optional) Test Mode Select is used to control the state of the TAP (Test Access Port) controller in the device. TRDY# Target Ready indicates the target agent’s (selected device’s) ability to complete the current data phase of the transaction. TRDY# is used in conjunction with IRDY#. During a read, TRDY# indicates that valid data is present on AD[31::00]. During a write, it indicates that the target is prepared to accept data. TRST# (optional) Test Reset provides an asynchronous initialization of the TAP controller. This signal is optional in the IEEE Standard Test Access Port and Boundary Scan Architecture. TRENTON Technology Inc. 2-17 ISA/PCI Reference T4I Technical Reference PICMG EDGE The pin assignments shown below are for the PICMG portion of the edge connector on CONNECTOR PIN the processor board. These pin assignments match those of the PICMG connector of the ASSIGNMENTS processor slot on the backplane. I/O Pin Signal Name I/O Pin Signal Name B1 -12V A1 NC 32-bit connector start B2 NC A2 +12V B3 Gnd A3 NC B4 NC A4 NC B5 +5V A5 +5V B6 +5V A6 INTA# B7 INTB# A7 INTC# B8 INTD# A8 +5V B9 REQ3# A9 CLKS2 B10 REQ1# A10 +5V B11 GNT3# A11 CLKS3 B12 Gnd A12 Gnd B13 Gnd A13 Gnd B14 CLKS0 A14 GNT1# B15 Gnd A15 RST# B16 CLKS1 A16 +5V B17 Gnd A17 GNT0# B18 REQ0# A18 Gnd B19 +5V A19 REQ2# B20 AD31 A20 AD30 B21 AD29 A21 NC B22 Gnd A22 AD28 B23 AD27 A23 AD26 B24 AD25 A24 Gnd B25 BKPL3.3V A25 AD24 B26 C/BE3# A26 GNT2# B27 AD23 A27 NC B28 Gnd A28 AD22 B29 AD21 A29 AD20 B30 AD19 A30 Gnd B31 NC A31 AD18 B32 AD17 A32 AD16 B33 C/BE2# A33 NC B34 Gnd A34 FRAME# B35 IRDY# A35 Gnd B36 NC A36 TRDY# B37 DEVSEL# A37 Gnd B38 Gnd A38 STOP# B39 LOCK# A39 NC B40 PERR# A40 SDONE B41 NC A41 SBO# B42 SERR# A42 Gnd B43 NC A43 PAR B44 C/BE1# A44 AD15 B45 AD14 A45 NC B46 Gnd A46 AD13 B47 AD12 A47 AD11 B48 AD10 A48 Gnd B49 M66EN A49 AD9 2-18 TRENTON Technology Inc. T4I Technical Reference ISA/PCI Reference PICMG EDGE CONNECTOR PIN ASSIGNMENTS (CONTINUED) I/O Pin Signal Name I/O Pin Signal Name B50 Connector Key A50 Connector Key B51 Connector Key A51 Connector Key B52 AD8 A52 C/BE0# B53 AD7 A53 NC B54 NC A54 AD6 B55 AD5 A55 AD4 B56 AD3 A56 Gnd B57 Gnd A57 AD2 B58 AD1 A58 AD0 B59 +5V A59 +5V B60 ACK64# A60 REQ64# B61 +5V A61 +5V B62 +5V A62 +5V 32-bit connector end TRENTON Technology Inc. 2-19 ISA/PCI Reference T4I Technical Reference PICMG EDGE The following pin assignments apply only to SBCs with 64-bit PICMG connectors. CONNECTOR PIN ASSIGNMENTS (CONTINUED) I/O Pin Signal Name I/O Pin Signal Name Connector Key Connector Key 64-bit spacer Connector Key Connector Key 64-bit spacer B63 NC A63 Gnd 64-bit connector start B64 Gnd A64 C/BE7# B65 C/BE6# A65 C/BE5# B66 C/BE4# A66 +5V B67 Gnd A67 PAR64 B68 AD63 A68 AD62 B69 AD61 A69 Gnd B70 +5V A70 AD60 B71 AD59 A71 AD58 B72 AD57 A72 Gnd B73 Gnd A73 AD56 B74 AD55 A74 AD54 B75 AD53 A75 +5V B76 Gnd A76 AD52 B77 AD51 A77 AD50 B78 AD49 A78 Gnd B79 +5V A79 AD48 B80 AD47 A80 AD46 B81 AD45 A81 Gnd B82 Gnd A82 AD44 B83 AD43 A83 AD42 B84 AD41 A84 +5V B85 Gnd A85 AD40 B86 AD39 A86 AD38 B87 AD37 A87 Gnd B88 +5V A88 AD36 B89 AD35 A89 AD34 B90 AD33 A90 Gnd B91 Gnd A91 AD32 B92 NC A92 NC B93 NC A93 Gnd B94 Gnd A94 NC 64-bit connector end Copyright 2002 by Trenton Technology Inc. All rights reserved. 2-20 TRENTON Technology Inc. T4I Technical Reference System BIOS Chapter 3 System BIOS BIOS OPERATION Sections 3 through 7 of this manual describe the operation of the American Megatrends AMIBIOS and the BIOS Setup Utility. Refer to Running AMIBIOS Setup later in this chapter for standard Setup screens, options and defaults. The available Setup screens, options and defaults may vary if you have a custom BIOS. When the system is powered on, AMIBIOS performs the Power-On Self Test (POST) routines. These routines are divided into two phases: 1) System Test and Initialization. Test and initialize system boards for normal operations. 2) System Configuration Verification. Compare defined configuration with hardware actually installed. If an error is encountered during the diagnostic tests, the error is reported in one of two different ways. If the error occurs before the display device is initialized, a series of beeps is transmitted. If the error occurs after the display device is initialized, the error message is displayed on the screen. See BIOS Errors later in this section for more infor- mation on error handling. The following are some of the Power-On Self Tests (POST’s) which are performed when the system is powered on: CMOS Checksum Calculation Keyboard Controller Test CMOS Shutdown Register Test 8254 Timer Test Memory Refresh Test Display Memory Read/Write Test Display Type Verification Entering Protected Mode Memory Size Calculation Conventional and Extended Memory Test DMA Controller Tests Keyboard Test System Configuration Verification and Setup AMIBIOS checks system memory and reports it on both the initial AMIBIOS screen and the AMIBIOS System Configuration screen which appears after POST is completed. AMIBIOS attempts to initialize the peripheral devices and if it detects a fault, the screen displays the error condition(s) which has/have been detected. If no errors are detected, AMIBIOS attempts to load the system from a bootable device, such as a floppy disk or hard disk. Boot order may be specified by the Boot Device Priority option on the Boot Setup Menu as described in the Boot Setup chapter later in this manual. TRENTON Technology Inc. 3-1 System BIOS T4I Technical Reference Normally, the only POST routine visible on the screen is the memory test. The following screen displays when the system is powered on: AMIBIOS (C)2002 American Megatrends, Inc. TRENTON Technology Inc. Press DEL to run Setup Initial Power-On Screen You have two options: Press to access the BIOS Setup Utility. This option allows you to change various system parameters such as date and time, disk drives, etc. The Running AMIBIOS Setup section of this manual describes the options available. You may be requested to enter a password before gaining access to the BIOS Setup Utility. (See Password Entry later in this section.) If you enter the correct password or no password is required, the BIOS Setup Utility Main Menu displays. (See Running AMIBIOS Setup later in this section.) Allow the bootup process to continue without invoking the BIOS Setup Utility. In this case, after AMIBIOS loads the system, you may be requested to enter a password. (See Password Entry later in this section.) Once the POST routines complete successfully, a screen displays showing the current configuration of your system, including processor type, base and extended memory amounts, floppy and hard drive types, display type and peripheral ports. Password Entry The system may be configured so that the user is required to enter a password each time the system boots or whenever an attempt is made to enter the BIOS Setup Utility. The password function may also be disabled so that the password prompt does not appear under any circumstances. The Password Check option in the Security Menu allows you to specify when the password prompt displays: Always or only when Setup is attempted. This option is available only if the supervisor and/or user password(s) have been established. The supervisor and user passwords may be changed using the Change Supervisor Password and Change User Password options on the Security Menu. If the passwords are null, the password prompt does not display at any time. See the Security Setup section of this chapter for details on setting up passwords. 3-2 TRENTON Technology Inc. T4I Technical Reference System BIOS When password checking is enabled, the following password prompt displays: Enter CURRENT Password: Type the password and press . _______________________________________________________________________ NOTE: The null password is the system default and is in effect if a password has not been assigned or if the CMOS has been corrupted. In this case, the password prompt does not display. To set up passwords, you may use the Change Supervisor Password and Change User Password options on the Security Menu of the BIOS Setup Utility. (See the Security Setup section later in this chapter.) _______________________________________________________________________ If an incorrect password is entered, the following screen displays: Enter CURRENT Password: X Enter CURRENT Password: You may try again to enter the correct password. If you enter the password incorrectly three times, the system responds in one of two different ways, depending on the value specified in the Password Check option on the Security Menu: 1) If the Password Check option is set to Setup, the system does not let you enter Setup, but does continue the booting process. You must reboot the system manually to retry entering the password. 2) If the Password Check option is set to Always, the system locks and you must reboot. After rebooting, you will be requested to enter the password. Once the password has been entered correctly, you are allowed to continue. BIOS Errors If an error is encountered during the diagnostic checks performed when the system is powered on, the error is reported in one of two different ways: TRENTON Technology Inc. 3-3 System BIOS T4I Technical Reference 1) If the error occurs before the display device is initialized, a series of beeps is transmitted. 2) If the error occurs after the display device is initialized, the screen displays the error message. In the case of a non-fatal error, a prompt to press the key may also appear on the screen. Explanations of the beep codes and BIOS error messages may be found in Appendix A - BIOS Messages. As the POST routines are performed, test codes are presented on Port 80H. These codes may be helpful as a diagnostic tool and are listed in Appendix A - BIOS Messages. If certain non-fatal error conditions occur, you are requested to run the BIOS Setup Utility. The error messages are followed by this screen: AMIBIOS (C)2002 American Megatrends, Inc. TRENTON Technology Inc. Press F1 to Run SETUP Press F2 to load default values and continue Press . You may be requested to enter a password before gaining access to the BIOS Setup Utility. (See Password Entry earlier in this section.) If you enter the correct password or no password is required, the BIOS Setup Utility Main Menu displays. 3-4 TRENTON Technology Inc. T4I Technical Reference System BIOS RUNNING AMIBIOS Setup keeps a record of system parameters, such as date and time, disk drives, AMIBIOS SETUP display type and other user-defined parameters. The Setup parameters reside in the Read Only Memory Basic Input/Output System (ROM BIOS) so that they are available each time the system is turned on. The BIOS Setup Utility stores the information in the complementary metal oxide semiconductor (CMOS) memory. When the system is turned off, a backup battery retains system parameters in the CMOS memory. Each time the system is powered on, it is configured with these values, unless the CMOS has been corrupted or is faulty. The BIOS Setup Utility is resident in the ROM BIOS so that it is available each time the computer is turned on. If, for some reason, the CMOS becomes corrupted, the system is configured with the default values stored in this ROM file. As soon as the system is turned on, the power-on diagnostic routines check memory, attempt to prepare peripheral devices for action, and offer you the option of pressing to run the BIOS Setup Utility. If certain non-fatal errors occur during the Power-On Self Test (POST) routines which are run when the system is turned on, you may be prompted to run the BIOS Setup Utility by pressing . TRENTON Technology Inc. 3-5 System BIOS T4I Technical Reference BIOS SETUP When you press in response to an error message received during the POST UTILITY MAIN routines or when you press the key to enter the BIOS Setup Utility, the following MENU screen displays: BIOS SETUP UTILITY Main Advanced PCIPnP Chipset Boot Security Exit System Overview Use [ENTER], {TAB] _____________________________________________ or [SHIFT-TAB] to select a field. AMIBIOS Version: 08.00.xx BIOS Build Date: 06/20/02 Use [+] or [-] to BIOS ID : 0ABAF013 configure System Time. Processor Type : Intel(r) Pentium(r) 4 Proc Speed : 2000MHz Count : 1 System Memory ←→ Select Screen Size : 1024MB ↑↓ Select Item +- Change Field System Time [00:00:00] Tab Select Field System Date [Mon 01/01/2001] F1 General Help F10 Save and Exit ESC Exit vxx.xx (C)Copyright 1985-2001, American Megatrends, Inc. BIOS Setup Utility Main Menu When you display the BIOS Setup Utility Main Menu, the format is similar to the sample shown above. The data displayed on the top portion of the screen details parameters detected by AMIBIOS for your processor board and may not be modified. The system time and date displayed on the bottom portion of the screen may be modified. BIOS SETUP The descriptions for the system options listed below show the values as they appear if you have not changed them yet. Once values have been defined, they display each time UTILITY MAIN the BIOS Setup Utility is run. MENU OPTIONS System Time/System Date These options allow you to set the correct system time and date. If you do not set these parameters the first time you enter the BIOS Setup Utility, you will receive a "Run SETUP" error message when you boot the system until you set the correct parameters. The Setup screen displays the system options: System Time [00:00:00] System Date [Mon 01/01/2001] 3-6 TRENTON Technology Inc. T4I Technical Reference System BIOS There are three fields for entering the time or date. Use the key or the key to move from one field to another and type in the correct value for the field. If you enter an invalid value in any field, the screen will revert to the previous value when you move to the next field. When you change the value for the month, day or year field, the day of the week changes automatically when you move to the next field. BIOS SETUP The BIOS Setup Utility allows you to change system parameters to tailor your system to your requirements. Various options which may be changed are listed below. Further UTILITY OPTIONS explanations of these options and available values may be found in later chapters of this manual, as noted below. _______________________________________________________________________ NOTE: Do not change the values for any option unless you understand the impact on system operation. Depending on your system configuration, selection of other values may cause unreliable system operation. _______________________________________________________________________ Use the Right Arrow key to display the desired menu. The following menus are available: Select Advanced to make changes to Advanced Setup parameters as described in the Advanced Setup chapter of this manual. The following options may be modified: CPU Configuration CPU Ratio CMOS Setting IDE Configuration OnBoard PCI IDE Controller Primary IDE Master/Primary IDE Slave Secondary IDE Master/Secondary IDE Slave Type LBA/Large Mode Block (Multi-Sector Transfer) PIO Mode DMA Mode S.M.A.R.T. 32Bit Data Transfer ARMD Emulation Type Hard Disk Write Protect IDE Detect Time Out (Sec) ATA(PI) 80Pin Cable Detection TRENTON Technology Inc. 3-7 System BIOS T4I Technical Reference Floppy Configuration Floppy A/Floppy B SuperIO Configuration OnBoard Floppy Controller Serial Port1 Address/Serial Port2 Address Serial Port2 IRQ Serial Port2 Mode Parallel Port Address Parallel Port Mode Parallel Port IRQ DMI Event Logging View Event Log Mark All Events as Read Clear Event Log Event Log Statistics Remote Access Configuration Remote Access Serial Port Number Serial Port Mode Post-Boot Support USB Configuration USB Function Legacy USB Support USB ZIP Emulation Type USB Beep Message Select PCIPnP to make changes to PCI Plug and Play Setup parameters as described in the PCI Plug and Play Setup chapter of this manual. The following options may be modified: On Board SCSI On Board (Intel 82540) Lan2 On Board VGA Plug & Play O/S Reset Config Data PCI Latency Timer 3-8 TRENTON Technology Inc. T4I Technical Reference System BIOS Allocate IRQ to PCI VGA Palette Snooping PCI IDE BusMaster OffBoard PCI/ISA IDE Card OffBoard PCI IDE Primary IRQ OffBoard PCI IDE Secondary IRQs 3, 4, 5, 7, 9, 10, 11, 12, 14 and 15 DMA Channels 0, 1, 3 5, 6 and 7 Reserved Memory Size Reserved Memory Address Select Chipset to make changes to Chipset Setup parameters as described in the Chipset Setup chapter of this manual. The following options may be modified: Intel ICH4 SouthBridge Configuration ICH4 Dev31 Func1, IDE ICH4 Dev31 Func3, SMBUS ICH4 Dev29 Func0, USB#1 ICH4 Dev29 Func7, ECHI LPC 4Eh-4Fh Decode/LPC 2Eh/2Fh Decode On Board Lan ISA BUS IOAPIC Extended IOAPIC CPU B.I.S.T. ICH4 DMA Collection PC/PCIB Select DMA Types 0, 1, 2, 3, 5, 6 and 7 Select Boot to make changes to Boot Setup parameters as described in the Boot Setup chapter of this manual. The following options may be modified: Boot Settings Configuration Quick Boot Quiet Boot AddOn ROM Display Mode Bootup Num-Lock TRENTON Technology Inc. 3-9 System BIOS T4I Technical Reference PS/2 Mouse Support System Keyboard Boot To OS/2 Wait For ‘F1’ If Error Hit ‘DEL’ Message Display Boot Device Priority Hard Disk Drives Removable Devices ATAPI CDROM Drives Interrupt 19 Capture Select Security to establish or change the supervisor or user password or to enable boot sector virus protection. These functions are described later in this chapter. The following options may be modified: Change Supervisor Password User Access Level Password Check Change User Password Unattended Start Password Check Clear User Password Boot Sector Virus Protection Select Exit to save or discard changes you have made to AMIBIOS param- eters or to load the Optimal or Failsafe default settings. These functions are described later in this chapter. The following options are available: Save Changes and Exit Discard Changes and Exit Discard Changes Load Optimal Defaults Load Failsafe Defaults 3-10 TRENTON Technology Inc. T4I Technical Reference System BIOS SECURITY SETUP When you select Security from the BIOS Setup Utility Main Menu, the following Setup screen displays: BIOS SETUP UTILITY Main Advanced PCIPnP Chipset Boot |Security| Exit Security Settings Install or Change the _____________________________________________ password. Supervisor Password :Not Installed User Password :Not Installed Change Supervisor Password Change User Password Clear User Password Boot Sector Virus Protection [Disabled] ←→ Select Screen ↑↓ Select Item Enter Change F1 General Help F10 Save and Exit ESC Exit vxx.xx (C)Copyright 1985-2001, American Megatrends, Inc. Security Setup Screen When you display the Security Setup screen, the format is similar to the sample shown above. Highlight the option you wish to change and press . _______________________________________________________________________ NOTE: The values on this screen do not necessarily reflect the values appropriate for your SBC. Refer to the explanations below for specific instructions about entering correct information. _______________________________________________________________________ SECURITY SETUP The Security Setup options allow you to establish, change or clear the supervisor or user password and to enable boot sector virus protection. OPTIONS The descriptions for the system options listed below show the values as they appear if you have not changed them yet. Once values have been defined, they display each time the BIOS Setup Utility is run. CHANGE This option allows you to establish a supervisor password, change the current password SUPERVISOR or disable the password prompt by entering a null password. The password is stored in PASSWORD CMOS RAM. If you have signed on under the user password, this option is not available. TRENTON Technology Inc. 3-11 System BIOS T4I Technical Reference The Change Supervisor Password feature can be configured so that a password must be entered each time the system boots or just when a user attempts to enter the BIOS Setup Utility. _______________________________________________________________________ NOTE: The null password is the system default and is in effect if a password has not been assigned or if the CMOS has been corrupted. In this case, the "Enter CURRENT Password" prompt is bypassed when you boot the system, and you must establish a new password. _______________________________________________________________________ If you select the Change Supervisor Password option, the following window displays: Enter New Password This is the message which displays before you have established a password, or if the last password entered was the null password. If a password has already been established, you are asked to enter the current password before being prompted to enter the new password. Type the new password and press . The password cannot exceed six (6) characters in length. The screen displays an asterisk (*) for each character you type. After you have entered the new password, the following window displays: Confirm New Password Re-key the new password as described above. If the password confirmation is miskeyed, AMIBIOS Setup displays the following message: Passwords do not match! [Ok] No retries are permitted; you must restart the procedure. If the password confirmation is entered correctly, the following message displays: Password installed [Ok] 3-12 TRENTON Technology Inc. T4I Technical Reference System BIOS Press the key to return to the Security screen. Installed displays on the screen next to the Supervisor Password option, indicating the password has been accepted. This setting will remain in effect until the supervisor password is either disabled or discarded upon exiting the BIOS Setup Utility. If you have created a new password, be sure to select Exit, then Save Changes and Exit to save the password. The password is then stored in CMOS RAM. The next time the system boots, you are prompted for the password. _______________________________________________________________________ NOTE: Be sure to keep a record of the new password each time it is changed. If you forget it, use the Password Clear jumper to reset it to the default (null password). See the Specifications chapter of this manual for details. _______________________________________________________________________ If a password has been established, the following options and their default values are added to the screen: User Access Level [Full Access] Password Check [Setup] User Access Level This option allows you to define the level of access the user will have to the system. The Setup screen displays the system option: User Access Level [Full Access] Four options are available: Select No Access to prevent user access to the BIOS Setup Utility. Select View Only to allow access to the BIOS Setup Utility for viewing, but to prevent the user from changing any of the fields. Select Limited to allow the user to change only a limited number of options, such as Date and Time. Select Full Access to allow the user full access to change any option in the BIOS Setup Utility. Password Check This option determines when a password is required for access to the system. The Setup screen displays the system option: Password Check [Setup] TRENTON Technology Inc. 3-13 System BIOS T4I Technical Reference Two options are available: Select Setup to have the password prompt appear only when an attempt is made to enter the BIOS Setup Utility program. Select Always to have the password prompt appear each time the system is powered on. DISABLING THE To disable password checking so that the password prompt does not appear, you may SUPERVISOR create a null password selecting the Change Supervisor Password function and PASSWORD pressing without typing in a new password. You will be asked to enter the current password before being allowed to enter the null password. After you press at the Enter New Password prompt, the following message displays: Password uninstalled [Ok] CHANGE USER The Change User Password option is similar in functionality to the Change Supervisor PASSWORD Password and displays the same messages. If you have signed on under the user password, the Change Supervisor Password function is not available for modification. If a user password has been established, the Password Check option and its default value is added to the screen. This option determines when a user password is required for access to the system. For details, refer to the description for Password Check under the Change Supervisor Password heading earlier in this section. CLEAR USER This option allows you to clear the user password. It disables the user password by PASSWORD entering a null password. If you select the Clear User Password option, the following window displays: Clear User Password? [Ok] [Cancel] You have two options: Select Ok to clear the user password. Select Cancel to leave the current user password in effect. BOOT SECTOR This option allows you to request AMIBIOS to issue a warning when any program or VIRUS PROTECTION virus issues a Disk Format command or attempts to write to the boot sector of the hard disk drive. 3-14 TRENTON Technology Inc. T4I Technical Reference System BIOS The Setup screen displays the system option: Boot Sector Virus Protection [Disabled] Available options are: Disabled Enabled _______________________________________________________________________ NOTE: You should not enable boot sector virus protection when formatting a hard drive. _______________________________________________________________________ TRENTON Technology Inc. 3-15 System BIOS T4I Technical Reference This page intentionally left blank. 3-16 TRENTON Technology Inc. T4I Technical Reference System BIOS EXIT MENU When you select Exit from the BIOS Setup Utility Main Menu, the following screen displays: BIOS SETUP UTILITY Main Advanced PCIPnP Chipset Boot Security |Exit| Exit Options Exit system setup _____________________________________________ after saving the Save Changes and Exit changes. Discard Changes and Exit Discard Changes F10 key can be used Load Optimal Defaults this operation. Load Failsafe Defaults ←→ Select Screen ↑↓ Select Item Enter Go to Sub Screen F1 General Help F10 Save and Exit ESC Exit vxx.xx (C)Copyright 1985-2001, American Megatrends, Inc. Exit Menu Screen When you display the Exit Menu screen, the format is similar to the sample shown above. Highlight the option you wish to select and press . EXIT MENU When you are running the BIOS Setup Utility program, you may either save or discard changes you have made to AMIBIOS parameters, or you may load the Optimal or OPTIONS Failsafe default settings. Save Changes and Exit The features selected and configured in the Setup screens are stored in the CMOS when this option is selected. The CMOS checksum is calculated and written to the CMOS. Control is then passed back to the AMIBIOS and the booting process continues, using the new CMOS values. If you select the Save Changes and Exit option, the following window displays: Save configuration changes and exit setup? [Ok] [Cancel] TRENTON Technology Inc. 3-17 System BIOS T4I Technical Reference You have two options: Select Ok to save the system parameters and continue with the booting process. Select Cancel to return to the BIOS Setup Utility screen. Discard Changes and Exit When the Discard Changes and Exit option is selected, the BIOS Setup Utility exits without saving the changes in the CMOS. Control is then passed back to AMIBIOS and the booting process continues, using the previous CMOS values. If you select the Discard Changes and Exit option, the following window displays: Discard changes and exit setup? [Ok] [Cancel] You have two options: Select Ok to continue the booting process without writing any changes to the CMOS. Select Cancel to return to the BIOS Setup Utility screen. Discard Changes When the Discard Changes option is selected, the BIOS Setup Utility resets any param- eters you have changed back to the values at which they were set when you entered the Setup Utility. Control is then passed back to the BIOS Setup Utility screen. If you select the Discard Changes option, the following window displays: Discard changes? [Ok] [Cancel] You have two options: Select Ok to reset any parameters you have changed back to the values at which they were set when you entered the BIOS Setup Utility. This option then returns you to the BIOS Setup Utility screen. Select Cancel to return to the BIOS Setup Utility screen without discarding any changes you have made. 3-18 TRENTON Technology Inc. T4I Technical Reference System BIOS Load Optimal or Failsafe Defaults Each AMIBIOS Setup option has two default settings (Optimal and Failsafe). These settings can be applied to all AMIBIOS Setup options when you select the appropriate configuration option from the BIOS Setup Utility Main Menu. You can use these configuration options to quickly set the system configuration param- eters which should provide the best performance characteristics, or you can select a group of settings which have a better chance of working when the system is having configuration-related problems. Load Optimal Defaults This option allows you to load the Optimal default settings. These settings are best-case values which should provide the best performance characteristics. If CMOS RAM is corrupted, the Optimal settings are loaded automatically. If you select the Load Optimal Defaults option, the following window displays: Load Optimal Defaults? [Ok] [Cancel] You have two options: Select Ok to load the Optimal default settings. Select Cancel to leave the current values in effect. Load Failsafe Defaults This option allows you to load the Failsafe default settings when you cannot boot your computer successfully. These settings are more likely to configure a workable computer. They may not provide optimal performance, but are the most stable settings. You may use this option as a diagnostic aid if your system is behaving erratically. Select the Failsafe settings and then try to diagnose the problem after the computer boots. If you select the Load Failsafe Defaults option, the following window displays: Load Failsafe Defaults? [Ok] [Cancel] TRENTON Technology Inc. 3-19 System BIOS T4I Technical Reference You have two options: Select Ok to load the Failsafe default settings. Select Cancel to leave the current values in effect. Copyright 2002 by Trenton Technology Inc. All rights reserved. 3-20 TRENTON Technology Inc. T4I Technical Reference Advanced Setup Chapter 4 Advanced Setup ADVANCED SETUP When you select Advanced from the BIOS Setup Utility Main Menu, the following Setup screen displays: BIOS SETUP UTILITY Main |Advanced| PCIPnP Chipset Boot Security Exit Advanced Settings Configure the CPU. ______________________________________________ WARNING: Setting wrong values in below sections may cause system to malfunction. > CPU Configuration > IDE Configuration > Floppy Configuration > SuperIO Configuration > DMI Event Logging > Remote Access Configuration > USB Configuration ←→ Select Screen ↑↓ Select Item Enter Go to Sub Screen F1 General Help F10 Save and Exit ESC Exit vxx.xx (C)Copyright 1985-2001, American Megatrends, Inc. Advanced Setup Screen When you display the Advanced Setup screen, the format is similar to the sample shown above, allowing you to continue to subscreens designed to change parameters for each of the Advanced Setup options. Highlight the option you wish to change and press to proceed to the appropriate subscreen. _______________________________________________________________________ NOTE: The values on the Advanced Setup subscreens do not necessarily reflect the values appropriate for your SBC. Refer to the explanations following each screen for specific instructions about entering correct information. _______________________________________________________________________ ADVANCED SETUP _______________________________________________________________________ OPTIONS NOTE: Do not change the values for any Advanced Setup option unless you understand the impact on system operation. Depending on your system configuration, selection of other values may cause unreliable system operation. _______________________________________________________________________ TRENTON Technology Inc. 4-1 Advanced Setup T4I Technical Reference CPU Configuration The CPU Configuration subscreen provides you with information about the processor in your system. The following option is displayed: CPU Ratio CMOS Setting IDE Configuration The options on the IDE Configuration subscreens allow you to set up or modify param- eters for your IDE controller and hard disk drive(s). The following options may be modified: OnBoard PCI IDE Controller Primary IDE Master/Primary IDE Slave Type LBA/Large Mode Block (Multi-Sector Transfer) PIO Mode DMA Mode S.M.A.R.T. 32Bit Data Transfer ARMD Emulation Type Secondary IDE Master/Secondary IDE Slave (see options above) Hard Disk Write Protect IDE Detect Time Out (Sec) ATA(PI) 80Pin Cable Detection Floppy Configuration The options on the Floppy Configuration subscreen allow you to set up or modify parameters for your floppy disk drive(s). The following options may be modified: Floppy A/Floppy B SuperIO Configuration The options on the SuperIO Configuration subscreen allow you to set up or modify parameters for your on-board peripherals. The following options may be modified: OnBoard Floppy Controller Serial Port1 Address/Serial Port2 Address 4-2 TRENTON Technology Inc. T4I Technical Reference Advanced Setup Serial Port2 IRQ Serial Port2 Mode Parallel Port Address Parallel Port Mode Parallel Port IRQ DMI Event Logging The options on the DMI Event Logging subscreen allow you to set up or modify param- eters for using the event log, which allows you to log errors and other events which occur in the system. The following options may be modified: View Event Log Mark All Events as Read Clear Event Log Event Log Statistics Remote Access Configuration The options on the Remote Access Configuration subscreen allow you to set up or modify parameters for configuring remote access type and parameters. The following options may be modified: Remote Access Serial Port Number Serial Port Mode Post-Boot Support USB Configuration The options on the USB Configuration subscreen allow you to set up or modify param- eters for your on-board peripherals. The following options may be modified: USB Configuration USB Function Legacy USB Support USB ZIP Emulation Type USB Beep Message TRENTON Technology Inc. 4-3 Advanced Setup T4I Technical Reference Saving and Exiting When you have made all desired changes to Advanced Setup, you may make changes to other Setup options by using the right and left arrow keys to access other menus. When you have made all of your changes, you may save them by selecting the Exit menu, or you may press at any time to exit the BIOS Setup Utility without saving the changes. 4-4 TRENTON Technology Inc. T4I Technical Reference Advanced Setup CPU When you select CPU Configuration from the Advanced Setup Screen, the following CONFIGURATION Setup screen displays: SETUP BIOS SETUP UTILITY |Advanced| Sets the ratio CPU Manufacturer :Intel between CPU Core CPU Brand String :Intel(r) Pentium(r) 4 Proc Clock and the FSB CPU Frequency :2000MHz Frequency. NOTE: If an invalid ratio _____________________________________________ is set in CMOS then actual and CPU Ratio Status :Locked setpoint values may CPU Ratio Actual Value :20 differ. CPU Ratio CMOS Setting : [ 8] ←→ Select Screen ↑↓ Select Item Enter Update F1 General Help F10 Save and Exit ESC Exit vxx.xx (C)Copyright 1985-2001, American Megatrends, Inc. CPU Configuration Screen When you display the CPU Configuration screen, the format is similar to the sample shown above. Highlight the option you wish to change and press to display the available settings. Select the appropriate setting and press again to accept the highlighted value. CPU The description for the system options listed below show the values as they appear if you have not yet run Advanced Setup. Once you change the settings, the new settings CONFIGURATION display each time Advanced Setup is run. SETUP OPTIONS CPU Ratio CMOS Setting For the T4I, the processors are locked at the correct processor speed before shipment. Changing the CPU Ratio CMOS Setting option to another value has no effect on actual processor speed. The Setup screen displays the system option: CPU Ratio CMOS Setting [ ##] where ## is the CPU ratio setting for the processor speed (e.g., 8 indicates 800MHz, 28 indicates 2.8GHz, etc.) TRENTON Technology Inc. 4-5 Advanced Setup T4I Technical Reference This page intentionally left blank. 4-6 TRENTON Technology Inc. T4I Technical Reference Advanced Setup IDE When you select IDE Configuration from the Advanced Setup Menu, the following CONFIGURATION Setup screen displays: BIOS SETUP UTILITY |Advanced| IDE Configuration DISABLED: disables the _____________________________________________ integrated IDE Controller. OnBoard PCI IDE Controller [Both] PRIMARY: enables only the Primary IDE > Primary IDE Master : [Hard Disk] Controller. > Primary IDE Slave : [Hard Disk] SECONDARY: enables > Secondary IDE Master: [ATAPI CDROM] only the Secondary IDE > Secondary IDE Slave : [Not Detected] Controller. BOTH: enables both IDE Hard Disk Write Protect [Disabled] Controllers. IDE Detect Time Out (Sec) [35] ATA(PI) 80Pin Cable Detection [Host & Device] ←→ Select Screen ↑↓ Select Item +- Change Option F1 General Help F10 Save and Exit ESC Exit vxx.xx (C)Copyright 1985-2001, American Megatrends, Inc. IDE Configuration Screen When you display the IDE Configuration screen, the format is similar to the sample shown above. Highlight the option you wish to change and press to display the available settings. Select the appropriate setting and press again to accept the highlighted value. Some of the options on this screen allow you to continue to subscreens designed to change parameters for that particular option. Highlight the option you wish to change and press to proceed to the appropriate subscreen. IDE The descriptions for the system options listed below show the values as they appear if you have not run the BIOS Setup Utility program yet. Once values have been defined, CONFIGURATION they display each time the BIOS Setup Utility is run. OPTIONS OnBoard PCI IDE Controller This option specifies whether or not the on-board integrated drive electronics (IDE) controllers are to be used. The Setup screen displays the system option: OnBoard PCI IDE Controller [Both] TRENTON Technology Inc. 4-7 Advanced Setup T4I Technical Reference Available options are: Disabled Primary Secondary Both Primary IDE Master/Primary IDE Slave Secondary IDE Master/Secondary IDE Slave The SBC has an enhanced IDE (EIDE) interface which can support up to four IDE disk drives through a primary and secondary controller in a master/slave configuration. This EIDE interface allows disk drives greater than 528MB to be used. Each of the four drives may be a different type. Devices attached to the primary and secondary controllers are detected automatically by AMIBIOS and displayed on the IDE Configuration screen. The Setup screen displays the system options: Primary IDE Master [Hard Disk] Primary IDE Slave [Hard Disk] Secondary IDE Master [ATAPI CDROM] Secondary IDE Slave [Not Detected] To view and/or change parameters for any IDE device, press to proceed to the IDE Device Setup screen, which is described later in this section. Hard Disk Write Protect This option allows you to disable or enable device write protection. Write protection will be effective only if the device is accessed through the BIOS. The Setup screen displays the system option: Hard Disk Write Protect [Disabled] Available options are: Disabled Enabled IDE Detect Time Out (Sec) This option allows you to select the time-out value (in seconds) for detecting an ATA/ ATAPI device. The Setup screen displays the system option: IDE Detect Time Out (Sec) [35] 4-8 TRENTON Technology Inc. T4I Technical Reference Advanced Setup Available options are: 0 5 10 15 20 25 30 35 ATA(PI) 80Pin Cable Detection This option allows you to select the mechanism for detecting an 80-pin ATA(PI) cable. The Setup screen displays the system option: ATA(PI) 80Pin Cable Detection [Host & Device] Available options are: Host & Device Host Device TRENTON Technology Inc. 4-9 Advanced Setup T4I Technical Reference This page intentionally left blank. 4-10 TRENTON Technology Inc. T4I Technical Reference Advanced Setup IDE DEVICE SETUP When you select one of the IDE devices from the IDE Configuration screen, a Setup screen similar to the following displays: BIOS SETUP UTILITY |Advanced| Primary IDE Master Select the type _____________________________________________ of device connected Device :Hard Disk to the system. Vendor :ST38418A Size :8.6GB LBA Mode :Supported Block Mode:32Sectors PIO Mode :4 Async DMA :MultiWord DMA-2 Ultra DMA :Ultra DMA-2 S.M.A.R.T.:Supported _____________________________________________ Type [Auto} ←→ Select Screen LBA/Large Mode [Auto] ↑↓ Select Item Block (Multi-Sector Transfer) [Auto] +- Change Option PIO Mode [Auto] F1 General Help DMA Mode [Auto] F10 Save and Exit S.M.A.R.T. [Auto] ESC Exit 32Bit Data Transfer [Disabled] ARMD Emulation Type [Auto] vxx.xx (C)Copyright 1985-2001, American Megatrends, Inc. IDE Device Screen When you display the IDE Device subscreen, the format is similar to the sample shown above. The data displayed on the top portion of the screen details the parameters detected by AMIBIOS for the specified device and may not be modified. The data displayed on the bottom portion of the screen may be modified. The drive information which displays the first time the BIOS Setup Utility is run indicates the drive(s) on your system which were detected by AMIBIOS upon initial bootup. IDE DEVICE SETUP The following options are available for each of the four IDE devices on the primary and secondary IDE controllers: OPTIONS Type This option allows you to specify what type of device is on the IDE controller. The Setup screen displays the system option: Type [Auto] TRENTON Technology Inc. 4-11 Advanced Setup T4I Technical Reference Available options are: Not Installed Auto CDROM ARMD If Not Installed is selected, the other options on the bottom portion of this screen do not display. If CDROM is selected, the ARMD Emulation Type option is not available. LBA/Large Mode This option allows you to enable IDE LBA (Logical Block Addressing) Mode for the specified IDE drive. Data is accessed by block addresses rather than by the traditional cylinder-head-sector format. This allows you to use drives larger than 528MB. The Setup screen displays the system option: LBA/Large Mode [Auto] Two options are available: Select Disabled to have AMIBIOS use the physical parameters of the hard disk and do no translation to logical parameters. The operating system which uses the parameter table will then see only 528MB of hard disk space even if the drive contains more than 528MB. Select Auto to enable LBA mode and translate the physical parameters of the drive to logical parameters. LBA Mode must be supported by the drive and the drive must have been formatted with LBA Mode enabled. Block (Multi-Sector Transfer) Mode This option supports transfer of multiple sectors to and from the specified IDE drive. Block mode boosts IDE drive performance by increasing the amount of data transferred during an interrupt. If Block Mode is set to Disabled, data transfers to and from the device occur one sector at a time. The Setup screen displays the system option: Block (Multi-Sector Transfer) [Auto] Available options are: Disabled Auto 4-12 TRENTON Technology Inc. T4I Technical Reference Advanced Setup PIO Mode IDE Programmed I/O (PIO) Mode programs timing cycles between the IDE drive and the programmable IDE controller. As the PIO mode increases, the cycle time decreases. Set the PIO Mode option to Auto to have AMIBIOS select the PIO mode used by the IDE drive being configured. If you select a specific value for the PIO mode, you must make absolutely certain that you are selecting the PIO mode supported by the IDE drive being configured. The Setup screen displays the system option: PIO Mode [Auto] Available options are: Auto 0 1 2 3 4 DMA Mode This option allows you to select DMA Mode for the device. The Setup screen displays the system option: DMA Mode [Auto] Available options are: Auto SWDMA0 (SingleWord DMA 0 - 2) SWDMA1 SWDMA2 MWDMA0 (MultiWord DMA 0 - 2) MWDMA1 MWDMA2 UDMA0 (UltraDMA 0 - 4) UDMA1 UDMA2 UDMA3 UDMA4 S.M.A.R.T. This option allows AMIBIOS to use the SMART (Self-Monitoring Analysis and Reporting Technology) protocol for reporting server system information over a network. TRENTON Technology Inc. 4-13 Advanced Setup T4I Technical Reference The Setup screen displays the system option: S.M.A.R.T. [Auto] Available options are: Auto Disabled Enabled 32Bit Data Transfer Hard disk drives connected to the SBC via the ISA Bus transfer data 16 bits at a time. An IDE drive on the PCI Local Bus can use a 32-bit data path. If the 32Bit Data Transfer parameter is set to Enabled, AMIBIOS enables 32-bit data transfers. If the host controller does not support 32-bit transfer, this feature must be set to Disabled. The Setup screen displays the system option: 32Bit Data Transfer [Disabled] Available options are: Disabled Enabled ARMD Emulation Type This option specifies the type of ARMD (ATAPI Removable Media Device) emulation used for a non-disk device attached to the specified IDE device. If the option is set to Auto, AMIBIOS automatically determines the proper emulation type and will support particular storage devices with ATAPI interface. If CDROM is selected in the Type field, this option is not available for modification. The Setup screen displays the system options: ARMD Emulation Type [Auto] Available options are: Auto Floppy Hard Disk 4-14 TRENTON Technology Inc. T4I Technical Reference Advanced Setup FLOPPY When you select Floppy Configuration from the Advanced Setup Menu, the following CONFIGURATION Setup screen displays: BIOS SETUP UTILITY |Advanced| Floppy Configuration Select the floppy _____________________________________________ drive type. Floppy A [1.44 MB 3½] Floppy B [Disabled] ←→ Select Screen ↑↓ Select Item +- Change Option F1 General Help F10 Save and Exit ESC Exit vxx.xx (C)Copyright 1985-2001, American Megatrends, Inc. Floppy Configuration Screen When you display the Floppy Configuration screen, the format is similar to the sample shown above. Highlight the option you wish to change and press to display the available settings. Select the appropriate setting and press again to accept the highlighted value. The drive information which displays the first time the BIOS Setup Utility is run indicates the drive(s) on your system which were detected by AMIBIOS upon initial bootup. FLOPPY The descriptions for the system options listed below show the values as they appear if you have not run the BIOS Setup Utility program yet. Once values have been defined, CONFIGURATION they display each time the BIOS Setup Utility is run. OPTIONS Floppy A/Floppy B The floppy drive(s) in your system can be configured using these options. The Disabled option can be used for diskless workstations. The Setup screen displays the system options: Floppy A [1.44 MB 3½"] Floppy B [Disabled] TRENTON Technology Inc. 4-15 Advanced Setup T4I Technical Reference Available options are: Disabled 360 KB 5¼" 1.2 MB 5¼" 720 KB 3½" 1.44MB 3½" 2.88MB 3½" 4-16 TRENTON Technology Inc. T4I Technical Reference Advanced Setup SUPERIO When you select SuperIO Configuration from the Advanced Setup Menu, the CONFIGURATION following Setup screen displays: SuperIO Chipset Smc27X |Advanced| Configure Smc27X Serial Port(s) & Parallel Port _______________________________________________ OnBoard Floppy Controller [Enabled] Serial Port1 Address [3F8/IRQ4] Serial Port2 Address [2F8/IRQ3] Serial Port2 Irq [IRQ4] Serial Port2 Mode [Normal] Parallel Port Address [378] Parallel Port Mode [Normal] Parallel Port IRQ [IRQ7] ←→ Select Screen ↑↓ Select Item +- Change Option F1 General Help F10 Save and Exit ESC Exit vxx.xx (C)Copyright 1985-2001, American Megatrends, Inc. SuperIO Configuration Screen When you display the SuperIO Configuration screen, the format is similar to the sample shown above. Highlight the option you wish to change and press to display the available settings. Select the appropriate setting and press again to accept the highlighted value. SUPERIO The descriptions for the system options listed below show the values as they appear if CONFIGURATION you have not run the BIOS Setup Utility program yet. Once values have been defined, they display each time the BIOS Setup Utility is run. OPTIONS OnBoard Floppy Controller The on-board floppy drive controller may be enabled or disabled using this option. The Setup screen displays the system option: OnBoard Floppy Controller [Enabled] Available options are: Disabled Enabled TRENTON Technology Inc. 4-17 Advanced Setup T4I Technical Reference Serial Port1 Address/Serial Port2 Address Each of these options enables the specified serial port on the SBC and establishes the base I/O address and the number of the interrupt request for the port. The Setup screen displays the system option: Serial Port1 Address [3F8/IRQ4] Serial Port2 Address [2F8/IRQ3] Available options are: Disabled 3F8/IRQ4 3E8/IRQ4 2F8/IRQ3 2E8/IRQ3 _______________________________________________________________________ NOTE: The values available for each on-board serial port may vary, depending on the setting previously selected for the other on-board serial port and any off-board serial ports. If an I/O address is assigned to another serial port, AMIBIOS automatically omits that address from the values available. _______________________________________________________________________ If the system has off-board serial ports which are configured to specific starting I/O ports via jumper settings, AMIBIOS configures the on-board serial ports to avoid conflicts. AMIBIOS checks the ISA Bus for serial ports. Any off-board serial ports found on the ISA Bus are left at their assigned addresses. Serial Port1, the first on-board serial port, is configured with the first available address and Serial Port2, the second on-board serial port, is configured with the next available address. The default address assignment order is 3F8H, 2F8H, 3E8H, 2E8H. Note that this same assignment order is used by AMIBIOS to place the active serial port addresses in lower memory (BIOS data area) for configuration as logical COM devices. For example, if there is one off-board serial port on the ISA Bus and its address is set to 2F8H, Serial Port1 is assigned address 3F8H and Serial Port2 is assigned address 3E8H. Configuration is then as follows: COM1 - Serial Port1 (at 3F8H) COM2 - off-board serial port (at 2F8H) COM3 - Serial Port2 (at 3E8H) If Serial Port2 Address is set to Disabled, the Serial Port2 IRQ and Serial Port2 Mode options are not available. Serial Port2 IRQ If the Serial Port2 Address option is set to Disabled, this option is not available for modification. 4-18 TRENTON Technology Inc. T4I Technical Reference Advanced Setup The Setup screen displays the system option: Serial Port2 IRQ [IRQ4] Available options are: Disabled IRQ3 IRQ4 Serial Port2 Mode If the Serial Port2 Address option is set to Disabled, this option is not available for modification. The Setup screen displays the system option: Serial Port2 Mode [Normal] Available options are: Normal IrDA Sir-A ASK IR IrDA Sir-B IrDA HDLC IrDA 4PPM Consumer Raw Ir Parallel Port Address This option enables the parallel port on the SBC and establishes the base I/O address for the port. The Setup screen displays the system option: Parallel Port Address [378] Available options are: Disabled 378 278 3BC AMIBIOS checks the ISA Bus for off-board parallel ports. Any parallel ports found on the ISA Bus are left at their assigned addresses. The on-board Parallel Port is automati- cally configured with the first available address not used by an off-board parallel port. If this option is set to Disabled, the Parallel Port Mode and Parallel Port IRQ options are not available. TRENTON Technology Inc. 4-19 Advanced Setup T4I Technical Reference Parallel Port Mode This option specifies the parallel port mode. ECP and EPP are both bidirectional data transfer schemes which adhere to the IEEE P1284 specifications. If the Parallel Port Address option is set to Disabled, this option is not available for modification. The Setup screen displays the system option: Parallel Port Mode [Normal] Four options are available: Select Normal to use normal parallel port mode. Select Bi-Directional to use bi-directional parallel port mode. Select EPP to allow the parallel port to be used with devices which adhere to the Enhanced Parallel Port (EPP) specification. EPP uses the existing parallel port signals to provide asymmetric bidirectional data transfer driven by the host device. Select ECP to allow the parallel port to be used with devices which adhere to the Extended Capabilities Port (ECP) specification. ECP uses the DMA protocol to achieve transfer rates of approximately 2.5MB/second. ECP provides symmetric bidirectional communication. Parallel Port IRQ This option specifies the interrupt request (IRQ) which is used by the parallel port. If the Parallel Port Address option is set to Disabled, this option is not available for modification. The Setup screen displays the system option: Parallel Port IRQ [IRQ7] Available options are: IRQ5 IRQ7 4-20 TRENTON Technology Inc. T4I Technical Reference Advanced Setup DMI EVENT When you select DMI Event Logging from the Advanced Setup Menu, the following LOGGING Setup screen displays: BIOS SETUP UTILITY |Advanced| Event Log Functions View all unread events _____________________________________________ on the Event Log View Event Log Mark All Events as Read Clear Event Log Event Log Statistics ←→ Select Screen ↑↓ Select Item Enter Go to Sub Screen F1 General Help F10 Save and Exit ESC Exit vxx.xx (C)Copyright 1985-2001, American Megatrends, Inc. DMI Event Logging Screen When you display the DMI Event Logging screen, the format is similar to the sample shown above. Highlight the option you wish to access and press . After you have finished, select the appropriate response. DMI EVENT View Event Log LOGGING OPTIONS When you select this option, a window similar to the following displays showing unread events in the Event Log: View Event Log 01/01/01 00:00:03 CMOS time not set 01/01/01 00:00:03 CMOS system options not set When you have finished viewing the Event Log, press to continue. TRENTON Technology Inc. 4-21 Advanced Setup T4I Technical Reference Mark All Events As Read After you have reviewed the events in the event log, you may select this option, which allows you to mark all unread event log entries as having been read. The following window displays: Mark all events as read now? [Ok] [Cancel] Selecting Ok marks all unread entries currently in the event log file as having been read. The next time you select the View Event Log option, only the new, unmarked events are displayed. Clear Event Log This option specifies whether or not the event log should be cleared. The following window displays: Clear Event Log now? [Ok] [Cancel] Selecting Ok discards all entries in the Event Log. The next time you select the View Event Log option, only new entries will display. Event Log Statistics When you select this option, a window similar to the following displays showing statistics for events which have been logged: Event Log Statistics Total size (in events) 63 Free size (in events) 62 Unread events 01 When you have finished viewing the Event Log statistics, press to continue. 4-22 TRENTON Technology Inc. T4I Technical Reference Advanced Setup REMOTE ACCESS When you select Remote Access Configuration from the Advanced Setup Menu, the CONFIGURATION following Setup screen displays: BIOS SETUP UTILITY |Advanced| Configure Remote Access Type and Parameters Select Remote access _____________________________________________ type Remote Access [Serial] Serial Port Number [COM1] Serial Port Mode [57600 8,n,1] Post-Boot Support [Disabled] ←→ Select Screen ↑↓ Select Item +- Change Option F1 General Help F10 Save and Exit ESC Exit vxx.xx (C)Copyright 1985-2001, American Megatrends, Inc. Remote Access Configuration Screen When you display the Remote Access Configuration screen, the format is similar to the sample shown above. Highlight the option you wish to change and press to display the available settings. Select the appropriate setting and press again to accept the highlighted value. REMOTE ACCESS The descriptions for the system options listed below show the values as they appear if CONFIGURATION you have not run the BIOS Setup Utility program yet. Once values have been defined, they display each time the BIOS Setup Utility is run. OPTIONS Remote Access This option allows you to use a terminal connected to the serial port of the SBC to control changes to the BIOS settings. The Setup screen displays the system option: Remote Access [Disabled] Available options are: Disabled Serial TRENTON Technology Inc. 4-23 Advanced Setup T4I Technical Reference If this option is set to Disabled, the Serial Port Number, Serial Port Mode and Post- Boot Support options are not available. Serial Port Number This option specifies the serial port on which remote access is to be enabled. If the Remote Access option is set to Disabled, this option is not available. The Setup screen displays the system option: Serial Port Number [COM1] Available options are: COM1 COM2 Serial Port Mode This option specifies settings for the serial port on which remote access is enabled. The settings indicate baud rate, eight bits per character, no parity and one stop bit. If the Remote Access option is set to Disabled, this option is not available. The Setup screen displays the system option: Serial Port Mode [57600 8,n,1] Available options are: 115200 8,n,1 57600 8,n,1 19200 8,n,1 Post-Boot Support This option specifies whether or not to keep redirection active after booting to DOS. If the Remote Access option is set to Disabled, this option is not available. The Setup screen displays the system option: Post-Boot Support [Disabled] Two options are available: Select Disabled to deactivate redirection. Select Enabled to keep redirection active. 4-24 TRENTON Technology Inc. T4I Technical Reference Advanced Setup USB When you select USB Configuration from the Advanced Setup Menu, the following CONFIGURATION Setup screen displays: BIOS SETUP UTILITY |Advanced| USB Configuration Enables USB host ___________________________________________ controllers. USB Function [Enabled] Legacy USB Support [Auto] USB ZIP Emulation Type [Auto] USB Beep Message [Enabled] ←→ Select Screen ↑↓ Select Item +- Change Option F1 General Help F10 Save and Exit ESC Exit vxx.xx (C)Copyright 1985-2001, American Megatrends, Inc. USB Configuration Screen When you display the USB Configuration screen, the format is similar to the sample shown above. Highlight the option you wish to change and press to display the available settings. Select the appropriate setting and press again to accept the highlighted value. USB The descriptions for the system options listed below show the values as they appear if you have not run the BIOS Setup Utility program yet. Once values have been defined, CONFIGURATION they display each time the BIOS Setup Utility is run. OPTIONS USB Function This option allows you to enable the Universal Serial Bus (USB). If this option is set to Disabled, the Legacy USB Support, USB ZIP Emulation Type and USB Beep Message options are not available. The Setup screen displays the system option: USB Function [Enabled] TRENTON Technology Inc. 4-25 Advanced Setup T4I Technical Reference Available options are: Disabled Enabled Legacy USB Support This option allows you to enable support for older USB devices. If the USB Function option is set to Disabled, this option is not available. The Setup screen displays the system option: Legacy USB Support [Auto] Available options are: Disabled Enabled Auto USB ZIP Emulation Type This option allows you to set the emulation type for USB Zip drives. If the USB Function option is set to Disabled, this option is not available. The Setup screen displays the system option: USB ZIP Emulation Type [Auto] Available options are: Auto Floppy Hard Disk USB Beep Message This option allows you to enable the beep during USB device enumeration. If the USB Function option is set to Disabled, this option is not available. The Setup screen displays the system option: USB Beep Message [Enabled] Available options are: Disabled Enabled Copyright 2002 by Trenton Technology Inc. All rights reserved. 4-26 TRENTON Technology Inc. T4I Technical Reference PCI Plug and Play Setup Chapter 5 PCI Plug and Play Setup PCI PLUG AND When you select PCIPnP from the BIOS Setup Utility Main Menu, the following Setup PLAY SETUP screen displays: BIOS SETUP UTILITY Main Advanced |PCIPnP| Chipset Boot Security Exit Advanced PCI/PnP Settings ______________________________________________ WARNING: Setting wrong values in below sections may cause system to malfunction. On board SCSI [Enabled] On board (Intel 82540) Lan2 [Enabled] On board VGA [Enabled] Plug & Play O/S [No] Reset Config Data [No] PCI Latency Timer [64] Allocate IRQ to PCI VGA [Yes] Palette Snooping [Disabled] PCI IDE BusMaster [Disabled] Offboard PCI/ISA IDE Card [Auto] IRQ3 [Available] IRQ4 [Available] IRQ5 [Available] IRQ7 [Available] IRQ9 [Available] IRQ10 [Available] IRQ11 [Available] IRQ12 [Available] IRQ14 [Available] IRQ15 [Available] DMA Channel 0 [Available] DMA Channel 1 [Available] ←→ Select Screen DMA Channel 3 [Available] ↑↓ Select Item DMA Channel 5 [Available] +- Change Option DMA Channel 6 [Available] F1 General Help DMA Channel 7 [Available] F10 Save and Exit ESC Exit Reserved Memory Size [Disabled] Reserved Memory Address [C8000] vxx.xx (C)Copyright 1985-2001, American Megatrends, Inc. PCIPnP Setup Screen When you display the PCIPnP Setup screen, the format is similar to the sample shown above, except the screen does not display all of the options at one time. If you need to change other options, use the down arrow key to locate the appropriate option. Highlight the option you wish to change and press to display the available settings. Select the appropriate setting and press again to accept the highlighted value. TRENTON Technology Inc. 5-1 PCI Plug and Play Setup T4I Technical Reference _______________________________________________________________________ NOTE: The values on the PCIPnP Setup screen do not necessarily reflect the values appropriate for your SBC. Refer to the explanations below for specific instructions about entering correct information. _______________________________________________________________________ PCIPNP SETUP The descriptions for the system options listed below show the values as they appear if you have not yet run PCIPnP Setup. Once values have been defined, they display each OPTIONS time PCIPnP Setup is run. _______________________________________________________________________ NOTE: Do not change the values for any PCIPnP Setup option unless you understand the impact on system operation. Depending on your system configuration, selection of other values may cause unreliable system operation. _______________________________________________________________________ On Board SCSI This option specifies whether or not the on-board SCSI controller is to be used. The Setup screen displays the system option: On board SCSI [Enabled] Available options are: Disabled Enabled On Board (Intel 82540) Lan2 This option specifies whether or not the second on-board Ethernet controller (Intel 82540) is to be used. The LAN 2 (P1) interface supports 10/100/1000Base-T operations. The Setup screen displays the system option: On board (Intel 82540) Lan2 [Enabled] Available options are: Disabled Enabled On Board VGA This option specifies whether there is an on-board VGA device on your system.. The Setup screen displays the system option: On board VGA [Enabled] 5-2 TRENTON Technology Inc. T4I Technical Reference PCI Plug and Play Setup Available options are: Disabled Enabled Plug & Play O/S This option indicates whether or not the operating system installed in the computer is Plug and Play-aware. AMIBIOS only detects and enables PnP ISA adapter cards which are required for system boot. An operating system which is PnP-aware detects and enables all other PnP-aware adapter cards. Set this option to No if the operating system (such as DOS, OS/2, Windows 3.x) does not use PnP. _______________________________________________________________________ NOTE: You must set this option correctly or PnP-aware adapter cards installed in your computer will not be configured properly. _______________________________________________________________________ The Setup screen displays the system option: Plug & Play O/S [No] Two options are available: Select No to allow AMIBIOS to configure the devices in the system. Select Yes if your system has a Plug and Play operating system and you want to allow the operating system to configure all Plug and Play (PnP) devices which are not required for bootup. Reset Config Data This option specifies whether the PCI/PnP configuration data which is stored in Flash will be cleared the next time the system is booted. The Setup screen displays the system option: Reset Config Data [No] Available options are: No Yes PCI Latency Timer This option specifies the latency of all PCI devices on the PCI Local Bus. The settings are in units equal to PCI clocks. The Setup screen displays the system option: PCI Latency Timer [64] TRENTON Technology Inc. 5-3 PCI Plug and Play Setup T4I Technical Reference Available options are: 32 160 64 192 96 224 128 248 Allocate IRQ to PCI VGA This option allows you to assign an IRQ to a PCI VGA card if the card requests an IRQ. The Setup screen displays the system option: Allocate IRQ to PCI VGA [Yes] Available options are: Yes No Palette Snooping This option, when set to Enabled, indicates to the PCI devices that an ISA graphics device is installed in the system so the card will function correctly. The Setup screen displays the system option: Palette Snooping [Disabled] Available options are: Disabled Enabled PCI IDE BusMaster This option specifies whether the IDE controller on the PCI Local Bus has bus mastering capability for reading and writing to IDE drives. The IDE drive(s) must support PCI bus mastering. The Setup screen displays the system option: PCI IDE BusMaster [Disabled] Available options are: Disabled Enabled 5-4 TRENTON Technology Inc. T4I Technical Reference PCI Plug and Play Setup OffBoard PCI/ISA IDE Card This option specifies the PCI expansion slot on the SBC where the off-board PCI IDE controller is installed, if any. The Setup screen displays the system option: OffBoard PCI/ISA IDE Card [Auto] Available options are: Auto PCI Slot1 PCI Slot2 PCI Slot3 PCI Slot4 PCI Slot5 PCI Slot6 If you select any value other than Auto, the following options and their default values are added to the screen: OffBoard PCI IDE Primary IRQ/OffBoard PCI IDE Secondary These options specify the PCI interrupts used by the primary and secondary IDE channels on the off-board PCI IDE controller. You may use the INTA, INTB, INTC and INTD options to assign IRQs to the Int Pin used by the specified channel. If the OffBoard PCI/ISA IDE Card option is set to Auto, these options are not available. The Setup screen displays the system options: OffBoard PCI IDE Primary IRQ [Disabled] OffBoard PCI IDE Secondary [Disabled] Available options are: Disabled INTA INTB INTC INTD Hardwired IRQ3/IRQ4/IRQ5/IRQ7/IRQ9/IRQ10/IRQ11/IRQ12/IRQ14/IRQ15 These options indicate whether or not the specified interrupt request (IRQ) is available for use by the system for PCI/Plug and Play devices or is reserved for use by legacy devices. This allows you to specify IRQs for use by legacy ISA adapter cards. TRENTON Technology Inc. 5-5 PCI Plug and Play Setup T4I Technical Reference The IRQ setup options indicate whether AMIBIOS should remove an IRQ from the pool of available IRQs passed to BIOS configurable devices. The Setup screen displays the system option: IRQ# [Available] where # is the number of the interrupt request (IRQ) Two options are available: Select Available to make the specified IRQ available for use by PCI/PnP devices. Select Reserved to reserve the specified IRQ for use by legacy ISA devices. DMA Channels 0, 1, 3, 5, 6 and 7 These options indicate whether or not the specified DMA channel is available for use by the system for PCI/Plug and Play devices or is reserved for use by legacy ISA devices. The Setup screen displays the system option: DMA Channel # [Available] where # is the DMA Channel number Two options are available: Available indicates that the specified DMA channel is available for use by PCI/PnP devices. Reserved indicates the specified DMA channel is reserved for use by legacy ISA devices. Reserved Memory Size This option specifies the size of the memory area reserved for legacy ISA devices. If this option is set to Disabled, the Reserved Memory Address option is not available. The Setup screen displays the system option: Reserved Memory Size [Disabled] Available options are: Disabled 16k 32k 64k 5-6 TRENTON Technology Inc. T4I Technical Reference PCI Plug and Play Setup Reserved Memory Address This option specifies the beginning address (in hexadecimal) of the ROM memory area reserved for use by legacy ISA adapter cards. If the Reserved Memory Size option is set to Disabled, this option is not available. The Setup screen displays the system option: Reserved Memory Address [C8000] Available options are: C0000 D0000 C4000 D4000 C8000 D8000 CC000 DC000 Saving and Exiting When you have made all desired changes to PCIPnP Setup, you may make changes to other Setup options by using the right and left arrow keys to access other menus. When you have made all of your changes, you may save them by selecting the Exit menu, or you may press at any time to exit the BIOS Setup Utility without saving the changes. TRENTON Technology Inc. 5-7 PCI Plug and Play Setup T4I Technical Reference This page intentionally left blank. Copyright 2002 by Trenton Technology Inc. All rights reserved. 5-8 TRENTON Technology Inc. T4I Technical Reference Chipset Setup Chapter 6 Chipset Setup CHIPSET SETUP When you select Chipset from the BIOS Setup Utility Main Menu, the following Setup screen displays: BIOS SETUP UTILITY Main Advanced PCIPnP |Chipset| Boot Security Exit Advanced Chipset Settings Intel ICH4 South _____________________________________________ Bridge chipset WARNING: Setting wrong values in the below configuration options. sections may cause system to malfunction. > Intel ICH4 SouthBridge Configuration ←→ Select Screen ↑↓ Select Item Enter Go to Sub Screen F1 General Help F10 Save and Exit ESC Exit vxx.xx (C)Copyright 1985-2001, American Megatrends, Inc. Chipset Setup Screen When you display the Chipset Setup screen, the format is similar to the sample shown above, allowing you to continue to a subscreen designed to change parameters for the Intel ICH4 SouthBridge Configuration options. Press to proceed to the subscreen. _______________________________________________________________________ NOTE: The values on the Chipset Setup subscreen do not necessarily reflect the values appropriate for your SBC. Refer to the explanations following the screen for specific instructions about entering correct information. _______________________________________________________________________ CHIPSET SETUP _______________________________________________________________________ OPTIONS NOTE: Do not change the values for any Chipset Setup option unless you understand the impact on system operation. Depending on your system configuration, selection of other values may cause unreliable system operation. _______________________________________________________________________ TRENTON Technology Inc. 6-1 Chipset Setup T4I Technical Reference Intel ICH4 SouthBridge Configuration The options on the ICH4 SouthBridge Configuration subscreen allow you to set up or modify parameters to configure the Intel ICH4 SouthBridge chip. The following options may be modified: ICH4 Dev31 Func1, IDE ICH4 Dev31 Func3, SMBUS ICH4 Dev29 Func0, USB#1 ICH4 Dev29 Func7, EHCI LPC 4Eh-4Fh Decode LPC 2Eh-2Fh Decode On board Lan ISA Bus IOAPIC Extended IOAPIC CPU B.I.S.T. ICH4 DMA Collection PC/PCIB Select DMA Types 0 through 7 Saving and Exiting When you have made all desired changes to Chipset Setup, you may make changes to other Setup options by using the right and left arrow keys to access other menus. When you have made all of your changes, you may save them by selecting the Exit menu, or you may press at any time to exit the BIOS Setup Utility without saving the changes. 6-2 TRENTON Technology Inc. T4I Technical Reference Chipset Setup INTEL ICH4 When you select Intel ICH4 SouthBridge Configuration from the Chipset Setup SOUTHBRIDGE Screen, the following Setup screen displays: CONFIGURATION BIOS SETUP UTILITY Main Advanced PCIPnP |Chipset| Boot Security Exit Configure advanced settings for SouthBridge Enable/Disable ICH4 _____________________________________________ IDE Controller ICH4 Dev31 Func1, IDE [Enabled] function. ICH4 Dev31 Func3, SMBUS [Enabled] ICH4 Dev29 Func0, USB#1 [Enabled] ICH4 Dev29 Func7, EHCI [Disabled] LPC 4Eh-4Fh Decode [Enabled] LPC 2Eh-2Fh Decode [Enabled] On board Lan [Enabled] ISA BUS [Enabled] IOAPIC [Enabled] Extended IOAPIC [Enabled] CPU B.I.S.T. [Enabled] ICH4 DMA Collection [Enabled] PC/PCIB Select [Disabled] DMA-0 Type [PC/PCI] ←→ Select Screen ↑↓ Select Item DMA-1 Type [PC/PCI] DMA-2 Type [LPC DMA] +- Change Option DMA-3 Type [PC/PCI] F1 General Help DMA-5 Type [PC/PCI] F10 Save and Exit DMA-6 Type [PC/PCI] ESC Exit DMA-7 Type [PC/PCI] vxx.xx (C)Copyright 1985-2001, American Megatrends, Inc. Intel ICH4 SouthBridge Configuration Screen When you display the Intel ICH4 SouthBridge Configuration screen, the format is similar to the sample shown above, except the screen does not display all of the options at one time. If you need to change other options, use the down arrow key to locate the appropriate option. Highlight the option you wish to change and press to display the available settings. Select the appropriate setting and press again to accept the highlighted value. INTEL ICH4 The descriptions for the system options listed below show the values as they appear if SOUTHBRIDGE you have not yet run Chipset Setup. Once values have been defined, they display each time Chipset Setup is run. CONFIGURATION OPTIONS ICH4 Dev31 Func1, IDE This option allows you to enable or disable ICH4 IDE Controller function. TRENTON Technology Inc. 6-3 Chipset Setup T4I Technical Reference The Setup screen displays the system option: ICH4 Dev31 Func1, IDE [Enabled] Available options are: Disabled Enabled ICH4 Dev31 Func3, SMBUS This option allows you to enable or disable ICH3 SMBUS Controller function. The Setup screen displays the system option: ICH4 Dev31 Func3, SMBUS [Enabled] Available options are: Disabled Enabled ICH4 Dev29 Func0, USB#1 This option allows you to enable or disable USB Host Controller #1 function. The Setup screen displays the system option: ICH4 Dev29 Func0, USB#1 [Enabled] Available options are: Disabled Enabled ICH4 Dev29 Func7, EHCI This option allows you to enable or disable EHCI USB Controller function. Be sure that the ICH4 Dev29 Func0, USB#1 option is set to Enabled before enabling this option. The Setup screen displays the system option: ICH4 Dev29 Func7, EHCI [Disabled] Available options are: Disabled Enabled 6-4 TRENTON Technology Inc. T4I Technical Reference Chipset Setup LPC 4Eh-4Fh Decode/LPC 2Eh-2Fh Decode The LPC 4Eh-4Fh Decode option allows you to enable or disable decoding of I/O locations 4Eh and 4Fh to the LPC interface. The LPC 2Eh-2Fh Decode option cannot be modified. The Setup screen displays the system options: LPC 4Eh-4Fh Decode [Enabled] LPC 2Eh-2Fh Decode [Enabled] Available options are: Disabled Enabled On Board Lan This option specifies whether or not the first on-board Ethernet controller (LAN 1/P16) is to be used. The LAN 1 interface supports 10/100Base-T operations. The Setup screen displays the system option: On board Lan [Enabled] Available options are: Disabled Enabled ISA BUS This option allows you to enable or disable the PCI/ISA on-board bridge. If this option is set to Enabled, the ICH4 Positive Decode option is not available. The Setup screen displays the system option: ISA BUS [Enabled] Available options are: Disabled Enabled ICH4 Positive Decode This option allows you to enable or disable positive decode in ICH4. Set this option to Enabled if the on-board PCI/1SA bridge is present. If the ISA BUS option is set to Enabled, this option is not available. TRENTON Technology Inc. 6-5 Chipset Setup T4I Technical Reference The Setup screen displays the system option: ICH4 Positive Decode [Enabled] Available options are: Disabled Enabled IOAPIC This option allows you to enable or disable the ICH4 IOAPIC function. The Setup screen displays the system option: IOAPIC [Enabled] Available options are: Disabled Enabled Extended IOAPIC This option allows you to enable or disable the extended mode of the ICH4 IOAPIC function. The Setup screen displays the system option: Extended IOAPIC [Enabled] Available options are: Disabled Enabled CPU B.I.S.T. This option allows you to enable or disable the CPU Built-In Self Test. The Setup screen displays the system option: CPU B.I.S.T. [Enabled] Available options are: Disabled Enabled 6-6 TRENTON Technology Inc. T4I Technical Reference Chipset Setup ICH4 DMA Collection This option allows you to enable or disable the DMA collection buffer. The Setup screen displays the system option: ICH4 DMA Collection [Enabled] Available options are: Disabled Enabled PC/PCIB Select The Setup screen displays the system option: PC/PCIB Select [Disabled] Available options are: Disabled Enabled DMA Types 0, 1, 2, 3, 5, 6 and 7 This option allows you to select the type of DMA performed on the specified channel. The Setup screen displays the system option: DMA-# Type [PC/PCI] where # is the DMA number Available options are: PC/PCI LPC DMA TRENTON Technology Inc. 6-7 Chipset Setup T4I Technical Reference This page intentionally left blank. Copyright 2002 by Trenton Technology Inc. All rights reserved. 6-8 TRENTON Technology Inc. T4I Technical Reference Boot Setup Chapter 7 Boot Setup BOOT SETUP When you select Boot from the BIOS Setup Utility Main Menu, the following Setup screen displays: BIOS SETUP UTILITY Main Advanced PCIPnP Chipset |Boot| Security Exit Advanced Boot Settings Configue Settings _____________________________________________ during System Boot. > Boot Settings Configuration > Boot Device Priority > Hard Disk Drives > Removable Devices > ATAPI CDROM Drives Interrupt 19 Capture [Disabled] ←→ Select Screen ↑↓ Select Item Enter Go to Sub Screen F1 General Help F10 Save and Exit ESC Exit vxx.xx (C)Copyright 1985-2001, American Megatrends, Inc. Boot Setup Screen When you display the Boot Setup screen, the format is similar to the sample shown above. Highlight the option you wish to change and press to display the available settings. Select the appropriate setting and press again to accept the highlighted value. Some of the options on this screen allow you to continue to subscreens designed to change parameters for that particular option. Highlight the option you wish to change and press to proceed to the appropriate subscreen. _______________________________________________________________________ NOTE: If no device is found for one of the device types, the line item for that device type does not display. _______________________________________________________________________ BOOT SETUP The descriptions for the system option listed below show the values as they appear if you OPTIONS have not yet run Boot Setup. Once values have been changed, they display each time Boot Setup is run. You may also continue to subscreens to specify boot parameters and the boot sequence of bootable devices in your system. TRENTON Technology Inc. 7-1 Boot Setup T4I Technical Reference Boot Settings Configuration The options on the Boot Settings Configuration subscreen allow you to set up or modify parameters for boot procedures. The following options may be modified: Quick Boot Quiet Boot AddOn ROM Display Mode Bootup Num-Lock PS/2 Mouse Support System Keyboard Boot To OS/2 Wait For ’F1’ If Error Hit ’DEL’ Message Display Boot Device Priority The options on the Boot Device Priority subscreen specify the order in which AMIBIOS attempts to boot devices available in the system. It allows you to select the type of drive which will be booted first, second, third, etc. If there are multiple drives of a particular type, you may specify the order in which each drive of that type will be selected by using the other options on the Boot Setup Menu. Hard Disk Drives The Hard Disk Drives subscreen specifies the boot sequence of the hard drives available in the system. Removable Devices The Removable Devices subscreen specifies the boot sequence of the removable devices available in the system. ATAPI CDROM Drives The ATAPI CDROM Drives subscreen specifies the boot sequence of the ATAPI CDROM devices available in the system. Interrupt 19 Capture The Setup screen displays the system option: Interrupt 19 Capture [Disabled] 7-2 TRENTON Technology Inc. T4I Technical Reference Boot Setup Available options are: Disabled Enabled Saving and Exiting When you have made all desired changes to Boot Setup, you may make changes to other Setup options by using the right and left arrow keys to access other menus. When you have made all of your changes, you may save them by selecting the Exit menu, or you may press at any time to exit the BIOS Setup Utility without saving the changes. TRENTON Technology Inc. 7-3 Boot Setup T4I Technical Reference This page intentionally left blank. 7-4 TRENTON Technology Inc. T4I Technical Reference Boot Setup BOOT SETTINGS When you select Boot Settings Configuration from the Boot Setup Menu, the following CONFIGURATION Setup screen displays: BIOS SETUP UTILITY |Boot| Boot Settings Configuration Allows BIOS to skip _____________________________________________ certain tests while Quick Boot [Disabled] booting. This will Quiet Boot [Disabled] decrease the time AddOn ROM Display Mode [Force BIOS] needed to boot the _____________________________________________ system. Bootup Num-Lock [On] PS/2 Mouse Support [Enabled] System Keyboard [Present] Boot To OS/2 [No] Wait For ‘F1’ If Error [Enabled] Hit ‘DEL’ Message Display [Enabled] ←→ Select Screen ↑↓ Select Item +- Change Option F1 General Help F10 Save and Exit ESC Exit vxx.xx (C)Copyright 1985-2001, American Megatrends, Inc. Boot Settings Configuration Screen When you display the Boot Settings Configuration screen, the format is similar to the sample shown above. Highlight the option you wish to change and press to display the available settings. Select the appropriate setting and press again to accept the highlighted value. BOOT SETTINGS The descriptions for the system options listed below show the values as they appear if you have not run the BIOS Setup Utility program yet. Once values have been defined, CONFIGURATION they display each time the BIOS Setup Utility is run. OPTIONS Quick Boot This option allows you to have the AMIBIOS boot quickly when the computer is powered on or go through more complete testing. If you set the Quick Boot option to Enabled, the BIOS skips certain tests while booting and decreases the time needed to boot the system. The Setup screen displays the system option: Quick Boot [Disabled] TRENTON Technology Inc. 7-5 Boot Setup T4I Technical Reference Available options are: Disabled Enabled Quiet Boot This option specifies what will be displayed on the screen while the system is performing the POST routines when the computer is powered on or a soft reboot is performed. The Setup screen displays the system option: Quiet Boot [Disabled] Two options are available: Select Disabled to display normal POST messages. Select Enabled to display the OEM logo instead of the POST messages. AddOn ROM Display Mode This option specifies the system display mode which is set at the time the AMIBIOS post routines initialize an optional option ROM. The Setup screen displays the system option: AddOn ROM Display Mode [Force BIOS] Two options are available: Select Force BIOS to use the display mode currently being used by AMIBIOS. Select Keep Current to use the current display mode. BootUp Num-Lock This option enables you to turn off the Num-Lock option on the enhanced keyboard when the system is powered on. If Num-Lock is turned off, the arrow keys on the numeric keypad can be used, as well as the other set of arrow keys on the enhanced keyboard. The Setup screen displays the system option: BootUp Num-Lock [On] Available options are: Off On 7-6 TRENTON Technology Inc. T4I Technical Reference Boot Setup PS/2 Mouse Support This option indicates whether or not a PS/2-type mouse is supported. The Setup screen displays the system option: PS/2 Mouse Support [Enabled] Available options are: Disabled Enabled System Keyboard This option indicates whether or not a keyboard is attached to the computer. The Setup screen displays the system option: System Keyboard [Present] Available options are: Absent Present Boot To OS/2 This option should be set to Yes if you are running the IBM OS/2 operating system and using more than 64MB of system memory on the SBC. The Setup screen displays the system option: Boot To OS/2 [No] Available options are: No Yes Wait For ’F1’ If Error Before the system boots up, the AMIBIOS executes the Power-On Self Test (POST) routines, a series of system diagnostic routines. If any of these tests fail but the system can still function, a non-fatal error has occurred. The AMIBIOS responds with an appro- priate error message followed by: Press F1 to RESUME TRENTON Technology Inc. 7-7 Boot Setup T4I Technical Reference If this option is set to Disabled, a non-fatal error does not generate the "Press F1 to RESUME" message. The AMIBIOS still displays the appropriate message, but continues the booting process without waiting for the key to be pressed. This eliminates the need for any user response to a non-fatal error condition message. Non-fatal error messages are listed in Appendix A - BIOS Messages. The Setup screen displays the system option: Wait For ’F1’ If Error [Enabled] Available options are: Disabled Enabled Hit ’DEL’ Message Display The "Hit DEL to run Setup" message displays when the system boots up. Disabling this option prevents the message from displaying. The Setup screen displays the system option: Hit ’DEL’ Message Display [Enabled] Available options are: Disabled Enabled 7-8 TRENTON Technology Inc. T4I Technical Reference Boot Setup BOOT DEVICE When you select Boot Device Priority from the Boot Setup Menu, the following Setup PRIORITY screen displays: BIOS SETUP UTILITY |Boot| Boot Device Priority Specifies the boot _____________________________________________ sequence from the available devices. 1st Boot Device [Removable Dev.] 2nd Boot Device [ATAPI CDROM] 3rd Boot Device [Hard Drive] ←→ Select Screen ↑↓ Select Item +- Change Option F1 General Help F10 Save and Exit ESC Exit vxx.xx (C)Copyright 1985-2001, American Megatrends, Inc. Boot Device Priority Screen When you display the Boot Device Priority screen, the format is similar to the sample shown above. Highlight the option you wish to change and press to display the available settings. Select the appropriate setting and press again to accept the highlighted value. _______________________________________________________________________ NOTE: The number of line items on this screen may vary depending on the number of bootable devices available on your system. _______________________________________________________________________ BOOT DEVICE 1st Boot Device/2nd Boot Device/3rd Boot Device PRIORITY OPTIONS This option specifies the device type of each boot drive from which AMIBIOS attempts to boot after the POST routines complete. Available options for each boot device line item are determined by the types of bootable devices available on your system. The Setup screen displays the system option(s): 1st Boot Device [Removable Dev.] 2nd Boot Device [ATAPI CDROM] 3rd Boot Device [Hard Drive] TRENTON Technology Inc. 7-9 Boot Setup T4I Technical Reference Available options are: Removable Dev. ATAPI CDROM Hard Drive Disabled 7-10 TRENTON Technology Inc. T4I Technical Reference Boot Setup HARD DISK DRIVES When you select Hard Disk Drives from the Boot Setup Menu, the following Setup screen displays: BIOS SETUP UTILITY |Boot| Hard Disk Drives Specifies the boot _____________________________________________ sequence from the 1st Hard Disk Drive [xxxxxxxxx] available devices. 2nd Hard Disk Drive [xxxxxxxxx] 3rd Hard Disk Drive [xxxxxxxxx] ←→ Select Screen ↑↓ Select Item +- Change Option F1 General Help F10 Save and Exit ESC Exit vxx.xx (C)Copyright 1985-2001, American Megatrends, Inc. Hard Disk Drives Screen When you display the Hard Disk Drives screen, the format is similar to the sample shown above. Highlight the option you wish to change and press to display the available settings. Select the appropriate setting and press again to accept the highlighted value. _______________________________________________________________________ NOTE: This screen is available only if there is at least one hard disk drive on your system. The number of line items is determined by the number of hard disk drives available. _______________________________________________________________________ HARD DISK DRIVES The SBC supports up to four hard disk drives through a primary and secondary controller in a master/slave configuration. OPTIONS 1st Hard Drive/2nd Hard Drive/3rd Hard Drive When the system boots up, it searches for all hard drives and displays the description of each disk drive(s) it has detected. If you have more than one hard disk drive, you may change the order in which the system will attempt to boot the available hard drives by changing these line items. The number of options displayed for each line item depends on the number of hard disk drives in your system. TRENTON Technology Inc. 7-11 Boot Setup T4I Technical Reference Disabled is also available as an option if you do not want a particular drive to be included in the boot sequence. The Setup screen displays the system options: 1st Hard Disk Drive [xxxxxxxxx] 2nd Hard Disk Drive [xxxxxxxxx] 3rd Hard Disk Drive [xxxxxxxxx] where xxxxxxxxx is the description of the hard drive 7-12 TRENTON Technology Inc. T4I Technical Reference Boot Setup REMOVABLE When you select Removable Devices from the Boot Setup Menu, the following Setup DEVICES screen displays: BIOS SETUP UTILITY |Boot| Specifies the boot 1st Removable Device [1st FLOPPY DRIVE] sequence from the 2nd Removable Device [IOMEGA ZIP 100] available devices. ←→ Select Screen ↑↓ Select Item +- Change Option F1 General Help F10 Save and Exit ESC Exit vxx.xx (C)Copyright 1985-2001, American Megatrends, Inc. Removable Devices Screen When you display the Removable Devices screen, the format is similar to the sample shown above. Highlight the option you wish to change and press to display the available settings. Select the appropriate setting and press again to accept the highlighted value. _______________________________________________________________________ NOTE: This screen is available only if there is at least one removable device on your system. The number of line items is determined by the number of removable devices available. _______________________________________________________________________ REMOVABLE The SBC supports multiple removable devices and allows you to change the boot sequence of these devices. DEVICES OPTIONS 1st Removable Device/2nd Removable Device When the system boots up, it searches for all removable devices and displays the description of each device it has detected. If you have more than one removable device, you may change the order in which the system will attempt to boot the available devices by changing these line items. The number of options displayed for each line item depends on the number of removable devices in your system. TRENTON Technology Inc. 7-13 Boot Setup T4I Technical Reference Disabled is also available as an option if you do not want a particular device to be included in the boot sequence. The Setup screen displays the system option: 1st Removable Device [xxxxxxxxx] 2nd Removable Device [xxxxxxxxx] where xxxxxxxxx is the description of the removable device (e.g., floppy drive, IOMEGA ZIP drive, etc.) 7-14 TRENTON Technology Inc. T4I Technical Reference Boot Setup ATAPI CDROM When you select ATAPI CDROM Drives from the Boot Setup Menu, the following DRIVES Setup screen displays: BIOS SETUP UTILITY |Boot| Specifies the boot 1st ATAPI CDROM [ATAPI 52X CDROM] sequence from the 2nd ATAPI CDROM [TEAC CD-210PU] available devices. ←→ Select Screen ↑↓ Select Item +- Change Option F1 General Help F10 Save and Exit ESC Exit vxx.xx (C)Copyright 1985-2001, American Megatrends, Inc. ATAPI CDROM Drives Screen When you display the ATAPI CDROM Drives screen, the format is similar to the sample shown above. Highlight the option you wish to change and press to display the available settings. Select the appropriate setting and press again to accept the highlighted value. _______________________________________________________________________ NOTE: This screen is available only if there is at least one ATAPI CDROM drive on your system. The number of line items is determined by the number of ATAPI CDROM drives available. _______________________________________________________________________ ATAPI CDROM The SBC supports multiple ATAPI CD-ROM devices and allows you to change the boot sequence of these devices. DRIVES OPTIONS 1st ATAPI CDROM/2nd ATAPI CDROM When the system boots up, it searches for all ATAPI CD-ROM drives and displays the description of each drive it has detected. If you have more than one ATAPI CD-ROM drive, you may change the order in which the system will attempt to boot the available drives by changing these line items. The number of options displayed for each line item depends on the number of ATAPI CD- ROM devices in your system. TRENTON Technology Inc. 7-15 Boot Setup T4I Technical Reference Disabled is also available as an option if you do not want a particular drive to be included in the boot sequence. The Setup screen displays the system option: 1st ATAPI CDROM [xxxxxxxxx] 2nd ATAPI CDROM [xxxxxxxxx] where xxxxxxxxx is the description of the ATAPI CD-ROM drive Copyright 2002 by Trenton Technology Inc. All rights reserved. 7-16 TRENTON Technology Inc. T4I Technical Reference BIOS Messages Appendix A BIOS Messages BIOS BEEP CODES Errors may occur during the POST (Power-On Self Test) routines which are performed each time the system is powered on. Non-fatal errors are those which, in most cases, allow the system to continue the bootup process. The error message normally appears on the screen. See BIOS Error Messages later in this section for descriptions of these messages. Fatal errors are those which will not allow the system to continue the bootup procedure. These fatal errors are usually communicated through a series of audible beeps. Each error message has its own specific beep code, defined by the number of beeps following the error detection. The following table lists the errors which are communicated audibly. Beep Count Description 1 Memory refresh timer error 2 Parity Error 3 Main memory read/write test error 4 Timer not operational 5 Processor error 6 Keyboard controller BAT test error 7 General exception error 8 Display memory error 9 ROM checksum error 10 CMOS shutdown register read/write error 11 Cache memory bad BIOS BEEP CODE TROUBLESHOOTING Beep Count Troubleshooting Action 1, 2 or 3 Reseat the memory or replace with known good modules. 4-7, 9-11 Fatal error. Perform the following steps before calling Technical Support. Remove all expansion cards and and try to reboot. If the beep code is still generated, call Technical Support. If the beep code is not generated, one of the add-in cards is causing the malfunction. Insert the cards back into the system one at a time until the problem recurs. This will indicate the malfunctioning card. 8 The board may be faulty. Call Technical Support. TRENTON Technology Inc. A-1 BIOS Messages T4I Technical Reference BIOS ERROR If a non-fatal error occurs during the POST routines performed each time the system is MESSAGES powered on, the error message will appear on the screen in the following format: ERROR Message Line 1 ERROR Message Line 2 Press F1 to Resume Note the error message and press the key to continue with the bootup procedure. _______________________________________________________________________ NOTE: If the "Wait for ’F1’ If Any Error" option in the Advanced Setup portion of the BIOS Setup Program has been set to Disabled, the "Press F1 to Resume" prompt will not appear on the last line. _______________________________________________________________________ For most of the error messages, there is no ERROR Message Line 2. Generally, for those messages containing an ERROR Message Line 2, the text will be "RUN SETUP UTILITY." Pressing the key will invoke the BIOS Setup Utility. A description of each error message appears below. MEMORY ERRORS Message Description Gate20 Error The BIOS is unable to properly control the SBC’s Gate A20 function, which controls access to memory over 1MB. This may indicate a problem with the board. Multi-Bit ECC Error This message only occurs on systems using ECC enabled memory modules. ECC memory has the ability to correct single- bit errors that may occur from faulty memory modules. A multiple bit corruption of memory has occurred, and the ECC memory algorithm cannot correct it. This may indicate a defective memory module. Parity Error Fatal memory parity error. System halts after displaying this message. BOOT ERRORS Message Description Boot Failure ... This is a generic message indicating the BIOS could not boot from a particular device. This message is usually followed by other information concerning the device. Invalid Boot Diskette A diskette was found in the drive, but it is not configured as a bootable diskette. Drive Not Ready The BIOS was unable to access the drive because it indicated it was not ready for data transfer. This is often reported by drives when no media is present. A-2 TRENTON Technology Inc. T4I Technical Reference BIOS Messages BIOS ERROR BOOT ERRORS (continued) MESSAGES (CONTINUED) Message Description A: Drive Error The BIOS attempted to configure the A: drive during POST, but was unable to properly configure the device. This may be due to a bad cable or faulty diskette drive. B: Drive Error The BIOS attempted to configure the B: drive during POST, but was unable to properly configure the device. This may be due to a bad cable or faulty diskette drive. Insert BOOT diskette in A: The BIOS attempted to boot from the A: drive, but could not find a proper boot diskette. Reboot and Select proper Boot BIOS could not find a bootable device in the system and/or device or Insert Boot Media in removable media drive does not contain media. selected Boot device NO ROM BASIC This message occurs on some systems when no bootable device can be detected. STORAGE DEVICE ERRORS Message Description The following errors are typically displayed when the BIOS is trying to detect and configure IDE/ ATAPI devices in POST. XXXXXX Hard Disk Error Messages in this format indicate that the specified device could XXXXXX - ATAPI Incompatible not be properly initialized by the BIOS. Possible message are: Primary Master Hard Disk Error Primary Slave Hard Disk Error Secondary Master Hard Disk Error Secondary Slave Hard Disk Error Primary Master Drive - ATAPI Incompatible Primary Slave Drive - ATAPI Incompatible Secondary Master Drive - ATAPI Incompatible Secondary Slave Drive - ATAPI Incompatible The following messages can be reported by an ATAPI device using the S.M.A.R.T. error reporting standard. The S.M.A.R.T. failure message may indicate the need to replace the hard disk. S.M.A.R.T. Capable but The BIOS tried to send a S.M.A.R.T. message to a hard disk, but Command Failed the command transaction failed. S.M.A.R.T. Command Failed The BIOS tried to send a S.M.A.R.T. message to a hard disk, but the command transaction failed. S.M.A.R.T. Status BAD, Backup A S.M.A.R.T. capable hard disk sends this message when it and Replace detects an imminent failure. S.M.A.R.T. Capable and Status A S.M.A.R.T. capable hard disk sends this message when it BAD detects an imminent failure. TRENTON Technology Inc. A-3 BIOS Messages T4I Technical Reference BIOS ERROR VIRUS RELATED ERRORS MESSAGES (CONTINUED) Message Description The following messages only display if Virus Detection is enabled in the BIOS Setup Utility. BootSector Write !! The BIOS has detected software attempting to write to a drive’s boot sector. This is flagged as possible virus activity. VIRUS: Continue (Y/N)? The BIOS has detected possible virus activity. SYSTEM CONFIGURATION ERRORS Message Description DMA-2 Error Error initializing secondary DMA controller. This is a fatal error, often indicating a problem with system hardware. DMA Controller Error POST error while trying to initialize the DMA controller. This is a fatal error, often indicating a problem with system hardware. Checking NVRAM..Update BIOS could not write to the NVRAM block. This message appears Failed when the FLASH part is write-protected or if there is no FLASH part (system uses a PROM or EPROM). Microcode Error BIOS could not find or load the CPU Microcode Update to the CPU. This message only applies to INTEL CPUs. The message is most likely to appear when a brand new CPU is installed in an SBC with an outdated BIOS. In this case, the BIOS must be updated to include the Microcode Update for the new CPU. NVRAM Checksum Bad, There was an error while validating the NVRAM data. This NVRAM Cleared causes POST to clear the NVRAM data. Resource Conflict More than one system device is trying to use the same non- shareable resources (memory or I/O). NVRAM Ignored The NVRAM data used to store Plug and Play (PnP) data was not used for system configuration in POST. NVRAM Bad The NVRAM data used to store Plug and Play (PnP) data was not used for system configuration in POST due to a data error. Static Resource Conflict Two or more static devices are trying to use the same resource space (usually memory or I/O). PCI I/O Conflict A PCI adapter generated an I/O resource conflict when configured by BIOS POST. PCI ROM Conflict A PCI adapter generated an I/O resource conflict when configured by BIOS POST. PCI IRQ Conflict A PCI adapter generated an I/O resource conflict when configured by BIOS POST. PCI IRQ Routing Table Error BIOS POST (DIM code) found a PCI device in the system but was unable to figure out how to route an IRQ to the device. Usually this error is caused by an incomplete description of the PCI Interrupt Routine of the system. A-4 TRENTON Technology Inc. T4I Technical Reference BIOS Messages BIOS ERROR SYSTEM CONFIGURATION ERRORS (continued) MESSAGES (CONTINUED) Message Description Timer Error Indicates an error while programming the count register of channel 2 of the 8254 timer. This may indicate a problem with system hardware. Interrupt Controller-1 Error BIOS POST could not initialize the Master Interrupt Controller. This may indicate a problem with system hardware. Interrupt Controller-2 Error BIOS POST could not initialize the Slave Interrupt Controller. This may indicate a problem with system hardware. CMOS ERRORS Message Description CMOS Date/Time Not Set The CMOS Date and/or Time are invalid. This error can be resolved by readjusting the system time in the BIOS Setup Utility. CMOS Battery Low CMOS Battery is low. This message usually indicates that the CMOS battery needs to be replaced. It could also appear when the user intentionally discharges the CMOS battery. CMOS Settings Wrong CMOS settings are invalid. This error can be resolved by using the BIOS Setup Utility. CMOS Checksum Bad CMOS contents failed the Checksum check. Indicates that the CMOS data has been changed by a program other than the BIOS or that the CMOS is not retaining its data due to malfunction. This error can typically be resolved by using the BIOS Setup Utility. MISCELLANEOUS ERRORS Message Description Keyboard Error Keyboard is not present or the hardware is not responding when the keyboard controller is initialized. Keyboard/Interface Error Keyboard Controller failure. This may indicate a problem with system hardware. System Halted The system has been halted. A reset or power cycle is required to reboot the machine. This message appears after a fatal error has been detected. TRENTON Technology Inc. A-5 BIOS Messages T4I Technical Reference BOOTBLOCK The Bootblock initialization code sets up the chipset, memory and other components INITIALIZATION before system memory is available. The following table describes the type of check- CODE points that may occur during the Bootblock initialization portion of the BIOS: CHECKPOINTS Check- point Description Before Early chipset initialization is done. Early super I/O initialization is done including RTC D1 and keyboard controller. NMI is disabled. D1 Perform keyboard controller BAT test. Check if waking up from power management suspend state. Save power-on CPUID value in scratch CMOS. Go to flat mode with 4GB limit and GA20 enabled. Verify the bootblock checksum. D0 Disable cache before memory detection. Execute full memory sizing module. Verify that flat mode is enabled. D2 If memory sizing module not executed, start memory refresh and do memory sizing in Bootblock code. Do additional chipset initialization. Reenable cache. Verify that flat D3 mode is enabled. Test base 512K memory. Adjust policies and cache first 8MB. Set stack. D4 Bootblock code is copied from ROM to lower system memory and control is given to it. BIOS now executes out of RAM. D5 Both key sequence and OEM specific method is checked to determine if BIOS recovery is forced. Main BIOS checksum is tested. If BIOS recovery is necessary, control flows to checkpoint E0. See the Bootblock Recovery Code Checkpoints D6 section of this appendix for more information. Restore CPUID value back into register. The Bootblock-Runtime interface module is moved to system memory and control is given to it. Determine whether to execute serial flash. D7 The Runtime module is uncompressed into memory. CPUID information is stored in memory. D8 Store the Uncompressed pointer for future use in PMM. Copy Main BIOS into memory. Leave all RAM below 1MB Read/Write including E000 and F000 shadow areas but closing SMRAM. D9 Restore CPUID value back into register. Give control to BIOS POST (ExecutePOSTK- ernel). See the POST Code Checkpoints section of this appendix for more information. DA A-6 TRENTON Technology Inc. T4I Technical Reference BIOS Messages BOOTBLOCK The Bootblock recovery code gets control when the BIOS determines that a BIOS RECOVERY CODE recovery needs to occur because the user has forced the update or the BIOS checksum is CHECKPOINTS corrupt. The following table describes the type of checkpoints that may occur during the Bootblock recovery portion of the BIOS: Check- point Description E0 Initialize the floppy controller in the super I/O. Some interrupt vectors are initialized. DMA contoller is initialized. 8259 interrupt controller is initialized. L1 cache is enabled. E9 Set up floppy controller and data. Attempt to read from floppy. EA Enable ATAPI hardware. Attempt to read from ARMD and ATAPI CDROM. Disable ATAPI hardware. Jump back to checkpoint E9. EB Read error occurred on media. Jump back to checkpoint EB. EF Determine information about root directory of recovery media. E9 or EA Search for pre-defined recovery file name in root directory. F0 Recovery file not found. F1 Start reading FAT table and analyze FAT to find the clusters occupied by the recovery F2 file. Start reading the recovery file cluster by cluster. F3 Disable L1 cache. F5 Check the validity of the recovery file configuration to the current configuration of the FA flash part. Make flash write enabled through chipset and OEM specific method. Detect proper FB flash part. Verify that the found flash part size equals the recovery file size. The recovery file size does not equal the found flash part size. F4 Erase the flash part. FC Program the flash part. FD The flash has been updated successfully. Make flash write disabled. Disable ATAPI hardware. Restore CPUID value back into register. Give control to F000 ROM at FF F000:FFF0h. TRENTON Technology Inc. A-7 BIOS Messages T4I Technical Reference POST CODE The POST code checkpoints are the largest set of checkpoints during the BIOS pre-boot CHECKPOINTS process. The following table describes the type of checkpoints that may occur during the POST portion of the BIOS: Check- point Description 03 Disable NMI, parity, video for EGA and DMA controllers. Initialize BIOS, POST, Runtime data area. Also initialize BIOS modules on POST entry and GPNV area. Initialize CMOS as mentioned in the Kernel Variable “wCMOSFlags.” 04 Check CMOS diagnostic byte to determine if battery power is OK and CMOS checksum is OK. Verify CMOS checksum manually by reading storage area. If the CMOS checksum is bad, update CMOS with power-on default values and clear passwords. Initialize status register A. Initialize data variables that are based on CMOS setup questions. Initialize both the 8259 compatible PICs in the system. 05 Initialize the interrupt controlling hardware (generally OPIC) and interrupt vector table. 06 Do read/write test to CH-2 count register. Initialize CH-0 as system timer. Install the POSTINT1Ch handler. Enable IRQ-0 in PIC for system timer interrupt. Traps INT1Ch vector to “POSTINT1ChHandlerBlock.” 08 Initialize the CPU. The BAT test is being done on KBC. Program the keyboard controller command byte is being done after auto detection of keyboard/mouse using AMI KB-5. 0A Initialize the 8042 compatible keyboard controller. 0B Detect the presence of PS/2 mouse. 0C Detect the presence of keyboard in KBC port. 0E Testing and initialization of different input devices. Also, update the Kernel variables. Traps the INT09h vector, so that the POST INT09h handler gets control for IRQ1. Uncompress all available language, BIOS logo and silent logo modules. 13 Early POST initialization of chipset registers. 24 Uncompress and initialize any platform specific BIOS modules. 30 Initialize System Management Interrupt. 2A Initialize different devices through DIM. See DIM Code Checkpoints section of this appendix for more information. 2C Initialize different devices. Detects and initializes the video adapter installed in the system. 2E Initialize all the output devices. 31 Allocate memory for ADM module and uncompress it. Give control to ADM module for initialization. Initialize language and font modules for ADM. Activate ADM module. 33 Initialize the silent boot module. Set the window for displaying text information. 37 Display sign-on message, CPU information, setup key message and any OEM specific information. A-8 TRENTON Technology Inc. T4I Technical Reference BIOS Messages POST CODE CHECKPOINTS Check- point Description (CONTINUED) 38 Initialize different devices through DIM. See DIM Code Checkpoints section of this appendix for more information. 39 Initialize DMAC-1 and DMAC-2. 3A Initialize RTC date/time. 3B Test for total memory installed in the system. Also, check for DEL or ESC keys to limit memory test. Display total memory in the system. 3C Mid POST initialization of chipset registers. 40 Detect different devices (parallel ports, serial ports and coprocessor in CPU, etc.) successfully installed in the system and update the BDA, EBDA, etc. 50 Program the memory hole or any kind of implementation that needs an adjustment in system RAM size if needed. 52 Updates CMOS memory size from memory found in memory test. Allocates memory for Extended BIOS Data Area from base memory. 60 Initialize NUM-LOCK status and program the keyboard Typematic rate. 75 Initialize INT13 and prepare for IPL detection. 78 Initialize IPL devices controlled by BIOS and option ROMs. 7A Initialize remaining option ROMs. 7C Generate and write contents of ESCD in NVRAM. 84 Log errors encountered during POST. 85 Display errors to the user and get the user response for error. 87 Execute BIOS setup if needed/requested. 8C Late POST initialization of chipset registers. 8E Program the peripheral parameters. Enable/disable NMI as selected. 90 Late POST initialization of system management interrupt. A0 Check boot password if installed. A1 Clean-up work needed before booting to OS. A2 Take care of runtime image preparation for different BIOS modules. Fill the free area in F000h segment with 0FFh. Initialize the Microsoft IRQ Routing Table. Prepare the runtime language module. Disable the system configuration display if needed. A4 Initialize runtime language module. TRENTON Technology Inc. A-9 BIOS Messages T4I Technical Reference POST CODE CHECKPOINTS Check- (CONTINUED) point Description A7 Display system configuration screen if enabled. Initialize the CPU before boot, which includes the programming of the MTRRs. A8 Prepare CPU for OS boot, including final MTRR values. A9 Wait for user input at configuration display if needed. AA Uninstall POST INT1Ch vector and INT09h vector. Deinitialize the ADM module. AB Prepare BBS for INT19 boot. AC End of POST initialization of chipset registers. B1 Save system context for ACPI. 00 Pass control to OS Loader (typically INT19h) DIM CODE The Device Initialization Manager module gets control at various times during BIOS C HECKPOINTS POST to initialize different buses. The following table describes the main checkpoints where the DIM module is accessed: Check- point Description 2A Initialize different buses and perform the following functions: Reset, Detect and Disable (function 0); Static Device Initialization (function 1); Boot Output Device Initial- ization (function 2). Function 0 disables all device nodes, PCI devices and PnP ISA cards. It also assigns PCI Bus numbers. Function 1 initializes all static devices, which include manually configured on-board peripherals, memory and I/O decode windows in PCI-to-PCI bridges and non-compliant PCI devices. Static resources are also reserved. Function 2 searches for and initializes any PnP, PCI or AGP video drivers. 38 Initialize different buses and perform the following functions: Boot Input Device Initial- ization (function 3); IPL Device Initialization (function 4); General Device Initialization (function 5). Function 3 searches for and configures PCI input devices and detects if system has standard keyboard controller. Function 4 searches for and configures all PnP and PCI boot devices. Function 5 configures all on-board peripherals that are set to an automatic configuration and configures all remaining PnP and PCI devices. A-10 TRENTON Technology Inc. T4I Technical Reference BIOS Messages ADDITIONAL While control is in the different functions, additional checkpoints are output to Port 80H CHECKPOINTS as word values to identify the routines being executed. The low byte value indicates the main POST Code Checkpoint. The high byte is divided into two nibbles and contains two sets of information. The details of the high byte of these checkpoints are detailed in the following table: HIGH BYTE XY The upper nibble ‘X’ indicates the function number that is being executed. ‘X’ can be from 0 to 7. 0 Function 0. Disable all devices on the bus. 1 Function 1. Initialize static devices on the bus. 2 Function 2. Initialize output devices on the bus. 3 Function 3. Initialize input devices on the bus. 4 Function 4. Initialize IPL devices on the bus. 5 Function 5. Initialize general devices on the bus. 6 Function 6. Error reporting for the bus. 7 Function 7. Initialize add-on ROMs for all buses. 8 Funciton 8. Initialize BBS ROMs for all buses. The lower nibble ‘Y’ indicates the bus on which the different routines are being executed. ‘Y’ can be from 0 to 5. 0 Generic DIM (Device Initialization Manager) 1 On-board system devices 2 ISA devices 3 EISA devices 4 ISA PnP devices 5 PCI devices TRENTON Technology Inc. A-11 BIOS Messages T4I Technical Reference This page intentionally left blank. Copyright 2002 by Trenton Technology Inc. All rights reserved. A-12 TRENTON Technology Inc. Declaration of Conformity APPLICATION OF COUNCIL DIRECTIVE(S) 89/336/EEC Standard(s) to which Conformity is Declared: EN55024: 1998; EN55022: 1998, CLASS B EN61000-3-2: 2000; EN61000-3-3: 1995 Manufacturer: TRENTON TECHNOLOGY Inc. 2350 Centennial Drive Gainesville, Georgia 30504 USA Telephone: (770) 287-3100 FAX: (770) 287-3150 Type of Equipment: PCI CPU Board Model Name(s): 92-006053 (Also Known As: T4I/2.8, T4I/2.66, T4I/2.53, T4I/2.4 and T4I/2.26; T4I/2.6, T4I/2.5, T4I/2.4A, T4I/2.2, T4I/2.0A and T4I/1.8A) I, the undersigned, hereby declare that the specified equipment conforms to the Directive(s) and Standard(s) listed above. Name: Charles B. Hinson Title: Development Quality Assurance Manager Date: September 16, 2002 TRENTON Technology Inc. 2350 Centennial Drive • Gainesville, Georgia 30504 Sales: (800) 875-6031 • Phone: (770) 287-3100 • Fax: (770) 287-3150 This page intentionally left blank. Copyright 2002 by Trenton Technology Inc. All rights reserved.