TEXAS INSTRUMENTS DDC112U

® DDC112 ® DDC112 DDC112 SBAS085A – JANUARY 2000 – REVISED – AUGUST 2002 Dual Current Input 20-Bit ANALOG-TO-DIGITAL CONVERTER FEATURES DESCRIPTION MONOLITHIC CHARGE MEASUREMENT ADC The DDC112 is a dual input, wide dynamic range, charge- digitizing analog-to-digital converter (ADC) with 20-bit resolu- DIGITAL FILTER NOISE REDUCTION: tion. Low level current output devices, such as photosensors, 3.2ppm, rms can be directly connected to its inputs. Charge integration is INTEGRAL LINEARITY: continuous as each input uses two integrators; while one is ±0.005% Reading ±0.5ppm FSR being digitized, the other is integrating. HIGH PRECISION, TRUE INTEGRATING FUNC- For each of its two inputs, the DDC112 combines current-to- TION voltage conversion, continuous integration, programmable PROGRAMMABLE FULL SCALE full-scale range, A/D conversion, and digital filtering to achieve SINGLE SUPPLY a precision, wide dynamic range digital result. In addition to the internal programmable full-scale ranges, external integrat- CASCADABLE OUTPUT ing capacitors allow an additional user-settable full-scale range of up to 1000pC. APPLICATIONS To provide single-supply operation, the internal ADC utilizes a differential input, with the positive input tied to V . When the DIRECT PHOTOSENSOR DIGITIZATION REF integration capacitor is reset at the beginning of each integra- CT SCANNER DAS tion cycle, the capacitor charges to V . This charge is REF INFRARED PYROMETER removed in proportion to the input current. At the end of the PRECISION PROCESS CONTROL integration cycle, the remaining voltage is compared to V . REF LIQUID/GAS CHROMATOGRAPHY The high-speed serial shift register which holds the result of the last conversion can be configured to allow multiple DDC112 BLOOD ANALYSIS units to be cascaded, minimizing interconnections. The DDC112 is available in a SO-28 or TQFP-32 package and is Protected by US Patent #5841310 offered in two performance grades. AV AGND V DV DGND DD REF DD CAP1A CHANNEL 1 CAP1A DCLK IN1 Dual DVALID Switched CAP1B ΔΣ Digital Digital DXMIT Integrator CAP1B Modulator DOUT Filter Input/Output CAP2A DIN CAP2A CHANNEL 2 RANGE2 IN2 Control RANGE1 RANGE0 Dual CAP2B Switched Integrator CAP2B TEST CONV CLK Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Copyright © 2000, Texas Instruments Incorporated Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. www.ti.com (1) ABSOLUTE MAXIMUM RATINGS ELECTROSTATIC AV to DV ....................................................................... –0.3V to +6V DD DD DISCHARGE SENSITIVITY AV to AGND ..................................................................... –0.3V to +6V DD DV to DGND ..................................................................... –0.3V to +6V DD This integrated circuit can be damaged by ESD. Texas Instru- AGND to DGND ............................................................................... ±0.3V ments recommends that all integrated circuits be handled with V Voltage to AGND ............................................ –0.3V to AV +0.3V REF DD Digital Input Voltage to DGND ................................ –0.3V to DV +0.3V DD appropriate precautions. Failure to observe proper handling Digital Output Voltage to DGND ............................. –0.3V to DV +0.3V DD and installation procedures can cause damage. Package Power Dissipation............................................. (T – T )/θ JMAX A JA Maximum Junction Temperature (T ) ...................................... +150°C JMAX ESD damage can range from subtle performance degradation Thermal Resistance, SO, θ .................................................... +150°C/W JA to complete device failure. Precision integrated circuits may be Thermal Resistance, TQFP, θ ................................................ +100°C/W JA Lead Temperature (soldering, 10s)............................................... +300°C more susceptible to damage because very small parametric changes could cause the device not to meet its published NOTE: (1) Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. Exposure to absolute maximum specifications. conditions for extended periods may affect device reliability. PACKAGE/ORDERING INFORMATION MAXIMUM SPECIFICATION INTEGRAL TEMPERATURE PACKAGE ORDERING TRANSPORT (1) (2) PRODUCT LINEARITY ERROR RANGE PACKAGE-LEAD DESIGNATOR NUMBER MEDIA DDC112U ±0.025% Reading ±1.0ppm FSR –40°C to +85°C SO-28 DW DDC112U Rails "" " " " DDC112U/1K Tape and Reel DDC112UK ±0.025% Reading ±1.0ppm FSR 0°C to +70°C SO-28 DW DDC112UK Rails "" " " " DDC112UK/1K Tape and Reel DDC112Y ±0.025% Reading ±1.0ppm FSR –40°C to +85°C TQFP-32 PJT DDC112Y/250 Tape and Reel "" " " " DDC112Y/2K Tape and Reel DDC112YK ±0.025% Reading ±1.0ppm FSR 0°C to +70°C TQFP-32 PJT DDC112YK/250 Tape and Reel "" " " " DDC112YK/2K Tape and Reel NOTES: (1) For the most current specifications and and package information, refer to our web site at www.ti.com. (2)Models with a slash (/) are available only in Tape and Reel in the quantities indicated (e.g., /1K indicates 1000 devices per reel). Ordering 1000 pieces of “DDC112U/1K” will get a single 1000-piece Tape and Reel. DDC112 2 SBAS085A www.ti.com ELECTRICAL CHARACTERISTICS At T = +25°C, AV = DV = +5V, DDC112U, Y: T = 500μs, CLK = 10MHz, DDC112UK, YK: T = 333.3μs, CLK = 15MHz, V = +4.096V, continuous mode A DD DD INT INT REF operation, and internal integration capacitors, unless otherwise noted. DDC112U, Y DDC112UK, YK PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX UNITS ANALOG INPUTS External, Positive Full-Scale Range 0 C = 250pF 1000✻pC EXT Internal, Positive Full-Scale Range 1 47.5 50 52.5 ✻✻✻pC Range 2 95 100 105 ✻✻✻pC Range 3 142.5 150 157.5 ✻✻✻pC Range 4 190 200 210 ✻✻✻pC Range 5 237.5 250 262.5 ✻✻✻pC Range 6 285 300 315 ✻✻✻pC Range 7 332.5 350 367.5 ✻✻✻pC Negative Full-Scale Input –0.4% of Positive FS✻pC DYNAMIC CHARACTERISTICS Conversion Rate 2 3 kHz Integration Time, T Continuous Mode 500 1,000,000 333.3✻μs INT Integration Time, T Non-continuous Mode 50✻μs INT System Clock Input (CLK) 1 10 12 ✻✻ 15 MHz Data Clock (DCLK) 12 15 MHz ACCURACY (1) (2) (3) Noise, Low Level Current Input C = 0pF, Range 5 (250pC) 3.2✻ppm of FSR , rms SENSOR C = 25pF, Range 5 (250pC) 3.8✻ppm of FSR, rms SENSOR C = 50pF, Range 5 (250pC) 4.2 6.0✻7 ppm of FSR, rms SENSOR Differential Linearity Error ±0.005% Reading ±0.5ppm FSR, max✻ (4) Integral Linearity Error ±0.005% Reading ±0.5ppm FSR, typ✻ ±0.025% Reading ±1.0ppm FSR, max✻ No Missing Codes 20✻Bits Input Bias Current T = +25°C 0.1 10 ✻✻ pA A Range Error Range 5 (250pC) 5✻% of FSR (5) Range Error Match All Ranges 0.1 0.5 ✻✻ % of FSR Range Sensitivity to V V = 4.096 ±0.1V 1:1✻REF REF Offset Error Range 5, (250pC) ±200✻±600 ppm of FSR (5) Offset Error Match ±100✻ppm of FSR (6) DC Bias Voltage (Input V ) ±0.05 ±2 ✻✻ mV OS Power Supply Rejection Ratio ±25 ±200 ✻✻ ppm of FSR/V Internal Test Signal 13✻pC Internal Test Accuracy ±10✻% PERFORMANCE OVER TEMPERATURE (10) Offset Drift ±0.5 ±3 ppm of FSR/°C (10) Offset Drift Stability ±0.2✻±0.7 ppm of FSR/minute DC Bias Voltage Drift Applied to Sensor Input 3 ±1 μV/°C (10) Input Bias Current Drift +25°C to +45°C 0.01 1 ✻✻ pA/°C (10) Input Bias Current T = +75°C250 ✻✻ pA A (7) (10) Range Drift Range 5 (250pC) 25 0 25 50 ppm/°C (5) Range Drift Match Range 5 (250pC) ±0.05✻ppm/°C REFERENCE Voltage 4.000 4.096 4.200 ✻✻✻V (8) Input Current T = 500μs 150 225 275 μA INT DIGITAL INPUT/OUTPUT Logic Levels V 4.0 DV + 0.3✻✻ V IH DD V –0.3 +0.8✻✻ V IL V I = –500μA 4.5✻V OH OH V I = 500μA 0.4✻V OL OL Input Current, I –10 +10✻✻ μA IN (9) Data Format Straight Binary✻ POWER SUPPLY REQUIREMENTS Power Supply Voltage AV and DV 4.75 5.25✻✻ V DD DD Supply Current Analog Current AV = +5V 14.8 15.2 mA DD Digital Current DV = +5V 1.2 1.8 mA DD Total Power Dissipation 80 100 85 130 mW TEMPERATURE RANGE Specified Performance –40 +85 0 +70 °C Storage –60 +100✻✻ °C NOTES: (1) Input is less than 1% of full scale. (2) C is the capacitance seen at the DDC112 inputs from wiring, photodiode, etc. (3) FSR is Full-Scale Range. SENSOR (4) A best-fit line is used in measuring linearity. (5) Matching between side A and side B, not input 1 to input 2. (6) Voltage produced by the DDC112 at its input which is applied to the sensor. (7) Range drift does not include external reference drift. (8) Input reference current decreases with increasing T (see text). (9) Data format INT is Straight Binary with a small offset (see text). (10) Guaranteed but not tested. DDC112 3 SBAS085A www.ti.com PIN CONFIGURATION PIN DESCRIPTIONS PIN LABEL DESCRIPTION Top View SO 1 IN1 Input 1: analog input for Integrators 1A and 1B. The integrator that is active is set by the CONV input. 2 AGND Analog Ground. 3 CAP1B External Capacitor for Integrator 1B. 4 CAP1B External Capacitor for Integrator 1B. 5 CAP1A External Capacitor for Integrator 1A. 6 CAP1A External Capacitor for Integrator 1A. 7AV Analog Supply, +5V nominal. DD 8 TEST Test Control Input. When HIGH, a test charge is IN1 1 28 IN2 applied to the A or B integrators on the next CONV transition. AGND 2 27 AGND 9 CONV Controls which side of the integrator is connected to CAP1B 3 26 CAP2B input. In continuous mode; CONV HIGH → side A is integrating, CONV LOW → side B is integrating. CAP1B 4 25 CAP2B CONV must be synchronized with CLK (see text). CAP1A 5 24 CAP2A 10 CLK System Clock Input, 10MHz nominal. 11 DCLK Serial Data Clock Input. This input operates the CAP1A 6 23 CAP2A serial I/O shift register. AV 7 22 V DD REF 12 DXMIT Serial Data Transmit Enable Input. When LOW, this DDC112U input enables the internal serial shift register. TEST 8 21 AGND 13 DIN Serial Digital Input. Used to cascade multiple CONV 9 20 RANGE2 (MSB) DDC112s. CLK 10 19 RANGE1 14 DV Digital Supply, +5V nominal. DD 15 DGND Digital Ground. DCLK 11 18 RANGE0 (LSB) 16 DOUT Serial Data Output, Hi-Z when DXMIT is HIGH. DXMIT 12 17 DVALID 17 DVALID Data Valid Output. A LOW value indicates valid data is available in the serial I/O register. DIN 13 16 DOUT 18 RANGE0 Range Control Input 0 (least significant bit). DV 14 15 DGND DD 19 RANGE1 Range Control Input 1. 20 RANGE2 Range Control Input 2 (most significant bit). 21 AGND Analog Ground. 22 V External Reference Input, +4.096V nominal. REF 23 CAP2A External Capacitor for Integrator 2A. 24 CAP2A External Capacitor for Integrator 2A. 25 CAP2B External Capacitor for Integrator 2B. 26 CAP2B External Capacitor for Integrator 2B. 27 AGND Analog Ground. 28 IN2 Input 2: analog input for Integrators 2A and 2B. The integrator that is active is set by the CONV input. DDC112 4 SBAS085A www.ti.com PIN CONFIGURATION Top View TQFP CAP1A 1 24 CAP2A CAP1A 2 23 CAP2A AV 3 22 V DD REF NC 4 21 AGND DDC112Y NC 5 20 NC TEST 6 19 NC CONV 7 18 RANGE2 (MSB) CLK 8 17 RANGE1 PIN DESCRIPTIONS PIN LABEL DESCRIPTION PIN LABEL DESCRIPTION 1 CAP1A External Capacitor for Integrator 1A. 15 DVALID Data Valid Output. A LOW value indicates valid data is available in the serial I/O register. 2 CAP1A Exteranl Capacitor for Integrator 1A. 16 RANGE0 Range Control Input 0 (least significant bit). 3AV Analog Supply, +5V nominal. DD 17 RANGE1 Range Control Input 1. 4 NC No Connection 18 RANGE2 Range Control Input 2. (most significant bit). 5 NC No Connection 19 NC No Connection 6 TEST Test Control Input. When HIGH, a test charge is applied to the A or B integrators on the necxt CONV 20 NC No Connection transition. 21 AGND Analog Ground. 7 CONV Controls which side of the integrator is connedted to External Reference Input, +4.096V nominal. 22 V REF input. In continuous mode; CONV HIGH side A is 23 CAP2A External Capacitor for Integrator 2A. integrating, CONV LOW side B is integrating CONV must be synchronized with CLK (see text). 24 CAP2A External Capacitor for Integrator 2A. 8 CLK System Clock Input, 10MHz nominal 25 CAP2B External Capacitor for Integrator 2B. 9 DCLK Serial Data Clock Input. This input operates the 26 CAP2B Exteranl Capacitor for Integrator 2B. serial I/O shift register. 27 AGND Analog Ground. 10 DXMIT Serial Data Transmit Enable Input. When LOW, this 28 IN2 Input 2: analog input for Integrators 2A and 2B. The input enables the internal serial shift register. integrator that is active is set by the CONV input. 11 DIN Serial Digital Input. Used to cascade multiple 29 IN1 Input 1: analog input for Integrators 1A and 1B. The DDC112s. integrator that is active is set by the CONV input. 12 DV Digital Supply, +5V nominal. DD 30 AGND Analog Ground. 13 DGND Digital Ground 31 CAP1B External Capacitor for Integrator 1B. 14 DOUT Serial Data Output, Hi-Z when DXMIT is HIGH. 32 CAP1B External Capacitor for Integrator 1B. DDC112 5 SBAS085A www.ti.com DCLK CAP1B 9 32 DXMIT CAP1B 10 31 DIN AGND 11 30 DV IN1 DD 12 29 DGND IN2 13 28 DOUT AGND 14 27 DVALID CAP2B 15 26 RANGE0 (LSB) CAP2B 16 25 TYPICAL CHARACTERISTICS At T = +25°C, characterization done with Range 5 (250pC), T = 500μs, V = +4.096, AV = DV = +5V, and CLK = 10MHz, unless otherwise noted. A INT REF DD DD NOISE vs C NOISE vs T SENSOR INT 6 70 Range 1 60 5 C = 50pF SENSOR 50 4 Range 2 Range 0 C = 0pF SENSOR 40 (C = 250pF) EXT 3 Range 7 30 2 20 Range 5 1 10 0 0 0.1 1 10 100 1000 0 200 400 600 800 1000 T (ms) C (pF) INT SENSOR NOISE vs TEMPERATURE NOISE vs INPUT LEVEL 5 9 Range 1 4.5 8 C = 50pF 4 SENSOR 7 3.5 6 Range 2 3 C = 0pF SENSOR 5 2.5 Range 3 4 2 3 1.5 Range 7 2 1 C = 0pF Range 5 SENSOR 1 0.5 0 0 10 20 30 40 50 60 70 80 90 10 100 –40 –15 10 35 60 85 Input Level (% of Full-Scale) Temperature (°C) RANGE DRIFT vs TEMPERATURE I vs TEMPERATURE B 2000 10 Ranges 1 - 7 1500 (Internal Integration Capacitor) All Ranges 1000 1 500 0 0.1 –500 –1000 –1500 0.01 –40 –15 10 35 60 85 25 35 45 55 65 75 85 Temperature (°C) Temperature (°C) DDC112 6 SBAS085A www.ti.com Range Drift (ppm) Noise (ppm of FSR, rms) Noise (ppm of FSR, rms) I (pA) B Noise (ppm of FSR, rms) Noise (ppm of FSR, rms) TYPICAL PERFORMANCE CURVES At T = +25°C, characterization done with Range 5 (250pC), T = 500μs, V = +4.096, AV = DV = +5V, and CLK = 10MHz, unless otherwise noted. A INT REF DD DD OFFSET DRIFT vs TEMPERATURE INPUT V vs RANGE OS 100 36 All Ranges 35 50 34 0 33 32 –50 31 –100 30 25 35 45 55 65 75 85 12 3 4 5 6 7 Range Temperature (°C) DIGITAL SUPPLY CURRENT vs TEMPERATURE ANALOG SUPPLY CURRENT vs TEMPERATURE 18 1.4 16 1.2 14 1.0 12 0.8 10 8 0.6 6 0.4 4 0.2 2 0 0 –40 –15 10 35 60 85 –40 –15 10 35 60 85 Temperature (°C) Temperature (°C) CROSSTALK vs FREQUENCY POWER SUPPLY REJECTION RATIO vs FREQUENCY 600 0 –20 500 Separation Measured –40 Between Inputs 1 and 2 400 –60 300 –80 200 –100 100 –120 0 –140 0 25 50 75 100 0 100 200 300 400 500 Frequency (KHz) Frequency (Hz) DDC112 7 SBAS085A www.ti.com Offset Drift (ppm of FSR) Separation (dB) Current (mA) PSRR (ppm of FSR/V) V (µV) Current (mA) OS The DVALID output goes LOW when the shift register THEORY OF OPERATION contains valid data. The basic operation of the DDC112 is illustrated in Figure 1. The digital interface of the DDC112 provides the digital The device contains two identical input channels where each results via a synchronous serial interface consisting of a data performs the function of current-to-voltage integration fol- clock (DCLK), a transmit enable pin (DXMIT), a valid data pin lowed by a multiplexed analog-to-digital (A/D) conversion. (DVALID), a serial data output pin (DOUT), and a serial data Each input has two integrators so that the current-to-voltage input pin (DIN). The DDC112 contains only one A/D con- integration can be continuous in time. The output of the four verter, so the conversion process is interleaved between the integrators are switched to one delta-sigma converter via a two inputs, as shown in Figure 2. The integration and four input multiplexer. With the DDC112 in the continuous conversion process is fundamentally independent of the data integration mode, the output of the integrators from one side retrieval process. Consequently, the CLK frequency and of both of the inputs will be digitized while the other two DCLK frequencies need not be the same. DIN is only used integrators are in the integration mode as illustrated in the when multiple converters are cascaded and should be tied to timing diagram in Figure 2. This integration and A/D conver- DGND otherwise. Depending on T , CLK, and DCLK, it is INT sion process is controlled by the system clock, CLK. With a possible to daisy chain over 100 converters. This greatly 10MHz system clock, the integrator combined with the delta- simplifies the interconnection and routing of the digital out- sigma converter accomplishes a single 20-bit conversion in puts in those cases where a large number of converters are approximately 220μs. The results from side A and side B of needed. each signal input are stored in a serial output shift register. AV AGND V DV DGND DD REF DD CAP1A Input 1 CAP1A DCLK IN1 Dual DVALID Switched CAP1B ΔΣ Digital Digital DXMIT Integrator CAP1B Modulator Filter Input/Output DOUT DIN CAP2A CAP2A Input 2 RANGE2 IN2 Control RANGE1 RANGE0 Dual Switched CAP2B Integrator CAP2B TEST CLK CONV FIGURE 1. DDC112 Block Diagram. IN1, Integrator A Integrate Integrate IN1, Integrator B Integrate Integrate IN2, Integrator A Integrate Integrate Integrate Integrate IN2, Integrator B Conversion in Progress IN1B IN2B IN1A IN2A IN1B IN2B IN1A IN2A DVALID FIGURE 2. Basic Integration and Conversion Timing for the DDC112 (continuous mode). DDC112 8 SBAS085A www.ti.com DEVICE OPERATION C INPUT RANGE F RANGE2 RANGE1 RANGE0 (pF, typ) (pC, typ) Basic Integration Cycle 0 0 0 External Up to 1000 The fundamental topology of the front end of the DDC112 is 12.5 to 250 a classical analog integrator as shown in Figure 3. In this 0 0 1 12.5 –0.2 to 50 diagram, only Input 1 is shown. This representation of the 01 0 25 –0.4 to 100 input stage consists of an operational amplifier, a selectable 0 1 1 37.5 –0.6 to 150 feedback capacitor network (C ), and several switches that 10 0 50 –0.8 to 200 F implement the integration cycle. The timing relationships of 1 0 1 62.5 –0.1 to 250 all of the switches shown in Figure 3 are illustrated in Figure 11 0 75 –1.2 to 300 4. Figure 4 is used to conceptualize the operation of the 1 1 1 87.5 –1.4 to 350 integrator input stage of the DDC112 and should not be used TABLE I. Range Selection of the DDC112. as an exact timing tool for design. Block diagrams of the reset, integrate, converter and wait states of the integrator S (see Figures 4 and 5a). This is done during the reset RESET section of the DDC112 are shown in Figure 5. This internal time. In this manner, the selected capacitor is charged to the switching network is controlled externally with the convert reference voltage, V . Once the integration capacitor is REF command (CONV), range selection pins (RANGE0-RANGE2), charged, S , and S are switched so that V is no REF1 RESET REF and the system clock (CLK). For the best noise performance, longer connected to the amplifier circuit while it waits to begin CONV must be synchronized with the rising edge of CLK. It integrating (see Figure 5b). With the rising edge on CONV, is recommended CONV toggle within ±10ns of the rising S closes which begins the integration of Channel A. This INTA edge of CLK. puts the integrator stage into its integrate mode (see Figure The non-inverting inputs of the integrators are internally 5c). referenced to ground. Consequently, the DDC112 analog Charge from the input signal is collected on the integration ground should be as clean as possible. The range switches, capacitor causing the voltage output of the amplifier to along with the internal and external capacitors (C ) are F decrease. A falling edge CONV stops the integration by shown in parallel between the inverting input and output of switching the input signal from side A to side B (S and INTA the operational amplifier. Table I shows the value of the S ). Prior to the falling edge of CONV, the signal on side INTB integration capacitor (C ) for each range. At the beginning of F B was converted by the A/D converter and reset during the a conversion, the switches S , S , S , S , S , A/D INTA INTB REF1 REF2 time that side A was integrating. With the falling edge of and S are set (see Figure 4). RESET CONV, side B starts integrating the input signal. Now the At the completion of an A/D conversion, the charge on the output voltage of side A’s operational amplifier is presented integration capacitor (C ) is reset with S and to the input of the ΔΣ A/D converter (see Figure 5d). F REF1 CAP1A CAP1A S REF1 V REF 50pF RANGE2 25pF RANGE1 12.5pF RANGE0 S S REF2 INTA S A/D1A Input IN1 S Current RESET To Converter Integrator A ESD Protection S INTB Diode Photodiode Integrator B (same as A) FIGURE 3. Basic Integrator Configuration for Input 1 Shown with a 250pC (C = 62.5pF) Input Range. F DDC112 9 SBAS085A www.ti.com CONV CLK S INTA S INTB S REF1 S REF2 S RESET S A/D1A Configuration of Convert Wait Integrate Convert Wait Integrator A V REF Integrator A Voltage Output FIGURE 4. Basic Integrator Timing Diagram as Illustrated in Figure 3. S C REF1 F V REF S INT S REF2 S REF1 C F IN V To Converter REF S RESET S A/D S INT S REF2 IN To Converter S RESET S A/D a) Reset Configuration S C REF1 F b) Wait Configuration V REF S INT S REF2 S C REF1 F IN V REF To Converter S RESET S A/D S INT S REF2 IN To Converter S RESET S A/D c) Integrate Configuration d) Convert Configuration FIGURE 5. Diagrams for the Four Configurations of the Front End Integrators of the DDC112. DDC112 10 SBAS085A www.ti.com Reset Wait Reset Wait Determining the Integration Capacitor (C ) Value EXTERNAL CAPACITOR PINS INTEGRATOR F DDC112U, UK DDC112Y, YK Channel Side The value of the integrator’s feedback capacitor, the integra- 5 and 6 1 and 2 1 A tion period, and the reference voltage determine the positive 3 and 4 31 and 32 1 B full-scale (+FS) value of the DDC112. The approximate 23 and 24 23 and 24 2 A positive full-scale value of the DDC112 is given by the 25 and 26 25 and 26 2 B following equations: TABLE II. External Capacitor Connections with Range Con- figuration of RANGE2-RANGE0 = 000. QI = •T IN IN INT Since the range accuracy depends on the characteristics of QV = (09 . 6) •C FS REF F the integration capacitor, they must be carefully selected. An 09 . 6VC • ( ) REF F I = external integration capacitor should have low voltage coef- FS T INT ficient, temperature coefficient, memory, and leakage cur- or rent. The optimum selection depends on the requirements of IT • FS INT the specific application. Suitable types include COG ceramic, C = F (. 096) V polycarbonate, polystyrene, and silver mica. REF Voltage Reference The “0.96” factor allows the front end integraters to reach full The external voltage reference is used to reset the integra- scale without having to completely swing to ground. The tion capacitors before an integration cycle begins. It is also negative full-scale (–FS) range is approximately 0.4% of the used by the ΔΣ converter while the converter is measuring positive full-scale range. For example, Range 5 has a nomi- the voltage stored on the integrators after an integration nal +FS range of 250pC. The –FS range is then approxi- cycle ends. During this sampling, the external reference must mately –1pC. This relationship holds for external capacitors supply charge needed by the ΔΣ converter. For an integration as well and is independent of V (for V within the REF REF time of 500μs, this charge translates to an average V REF allowable range, see the Specification table). current of approximately 150μA. The amount of charge Integration Capacitors needed by the ΔΣ converter is independent of the integration There are seven different capacitors available on chip for time, therefore, increasing the integration time lowers the each side of each channel in the DDC112. These internal average current. For example, an integration time of 1000μs capacitors are trimmed in production to achieve the specified lowers to average V current to 75μA. REF performance for range error of the DDC112. The range It is critical that V be stable during the different modes of REF control pins (RANGE0-RANGE2) change the capacitor value operation shown in Figure 5. The ΔΣ converter measures the for all four integrators. Consequently, both inputs and both voltage on the integrator with respect to V . Since the REF sides of each input will always have the same full scale integrator’s capacitors are initially reset to V , any droop in REF range unless external capacitors are used. V from the time the capacitors are reset to the time when REF the converter measures the integrator’s output will introduce External integration capacitors may be used instead of the an offset. It is also important that V be stable over longer internal capacitors values by setting RANGE2-RANGE0 = REF periods of time as changes in V correspond directly to 000. The external capacitor pin connections are summa- REF changes in the full-scale range. Finally, V should intro- rized in Table II. Usually, all four external capacitors are REF duce as little additional noise as possible. equal in value, however, it is possible to have differing pairs of external capacitors between Input 1 and For reasons mentioned above, it is strongly recommended Input 2 of the DDC112. Regardless of the selected value that the external reference source be buffered with an of the capacitor, it is strongly recommended that the operational amplifier, as shown in Figure 6. In this circuit, capacitors for sides A and B be the same. the voltage reference is generated by a 4.096V reference. +5V 0.10μF +5V 7 0.47μF 2 1 To V 6 REF OPA350 Pin 22 of 10kΩ 3 2 the DDC112 REF3040 + 10μF 0.1μF + 10μF 0.10μF 4 3 FIGURE 6. Recommended External Voltage Reference Circuit for Best Low Noise Operation with the DDC112. DDC112 11 SBAS085A www.ti.com A low-pass filter to reduce noise connects it to an opera- DDC112 Frequency Response tional amplifier configured as a buffer. This amplifier should The frequency response of the DDC112 is set by the front end have a unity gain bandwidth greater than 4MHz, low noise, integrators and is that of a traditional continuous time integra- and input/output common-mode ranges that support V . REF tor, as shown in Figure 7. By adjusting T , the user can INT Following the buffer are capacitors placed close to the change the 3dB bandwidth and the location of the notches in DDC112’s V pin. Even though the circuit in Figure 6 REF the response. The frequency response of the ΔΣ converter that might appear to be unstable due to the large output capaci- follows the front end integrator is of no consequence because tors, it works well for most operational amplifiers. It is NOT the converter samples a held signal from the integrators. That recommended that series resistance be placed in the output is, the input to the ΔΣ converter is always a DC signal. Since lead to improve stability since this can cause droop in V REF the output of the front end integrators are sampled, aliasing can which produces large offsets. occur. Whenever the frequency of the input signal exceeds one-half of the sampling rate, the signal will “fold” back down to lower frequencies. 0 Test Mode When TEST is used, pins IN1 and IN2 are grounded and –10 “packets” of approximately 13pC charge are transferred to the integration capacitors of both Input 1 and Input 2. This –20 fixed charge can be transferred to the integration capacitors either once during an integration cycle or multiple times. In –30 the case where multiple packets are transferred during one integration period, the 13pC charge is additive. This mode –40 can be used in both the continuous and non-continuous mode timing. The timing diagrams for test mode are shown –50 in Figure 8. The top three lines in Figure 8 define the timing 0.1 1 10 100 when one packet of 13pC is sent to the integration capaci- T T T T INT INT INT INT tors. The bottom three lines define the timing when multiple Frequency packets are sent to the integration capacitors. FIGURE 7. Frequency Response of the DDC112. Test Mode Disabled Test Mode Disabled Test Mode Enabled Action Integrate B Integrate A 13pC into B 13pC into A 13pC into B 13pC into A Integrate B Integrate A CONV TEST t t 1 2 Test Mode Disabled Test Mode Enabled Test Mode Disabled Action Integrate B Integrate A 13pC into B 26pC into A 39pC into B 52pC into A Integrate B Integrate A CONV t t t 4 5 2 TEST t t t 1 3 4 FIGURE 8. Timing Diagram of the Test Mode of the DDC112. CLK = 10MHz CLK = 15MHz SYMBOL DESCRIPTION MIN TYP MAX MIN TYP MAX UNITS t Setup Time for Test Mode Enable 100 100 ns 1 t Setup Time for Test Mode Disable 100 100 ns 2 t Hold Time for Test Mode Enable 100 100 ns 3 t From Rising Edge of TEST to the Edge of CONV 5.4 3.6 μs 4 while Test Mode Enabled t Rising Edge to Rising Edge of TEST 5.4 3.6 μs 5 TABLE III. Timing for the DDC112 in the Test Mode. DDC112 12 SBAS085A www.ti.com Gain (dB) TEST and CONV work together to implement this feature. Continuous and Non-Continuous The test mode is entered when TEST is HIGH prior to a Operational Modes CONV edge. At that point, a CONV edge triggers the ground- The state diagram of the DDC112 is shown in Figure 9. In all, ing of the analog inputs and the switching of 13pC packets there are 8 states. Table IV provides a brief explanation of of charge onto the integration capacitors. If TEST is kept each of the states. HIGH through at least two conversions (i.e., a rise and fall of CONV), all four integrators will be charged with a 13pC STATE MODE DESCRIPTION packet. At the end of each conversion, the voltage at the 1 Ncont Complete m/r/az of side A, then side B (if previous output of the integrators is digitized as discussed in the state is state 4). Initial power-up state when CONV is initially held HIGH. “Continuous Mode” and “Non-Continuous Mode” section of 2 Ncont Prepare side A for integration. this data sheet. The test mode is exited when TEST is LOW 3 Cont Integrate on side A. and a CONV edge occurs. 4 Cont Integrate on side B; m/r/az on side A. Once the test mode is entered as described above, TEST 5 Cont Integrate on side A; m/r/az on side B. can cycle as many times as desired. When this is done, 6 Cont Integrate on side B. additional 13pC packets are added on the rising edge of 7 Ncont Prepare side B for integration. TEST to the existing charge on the integrator capacitors. 8 Ncont Complete m/r/az of side B, then side A (if previous Multiple charge packets can be added in this way as long as state is state 5). Initial power-up state when CONV the TEST pin is not LOW when CONV toggles. is initially held LOW. TABLE IV. State Descriptions. DIGITAL ISSUES The digital interface of the DDC112 provides the digital results via a synchronous serial interface consisting of a data clock mbsy (DCLK), a transmit enable pin (DXMIT), a valid data pin (DVALID), a serial data output pin (DOUT), and a serial data 1 2 CONV • mbsy input pin (DIN). The DDC112 contains only one A/D converter, Ncont Ncont so the conversion process is interleaved between the two inputs (see Figure 2). The integration and conversion process CONV is fundamentally independent of the data retrieval process. 3 Consequently, the CLK frequency and DCLK frequencies Int A CONV • mbsy need not be the same. DIN is used when multiple converters Cont are cascaded. Cascading or “daisy chaining” greatly simplifies CONV the interconnection and routing of the digital outputs in cases 4 5 CONV • mbsy where a large number of converters are needed. Refer to Int B/Meas A Int A/Meas B “Cascading Multiple Converters” section of this data sheet for Cont CONV • mbsy Cont more detail. The conversion rate of the DDC112 is set by a combination of CONV 6 the integration time (determined by the user) and the speed of CONV • mbsy Int B the A/D conversion process. The A/D conversion time is Cont primarily a function of the system clock (CLK) speed. One CONV A/D conversion cycle encompasses the conversion of two signals (one from each input of the DDC112) and reset time 7 8 for each of the integrators involved in the two conversions. In Ncont Ncont most situations, the A/D conversion time is shorter than the CONV • mbsy integration time. If this condition exists, the DDC112 will mbsy operate in the continuous mode. When the DDC112 is in the continuous mode, the sensor output is continuously integrated by one of the two sides of each input. FIGURE 9. State Diagram. In the event that the A/D conversion takes longer than the integration time, the DDC112 will switch into a non-continu- Four signals are used to control progression around the state ous mode. In non-continuous mode, the A/D converter is not diagram: CONV and mbsy and their complements. The state able to keep pace with the speed of the integration process. machine uses the level as opposed to the edges of CONV to Consequently, the integration process is periodically halted control the progression. mbsy is an internally generated until the digitizing process catches up. These two basic signal not available to the user. It is active whenever a modes of operation for the DDC112—continuous and non- measurement/reset/auto-zero (m/r/az) cycle is in progress. continuous modes—are described below. DDC112 13 SBAS085A www.ti.com During the cont mode, mbsy is not active when CONV V can be easily found for a given CLK. For example, if CLK toggles. The non-integrating side is always ready to begin = 10MHz, then a CLK period = 0.1μs. t in Table V would then 6 integrating when the other side finishes its integration. Con- be 479.4μs. sequently, keeping track of the current status of CONV is all that is needed to know the current state. Cont mode opera- SYMBOL DESCRIPTION VALUE (CLK periods) tion corresponds to states 3-6. Two of the states, 3 and 6, t Cont mode m/r/az cycle 4794 6 only perform an integration (no m/r/az cycle). t Cont mode data ready 4212 (t > 4794) 7 INT 4212 ±3(t = 4794) INT mbsy becomes important when operating in the ncont mode; t 1st ncont mode data ready 4212 ±3 8 states 1, 2, 7, and 8. Whenever CONV is toggled while mbsy t 2nd ncont mode data ready 4548 9 is active, the DDC112 will enter or remain in either ncont t Ncont mode m/r/az cycle 9108 10 state 1 (or 8). After mbsy goes inactive, state 2 (or 7) is TABLE V. Timing Specifications Generalized in CLK Periods. entered. This state prepares the appropriate side for integra- tion. As mentioned above, in the ncont states, the inputs to the DDC112 are grounded. Figure 10 shows a few integration cycles beginning with One interesting observation from the state diagram is that the initial power-up for a cont mode example. The top signal is integrations always alternate between sides A and B. This CONV and is supplied by the user. The next line indicates the relationship holds for any CONV pattern and is independent current state in the state diagram. The following two traces of the mode. States 2 and 7 insure this relationship during the show when integrations and measurement cycles are under- ncont mode. way. The internal signal mbsy is shown next. Finally, DVALID is given. As described in the data sheet, DVALID goes active When power is first applied to the DDC112, the beginning LOW when data is ready to be retrieved from the DDC112. state is either 1 or 8, depending on the initial level of CONV. It stays LOW until DXMIT is taken LOW by the user. In Figure For CONV held HIGH at power-up, the beginning state is 1. 10 and the following timing diagrams, it is assumed that Conversely, for CONV held LOW at power-up, the beginning DXMIT it taken LOW soon after DVALID goes LOW. The text state is 8. In general, there is a symmetry in the state below the DVALID pulse indicates the side of the data and diagram between states 1-8, 2-7, 3-6 and 4-5. Inverting arrows help match the data to the corresponding integration. CONV results in the states progressing through their sym- The signals shown in Figures 10 through 19 are drawn at metrical match. approximately the same scale. In Figure 10, the first state is ncont state 1. The DDC112 TIMING EXAMPLES always powers up in the ncont mode. In this case, the first Cont Mode state is 1 because CONV is initially HIGH. After the first two states, cont mode operation is reached and the states begin A few timing diagrams will now be discussed to help illustrate toggling between 4 and 5. From now on, the input is being the operation of the state machine. These are shown in continuously integrated, either by side A or side B. The time Figures 10 through 19. Table V gives generalized timing needed for the m/r/az cycle, t , is the same time that specifications in units of CLK periods. Values in μs for Table 6 CONV State 15 2 3 4 4 Integration Integrate A Integrate B Integrate A Integrate B Status m/r/az m/r/az A m/r/az B m/r/az A Status t 6 mbsy DVALID t 7 t = 0 Side A Side B Side A Power-Up Data Data Data SYMBOL DESCRIPTION VALUE (CLK = 10MHz) VALUE (CLK = 15MHz) t Cont mode m/r/az cycle 479.4μs 319.6μs 6 t Cont mode data ready 421.2μs(T > 479.4μs) 280.8μs(T > 319.6μs) 7 INT INT 421.2 ±0.3μs(T = 479.4μs) 280.8 ±0.2μs(T = 319.6μs) INT INT FIGURE 10. Continuous Mode Timing (CONV HIGH at power-up). DDC112 14 SBAS085A www.ti.com determines the boundary between the cont and ncont modes Figure 11 shows the result of inverting the logic level of described earlier in the Overview section. DVALID goes CONV. The only difference is in the first three states. After- LOW after CONV toggles in time t , indicating that data is wards, the states toggle between 4 and 5 just as in the 7 ready to be retrieved. As shown in Figure 10, there are two previous example. Figure 12 shows the timing diagram of the values for t , depending on T . The reason for this will be internal operations occurring during continuous mode opera- 7 INT discussed in the Special Considerations section. tion. CONV State84 7 6 5 5 Integration Integrate B Integrate A Integrate B Integrate A Status m/r/az m/r/az B m/r/az A m/r/az B Status t 6 mbsy DVALID t 7 t = 0 Side B Side A Side B Power-Up Data Data Data FIGURE 11. Continuous Mode Timing (CONV LOW at power-up). End Integration Side A End Integration Side B End Integration Side A Start Integration Side B Start Integration Side A Start Integration Side B T INT CONV T INT Side A Side B Side A A/D Conversion t 12 Input 1 (Internal) Side A Side B A/D Conversion Input 2 (Internal) t 12 t t 13 14 DVALID Side A Side B Data Ready Data Ready FIGURE 12. Timing Diagram of the Internal Operation in Continuous Mode of the DDC112. CLK = 10MHz CLK = 15MHz SYMBOL DESCRIPTION MIN TYP MAX MIN TYP MAX UNITS T Integration Period (continuous mode) 500 1,000,000 333 1,000,000 μs INT t A/D Conversion Time (internally controlled) 202.2 134.8 μs 12 t A/D Conversion Reset Time (internally controlled) 13.2 8.8 μs 13 t Integrator and A/D Conversion Reset Time 61.8 41.2 μs 14 (internally controlled) TABLE VI. Timing for the Internal Operation in the Continuous Mode. DDC112 15 SBAS085A www.ti.com Ncont Mode same time as in the cont mode. The second data will be ready in time t after the first data is ready. One result of the 9 Figure 13 illustrates operation in the ncont mode. The naming convention used in this application bulletin is that integrations come in pairs (i.e., sides A/B or sides B/A) when the DDC112 is operating in the “ncont mode”, it followed by a time during which no integrations occur. passes through both “ncont mode states” and “cont mode During that time, the previous integrations are being mea- states”. For example, in Figure 13, the state pattern is 3, 4, sured, reset and auto-zeroed. Before the DDC112 can 1, 2, 3, 4, 1, 2, 3, 4...where 3 and 4 are cont mode states. advance to states 3 or 6, both sides A and B must be “Ncont mode” by definition means that for some portion of finished with the m/r/az cycle which takes time t . When the 10 the time, neither side A nor B is integrating. States that m/r/az cycles are completed, time t is needed to prepare 11 perform an integration are labeled “cont mode states” while the next side for integration. This time is required for the those that do not are called “ncont mode states”. Since ncont mode because the m/r/az cycle of the ncont mode is integrations are performed in the ncont mode, just not slightly different from that of the cont mode. After the first continuously, some cont mode states must be used in a integration ends, DVALID goes LOW in time t . This is the 8 ncont mode state pattern. CONV State 34 1 23 4 1 2 t 11 Integration Int A Int B Int A Int B Status m/r/az m/r/az A m/r/az B m/r/az A m/r/az B Status t 10 mbsy t 9 DVALID t 8 Side A Side B Side A Side B Data Data Data Data SYMBOL DESCRIPTION VALUE (CLK = 10MHz) VALUE (CLK = 15MHz) t 1st ncont mode data ready 421.2 ±0.3μs 280.8 ±0.2μs 8 t 2nd ncont mode data ready 454.8μs 303.2μs 9 t Ncont mode m/r/az cycle 910.8μs 607.2μs 10 t Prepare side for integration ≥ 24.0μs ≥ 24.0μs 11 FIGURE 13. Non-Continuous Mode Timing. DDC112 16 SBAS085A www.ti.com Start Integration Side A Start Integration Side A End Integration Side A Start Integration Side B End Integration Side B Release State Wait State T INT t 17 CONV T INT t 16 A/D Conversion t Input 1 12 A/D Conversion t Input 2 12 t 13 t 15 DVALID Side A Side B Data Ready Data Ready FIGURE 14. Conversion Detail for the Internal Operation of the Non-Continuous Mode with Side A Integrated First. CLK = 10MHz CLK = 15MHz SYMBOL DESCRIPTION MIN TYP MAX MIN TYP MAX UNITS T Integration Time (non-continuous mode) 50 1,000,000 50 1,000,000 μs INT t A/D Conversion Time (internally controlled) 202.2 134.8 μs 12 t A/D Conversion Reset Time (internally controlled) 13.2 8.8 μs 13 t Integrator and A/D Conversion Reset Time 37.8 25.2 μs 15 (internally controlled) t Total A/D Conversion and Rest Time 910.8 607.2 μs 16 (internally controlled) t Release Time 24 24 μs 17 TABLE VII. Internal Timing for the DDC112 in the Non-Continuous Mode. Start Integration Side B Start Integration Side B End Integration Side B Start Integration Side A End Integration Side A Release State Wait State T INT CONV T t INT 17 t 16 A/D Conversion t Input 1 12 A/D Conversion Input 2 t 12 t 13 t 15 DVALID Side B Side A Data Ready Data Ready FIGURE 15. Internal Operation Timing Diagram of the Non-Continuous Mode with Side B Integrated First. DDC112 17 SBAS085A www.ti.com Looking at the state diagram, one can see that the CONV a 50% duty cycle CONV signal with T = 1620 CLK INT pattern needed to generate a given state progression is not periods. Care must be exercised when using a square wave unique. Upon entering states 1 or 8, the DDC112 remains in to generate CONV. There are certain integration times that those states until mbsy goes LOW, independent of CONV. must be avoided since they produce very short intervals for As long as the m/r/az cycle is underway, the state machine state 2 (or state 7 if CONV is inverted). As seen in the state ignores CONV (see Figure 9). The top two signals are diagram, the state progresses from 2 to 3 as soon as CONV different CONV patterns that produce the same state. is HIGH. The state machine does not insure that the duration This feature can be a little confusing at first, but it does allow of state 2 is long enough to properly prepare the next side flexibility in generating ncont mode CONV patterns. For for integration (t ). This must be done by the user with 11 example, the DDC112 Evaluation Fixture operates in the proper timing of CONV. For example, if CONV is a square ncont mode by generating a square wave with pulse width wave with T = 3042 CLK periods, state 2 will only be 18 INT < t . Figure 17 illustrates operation in the ncont mode using CLK periods long, therefore, t will not be met. 6 11 CONV1 CONV2 mbsy State 34 1 23 4 1 2 FIGURE 16. Equivalent CONV Signals in Non-Continuous Mode. CONV State 34 1 2341 Integration Int A Int B Int A Int B Status mbsy DVALID Side A Side B Side A Data Data Data FIGURE 17. Non-Continuous Mode Timing with a 50% Duty Cycle CONV Signal. DDC112 18 SBAS085A www.ti.com Changing Between Modes Changing from the ncont to cont mode occurs when T is INT increased so that T is always ≥ t (see Figure 14). With a INT 6 Changing from the cont to ncont mode occurs whenever longer T , the m/r/az cycle has enough time to finish before INT T < t . Figure 18 shows an example of this transition. INT 6 the next integration begins and continuous integration of the In this figure, the cont mode is entered when the integration input signal is possible. For the special case of the very first on side A is completed before the m/r/az cycle on side B is integration when changing to the cont mode, T can be INT complete. The DDC112 completes the measurement on < t . This is allowed because there is no simultaneous 6 sides B and A during states 8 and 7 with the input signal m/r/az cycle on the side B during state 3—there is no need shorted to ground. Ncont integration begins with state 6. to wait for it to finish before ending the integration on side A. CONV State 5 45 87 65 Continuous Non-Continuous Integration Integrate A Integrate B Int A Int B Int A Status m/r/az m/r/az B m/r/az A m/r/az B m/r/az A m/r/az B Status mbsy FIGURE 18. Changing from Continuous Mode to Non-Continuous Mode. CONV State33 4 1 2 4 Non-Continuous Continuous Integration Int A Int B Integrate A Integrate B Status m/r/az m/r/az A m/r/az B m/r/az A Status mbsy FIGURE 19. Changing from Non-Continuous Mode to Continuous Mode. DDC112 19 SBAS085A www.ti.com For T ≤ t , the internal slow clock, is not allowed to shut INT 6 SPECIAL CONSIDERATIONS down and the synchronization never occurs. Therefore, the NCONT MODE INTEGRATION TIME time between CONV toggling and DVALID indicating data is ready has uncertainty due to the random phase relationship The DDC112 uses a relatively fast clock. For CLK = 10MHz, between CONV and the slow clock. This variation is this allows T to be adjusted in steps of 100ns since CONV INT ±1/(2f ) or ±3/f . The timing to the second DVALID should be synchronized to CLK. However, for the internal SLOWCLOCK CLK in the ncont mode will not have a variation since it is measurement, reset and auto-zero operations, a slower triggered off the first data ready (t ) and both are derived clock is more efficient. The DDC112 divides CLK by six and 9 from the slow clock. uses this slower clock with a period of 600ns to run the m/r/ az cycle and data ready logic. Polling DVALID to determine when data is ready eliminates any concern about the variation in timing since the readback Because of the divider, it is possible for the integration time is automatically adjusted as needed. If the data readback is to be a non-integer number of slow clock periods. For triggered off the toggling of CONV directly (instead of poll- example, if T = 5000 CLK periods (500μs for CLK = 10MHz), INT ing), then waiting the maximum value of t or t insures that there will be 833 1/3 slow clocks in an integration period. This 7 8 data will always be ready before readback occurs. non-integer relationship between T and the slow clock INT period causes the number of rising and falling slow clock Data Retrieval edges within an integration period to change from integration In the continuous and non-continuous modes of operation, to integration. The digital coupling of these edges to the the data from the last conversion is available for retrieval with integrators will in turn change from integration to integration the falling edge of DVALID (see Figure 22). The falling edge which produces noise. The change in the clock edges is not of DXMIT in combination with the data clock (DCLK) will random, but will repeat every 3 integrations. The coupling initiate the serial transmission of the data from the DDC112. noise on the integrators appears as a tone with a frequency Typically, data is retrieved from the DDC112 as soon as equal to the rate at which the coupling repeats. DVALID falls and completed before the next CONV transition To avoid this problem in cont mode, the internal slow clock from HIGH to LOW or LOW to HIGH occurs. If this is not the is shut down after the m/r/az cycle is complete when it is no case, care should be taken to stop activity on DCLK and longer needed. It starts up again just after the next integra- consequently DOUT by at least 10μs around a CONV tran- tion begins. Since the slow clock is always off when CONV sition. If this caution is ignored it is possible that the integra- toggles, the same number of slow clock edges fall within an tion that is being initiated by CONV will have additional noise integration period regardless of its length. Therefore, introduced. T ≥ 4794 CLK periods will not produce the coupling INT The serial output data at DOUT is transmitted in Straight problem described above. Binary Code per Table VIII. An output offset has been built For the ncont mode however, the slow clock must always be into the DDC112 to allow for the measurement of input left running. The m/r/az cycle is not completed before an signals near and below zero. Board leakage up to ≈ –0.4% integration ends. It is then possible to have digital coupling to of the positive full scale can be tolerated before the digital the integrators. The digital coupling noise depends heavily on output clips to all zeroes. the layout of the printed circuit board used for the DDC112. For solid grounds and power supplies with good bypassing, CODE INPUT SIGNAL it is possible to greatly reduce the coupling. However, for guaranteeing the best performance in the ncont mode, the 1111 1111 1111 1111 1111 FS 1111 1111 1111 1111 1110 FS – 1LSB integration time should be chosen to be an integer multiple of 0000 0001 0000 0000 0001 +1LSB 1/(2f ). For CLK = 10MHz, the integration time SLOWCLOCK 0000 0001 0000 0000 0000 Zero should be an integer multiple of 300ns—T = 100μs is not. INT 0000 0000 0000 0000 0000 –0.4% FS A better choice would be T = 99μs. INT TABLE VIII. Straight Binary Code Table. DATA READY Cascading Multiple Converters The DVALID signal which indicates that data is ready is generated using the internal slow clock. The phase relation- Multiple DDC112 units can be connected in serial or parallel ship between this clock and CLK is set when power is first configurations, as illustrated in Figures 20 and 21. applied and is random. Since CONV is synchronized with DOUT can be used with DIN to “daisy chain” several DDC112 CLK, it will have a random phase relationship with respect to devices together to minimize wiring. In this mode of opera- the slow clock. When T > t , the slow clock will temporarily INT 6 tion, the serial data output is shifted through multiple DDC112s, shut down as described above. This shutdown process as illustrated in Figure 20. synchronizes the internal clock with CONV so that the time R prevents DIN from floating when DXMIT is HIGH. between when CONV toggles to when DVALID goes LOW PULLUP Care should be taken to keep the capacitive load on DOUT (t and t ) is fixed. 7 8 as low as possible when running CLK=15MHz. DDC112 20 SBAS085A www.ti.com Sensor “F” Sensor “E” Sensor “D” Sensor “C” Sensor “B” Sensor “A” IN1 IN2 IN1 IN2 IN1 IN2 DDC112 DDC112 DDC112 DCLK DCLK DCLK DXMIT DVALID DXMIT DVALID DXMIT DVALID R R R Data Retrieval P P P DIN DOUT DIN DOUT DIN DOUT Outputs “F”“E” “D”“C” “B”“A” 40 Bits 40 Bits 40 Bits Data Retrievel Inputs FIGURE 20. Daisy-Chained DDC112’s. DDC112 DIN DOUT DXMIT DDC112 Data Output DOUT DIN DXMIT DDC112 DOUT DIN DXMIT Enable FIGURE 21. DDC112 in Parallel Operation. CLK t 18 DVALID t 19 DXMIT t 20 (1) DCLK t 22 t t 21 23 Input 2 Input 2 Input 1 Input 1 DOUT Bit 1 Bit 20 Bit 1 Bit 20 Output Disabled Output Disabled MSB LSB MSB LSB Output Enabled NOTE: (1) Disable DCLK (preferably hold LOW) when DXMIT is HIGH. FIGURE 22. Digital Interface Timing Diagram for Data Retrieval From a Single DDC112. SYMBOL DESCRIPTION MIN TYP MAX UNITS t Propagation Delay from Rising Edge of CLK to DVALID LOW 30 ns 18 Propagation Delay from DXMIT LOW to DVALID HIGH 30 ns t 19 t Setup Time from DCLK LOW TO DXMIT LOW 20 ns 20 t Propagation Delay from DXMIT LOW to Valid DOUT 30 ns 21 Hold Time that DOUT is Valid After Falling Edge of DCLK 5 ns t 22 t Propagation Delay from DXMIT HIGH to DOUT Disabled 30 ns 23 (1) t Propagation Delay from Falling Edge of DCLK to Valid DOUT 25 ns 22A (2) Propagation Delay from Falling Edge of DCLK to Valid DOUT 30 ns t 22B NOTES: (1) Applies to DDC112UK, YK only, with a maximum load of one DDC112UK, YK DIN (4pF typical) with an additional load of (5pF 100kΩ). (2) Applies to DDC112U, Y only, with a maximum load of one DDC112U,Y DIN (4pF typical) with an additional load of (5pF 100kΩ). TABLE IX. Timing for the DDC112 Data Retrieval. DDC112 21 SBAS085A www.ti.com CLK t 18 t 26 DVALID t 14 DXMIT t 20 (1) DCLK t t t 22 24 25 DIN t t t t 22A, 22B 23 21 Input A Input E Input F Input F DOUT Bit 20 Bit 1 Bit 1 Bit 20 Output Disabled Output Disabled MSB LSB MSB LSB Output Disabled Output Disabled Output Enabled Output Enabled NOTE: (1) Disable DCLK (preferably LOW) when DXMIT is HIGH. FIGURE 23. Timing Diagram When Using the DIN Function of the DDC112. CLK = 10MHz CLK = 15MHz SYMBOL DESCRIPTION MIN TYP MAX MIN TYP MAX UNITS t Set-Up Time From DIN to Rising Edge of DCLK 10 5 ns 24 t Hold Time For DIN After Rising Edge of DCLK 10 10 ns 25 t Hold Time for DXMIT HIGH Before Falling 2 1.33 μs 26 Edge of DVALID TABLE X. Timing for the DDC112 Data Retrieval Using DIN. RETRIEVAL BEFORE CONV TOGGLES RETRIEVAL AFTER CONV TOGGLES (CONTINUOUS MODE) (CONTINUOUS MODE) For shorter integration times, more time is available if data This is the most straightforward method. Data retrieval be- retrieval begins after CONV toggles and ends before the new gins soon after DVALID goes LO and finishes before CONV data is ready. Data retrieval must wait t after CONV toggles 29 toggles, see Figure 24. For best performance, data retrieval before beginning. Figure 25 shows an example of this. The must stop t before CONV toggles. This method is the most 28 maximum time available for retrieval is t – t –t (421.2μs 27 29 26 appropriate for longer integration times. The maximum time – 10μs –2μs for CLK = 10MHz), regardless of TINT. The available for readback is T – t – t . INT 27 28 maximum number of DDC112s that can be daisy-chained For DCLK and CLK = 10MHz, the maximum number of together is: DDC112s that can be daisy-chained together is: 409.2μs Ts – 431.2μ INT 40τ 40τ DCLK DCLK For DCLK = 10MHz, the maximum number of DDC112s is Where τ is the period of the data clock. For example, if DCLK 102. TINT = 1000μs and DCLK = 10MHz, the maximum number of DDC112s is: 1000μμ ss – 431.2 =→ 142.2 142 DDC112s () 40(100ns) DDC112 22 SBAS085A www.ti.com CONV T T INT INT DVALID t 27 t 28 DXMIT DCLK ••• ••• DOUT ••• ••• Side B Side A Data Data CLK = 10MHz CLK = 15MHz SYMBOL DESCRIPTION MIN TYP MAX MIN TYP MAX UNITS t Cont Mode Data Ready 421.2 280.8 μs 27 t Data Retrieval Shutdown Before Edge of CONV 10 10 μs 28 FIGURE 24. Readback Before CONV Toggles. T T T CONV INT INT INT DVALID t 27 t t 29 26 DXMIT DCLK ••• ••• ••• DOUT ••• ••• ••• Side A Side B Side A Data Data Data CLK = 10MHz CLK = 15MHz SYMBOL DESCRIPTION MIN TYP MAX MIN TYP MAX UNITS t Hold Time for DXMIT HIGH Before Falling Edge 2 1.33 μs 26 of DVALID t Cont Mode Data Ready 421.2 280.8 μs 27 t Data Retrieval Start-Up After Edge of CONV 10 10 μs 29 FIGURE 25. Readback After CONV Toggles. DDC112 23 SBAS085A www.ti.com RETRIEVAL BEFORE AND AFTER CONV goes LOW in time t after the first integration completes. If 30 TOGGLES (CONTINUOUS MODE) T is shorter than this time, all of t is available to retrieve INT 31 data before the other side’s data is ready. For T > t , the INT 30 For the absolute maximum time for data retrieval, data can first integration’s data is ready before the second integration be retrieved before and after CONV toggles. Nearly all of T INT completes. Data retrieval must be delayed until the second is available for data retrieval. Figure 26 illustrates how this is integration completes leaving less time available for retrieval. done by combining the two previous methods. You must The time available is t – (T – t ). The second integration’s 31 INT 30 pause the retrieval during CONV’s toggling to prevent digital data must be retrieved before the next round of integrations noise, as discussed previously, and finish before the next begin. This time is highly dependent on the pattern used to data is ready. The maximum number of DDC112s that can generate CONV. As with the continuous mode, data retrieval be daisy-chained together is: must halt before and after CONV toggles (t , t ) and be 28 29 Ts–– 20μμ 2s INT completed before new data is ready (t ). 26 40τ DCLK POWER-UP SEQUENCING For T = 500μs and DCLK = 10MHz, the maximum number INT of DDC112s is 119. Prior to power-up, all digital and analog input pins must be LOW. At the time of power-up, these signal inputs can be biased to a voltage other than 0V, however, they should RETRIEVAL: NONCONTINUOUS MODE never exceed AV or DV . The level of CONV at power- DD DD Retrieving in noncontinuous mode is slightly different as up is used to determine which side (A or B) will be integrated compared with the continuous mode. As shown in Figure 27 first. Before integrations can begin though, CONV must and described in detail in Application Bulletin AB-131, DVALID toggle, as shown in Figure 28. CONV T T T INT INT INT t DVALID 29 t 26 t 28 DXMIT DCLK ••• ••• ••• ••• ••• ••• ••• ••• ••• ••• ••• ••• DOUT Side B Side A Data Data CLK = 10MHz CLK = 15MHz SYMBOL DESCRIPTION MIN TYP MAX MIN TYP MAX UNITS t Hold Time for DXMIT HIGH Before Falling 2 1.33 μs 26 Edge of DVALID t Data Retrieval Shutdown Before Edge of CONV 10 10 μs 28 t Data Retrieval Start-Up After dge of CONV 10 10 μs 29 FIGURE 26. Readback Before and After CONV Toggles. DDC112 24 SBAS085A www.ti.com T T INT INT CONV T T INT INT DVALID t t 30 31 DXMIT ••• ••• DCLK DOUT ••• ••• Side A Side B Data Data CLK = 10MHz CLK = 15MHz SYMBOL DESCRIPTION MIN TYP MAX MIN TYP MAX UNITS t 1st Ncont Mode Data Ready (see AB-131) 421.1 ±0.3 280.8 μs 30 t 2nd Ncont Mode Data Ready (see AB-131) 454.8 303.2 μs 31 FIGURE 27. Readback in Noncontinuous Mode. Release State Power-Up Start Initialization Integration CONV (HIGH at power-up) t t Integrate Side A 32 33 CONV (LOW at power-up) Integrate Side B Power Supplies FIGURE 28. Timing Diagram at Power-Up of the DDC112. SYMBOL DESCRIPTION MIN TYP MAX UNITS t Power-On Initialization Period 50 μs 32 t From Release Edge to Integration Start 50 μs 33 TABLE XI. Timing for the DDC112 Power-Up Sequence. shows the DV power supply derived from the AV supply DD DD LAYOUT with a < 10Ω isolation resistor. In both cases, the 0.1μF Power Supplies and Grounding capacitors should be placed as close to the DDC112 pack- age as possible. Both AV and DV should be as quiet as possible. It is DD DD particularly important to eliminate noise from AV that is Shielding Analog Signal Paths DD non-synchronous with the DDC112 operation. Figure 29 As with any precision circuit, careful printed circuit layout will illustrates two acceptable ways to supply power to the ensure the best performance. It is essential to make short, DDC112. The first case shows two separate +5V supplies for direct interconnections and avoid stray wiring capacitance— AV and DV . In this case, each +5V supply of the DD DD particularly at the analog input pins. Digital signals should be DDC112 should be bypassed with 10μF solid tantalum ca- kept as far from the analog input signals as possible on the pacitors and 0.1μF ceramic capacitors. The second case PC board. DDC112 25 SBAS085A www.ti.com are used for the external integration capacitors should be Input shielding practices should be taken into consideration guarded by a ground plane when the external capacitors are when designing the circuit layout for the DDC112. The inputs used. to the DDC112 are high impedance and extremely sensitive to extraneous noise. Leakage currents between the PCB The approach above reduces leakage affects by surrounding traces can exceed the input bias current of the DDC112 if these sensitive pins with a low impedance analog ground. shielding is not implemented. Figure 30 illustrates an accept- Leakage currents from other portions of the circuit will flow able approach to this problem. A PC ground plane is placed harmlessly to the low impedance analog ground rather than around the inputs of the DDC112. This shield helps minimize into the analog input stage of the DDC112. coupled noise into the input pins. Additionally, the pins that IN1 IN2 Analog Ground V + S AV DD 1 28 Analog Analog 10μF 0.1μF 2 27 Ground Ground DDC112 V + 3 26 Shield DD Shield external external 4 25 DV caps when DD caps when used 10μF 0.1μF used 5 24 6 23 Separate +5V Supplies Analog 7 22 Power DDC112U Analog 8 21 V + Ground S 9 20 AV DD 10μF 10 19 0.1μF 11 18 DDC112 < 10Ω 12 17 DV DD 13 16 0.1μF 14 15 One +5V Supply Digital I/O Digital I/O and and Digital Power Digital Power FIGURE 30. Recommended Shield for DDC112U Layout FIGURE 29. Power Supply Connection Options. Design. DDC112 26 SBAS085A www.ti.com PACKAGE DRAWINGS MSOI003E – JANUARY 1995 – REVISED SEPTEMBER 2001 DW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 16 PINS SHOWN 0.050 (1,27) 0.020 (0,51) 0.010 (0,25) M 0.014 (0,35) 16 9 0.419 (10,65) 0.400 (10,15) 0.299 (7,59) 0.010 (0,25) NOM 0.291 (7,39) Gage Plane 0.010 (0,25) 1 8 0 ñ8 0.050 (1,27) A 0.016 (0,40) Seating Plane 0.012 (0,30) 0.004 (0,10) 0.104 (2,65) MAX 0.004 (0,10) PINS ** 16 18 20 24 28 DIM 0.410 0.462 0.510 0.610 0.710 A MAX (10,41) (11,73) (12,95) (15,49) (18,03) 0.400 0.453 0.500 0.600 0.700 A MIN (10,16) (11,51) (12,70) (15,24) (17,78) 4040000 /E 08/01 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15). D. Falls within JEDEC MS-013 DDC112 27 SBAS085A www.ti.com PACKAGE DRAWINGS (Cont) MPQF112 ñ NOVEMBER 2001 PJT (S-PQFPñN32) PLASTIC QUAD FLATPACK 0,45 0,80 0,20 M 0,30 0,20 0,09 Gage Plane 32 0,15 0,25 0,05 1 0 ñ 7 7,00 SQ 0,75 9,00 SQ 0,45 1,05 0,95 Seating Plane 1,20 0,10 1,00 4203540/A 11/01 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Falls within JEDEC MS-026 DDC112 28 SBAS085A www.ti.com PACKAGE OPTION ADDENDUM www.ti.com 3-Oct-2003 PACKAGING INFORMATION ORDERABLE DEVICE STATUS(1) PACKAGE TYPE PACKAGE DRAWING PINS PACKAGE QTY DDC112U ACTIVE SOIC DW 28 28 DDC112U/1K ACTIVE SOIC DW 28 1000 DDC112UK ACTIVE SOIC DW 28 28 DDC112UK/1K ACTIVE SOIC DW 28 1000 DDC112Y/250 ACTIVE TQFP PJT 32 250 DDC112Y/2K ACTIVE TQFP PJT 32 2000 DDC112YK/250 ACTIVE TQFP PJT 32 250 DDC112YK/2K ACTIVE TQFP PJT 32 2000 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. 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