TEXAS INSTRUMENTS DAC7734EG4

DAC7734 ® DAC7734 For most current data sheet and other product information, visit www.burr-brown.com 16-Bit, Quad Voltage Output, Serial Input DIGITAL-TO-ANALOG CONVERTER FEATURES DESCRIPTION The DAC7734 is a 16-bit, quad voltage output, digital-l LOW POWER: 200mW to-analog converter with guaranteed 16-bit monotonic l UNIPOLAR OR BIPOLAR OPERATION performance over the specified temperature range. It l SINGLE SUPPLY OUTPUT RANGE: +10V accepts 24-bit serial input data, has double-buffered l DUAL SUPPLY OUTPUT RANGE: ±10V DAC input logic (allowing simultaneous update of all l SETTLING TIME: 10μs to 0.003% DACs), and provides a serial data output for daisy chaining multiple DACs. Programmable asynchronous l 16-BIT MONOTONICITY: –40°C to +85°C reset clears all registers to a mid-scale code of 8000 or Hl PROGRAMMABLE RESET TO MID-SCALE to a zero-scale of 0000 . The DAC7734 can operate H OR ZERO-SCALE from a single +15V supply or from +15V and –15V, and l DOUBLE-BUFFERED DATA INPUTS +5V supplies. l ±1 LSB DNL: –40°C to +85°C Low power and small size per DAC make the DAC7734 ideal for automatic test equipment, DAC-per-pin pro- APPLICATIONS grammers, data acquisition systems, and closed-loop servo-control. The DAC7734 is available in a 48-lead l PROCESS CONTROL SSOP package and offers guaranteed specifications l ATE PIN ELECTRONICS over the –40°C to +85°C temperature range. l CLOSED-LOOP SERVO-CONTROL l MOTOR CONTROL l DATA ACQUISITION SYSTEMS l DAC-PER-PIN PROGRAMMERS V L V H REF REF AB Sense AB Sense V V V V L AB V H AB REF REF DD SS CC DAC7734 SDI Input DAC DAC A Shift Register A Register A V A OUT Register SDO V A Sense OUT Input DAC DAC B Register B Register B V B OUT V B Sense OUT Input DAC CS DAC C Register C Register C V C OUT CLOCK RST Control V C Sense OUT Logic RESTSEL Input DAC DAC D Register D Register D LDAC V D OUT LOAD V D Sense OUT V L V L CD V H CD V H AGND DGND REF REF REF REF CD Sense CD Sense International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 Twx: 910-952-1111 • Internet: http://www.burr-brown.com/ • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132 ® © 1999 Burr-Brown Corporation PDS-1570A Printed in U.S.A. December, 1999 1 DAC7734 SBAS138 SPECIFICATIONS (Dual Supply) At T = T to T , V = +15V, V = +5V, V = –15V, V H = +10V, and V L = –10V, unless otherwise noted. A MIN MAX CC DD SS REF REF DAC7734E DAC7734EB DAC7734EC PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS ACCURACY Linearity Error (INL) T = 25°C ±3[±2 LSB to T ±4[±3 LSB T MIN MAX Linearity Match ±4[±2 LSB Differential Linearity Error (DNL) T = 25°C ±3 ±2 ±1 LSB T to T ±3 ±2 ±1 LSB MIN MAX to T 14 15 16 Bits Monotonicity, T MIN MAX Bipolar Zero Error T = 25°C ±0.01 ±0.025 [[ % of FSR Bipolar Zero Error, T to T ±0.05 [[ % of FSR MIN MAX Full-Scale Error T = 25°C ±0.025 [[ % of FSR to T ±0.05 [[ % of FSR Full-Scale Error, T MIN MAX Bipolar Zero Matching Channel-to-Channel ±0.024 [[ % of FSR Matching Full-Scale Matching Channel-to-Channel ±0.024 [[ % of FSR Matching Power Supply Rejection Ratio (PSRR) At Full Scale 25 [[ ppm/V ANALOG OUTPUT Voltage Output VLV H[[[[V REF REF Output Current ±5 [[ mA Maximum Load Capacitance 500 [[ pF Short-Circuit Current ±20 [[ mA Short-Circuit Duration To V , V or GND Indefinite [[ SS CC REFERENCE INPUT Ref High Input Voltage Range V L + 1.25 +10[[[[V REF V H – 1.25[[[[V Ref Low Input Voltage Range –10 REF Ref High Input Current –0.3 2.6 [[ mA Ref Low Input Current –3.2 –0.3 [[ mA DYNAMIC PERFORMANCE Settling Time To ±0.003%, 20V 9 11 [[[[μs Output Step Channel-to-Channel Crosstalk See Figure 5 0.5 [[ LSB Digital Feedthrough 2 [[ nV-s Output Noise Voltage f = 10kHz 60 [[ nV/√Hz DIGITAL INPUT V 0.7 • V V[[ V IH DD DD V 0 0.3 • V[V IL DD I ±10[μA IH I ±10[μA IL DIGITAL OUTPUT V I = –0.8mA 3.6 4.5 [[ [[ V OH OH I = 1.6mA 0.3 0.4 [[[[V V OL OL POWER SUPPLY V +4.75 +5.0 +5.25 [[[ [[[V DD V +14.25 +15.0 +15.75 [[[ [[[V CC V –14.25 –15.0 –15.75 [[[ [[[V SS I 50 [[ μA DD I 6 [[ mA CC I –5 [[ mA SS Power 170 200 [[ mW TEMPERATURE RANGE Specified Performance –40 +85[[[[°C [ Specifications same as grade to the left. The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems. ® 2 DAC7734 SPECIFICATIONS (Single Supply) At T = T to T , V = +15V, V = +5V, V = GND, V H = +10V, and V L = +50mV, unless otherwise noted. A MIN MAX CC DD SS REF REF DAC7734E DAC7734EB DAC7734EC PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS ACCURACY (1) Linearity Error (INL) T = 25°C ±3[±2 LSB to T ±4[±3 LSB T MIN MAX Linearity Match ±4[±2 LSB Differential Linearity Error (DNL) T = 25°C ±3 ±2 ±1 LSB T to T ±3 ±2 ±1 LSB MIN MAX to T 14 15 16 Bits Monotonicity, T MIN MAX Unipolar Zero T = 25°C ±0.01 ±0.025 [[ % of FSR Unipolar Zero Error, T to T ±0.05 [[ % of FSR MIN MAX Full-Scale Error T = 25°C ±0.025 [[ % of FSR T to T ±0.05 [[ % of FSR Full-Scale Error, MIN MAX Unipolar Zero Matching Channel-to-Channel ±0.024 [[ % of FSR Matching Full-Scale Matching Channel-to-Channel ±0.024 [[ % of FSR Matching Power Supply Rejection Ratio (PSRR) At Full Scale 25 [[ ppm/V ANALOG OUTPUT Voltage Output V L = 0V, V = 0V 0 V H[[[[V REF SS REF R = 10kΩ Output Current ±5 [[ mA Maximum Load Capacitance 500 [[ pF Short-Circuit Current ±20 [[ mA Short-Circuit Duration To V or GND Indefinite [[ CC REFERENCE INPUT V L + 1.25 +10[[[[V Ref High Input Voltage Range REF Ref Low Input Voltage Range 0 V H – 1.25[[[[V REF Ref High Input Current –0.3 1.0 [[ mA Ref Low Input Current –1.5 –0.3 [[ mA DYNAMIC PERFORMANCE Settling Time To ±0.003%, 10V 8 10 [[[[μs Output Step Channel-to-Channel Crosstalk See Figure 6 0.5 [[ LSB Digital Feedthrough 2 [[ nV-s Output Noise Voltage f = 10kHz 60 [[ nV/√Hz DIGITAL INPUT V 0.7 • V V[[ V IH DD DD V 0 0.3 • V[V IL DD I ±10[μA IH I ±10[μA IL DIGITAL OUTPUT I = –0.8mA 3.6 4.5 [[[[V V OH OH V I = 1.6mA 0.3 0.4 [[[[V OL OL POWER SUPPLY V +4.75 +5.0 +5.25 [[[[[[V DD V +14.25 +15.0 +15.75 [[[[[[V CC V 0 [[ V SS I 50 [[ μA DD I 3.5 [[ mA CC Power 50 70 [[ mW TEMPERATURE RANGE Specified Performance –40 +85[[[[°C [ Specifications same as grade to the left. = 0V, the specification applies at code 0021 and above, due to possible negative zero scale error. NOTE: (1) If V SS H ® 3 DAC7734 (1) ABSOLUTE MAXIMUM RATINGS ELECTROSTATIC V to V ........................................................................... –0.3V to +32V CC SS DISCHARGE SENSITIVITY V to AGND ...................................................................... –0.3V to +16V CC to AGND ...................................................................... +0.3V to –16V V SS This integrated circuit can be damaged by ESD. Burr-Brown AGND to DGND ................................................................. –0.3V to +0.3V H to AGND ..................................................................... –9V to +11V recommends that all integrated circuits be handled with V REF V L to AGND ...................................................................... –11V to +9V REF appropriate precautions. Failure to observe proper handling to GND ........................................................................... –0.3V to +6V V DD and installation procedures can cause damage. V H to V L ........................................................................ –1V to 22V REF REF + 0.3V Digital Input Voltage to GND ................................... –0.3V to V DD ESD damage can range from subtle performance degradation Digital Output Voltage to GND ................................. –0.3V to V + 0.3V DD to complete device failure. Precision integrated circuits may Maximum Junction Temperature ................................................... +150°C Operating Temperature Range ........................................–40°C to +85°C be more susceptible to damage because very small parametric Storage Temperature Range .........................................–65°C to +150°C changes could cause the device not to meet its published Lead Temperature (soldering, 10s)............................................... +300°C specifications. NOTE: (1) Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. Exposure to absolute maximum conditions for extended periods may affect device reliability. PACKAGE/ORDERING INFORMATION LINEARITY DIFFERENTIAL PACKAGE SPECIFICATION ERROR NONLINEARITY DRAWING TEMPERATURE ORDERING TRANSPORT (1) PRODUCT (LSB) (LSB) PACKAGE NUMBER RANGE NUMBER MEDIA DAC7734E ±4 ±3 SSOP-48 333 –40°C to +85°C DAC7734E Rails "" " " " " DAC7734E/1K Tape and Reel DAC7734EB ±4 ±2 SSOP-48 333 –40°C to +85°C DAC7734EB Rails "" " " " " DAC7734EB/1K Tape and Reel DAC7734EC ±3 ±1 SSOP-48 333 –40°C to +85°C DAC7734EC Rails "" " " " " DAC7734EC/1K Tape and Reel NOTE: (1) Models with a slash (/) are available only in Tape and Reel in the quantities indicated (e.g., /1K indicates 1000 devices per reel). Ordering 1000 pieces of “DAC7734E/1K” will get a single 1000-piece Tape and Reel. ESD PROTECTION CIRCUITS V CC V CC V Sense RefH OUT RefH Sense V AGND OUT RefL Sense RefL V SS V SS 1 of 2 1 of 4 V DD V DD Typ of Each Logic Input Pin DGND DGND SDO ® 4 DAC7734 PIN CONFIGURATION PIN DESCRIPTIONS Top View SSOP PIN NAME DESCRIPTION 1 NC No Connection 2 NC No Connection NC 1 48 V A Sense OUT 3 SDI Serial Data Input NC 2 47 V A OUT 4 DGND Digital Ground 5 CLK Data Clock Input SDI 3 46 AGND 6 DGND Digital Ground DGND 4 45 V SS 7 LDAC DAC Register Load Control, Rising Edge Triggered CLK 5 44 V L AB Sense REF 8 DGND Digital Ground DGND 6 43 V L AB REF 9 LOAD DAC Input Register Load Control, Active Low 10 DGND Digital Ground LDAC 7 42 V H AB REF 11 CS Chip Select, Active Low DGND 8 41 V H AB Sense REF 12 DGND Digital Ground 13 SDO Serial Data Output LOAD 9 40 V B Sense OUT 14 DGND Digital Ground DGND 10 39 V B OUT 15 RSTSEL Reset Select. Determines the action of RST. If HIGH, a RST common will set the DAC registers CS 11 38 V C Sense OUT to mid-scale (8000H). If LOW, a RST command DGND 12 37 V C will set the DAC registers to zero (0000H). OUT DAC7734 16 DGND Digital Ground SDO 13 36 V H CD Sense REF 17 RST Reset, Rising Edge Triggered. Depending on the state of RSTSEL, the DAC registers are set to DGND 14 35 V H CD REF either mid-scale or zero. RSTSEL 15 34 V L CD REF 18 DGND Digital Ground 19 NC No Connection DGND 16 33 V L CD Sense REF 20 NC No Connection RST 17 32 V D Sense OUT 21 DGND Digital Ground 22 DGND Digital Ground DGND 18 31 V D OUT 23 V Digital +5V Power Supply DD NC 19 30 V SS 24 V Digital +5V Power Supply DD NC 20 29 V 25 V Analog +15V Power Supply SS CC 26 V Analog +15V Power Supply CC DGND 21 28 AGND 27 AGND Analog Ground DGND 22 27 AGND 28 AGND Analog Ground 29 V Analog –15V Power Supply or 0V Single Supply SS V 23 26 V DD CC 30 V Analog –15V Power Supply or 0V Single Supply SS V 24 25 V DD CC 31 V D DAC D Output Voltage OUT 32 V D Sense DAC D’s Output Amplifier Inverting Input. Used OUT to close feedback loop at load. 33 V L CD Sense DAC C and D Reference Low Sense Input REF 34 V L CD DAC C and D Reference Low Input REF 35 V H CD DAC C and D Reference High Input REF 36 V H CD Sense DAC C and D Reference High Sense Input REF 37 V C DAC C Output Voltage OUT 38 V C Sense DAC C’s Output Amplifier Inverting Input. Used OUT to close the feedback loop at the load. 39 V B DAC B Output Voltage OUT 40 V B Sense DAC B’s Output Amplifier Inverting Input. Used OUT to close the feedback loop at the load. 41 V H AB Sense DAC A and B Reference High Sense Input REF 42 V H AB DAC A and B Reference High Input REF 43 V L AB DAC A and B Reference Low Input OUT 44 V L AB Sense DAC A and B Reference Low Sense Input REF 45 V Analog –15V Power Supply or 0V Single Supply SS 46 AGND Analog Ground 47 V A DAC A Output Voltage OUT 48 V A Sense DAC A’s Output Amplifier Inverting Input. Used OUT to close the feedback loop at the load. ® 5 DAC7734 TYPICAL PERFORMANCE CURVES: V = 0V SS At T = +25°C, V = +5V, V = +15V, V = 0, V H = +10V, and V L = 0V, representative unit, unless otherwise specified. A DD CC SS REF REF +25°C LINEARITY ERROR AND LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs CODE DIFFERENTIAL LINEARITY ERROR vs CODE (DAC A, +25°C) (DAC B, +25°C) 2.0 2.0 1.5 1.5 1.0 1.0 0.5 0.5 0 0 –0.5 –0.5 –1.0 –1.0 –1.5 –1.5 –2.0 –2.0 2.0 2.0 1.5 1.5 1.0 1.0 0.5 0.5 0 0 –0.5 –0.5 –1.0 –1.0 –1.5 –1.5 –2.0 –2.0 0000 2000 4000 6000 8000 A000 C000 E000 FFFF 0000 2000 4000 6000 8000 A000 C000 E000 FFFF H H H H H H H H H H H H H H H H H H Digital Input Code Digital Input Code LINEARITY ERROR AND LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs CODE DIFFERENTIAL LINEARITY ERROR vs CODE (DAC D, +25°C) (DAC C, +25°C) 2.0 2.0 1.5 1.5 1.0 1.0 0.5 0.5 0 0 –0.5 –0.5 –1.0 –1.0 –1.5 –1.5 –2.0 –2.0 2.0 2.0 1.5 1.5 1.0 1.0 0.5 0.5 0 0 –0.5 –0.5 –1.0 –1.0 –1.5 –1.5 –2.0 –2.0 0000 2000 4000 6000 8000 A000 C000 E000 FFFF 0000 2000 4000 6000 8000 A000 C000 E000 FFFF H H H H H H H H H H H H H H H H H H Digital Input Code Digital Input Code +85°C LINEARITY ERROR AND LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs CODE DIFFERENTIAL LINEARITY ERROR vs CODE (DAC B, +85°C) (DAC A, +85°C) 2.0 2.0 1.5 1.5 1.0 1.0 0.5 0.5 0 0 –0.5 –0.5 –1.0 –1.0 –1.5 –1.5 –2.0 –2.0 2.0 2.0 1.5 1.5 1.0 1.0 0.5 0.5 0 0 –0.5 –0.5 –1.0 –1.0 –1.5 –1.5 –2.0 –2.0 0000 2000 4000 6000 8000 A000 C000 E000 FFFF 0000 2000 4000 6000 8000 A000 C000 E000 FFFF H H H H H H H H H H H H H H H H H H Digital Input Code Digital Input Code ® 6 DAC7734 DLE (LSB) LE (LSB) DLE (LSB) LE (LSB) DLE (LSB) LE (LSB) DLE (LSB) LE (LSB) DLE (LSB) LE (LSB) DLE (LSB) LE (LSB) TYPICAL PERFORMANCE CURVES: V = 0V (Cont.) SS At T = +25°C, V = +5V, V = +15V, V = 0, V H = +10V, and V L = 0V, representative unit, unless otherwise specified. A DD CC SS REF REF +85°C (cont.) LINEARITY ERROR AND LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs CODE DIFFERENTIAL LINEARITY ERROR vs CODE (DAC C, +85°C) (DAC D, +85°C) 2.0 2.0 1.5 1.5 1.0 1.0 0.5 0.5 0 0 –0.5 –0.5 –1.0 –1.0 –1.5 –1.5 –2.0 –2.0 2.0 2.0 1.5 1.5 1.0 1.0 0.5 0.5 0 0 –0.5 –0.5 –1.0 –1.0 –1.5 –1.5 –2.0 –2.0 0000 2000 4000 6000 8000 A000 C000 E000 FFFF 0000 2000 4000 6000 8000 A000 C000 E000 FFFF H H H H H H H H H H H H H H H H H H Digital Input Code Digital Input Code LINEARITY ERROR AND LINEARITY ERROR AND –40°C DIFFERENTIAL LINEARITY ERROR vs CODE DIFFERENTIAL LINEARITY ERROR vs CODE (DAC A, –40°C) (DAC B, –40°C) 2.0 2.0 1.5 1.5 1.0 1.0 0.5 0.5 0 0 –0.5 –0.5 –1.0 –1.0 –1.5 –1.5 –2.0 –2.0 2.0 2.0 1.5 1.5 1.0 1.0 0.5 0.5 0 0 –0.5 –0.5 –1.0 –1.0 –1.5 –1.5 –2.0 –2.0 0000 2000 4000 6000 8000 A000 C000 E000 FFFF 0000 2000 4000 6000 8000 A000 C000 E000 FFFF H H H H H H H H H H H H H H H H H H Digital Input Code Digital Input Code LINEARITY ERROR AND LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs CODE DIFFERENTIAL LINEARITY ERROR vs CODE (DAC C, –40°C) (DAC D, –40°C) 2.0 2.0 1.5 1.5 1.0 1.0 0.5 0.5 0 0 –0.5 –0.5 –1.0 –1.0 –1.5 –1.5 –2.0 –2.0 2.0 2.0 1.5 1.5 1.0 1.0 0.5 0.5 0 0 –0.5 –0.5 –1.0 –1.0 –1.5 –1.5 –2.0 –2.0 0000 2000 4000 6000 8000 A000 C000 E000 FFFF 0000 2000 4000 6000 8000 A000 C000 E000 FFFF H H H H H H H H H H H H H H H H H H Digital Input Code Digital Input Code ® 7 DAC7734 DLE (LSB) LE (LSB) DLE (LSB) LE (LSB) DLE (LSB) LE (LSB) DLE (LSB) LE (LSB) DLE (LSB) LE (LSB) DLE (LSB) LE (LSB) TYPICAL PERFORMANCE CURVES: V = 0V (Cont.) SS At T = +25°C, V = +5V, V = +15V, V = 0, V H = +10V, and V L = 0V, representative unit, unless otherwise specified. A DD CC SS REF REF POSITIVE FULL-SCALE ERROR ZERO-SCALE ERROR vs TEMPERATURE vs TEMPERATURE 2 2 Code (FFFF ) Code (0040 Code (0000 ) ) H H H 1.5 1.5 DAC B 1 1 DAC D DAC A 0.5 0.5 0 0 DAC C DAC B –0.5 –0.5 DAC D DAC C DAC A –1 –1 –1.5 –1.5 –2 –2 –40 –30 –20 –10 0 10 20 30 40 50 60 70 80 90 –40 –30 –20 –10 0 10 20 30 40 50 60 70 80 90 Temperature (°C) Temperature (°C) REFERENCE CURRENT vs CODE REFERENCE CURRENT vs CODE All DACs Sent to Indicated Code All DACs Sent to Indicated Code (DAC A and B) (DAC C and D) V V REFH REFH 1.0 1.0 0.8 0.8 0.6 0.6 0.4 0.4 0.2 0.2 0 0 –0.2 –0.2 –0.4 –0.4 V V REFL REFL 0 0 –0.2 –0.2 –0.4 –0.4 –0.6 –0.6 –0.8 –0.8 –1.0 –1.0 –1.2 –1.2 –1.4 –1.4 0000 2000 4000 6000 8000 A000 C000 E000 FFFF 0000 2000 4000 6000 8000 A000 C000 E000 FFFF H H H H H H H H H H H H H H H H H H Digital Input Code Digital Input Code POSITIVE SUPPLY CURRENT POWER SUPPLY CURRENT vs TEMPERATURE vs DIGITAL INPUT CODE 4.0 4.0 Data = FFFF (all DACs) I No Load I H CC CC 3.5 3.5 No Load 3.0 3.0 2.5 2.5 2.0 2.0 1.5 1.5 1.0 1.0 0.5 0.5 I I DD DD 0 0 –0.5 –0.5 –40 –30 –20 –10 0 10 20 30 40 50 60 70 80 90 0 2000 4000 6000 8000 A000 C000 E000 FFFF H H H H H H H H Temperature (°C) Digital Input Code ® 8 DAC7734 Quiescent Current (mA) V (Current (mA) V (Current (mA) Negative Full-Scale Error (mV) REF REF V (Current (mA) V (Current (mA) Positive Full-Scale Error (mV) I (mA) REF REF CC TYPICAL PERFORMANCE CURVES: V = 0V (Cont.) SS At T = +25°C, V = +5V, V = +15V, V = 0, V H = +10V, and V L = 0V, representative unit, unless otherwise specified. A DD CC SS REF REF OUTPUT VOLTAGE vs SETTLING TIME OUTPUT VOLTAGE vs SETTLING TIME (0V to +10V) (+10V to 0V) Large-Signal Settling Time: 5V/div Small-Signal Settling Time: Small-Signal Settling Time: 3LSB/div 3LSB/div Large-Signal Settling Time: 5V/div +5V +5V LDAC LDAC 0 0 Time (2μs/div) Time (2μs/div) OUTPUT VOLTAGE OUTPUT VOLTAGE MIDSCALE GLITCH PERFORMANCE MIDSCALE GLITCH PERFORMANCE 7FFF to 8000 8000 to 7FFF H H H H +5V +5V LDAC LDAC 0 0 Time (1μs/div) Time (1μs/div) BROADBAND NOISE OUTPUT NOISE VOLTAGE vs FREQUENCY 120 100 80 60 40 BW = 10kHz 20 Code = 8000 H 0 100 1k 10k 100k 1M Time (100μs/div) Frequency (Hz) ® 9 DAC7734 Noise Voltage (20μV/div) Output Voltage (200mV/div) Output Voltage Noise (nV/√Hz) Output Voltage (200mV/div) Output Voltage TYPICAL PERFORMANCE CURVES: V = 0V (Cont.) SS At T = +25°C, V = +5V, V = +15V, V = 0, V H = +10V, and V L = 0V, representative unit, unless otherwise specified. A DD CC SS REF REF POWER SUPPLY REJECTION RATIO vs FREQUENCY OUTPUT VOLTAGE vs R LOAD 0 16 –10 14 –20 12 Source –30 10 +15V –40 8 –50 6 –60 +5V 4 –70 2 –80 Sink –90 0 100 1k 10k 100k 1M 0.01 0.1 1 10 100 Frequency (Hz) R (kΩ) LOAD CLOCK FEEDTHROUGH SINGLE-SUPPLY CURRENT LIMIT vs INPUT CODE 30 25 20 Short to Ground 15 10 5 0 –5 –10 –15 –20 Short to V +5V CC –25 CLK 0V –30 0000 2000 4000 6000 8000 A000 C000 E000 FFFF Time (50ns/div) H H H H H H H H H Input Code ® 10 DAC7734 PSRR (dB) I (mA) OUT V (V) OUT Output Voltage (5mV/div) TYPICAL PERFORMANCE CURVES: V = –15V SS At T = +25°C, V = +5V, V = +15V, V = –15V, V H = +10V, and V L = –10V, representative unit, unless otherwise specified. A DD CC SS REF REF +25°C LINEARITY ERROR AND LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs CODE DIFFERENTIAL LINEARITY ERROR vs CODE (DAC A, +25°C) (DAC B, +25°C) 2.0 2.0 1.5 1.5 1.0 1.0 0.5 0.5 0 0 –0.5 –0.5 –1.0 –1.0 –1.5 –1.5 –2.0 –2.0 2.0 2.0 1.5 1.5 1.0 1.0 0.5 0.5 0 0 –0.5 –0.5 –1.0 –1.0 –1.5 –1.5 –2.0 –2.0 0000 2000 4000 6000 8000 A000 C000 E000 FFFF 0000 2000 4000 6000 8000 A000 C000 E000 FFFF H H H H H H H H H H H H H H H H H H Digital Input Code Digital Input Code LINEARITY ERROR AND LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs CODE DIFFERENTIAL LINEARITY ERROR vs CODE (DAC C, +25°C) (DAC D, +25°C) 2.0 2.0 1.5 1.5 1.0 1.0 0.5 0.5 0 0 –0.5 –0.5 –1.0 –1.0 –1.5 –1.5 –2.0 –2.0 2.0 2.0 1.5 1.5 1.0 1.0 0.5 0.5 0 0 –0.5 –0.5 –1.0 –1.0 –1.5 –1.5 –2.0 –2.0 0000 2000 4000 6000 8000 A000 C000 E000 FFFF 0000 2000 4000 6000 8000 A000 C000 E000 FFFF H H H H H H H H H H H H H H H H H H Digital Input Code Digital Input Code +85°C LINEARITY ERROR AND LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs CODE DIFFERENTIAL LINEARITY ERROR vs CODE (DAC B, +85°C) (DAC A, +85°C) 2.0 2.0 1.5 1.5 1.0 1.0 0.5 0.5 0 0 –0.5 –0.5 –1.0 –1.0 –1.5 –1.5 –2.0 –2.0 2.0 2.0 1.5 1.5 1.0 1.0 0.5 0.5 0 0 –0.5 –0.5 –1.0 –1.0 –1.5 –1.5 –2.0 –2.0 0000 2000 4000 6000 8000 A000 C000 E000 FFFF 0000 2000 4000 6000 8000 A000 C000 E000 FFFF H H H H H H H H H H H H H H H H H H Digital Input Code Digital Input Code ® 11 DAC7734 DLE (LSB) LE (LSB) DLE (LSB) LE (LSB) DLE (LSB) LE (LSB) DLE (LSB) LE (LSB) DLE (LSB) LE (LSB) DLE (LSB) LE (LSB) TYPICAL PERFORMANCE CURVES: V = –15V (Cont.) SS At T = +25°C, V = +5V, V = +15V, V = –15V, V H = +10V, and V L = –10V, representative unit, unless otherwise specified. A DD CC SS REF REF +85°C (cont.) LINEARITY ERROR AND LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs CODE DIFFERENTIAL LINEARITY ERROR vs CODE (DAC C, +85°C) (DAC D, +85°C) 2.0 2.0 1.5 1.5 1.0 1.0 0.5 0.5 0 0 –0.5 –0.5 –1.0 –1.0 –1.5 –1.5 –2.0 –2.0 2.0 2.0 1.5 1.5 1.0 1.0 0.5 0.5 0 0 –0.5 –0.5 –1.0 –1.0 –1.5 –1.5 –2.0 –2.0 0000 2000 4000 6000 8000 A000 C000 E000 FFFF 0000 2000 4000 6000 8000 A000 C000 E000 FFFF H H H H H H H H H H H H H H H H H H Digital Input Code Digital Input Code LINEARITY ERROR AND LINEARITY ERROR AND –40°C DIFFERENTIAL LINEARITY ERROR vs CODE DIFFERENTIAL LINEARITY ERROR vs CODE (DAC A, –40°C) (DAC B, –40°C) 2.0 2.0 1.5 1.5 1.0 1.0 0.5 0.5 0 0 –0.5 –0.5 –1.0 –1.0 –1.5 –1.5 –2.0 –2.0 2.0 2.0 1.5 1.5 1.0 1.0 0.5 0.5 0 0 –0.5 –0.5 –1.0 –1.0 –1.5 –1.5 –2.0 –2.0 0000 2000 4000 6000 8000 A000 C000 E000 FFFF 0000 2000 4000 6000 8000 A000 C000 E000 FFFF H H H H H H H H H H H H H H H H H H Digital Input Code Digital Input Code LINEARITY ERROR AND LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs CODE DIFFERENTIAL LINEARITY ERROR vs CODE (DAC C, –40°C) (DAC D, –40°C) 2.0 2.0 1.5 1.5 1.0 1.0 0.5 0.5 0 0 –0.5 –0.5 –1.0 –1.0 –1.5 –1.5 –2.0 –2.0 2.0 2.0 1.5 1.5 1.0 1.0 0.5 0.5 0 0 –0.5 –0.5 –1.0 –1.0 –1.5 –1.5 –2.0 –2.0 0000 2000 4000 6000 8000 A000 C000 E000 FFFF H H H H H H H H H 0000 2000 4000 6000 8000 A000 C000 E000 FFFF H H H H H H H H H Digital Input Code Digital Input Code ® 12 DAC7734 DLE (LSB) LE (LSB) DLE (LSB) LE (LSB) DLE (LSB) LE (LSB) DLE (LSB) LE (LSB) DLE (LSB) LE (LSB) DLE (LSB) LE (LSB) TYPICAL PERFORMANCE CURVES: V = –15V (Cont.) SS At T = +25°C, V = +5V, V = +15V, V = –15V, V H = +10V, and V L = –10V, representative unit, unless otherwise specified. A DD CC SS REF REF REFERENCE CURRENT vs CODE REFERENCE CURRENT vs CODE All DACs Sent to Indicated Code All DACs Sent to Indicated Code (DAC A and B) (DAC C and D) V V REFH REFH 2.5 2.5 2.0 2.0 1.5 1.5 1.0 1.0 0.5 0.5 0 0 –0.5 –0.5 V V REFL REFL 0.0 0.0 –0.5 –0.5 –1.0 –1.0 –1.5 –1.5 –2.0 –2.0 –2.5 –2.5 –3.0 –3.0 0000 2000 4000 6000 8000 A000 C000 E000 FFFF 0000 2000 4000 6000 8000 A000 C000 E000 FFFF H H H H H H H H H H H H H H H H H H Digital Input Code Digital Input Code POSITIVE FULL-SCALE ERROR vs TEMPERATURE BIPOLAR ZERO SCALE ERROR vs TEMPERATURE (Code FFFF ) (Code 8000 ) H H 2 2 1.5 1.5 1.0 1 DAC A DAC A 0.5 0.5 0 0 –0.5 –0.5 DAC D DAC D DAC C DAC B DAC B DAC C –1 –1.0 –1.5 –1.5 –2 –2.0 –40 –30 –20 –10 0 10 20 30 40 50 60 70 80 90 –40–30–20–10 0 102030405060708090 Temperature (°C) Temperature (°C) NEGATIVE FULL-SCALE ERROR vs TEMPERATURE (Code 0000 ) POWER SUPPLY CURRENT vs TEMPERTURE H 2 7 6 1.5 5 4 I CC 1.0 3 DAC A 2 0.5 1 0 0 –1 –0.5 I –2 DD DAC B DAC C I DAC D SS –3 –1.0 –4 –5 Data = FFFF (all DACs) –1.5 H –6 No Load –2.0 –7 –40 –30 –20 –10 0 10 20 30 40 50 60 70 80 90 –40 –30 –20 –10 0 10 20 30 40 50 60 70 80 90 Temperature (°C) Temperature (°C) ® 13 DAC7734 Negative Full-Scale Error (mV) Bipolar Zero Scale Error (mV) V (Current (mA) V (Current (mA) REF REF Positive Full-Scale Error (mV) V (Current (mA) V (Current (mA) REF REF Quiescent Current (mA) TYPICAL PERFORMANCE CURVES: V = –15V (Cont.) SS At T = +25°C, V = +5V, V = +15V, V = –15V, V H = +10V, and V L = –10V, representative unit, unless otherwise specified. A DD CC SS REF REF SUPPLY CURRENT vs CODE OUTPUT VOLTAGE vs R LOAD 7 15 I CC 6 5 10 Source 4 3 5 2 1 I DD 0 0 –1 –2 –5 –3 I SS Sink –4 –10 –5 –6 –7 –15 0000 2000 4000 6000 8000 A000 C000 E000 FFFF 0.01 0.1 1 10 100 H H H H H H H H H Digital Input Code R (kΩ) LOAD OUTPUT VOLTAGE vs SETTLING TIME OUTPUT VOLTAGE vs SETTLING TIME (–10V to +10V) (+10V to –10V) Large-Signal Settling Time: 5V/div Small-Signal Settling Time: 3LSB/div Small-Signal Settling Time: 3LSB/div Large-Signal Settling Time: 5V/div +5V +5V LDAC LDAC 0 0 Time (2μs/div) Time (2μs/div) DUAL-SUPPLY CURRENT LIMIT vs INPUT CODE (Short-to-Ground) POWER SUPPLY REJECTION RATIO vs FREQUENCY 20 0 –10 15 –20 10 –30 5 –40 0 –50 –15V –60 +15V –5 –70 –10 –80 –15 –90 +5V –20 –100 0000 2000 4000 6000 8000 A000 C000 E000 FFFF 100 1k 10k 100k 1M H H H H H H H H H Digital Input Code Frequency (Hz) ® 14 DAC7734 V (V) I (mA) OUT OUT Output Voltage PSRR (dB) (mA) Output Voltage TYPICAL PERFORMANCE CURVES: V = –15V (Cont.) SS At T = +25°C, V = +5V, V = +15V, V = –15V, V H = +10V, and V L = –10V, representative unit, unless otherwise specified. A DD CC SS REF REF OUTPUT VOLTAGE OUTPUT VOLTAGE MID-SCALE GLITCH PERFORMANCE MID-SCALE GLITCH PERFORMANCE 7FFF to 8000 8000 to 7FFF H H H H +5V +5V LDAC LDAC 0 0 Time (1μs/div) Time (1μs/div) ® 15 DAC7734 Output Voltage (200mV/div) Output Voltage (200mV/div) The digital input is a 24-bit serial word that contains a 2-bit THEORY OF OPERATION address code for selecting one of four DACs, a quick load The DAC7734 is a quad voltage output, 16-bit Digital-to- bit, five unused bits and the 16-bit DAC code (MSB first). Analog Converter (DAC). The architecture is an R-2R The converters can be powered from either a single +15V ladder configuration with the three MSB’s segmented, fol- supply or a dual ±15V supply and a +5V logic supply. The lowed by an operational amplifier that serves as a buffer. device offers a reset function which immediately sets all Each DAC has its own R-2R ladder network, segmented DAC output voltages and DAC registers to mid-scale code MSBs, and output op amp, as shown in Figure 1. The 8000 or to zero-scale, code 0000 . See Figures 2 and 3 for H H minimum voltage output (zero-scale) and maximum voltage the basic operation of the DAC7734. output (full-scale) are set by the external voltage references V L and V H. REF REF R F V Sense OUT V R OUT 2R 2R 2R 2R 2R 2R 2R 2R 2R V H REF V H Sense REF V L REF V L Sense REF FIGURE 1. DAC7734 Architecture. 1 48 NC V A Sense OUT 0V to +10V 2 NC V A 47 OUT 3 SDI AGND 46 Serial Data In 4 DGND V 45 SS 5 CLK V L AB Sense 44 Clock REF 6 DGND V L AB 43 REF +10.000V 7 LDAC V H AB 42 Load DAC Registers REF 8 DGND V H AB Sense 41 REF 9 LOAD V B Sense 40 Load OUT 0V to +10V 10 DGND V B 39 OUT Chips Select 11 CS V C Sense 38 OUT 0V to +10V 12 DGND DAC7734 V C 37 OUT Serial Data Out 13 SDO V H CD Sense 36 REF +10.000V 14 DGND V H CD 35 REF 15 RSTSEL V L CD 34 REF 16 DGND V L CD Sense 33 REF Reset DAC Registers 17 RST V D Sense 32 OUT 0V to +10V 18 DGND V D 31 OUT 19 NC V 30 SS 20 29 NC V SS 21 DGND AGND 28 22 27 DGND AGND +5V 23 V V 26 DD CC + 1μF 0.1μF 0.1μF 1μF 24 25 + V V DD CC +15V NC = No Connection FIGURE 2. Basic Single-Supply Operation of the DAC7734. ® 16 DAC7734 1 NC V A Sense 48 OUT 2 NC V A 47 –10V to +10V OUT Serial Data In 3 SDI AGND 46 –15V 4 DGND V 45 SS 5 CLK V L AB Sense 44 Clock REF –10.000V 6 DGND V L AB 43 REF +10.000V 7 42 Load DAC Registers LDAC V H AB REF 8 DGND V H AB Sense 41 REF Load 9 LOAD V B Sense 40 OUT –10V to +10V 10 DGND V B 39 OUT Chips Select 11 CS V C Sense 38 OUT –10V to +10V 12 DGND DAC7734 V C 37 OUT Serial Data Out 13 SDO V H CD Sense 36 REF +10.000V 14 DGND V H CD 35 REF +5V 15 RSTSEL V L CD 34 REF –10.000V 16 DGND V L CD Sense 33 REF Reset DAC Registers 17 RST V D Sense 32 OUT 18 DGND V D 31 –10V to +10V OUT 19 V 30 –15V NC SS 20 29 NC V SS 0.1μF 1μF + 21 DGND AGND 28 22 DGND AGND 27 1μF 0.1μF 0.1μF 1μF + 23 V V 26 + DD CC +5V +15V 24 V V 25 DD CC NC = No Connection FIGURE 3. Basic Dual-Supply Operation of the DAC7734. ANALOG OUTPUTS The DAC7734 offers a force and sense output configuration for the high open-loop gain output amplifier. This feature When V = –15V (dual supply operation), the output SS allows the loop around the output amplifier to be closed at amplifier can swing to within 4V of the supply rails, guar- the load (as shown in Figure 4), thus ensuring an accurate anteed over the –40°C to +85°C temperature range. When output voltage. V = 0V (single-supply operation), and with R also SS LOAD connected to ground, the output can swing to ground. Care must also be taken when measuring the zero-scale error R W1 when V = 0V. Since the output voltage cannot swing SS below ground, the output voltage may not change for the 48 V A Sense OUT R W2 first few digital input codes (0000 , 0001 , 0002 , etc.) if H H H V A 47 V OUT OUT the output amplifier has a negative offset. At the negative AGND 46 DAC7734 limit of –5mV, the first specified output starts at code 0021 . H V 45 SS Due to the high accuracy of these D/A converters, system V L AB Sense 44 REF +V design problems such as grounding and contact resistance V L AB 43 REF become very important. A 16-bit converter with a 10V full- V H AB 42 +10V REF scale range has a 1LSB value of 152μV. With a load current V H AB Sense 41 of 1mA, series wiring and connector resistance of only REF R W1 150mΩ (R ) will cause a voltage drop of 150μV, as shown V B Sense 40 OUT W2 in Figure 4. To understand what this means in terms of a 39 V B OUT R W2 system layout, the resistivity of a typical 1 ounce copper- V OUT clad printed circuit board is 1/2 mΩ per square. For a 1mA load, a 20 milli-inch wide printed circuit conductor 6 inches FIGURE 4. Analog Output Closed-Loop Configuration long will result in a voltage drop of 150μV. (1/2 DAC7734). R represents wiring resis- W tances. ® 17 DAC7734 REFERENCE INPUTS The current into the V H input and out of V L depends REF REF on the DAC output voltages, and can vary from a few The reference inputs, V L and V H, can be any voltage REF REF microamps to approximately 2.0mA. The reference input between V + 4V and V – 4V, provided that V H is at SS CC REF appears as a varying load to the reference. The DAC7734 least 1.25V greater than V L. The minimum output of REF features a reference drive and sense connection such that the each DAC is equal to V L plus a small offset voltage REF internal errors caused by the changing reference current and (essentially, the offset of the output op amp). The maximum the circuit impedances can be minimized. Figures 5 through output is equal to V H plus a similar offset voltage. Note REF 9 show different reference configurations, and the effect on that V (the negative power supply) must either be SS the linearity and differential linearity. connected to ground or must be in the range of –14.25V to –15.75V. The voltage on V sets several bias points within The analog supplies have to come up first. If V and V SS CC SS the converter. If V is not in one of these two configura- don't come up together, then V should come up first. If the SS SS tions, the bias values may be in error and proper operation power supplies for the reference come up first, then the V CC of the device is not guaranteed. and V supplies will be “powered from the reference via the SS ESD protection diode”, see page 4. +V V A Sense 48 OUT OPA2234 V A 47 V OUT OUT AGND 46 DAC7734 2200pF –10V 100Ω V 45 –15V SS V L AB Sense 44 REF –V V L AB 43 REF 1000pF +V V H AB 42 REF 100Ω V H AB Sense 41 REF 1000pF +10V 2200pF V B Sense 40 OUT V B 39 OUT V OUT –V FIGURE 5. Dual Supply Configuration-Buffered References, used for Dual Supply Performance (1/2 DAC7734). +V V A Sense 48 OUT V V A 47 OUT OUT DAC7734 AGND 46 500Ω 2200pF 100Ω OPA350 V 45 SS +0.050V 50Ω V L AB Sense 44 REF +V 99.5kΩ V L AB 43 REF 1000pF V H AB 42 REF +10V 100Ω OPA227 V H AB Sense 41 REF 1000pF 2200pF V B Sense 40 OUT V B 39 OUT V OUT NOTE: V L has been chosen to be 50mV to allow for current sinking voltage drops across the 100Ω resistor and the output stage of the buffer op amp. REF FIGURE 6. Single-Supply Buffered Reference with a Reference Low of 50mV used for Single-Supply Performance Curves (1/2 DAC7734). ® 18 DAC7734 LINEARITY ERROR AND LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs CODE DIFFERENTIAL LINEARITY ERROR vs CODE (DAC A, 25°C) (DAC B, 25°C) 2.0 2.0 1.5 1.5 1.0 1.0 0.5 0.5 0 0 –0.5 –0.5 –1.0 –1.0 –1.5 –1.5 –2.0 –2.0 2.0 2.0 1.5 1.5 1.0 1.0 0.5 0.5 0 0 –0.5 –0.5 –1.0 –1.0 –1.5 –1.5 –2.0 –2.0 0000 2000 4000 6000 8000 A000 C000 E000 FFFF 0000 2000 4000 6000 8000 A000 C000 E000 FFFF H H H H H H H H H H H H H H H H H H Digital Input Code Digital Input Code LINEARITY ERROR AND LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs CODE DIFFERENTIAL LINEARITY ERROR vs CODE (DAC C, 25°C) (DAC D, 25°C) 2.0 2.0 1.5 1.5 1.0 1.0 0.5 0.5 0 0 –0.5 –0.5 –1.0 –1.0 –1.5 –1.5 –2.0 –2.0 2.0 2.0 1.5 1.5 1.0 1.0 0.5 0.5 0 0 –0.5 –0.5 –1.0 –1.0 –1.5 –1.5 –2.0 –2.0 0000 2000 4000 6000 8000 A000 C000 E000 FFFF 0000 2000 4000 6000 8000 A000 C000 E000 FFFF H H H H H H H H H H H H H H H H H H Digital Input Code Digital Input Code FIGURE 7. Integral Linearity and Differential Linearity Error Curves for Figure 8. +V V A Sense 48 OUT OPA2234 V V A 47 OUT OUT AGND 46 DAC7734 2200pF –5V 100Ω V 45 SS V L AB Sense 44 REF –V V L AB 43 REF 1000pF +V V H AB 42 REF 100Ω V H AB Sense 41 REF 1000pF +5V 2200pF V B Sense 40 OUT V B 39 OUT V OUT –V FIGURE 8. Dual-Supply Buffered Reference with V L = –5V and V H = +5V (1/2 DAC7734). REF REF ® 19 DAC7734 DLE (LSB) LE (LSB) DLE (LSB) LE (LSB) DLE (LSB) LE (LSB) DLE (LSB) LE (LSB) V A Sense 48 V OUT OUT V A 47 +V OUT 46 AGND V 45 SS DAC7734 V L AB Sense 44 1kΩ REF 100Ω 2200pF V L AB 43 OPA350 REF 1000pF 0.05V 50Ω V H AB 42 REF 100Ω V H AB Sense 41 99kΩ REF +V 1000pF 2200pF V B Sense 40 OUT OPA227 V B 39 OUT +5V V OUT NOTE: V L has been chosen to be 50mV to allow for current sinking voltage drops across the 100Ω resistor and the output stage of the buffer op amp. REF FIGURE 9. Single-Supply Buffered Reference with a Reference Low of 50mV and Reference High of +5V. LINEARITY ERROR AND LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs CODE DIFFERENTIAL LINEARITY ERROR vs CODE (DAC A, 25°C) (DAC B, 25°C) 2.0 2.0 1.5 1.5 1.0 1.0 0.5 0.5 0 0 –0.5 –0.5 –1.0 –1.0 –1.5 –1.5 –2.0 –2.0 2.0 2.0 1.5 1.5 1.0 1.0 0.5 0.5 0 0 –0.5 –0.5 –1.0 –1.0 –1.5 –1.5 –2.0 –2.0 0000 2000 4000 6000 8000 A000 C000 E000 FFFF 0000 2000 4000 6000 8000 A000 C000 E000 FFFF H H H H H H H H H H H H H H H H H H Digital Input Code Digital Input Code LINEARITY ERROR AND LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs CODE DIFFERENTIAL LINEARITY ERROR vs CODE (DAC C, 25°C) (DAC D, 25°C) 2.0 2.0 1.5 1.5 1.0 1.0 0.5 0.5 0 0 –0.5 –0.5 –1.0 –1.0 –1.5 –1.5 –2.0 –2.0 2.0 2.0 1.5 1.5 1.0 1.0 0.5 0.5 0 0 –0.5 –0.5 –1.0 –1.0 –1.5 –1.5 –2.0 –2.0 0000 2000 4000 6000 8000 A000 C000 E000 FFFF 0000 2000 4000 6000 8000 A000 C000 E000 FFFF H H H H H H H H H H H H H H H H H H Digital Input Code Digital Input Code FIGURE 10. Integral Linearity and Differential Linearity Error Curves for Figure 9. ® 20 DAC7734 DLE (LSB) LE (LSB) DLE (LSB) LE (LSB) DLE (LSB) LE (LSB) DLE (LSB) LE (LSB) DIGITAL INTERFACE device, all of the DAC outputs can be updated simulta- neously by the rising edge of LDAC. Additionally, it allows Table I shows the basic control logic for the DAC7734. The the DAC input registers to be written to at any point, then the interface consists of a Signal Data Clock (CLK) input, Serial DAC output voltages can be synchronously changed via a Data (SDI), DAC Input Register Load Control Signal trigger signal (LDAC). (LOAD), and DAC Register Load Control Signal (LDAC). In addition, a Chip Select (CS) input is available to enable Note that CS and CLK are combined with an OR gate, which serial communication when there are multiple serial devices. controls the serial-to-parallel shift register. These two inputs An asynchronous Reset (RST) input, by the rising edge, is are completely interchangeable. In addition, care must be provided to simplify start-up conditions, periodic resets, or taken with the state of CLK when CS rises at the end of a emergency resets to a known state, depending on the status serial transfer. If CLK is LOW when CS rises, the OR gate of the reset select (RSTSEL) signal. will provide a rising edge to the shift register, shifting the internal data one additional bit. The result will be incorrect The DAC code, quick load control, and address are provided data and possible selection of the wrong input register(s). If via a 24-bit serial interface (see Table I). The first two bits both CS and CLK are used, CS should rise only when CLK shifted into the shift register, B23 and B22, are the DAC is HIGH. If not, then either CS or CLK can be used to register address. These bits select the input register that will operate the shift register. See Table II for more information. be updated when LOAD goes LOW. The third bit, B21, is a “Quick Load” bit such that if HIGH, the code in the shift register is loaded into ALL DAC input registers when the (1) (1) CS CLK LOAD RST SERIAL SHIFT REGISTER LOAD signal goes LOW, independent of the state of the (2) (3) H X H H No Change address bits, B23 and B22. If the “Quick Load” bit is LOW, (4) L L H H No Change the contents of the shift register is loaded only to the DAC (5) L ↑ H H Advanced One Bit register that is addressed. Bits B20 through B16 are not used ↑ L H H Advanced One Bit and can assume any logical value. The last sixteen bits, B15 (6) (7) H XL H No Change through B0, make up the DAC code to be loaded into the (6) (8) H XH ↑ No Change selected input register. NOTES: (1) CS and CLK are interchangeable. (2) H = Logic HIGH. The internal DAC register is edge triggered and not level (3) X = Don’t Care. (4) L = Logic LOW (5) = Positive Logic Transition. triggered. When the LDAC signal is transitioned from LOW (6) A HIGH value is suggested in order to avoid a “false clock” from advancing to HIGH, the digital word currently in the DAC input the shift register and changing the shift register. (7) If data is clocked into the serial register while LOAD is LOW, the selected DAC register will change as register is latched. The first set of registers (the DAC input the shift register bits “flow” through A1 and A0. This will corrupt the data in registers) are level triggered via the LOAD signal. This each DAC register that has been erroneously selected. (8) Rising edge of RST double-buffered architecture has been designed so that new causes no change in the contents of the serial shift register. data can be entered for each DAC without disturbing the TABLE II. Serial Shift Register Truth Table. analog outputs. When the new data has been entered into the SERIAL DATA INPUT B23 B22 B21 B20 B19 B18 B17 B16 B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 QUICK A1 A0 X X X X X D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 LOAD INPUT DAC LDAC LOAD REGISTER REGISTER MODE DAC A1 A0 CS RST RSTSEL L L L H X X L Write Hold Write Input A L H L H X X L Write Hold Write Input B H L L H X X L Write Hold Write Input C H H L H X X L Write Hold Write Input D XX H H X ↑ H Hold Write Update All X X H H X H H Hold Hold Hold All XXX ↑ L X X Reset to Zero Reset to Zero Reset to Zero All XXX ↑ H X X Reset to Midscale Reset to Midscale Reset to Midscale All TABLE I. DAC7734 Logic Truth Table. ® 21 DAC7734 SERIAL-DATA OUTPUT DIGITALLY-PROGRAMMABLE CURRENT SOURCE The Serial-Data Output (SDO) is the internal shift register's The DAC7734 offers a unique set of features that allows a output. For DAC7734, the SDO is a driven output and does wide range of flexibility in designing applications circuits not require an external pull-up. Any number of DAC7734's such as programmable current sources. The DAC7734 offers can be daisy chained by connecting the SDO pin of one both a differential reference input, as well as an open-loop device to the SDI pin of the following device in the chain, configuration around the output amplifier. The open-loop as shown in Figure 11. configuration around the output amplifier allows a transistor to be placed within the loop to implement a digitally- DIGITAL TIMING programmable, unidirectional current source. The availabil- Figure 12 and Table III provide detailed timing for the ity of a differential reference allows programmability for digital interface of the DAC7734. both the full-scale and zero-scale currents. The output cur- rent is calculated as: DIGITAL INPUT CODING The DAC7734 input data is in Straight Binary format. The     VH –V L  N  REF REF I = • (2) output voltage is given by Equation 1.   OUT     R  65,536     SENSE where N is the digital input code. This equation does not +VL /R () REF SENSE VH–• V L N () REF REF (1) VV=+L OUT REF 65,536 include the effects of offset (zero-scale) or gain (full-scale) errors. DAC7734 DAC7734 DAC7734 LDAC LDAC LDAC LDAC SCK CLK CLK CLK SDO SDO SDO DIN SDI SDI SDI CS CS CS CS LOAD LOAD LOAD To Other Serial Devices LOAD FIGURE 11. Daisy-Chaining DAC7734. ® 22 DAC7734 (LSB) (MSB) QUICK SDI A1 A0 XXXXX D15 D14 D13 D3 D2 D1 D0 LOAD CLK t t CSH css CS t LDDD t t LD2 LD1 LOAD t LDRW LDAC t t DS DH SDI t SDO t t CL CH CLK SDO t t LDDL LDDH LDAC t t S S –0.003%–0.003% V OUT ERROR BAND ERROR BAND t t RSTL RSTH RESET t RSSH t RSSS RESETSEL FIGURE 12. Digital Input and Output Timing. SYMBOL DESCRIPTION MIN MAX UNITS t Data Valid to CLK Rising 10 ns DS t Data Held Valid after CLK Rises 20 ns DH t CLK HIGH 25 ns CH t CLK LOW 25 ns CL t CS LOW to CLK Rising 15 ns CSS t CLK HIGH to CS Rising 0 ns CSH t LOAD HIGH to CLK Rising 10 ns LD1 t CLK Rising to LOAD LOW 30 ns LD2 t LOAD LOW Time 30 ns LDRW t LDAC LOW Time 40 ns LDDWL t LDAC HIGH Time 40 ns LDDH t SDO Propagation Delay 10 45 ns SDO t RESETSEL Valid to RESET HIGH 0 ns RSSS t RESET HIGH to RESETSEL Not Valid 100 ns RSSH t RESET LOW Time 10 ns RSTL t RESET HIGH Time 10 ns RSTH t LOAD LOW to LDAC Rising Time 40 ns LDDD t Settling Time 10 (dual)/11(single) μs S TABLE III. Timing Specifications (T = –40°C to +85°C). A ® 23 DAC7734 Figure 13 shows a DAC7734 in a 4mA to 20mA current At full-scale, the output current is 16mA, plus the 4mA, for output configuration. The output current can be determined the zero current. At zero scale the output current is the offset by Equation 3: current of 4mA (1V/250Ω). (3)   51 VV –  N  1V     I = • +   OUT       250ΩΩ  65,536 250   I OUT V PROGRAMMED R SENSE +V 250Ω V A Sense 48 OUT OPA2350 V A 47 OUT AGND 46 DAC7734 20kΩ 2200pF 100Ω V 45 SS 1.0V V L AB Sense 44 REF +V 80kΩ V L AB 43 REF 1000pF V H AB 42 REF 5V 100Ω V H AB Sense 41 REF 1000pF 2200pF V B Sense 40 OUT V B 39 OUT I OUT V PROGRAMMED R SENSE 250Ω FIGURE 13. 4-to-20mA Digitally Controlled Current Source (1/2 DAC7734). ® 24 DAC7734 PACKAGE OPTION ADDENDUM www.ti.com 14-Mar-2007 PACKAGING INFORMATION (1) (2) (3) Orderable Device Status Package Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Type Drawing Qty DAC7734E ACTIVE SSOP DL 48 30 Green (RoHS & CU NIPDAU Level-3-260C-168 HR no Sb/Br) DAC7734E/1K ACTIVE SSOP DL 48 1000 Green (RoHS & CU NIPDAU Level-3-260C-168 HR no Sb/Br) DAC7734E/1KG4 ACTIVE SSOP DL 48 1000 Green (RoHS & CU NIPDAU Level-3-260C-168 HR no Sb/Br) DAC7734EB ACTIVE SSOP DL 48 30 Green (RoHS & CU NIPDAU Level-3-260C-168 HR no Sb/Br) DAC7734EB/1K ACTIVE SSOP DL 48 1000 Green (RoHS & CU NIPDAU Level-3-260C-168 HR no Sb/Br) DAC7734EB/1KG4 ACTIVE SSOP DL 48 1000 Green (RoHS & CU NIPDAU Level-3-260C-168 HR no Sb/Br) DAC7734EBG4 ACTIVE SSOP DL 48 30 Green (RoHS & CU NIPDAU Level-3-260C-168 HR no Sb/Br) DAC7734EC ACTIVE SSOP DL 48 30 Green (RoHS & CU NIPDAU Level-3-260C-168 HR no Sb/Br) DAC7734EC/1K ACTIVE SSOP DL 48 1000 Green (RoHS & CU NIPDAU Level-3-260C-168 HR no Sb/Br) DAC7734EC/1KG4 ACTIVE SSOP DL 48 1000 Green (RoHS & CU NIPDAU Level-3-260C-168 HR no Sb/Br) DAC7734ECG4 ACTIVE SSOP DL 48 30 Green (RoHS & CU NIPDAU Level-3-260C-168 HR no Sb/Br) DAC7734EG4 ACTIVE SSOP DL 48 30 Green (RoHS & CU NIPDAU Level-3-260C-168 HR no Sb/Br) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. Addendum-Page 1 PACKAGE OPTION ADDENDUM www.ti.com 14-Mar-2007 In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. 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