® ADS7852 ADS7852 SBAS111B – JANUARY 1998 – REVISED JULY 2003 12-Bit, 8-Channel, Parallel Output ANALOG-TO-DIGITAL CONVERTER FEATURES DESCRIPTION 2.5V INTERNAL REFERENCE The ADS7852 is an 8-channel, 12-bit Analog-to-Digital (A/D) converter complete with sample-and-hold, internal 2.5V 8 INPUT CHANNELS reference and a full 12-bit parallel output interface. Typical 500kHz SAMPLING RATE power dissipation is 13mW at 500kHz throughput rate. The SINGLE 5V SUPPLY ADS7852 features both a nap mode and a sleep mode, further ±1LSB: INL, DNL reducing the power consumption to 2mW. The input range is from 0V to twice the reference voltage. The reference voltage GUARANTEED NO MISSING CODES can be overdriven by an external voltage. 70dB SINAD The ADS7852 is ideal for multi-channel applications where LOW POWER: 13mW low power and small size are critical. Medical instrumenta- TQFP-32 PACKAGE tion, high-speed data acquisition and laboratory equipment are just a few of the applications that would take advantage of the special features offered by the ADS7852. The ADS7852 APPLICATIONS is available in an TQFP-32 package and is fully specified and DATA ACQUISITION guaranteed over the –40°C to +85°C temperature range. TEST AND MEASUREMENT INDUSTRIAL PROCESS CONTROL MEDICAL INSTRUMENTS A0 A1 A2 ADS7852 SAR AIN0 AIN1 AIN2 3-State AIN3 8-Channel Parallel MUX Data Bus AIN4 AIN5 Output CLK CDAC AIN6 Latches BUSY AIN7 and WR 3-State Comparator Drivers CS RD Internal Buffer +2.5V Ref 10kΩ V REF Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Copyright © 1998-2003, Texas Instruments Incorporated Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. www.ti.com (1) ABSOLUTE MAXIMUM RATINGS ELECTROSTATIC Analog Inputs to AGND, Any Channel Input .............. –0.3V to (V + 0.3V) D DISCHARGE SENSITIVITY REF ......................................................................... –0.3V to (V + 0.3V) IN D Digital Inputs to DGND .............................................. –0.3V to (V + 0.3V) D This integrated circuit can be damaged by ESD. Texas Instru- Ground Voltage Differences: AGND, DGND ..................................... ±0.3V +V to AGND ..........................................................................–0.3V to 6V ments recommends that all integrated circuits be handled with SS Power Dissipation .......................................................................... 325mW appropriate precautions. Failure to observe proper handling Maximum Junction Temperature ................................................... +150°C and installation procedures can cause damage. Operating Temperature Range ......................................... –40°C to +85°C Storage Temperature Range .......................................... –65°C to +150°C ESD damage can range from subtle performance degrada- Lead Temperature (soldering, 10s) ............................................... +300°C tion to complete device failure. Precision integrated circuits NOTE: (1) Stresses above those listed under “Absolute Maximum Ratings” may may be more susceptible to damage because very small cause permanent damage to the device. Exposure to absolute maximum condi- parametric changes could cause the device not to meet tions for extended periods may affect device reliability. published specifications. PACKAGE/ORDERING INFORMATION MAXIMUM MAXIMUM RELATIVE GAIN SPECIFIED ACCURACY ERROR PACKAGE TEMPERATURE ORDERING TRANSPORT (1) PRODUCT (LSB) (LSB) PACKAGE-LEAD DESIGNATOR RANGE NUMBER MEDIA, QUANTITY ADS7852Y ±2 ±40 TQFP-32 PBS –40°C to +85°C ADS7852Y/250 Tape and Reel, 250 ADS7852Y "" " " " ADS7852Y/2K Tape and Reel, 2000 ADS7852YB ±1 ±25 TQFP-32 PBS –40°C to +85°C ADS7852YB/250 Tape and Reel, 250 "" " " " ADS7852YB/2K Tape and Reel, 2000 ADS7852YB NOTE: (1) For the most current specifications and package information, refer to our web site at www.ti.com. ADS7852 CHANNEL SELECTION A2 A1 A0 CHANNEL SELECTED 0 0 0 Channel 0 0 0 1 Channel 1 0 1 0 Channel 2 0 1 1 Channel 3 1 0 0 Channel 4 1 0 1 Channel 5 1 1 0 Channel 6 1 1 1 Channel 7 ADS7852 2 SBAS111B ELECTRICAL CHARACTERISTICS At T = –40°C to +85°C, f = 500kHz, f = 16 • f , and V = +5V, using internal reference, unless otherwise specified. A S CLK S SS ADS7852Y ADS7852YB PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX UNITS RESOLUTION 12✻Bits ANALOG INPUT Input Voltage Range 0 5✻✻ V Input Impedance 5M✻Ω Input Capacitance 15✻pF Input Leakage Current ±1✻μA DC ACCURACY No Missing Codes 12✻Bits (1) Integral Linearity Error ±2 ±1 LSB Differential Linearity Error ±1 ±0.5 ±1 LSB Offset Error ±2 ±5 ±1✻LSB Offset Error Drift ±4✻ppm/°C Offset Error Match ±1✻LSB (1) Gain Error Ext Ref = 2.5000V ±15 ±10 LSB Gain Error Int Ref ±40 ±25 LSB Gain Error Drift ±25✻ppm/°C Gain Error Match ±1✻LSB Noise 150✻μVrms Power Supply Rejection Ratio Worst-Case Δ, +V = 5V ±5% 1.2✻LSB SS SAMPLING DYNAMICS Conversion Time 13.5✻Clk Cycles Acquisition Time 1.5✻Clk Cycles Throughput Rate 500✻kHz Multiplexer Settling Time 500✻ns Aperture Delay 5✻ns Aperture Jitter 30✻ps AC ACCURACY Signal-to-Noise Ratio 72✻dB (3) Total Harmonic Distortion V = 5Vp-p at 50kHz –74 –72 –77 –76 dB IN Signal-to-(Noise+Distortion) V = 5Vp-p at 50kHz 68 70 71 72 dB IN Spurious Free Dynamic Range V = 5Vp-p at 50kHz 76 74 78 77 dB IN Channel-to-Channel Isolation V = 5Vp-p at 50kHz 95✻dB IN REFERENCE OUTPUT Internal Reference Voltage 2.48 2.50 2.52 ✻✻✻V Internal Reference Drift 30✻ppm/°C Input Impedance CS = GND 5✻GΩ CS = V 5✻GΩ SS (4) Source Current Static Load 50✻μA REFERENCE INPUT Range 2.0 2.55✻✻ V (5) Resistance to Internal Reference Voltage 10✻kΩ DIGITAL INPUT/OUTPUT Logic Family CMOS✻ Logic Levels: V I = +5μA3 +V + 0.3✻✻ V IH IH SS V I = +5μA –0.3 0.8✻✻ V IL IL V I = 250μA 3.5✻V OH OH V I = 250μA 0.4✻V OL OL Data Format Straight Binary✻ POWER SUPPLY REQUIREMENT +V Specified Performance 4.75 5.25✻✻ V SS Quiescent Current 2.6 3.5 ✻✻ mA Normal Power 13 17.5 ✻✻ mW (6) Nap Mode Current 600 800 ✻✻ μA (6) Sleep Mode Current 10 30 ✻✻ μA TEMPERATURE RANGE Specified Performance –40 +85✻✻ °C Storage –65 +150✻✻ °C ✻ Specifications same as ADS7852Y. NOTES: (1) LSB means Least Significant Bit, with V equal to +2.5V, one LSB is 1.22mV. (2) Measured relative to an ideal, full-scale input of 4.999V. Thus, REF gain error includes the error of the internal voltage reference. (3) Calculated on the first nine harmonics of the input frequency. (4) If the internal reference is required to source current to an external load, the reference voltage will change due to the internal 10kΩ resistor. (5) Can vary ±30%. (6) See Timing Characteristics for further detail. ADS7852 3 SBAS111B PIN DESCRIPTIONS PIN CONFIGURATION PIN NAME DESCRIPTION Top View TQFP 1 AIN0 Analog Input Channel 0 2 AIN1 Analog Input Channel 1 3 AIN2 Analog Input Channel 2 4 AIN3 Analog Input Channel 3 5 AIN4 Analog Input Channel 4 6 AIN5 Analog Input Channel 5 7 AIN6 Analog Input Channel 6 8 AIN7 Analog Input Channel 7 9 AGND Analog Ground, GND = 0V 1 24 DB2 AIN0 10 V Voltage Reference Input and Output. See REF Electrical Characteristics table for ranges. 2 23 DB3 AIN1 Decouple to ground with a 0.1μF ceramic 3 22 DB4 AIN2 capacitor and a 2.2μF tantalum capacitor. 11 DGND Digital Ground, GND = 0V 4 21 DB5 AIN3 ADS7852Y 12 A2 Channel Address. See Channel Selection 5 20 DB6 AIN4 Table for details. 13 A1 Channel Address. See Channel Selection 6 19 DB7 AIN5 Table for details. 7 18 DB8 AIN6 14 A0 Channel Address. See Channel Selection Table for details. 8 17 DB9 AIN7 15 DB11 Data Bit 11 (MSB) 16 DB10 Data Bit 10 17 DB9 Data Bit 9 18 DB8 Data Bit 8 19 DB7 Data Bit 7 20 DB6 Data Bit 6 21 DB5 Data Bit 5 22 DB4 Data Bit 4 23 DB3 Data Bit 3 24 DB2 Data Bit 2 25 DB1 Data Bit 1 26 DB0 Data Bit 0 (LSB) 27 WR Write Input. Active LOW. Use to start a new conversion and to select an analog channel via address inputs A0, A1 and A2 in combination with CS. 28 BUSY BUSY output goes LOW and stays LOW during a conversion. BUSY rises when a conversion is complete. 29 CLK External Clock Input. The clock speed determines the conversion rate by the equation: f = 16 • f . CLK SAMPLE 30 RD Read Input. Active LOW. Use to read the data outputs in combination with CS. Also use (in conjunction with A0 or A1) to place device in power-down mode. 31 CS Chip Select Input. Active LOW. The combination of CS taken LOW and WR taken LOW initiates a new conversion and places the outputs in tri-state mode. 32 V Voltage Supply Input. Nominally +5V. SS Decouple to ground with a 0.1μF ceramic capacitor and a 10μF tantalum capacitor. ADS7852 4 SBAS111B AGND 9 32 V SS V 10 31 CS REF DGND 11 30 RD A2 12 29 CLK A1 13 28 BUSY A0 14 27 WR DB11 (MSB) 15 26 DB0 (LSB) DB10 16 25 DB1 TYPICAL CHARACTERISTICS At T = +25°C, V = +5V, f = 500kHz, f = 16 • f , and internal reference, unless otherwise specified. A SS SAMPLE CLK SAMPLE SPECTRAL PERFORMANCE SPECTRAL PERFORMANCE (4096 Point FFT, f = 49.561kHz, –0.5dB) (4096 Point FFT, f = 100.7081kHz, –0.5dB) IN IN 0 0 –20 –20 –40 –40 –60 –60 –80 –80 –100 –100 –120 –120 0 50 100 150 200 250 0 50 100 150 200 250 Frequency (kHz) Frequency (kHz) SPECTRAL PERFORMANCE SPECTRAL PERFORMANCE (4096 Point FFT, f = 199.5851kHz, –0.5dB) (4096 Point FFT, f = 247.1921kHz, –0.5dB) IN IN 0 0 –20 –20 –40 –40 –60 –60 –80 –80 –100 –100 –120 –120 0 50 100 150 200 250 0 50 100 150 200 250 Frequency (kHz) Frequency (kHz) CHANGE IN SIGNAL-TO-NOISE RATIO AND CHANGE IN SPURIOUS FREE DYNAMIC RANGE AND SIGNAL-TO-(NOISE+DISTORTION) vs TEMPERATURE TOTAL HARMONIC DISTORTION vs TEMPERATURE 0.4 1.0 –1.0 f = 49.6kHz,–0.5dB f = 49.6kHz,–0.5dB NOTE: (1) First nine harmonics IN IN 0.3 of the input frequency 0.2 0.5 –0.5 SNR (1) THD 0.1 SINAD 0.0 0.0 0.0 –0.1 SFDR –0.2 –0.5 0.5 –0.3 –0.4 –0.5 –1.0 1.0 –50 –25 0 25 50 75 100 –50 –25 0 25 50 75 100 Temperature (°C) Temperature (°C) ADS7852 5 SBAS111B Amplitude (dB) SFDR Delta from +25°C (dB) Amplitude (dB) THD Delta from +25°C (dB) Amplitude (dB) Amplitude (dB) SNR and SINAD Delta from +25°C (dB) TYPICAL CHARACTERISTICS (Cont.) At T = +25°C, V = +5V, f = 500kHz, f = 16 • f , and internal reference, unless otherwise specified. A SS SAMPLE CLK SAMPLE SIGNAL-TO-NOISE and SPURIOUS FREE DYNAMIC RANGE and SIGNAL-TO-(NOISE+DISTORTION) TOTAL HARMONIC DISTORTION vs INPUT FREQUENCY vs INPUT FREQUENCY 76 90 –90 SNR SFDR 74 85 –85 72 THD* SINAD 80 –80 70 75 –75 68 *First nine harmonics of the input frequency 66 70 –70 1k 10k 100k 1M 1k 10k 100k 1M Input Frequency (Hz) INTEGRAL LINEARITY ERROR vs CODE DIFFERENTIAL LINEARITY ERROR vs CODE 1.00 1.00 0.75 0.75 0.50 0.50 0.25 0.25 0.00 0.00 –0.25 –0.25 –0.50 –0.50 –0.75 –0.75 –1.00 –1.00 000 400 800 C00 FFF 000 400 800 C00 FFF H H H H H H H H H H Output Code Output Code CHANGE IN INTERNAL REFERENCE VOLTAGE vs TEMPERATURE CHANGE IN GAIN ERROR vs TEMPERATURE 6.0 8 6 4.0 4 2.0 2 0.0 0 –2 –2.0 –4 –4.0 –6 –6.0 –8 –50 –25 0 25 50 75 100 –50 –25 0 25 50 75 100 Temperature (°C) Temperature (°C) ADS7852 6 SBAS111B ILE (LSBs) Delta from +25°C (mV) SNR and SINAD (dB) DLE (LSBs) Delta from +25°C (LSB) SFDR (dB) THD (dB) TYPICAL CHARACTERISTICS (Cont.) At T = +25°C, V = +5V, f = 500kHz, f = 16 • f , and internal reference, unless otherwise specified. A SS SAMPLE CLK SAMPLE CHANGE IN GAIN ERROR vs TEMPERATURE (With External 2.5V Reference) CHANGE IN OFFSET vs TEMPERATURE 0.5 1.0 0.4 0.8 0.3 0.6 0.2 0.1 0.4 0 0.2 –0.1 –0.2 0.0 –0.3 –0.2 –0.4 –0.5 –0.4 –50 –25 0 25 50 75 100 –50 –25 0 25 50 75 100 Temperature (°C) Temperature (°C) CHANGE IN WORST-CASE CHANNEL-TO-CHANNEL CHANGE IN WORST-CASE CHANNEL-TO-CHANNEL OFFSET MISMATCH vs TEMPERATURE GAIN MISMATCH vs TEMPERATURE 0.10 0.020 0.015 0.05 0.010 0.005 0.00 0.000 –0.005 –0.05 –0.010 –0.015 –0.10 –0.020 –50 –25 0 25 50 75 100 –50 –25 0 25 50 75 100 Temperature (°C) Temperature (°C) CHANGE IN WORST-CASE INTEGRAL LINEARITY CHANGE IN WORST-CASE INTEGRAL LINEARITY AND DIFFERENTIAL LINEARITY vs TEMPERATURE AND DIFFERENTIAL LINEARITY vs SAMPLE RATE 3.0 0.050 2.5 Delta IL 0.025 2.0 1.5 1.0 0.000 Delta IL 0.5 –0.025 Delta DL 0.0 Delta DL –0.5 –1.0 –0.050 100 200 300 400 500 600 700 800 –50 –25 0 25 50 75 100 Sample Rate (kHz) Temperature (°C) ADS7852 7 SBAS111B Delta from +25°C (LSB) Delta Relative to f = 500kHz (LSB) Delta from +25°C (LSB) SAMPLE Delta from +25°C (LSB) Delta from +25°C (LSB) Delta from +25°C (LSB) TYPICAL CHARACTERISTICS (Cont.) At T = +25°C, V = +5V, f = 500kHz, f = 16 • f , and internal reference, unless otherwise specified. A SS SAMPLE CLK SAMPLE SUPPLY CURRENT vs TEMPERATURE SUPPLY CURRENT vs SAMPLE RATE 2.680 2.9 f = 500kHz SAMPLE 2.8 2.675 2.7 2.670 2.6 2.665 2.5 2.660 2.4 2.655 2.3 –50 –25 0 25 50 75 100 100 200 300 400 500 600 Temperature (°C) Sample Rate (kHz) CHANGE IN NAP CURRENT AND SLEEP CURRENT vs TEMPERATURE CHANGE IN GAIN AND OFFSET vs SUPPLY VOLTAGE 25 0.25 0.20 Gain 20 0.15 15 0.10 Nap 0.05 10 0.00 Offset 5 –0.05 –0.10 0 Sleep –0.15 –5 –0.20 –10 –0.25 –50 –25 0 25 50 75 100 4.75 4.80 4.85 4.90 4.95 5.00 5.05 5.10 5.15 5.20 5.25 Temperature (°C) V (V) SS POWER SUPPLY REJECTION vs POWER SUPPLY RIPPLE FREQUENCY 30 25 20 15 10 5 0 10 100 1k 10k 100k 1M ADS7852 8 SBAS111B Supply Current (mA) Delta from +25°C (μA) Power Supply Rejection (mV/V) Delta from V = 5.00V (LSB) SS Supply Current (mA) The front-end input multiplexer of the ADS7852 features THEORY OF OPERATION eight single-ended analog inputs. Channel selection is per- The ADS7852 is a high-speed successive approximation formed using the address pins A0 (pin 14), A1 (pin 13), and register (SAR) Analog-to-Digital (A/D) converter with an A2 (pin 12). When a conversion is initiated, the input internal 2.5V bandgap reference. The architecture is based voltage is sampled on the internal capacitor array. While a on capacitive redistribution, which inherently includes a conversion is in progress, all channel inputs are discon- sample/hold function. The converter is fabricated on a 0.6mi- nected from any internal function. cron CMOS process. Figure 1 shows the basic operating The range of the analog input is set by the voltage on the circuit for the ADS7852. V pin. With the internal 2.5V reference, the input range REF The ADS7852 requires an external clock to run the conver- is 0V to 5V. An external reference voltage can be placed on sion process. This clock can vary between 200kHz (12.5Hz V , overdriving the internal voltage. The range for the REF throughput) and 8MHz (500kHz throughput). The duty cycle external voltage is 2.0V to 2.55V, giving an input voltage of the clock is unimportant as long as the minimum HIGH range of 4.0V to 5.1V. and LOW times are at least 50ns and the clock period is at least 125ns. The minimum clock frequency is governed by the parasitic leakage of the Capacitive Digital-to-Analog (CDAC) capacitors internal to the ADS7852. +5V Analog Supply + + 10μF 0.1μF 0V to 5V 1 AIN0 DB2 24 2 AIN1 DB3 23 3 AIN2 DB4 22 4 AIN3 DB5 21 ADS7852Y 5 AIN4 DB6 20 6 AIN5 DB7 19 7 AIN6 DB8 18 8 AIN7 DB9 17 + + 0.1μF 2.2μF FIGURE 1. Typical Circuit Configuration. ADS7852 9 SBAS111B 9 AGND V 32 SS Chip Select 10 V CS 31 REF Read Input 11 DGND RD 30 Clock Input A2 Select 12 A2 CLK 29 Busy Output A1 Select 13 A1 BUSY 28 Write Input A0 Select 14 A0 WR 27 15 DB11 (MSB) DB0 (LSB) 26 16 DB10 DB1 25 10kΩ resistor that is connected to the 2.5V internal reference. ANALOG INPUTS Accounting for the maximum difference between the external The ADS7852 features eight single-ended inputs. While the reference voltage and the internal reference voltage, and the static current into each analog input is basically zero, the processing variations for the on-chip 10kΩ resistor, this current dynamic current depends on the input voltage and sample can be as high as 75μA. In addition, the V pin should still REF rate. The current into the device must charge the internal be bypassed to ground with at least a 0.1μF ceramic capacitor hold capacitor during the sample period. After this capacitor placed as close to the ADS7852 as possible. Depending on the has been fully charged, no further input current is required. particular reference and A/D conversion speed, additional For optimum performance, the source driving the analog bypass capacitance may be required, such as the 2.2μF tanta- inputs must be capable of charging the input capacitance to lum capacitor shown in the Typical Circuit Configuration a 12-bit settling level within the sample period. This can be (Figure 1). Close attention should be paid to the stability of any as little as 350ns in some operating modes. While the external reference source that is driving the large bypass converter is in the hold mode, or after the sampling capacitor capacitors present at the V pin. REF has been fully charged, the input impedance of the analog input is greater than 1GΩ. BASIC OPERATION Figure 1 shows the simple circuit required to operate the REFERENCE ADS7852 with Channel 0 selected. A conversion can be The reference voltage on the V pin establishes the full- REF initiated by bringing the WR pin (pin 27) LOW for a scale range of the analog input. The ADS7852 can operate minimum of 35ns. BUSY (pin 28) will output a LOW during with a reference in the range of 2.0V to 2.55V corresponding the conversion process and rises only after the conversion is to a full-scale range of 4.0V to 5.1V. complete. The 12 bits of output data will be valid on pins 15 through 26 following the rising edge of BUSY. The voltage at the V pin is internally buffered, and this REF buffer drives the capacitor DAC portion of the converter. This feature is important because the buffer greatly reduces STARTING A CONVERSION the dynamic load placed on the reference source. Since the A conversion is initiated on the falling edge of the WR voltage at V will be unavoidably affected by noise and REF input, with valid signals on A0, A1, A2, and CS. The glitches generated during the conversion process, it is highly ADS7852 will enter the conversion mode on the first rising recommended that the V pin be bypassed to ground as REF edge of the external clock following the WR pin going outlined in the sections that follow. LOW. The conversion process takes 13.5 clock cycles (1.5 cycles for the DB0 decision, 2 clock cycles for the DB5 INTERNAL REFERENCE decision, and 1 clock cycle for each of the other bit deci- sions). This allows 2.5 clock cycles for sampling. Upon The ADS7852 contains an onboard 2.5V reference, resulting initiating a conversion, the BUSY output will go LOW in a 0V to 5V input range on the analog input. The Specifi- approximately 20ns after the falling edge of the WR pin. cations Table gives the various specifications for the internal The BUSY output will return HIGH just after the ADS7852 reference. This reference can be used to supply a small has finished a conversion and the output data will be valid amount of source current to an external load but the load on pins 15 through 26. The rising edge of BUSY can be used should be static. Due to the internal 10kΩ resistor, a dy- to latch the output data into an external device. It is recom- namic load will cause variations in the reference voltage, mended that the data be read immediately after each conver- and will dramatically affect the conversion result. Note that sion since the switching noise of the asynchronous data even a static load will reduce the internal reference voltage transfer can cause digital feedthrough degrading the con- seen at the buffer input. The amount of reduction depends on verter performance (see Figure 2). the load and the actual value of the internal 10kΩ resistor. The value of this resistor can vary by ±30%. CHANNEL ADDRESSING The V pin should be bypassed with a 0.1μF ceramic REF capacitor placed as close to the ADS7852 as possible. In The selection of the analog input channel to be converted is addition, a 2.2μF tantalum capacitor should be used in controlled by address pins A0, A1, and A2. This channel parallel with the ceramic capacitor. becomes active on the rising edge of WR with CS held LOW. The data on the address pins should be stable for at least 10ns prior to WR going HIGH. EXTERNAL REFERENCE The address pins are also used to control the power-down The internal reference is connected to the V pin and to the REF functions of the ADS7852. Careful attention must be paid to internal buffer via an on-chip 10kΩ series resistor. Because of the status of the address pins following each conversion. If this configuration, the internal reference voltage can easily be the user does not want the ADS7852 to enter either of the overridden by an external reference voltage. The voltage range power-down modes following a conversion, the A0 and A1 for the external voltage is 2.00V to 2.55V, corresponding to an pins must be LOW when RD and CS are returned HIGH after analog input range of 4.0V to 5.1V. reading the data at the end of a conversion (see the Power- While the external reference will not have to provide significant Down Mode section of this data sheet for more details). dynamic current to the V in, it does have to drive the series REF ADS7852 10 SBAS111B HOLD t t CKH CKP CLK 1 2 34 5 6 78 9 10 11 12 13 14 15 16 1 2 34 5 6 78 9 10 11 12 13 14 15 16 1 2 34 5 6 78 t CKL t 4 t t 1 2 WR t 4 t 3 CS t 5 Conversion n Conversion n + 1 BUSY t t CONV ACQ t 6 RD t 7 t 8 Address Address n + 1 Address n + 2 Bus t 9 t 10 Data Data Data Hi-Z Hi-Z Hi-Z Valid Valid Bus SYMBOL DESCRIPTION MIN TYP MAX UNITS t Conversion Time 1.75 μs CONV t Acquisition Time 0.25 μs ACQ t Clock Period 125 5000 ns CKP t Clock LOW 40 ns CKL t Clock HIGH 40 ns CKH t WR LOW Prior to Rising Edge of CLK 35 ns 1 t WR LOW After Rising Edge of CLK 20 ns 2 t CS LOW After Rising Edge of CLK 20 ns 3 t CS and RD HIGH 25 ns 4 t BUSY Delay After CS LOW 20 ns 5 t RD LOW 25 ns 6 t Address Hold Time 5 ns 7 t Address Setup Time 5 ns 8 t Bus Access Time 30 ns 9 t Bus Relinquish Time 5 ns 10 t CS to RD Setup Time 0 ns 11 t RD to CS Hold Time 0 ns 12 t CLK LOW to BUSY HIGH 10 ns 13 t BUSY to RD Delay 0 ns 14 t RD HIGH to CLK LOW 50 ns 15 FIGURE 2. ADS7852 Write/Read Timing. DIGITAL OUTPUT READING DATA STRAIGHT BINARY Data from the ADS7852 will appear at pins 15 through 26. DESCRIPTION ANALOG INPUT BINARY CODE HEX CODE The MSB will output on pin 15 while the LSB will output Least Significant 1.2207mV on pin 26. The outputs are coded in Straight Binary (with Bit (LSB) 0V = 000 and 5V = FFF ). Following a conversion, the Full Scale 4.99878V 1111 1111 1111 FFF H H Midscale 2.5V 1000 0000 0000 800 BUSY pin will go HIGH. After BUSY has been HIGH for Midscale –1LSB 2.49878V 0111 1111 1111 7FF at least t seconds, the CS and RD pins may be brought 14 Zero Full Scale 0V 0000 0000 0000 000 LOW to enable the 12-bit output bus. CS and RD must be held LOW for at least 25ns following BUSY HIGH. Data Table I. Ideal Input Voltages and Output Codes. will be valid 30ns after the falling edge of both CS and RD. The output data will remain valid for 20ns following the rising edge of both CS and RD (see Figure 2 for the read cycle timing diagram). ADS7852 11 SBAS111B POWER-DOWN MODE Since the Nap mode maintains the voltage on the V pin by REF keeping the internal reference powered-up, valid conversions The ADS7852 has two different power-down modes: the are available immediately after the Nap mode is terminated. Nap mode and the Sleep mode. In Nap mode, all analog and digital circuitry is powered off, with the exception of the The simplest way to use the power-down mode is following voltage reference. In Sleep mode, the device is completely a conversion. After a conversion has finished and BUSY has powered off. returned HIGH, CS and RD must be brought LOW for a minimum of 25ns. When RD and CS are returned HIGH, the While the Sleep mode affords the lowest power consump- ADS7852 will enter the power-down mode on the rising tion, the time to come out of Sleep mode can be considerable edge of RD. If CS is always kept LOW, the power-down since it takes the internal reference voltage a finite amount of mode will be controlled exclusively by RD. Depending on time to power up and reach a stable value. This latency can the status of the A0 and A1 address pins, the ADS7852 will result in spurious output data for a minimum of ten conver- either enter the Nap mode, the Sleep mode, or be returned sion cycles at a 500kHz sampling rate. It should also be to normal operation in the sampling mode. See Table II and noted that any external load connected to the V pin will REF Figures 3 and 4 for further details. increase this effect since a discharge path for the V REF bypass capacitor is provided during the Sleep cycle. Even the RD A2 A1 A0 POWER-DOWN MODE parasitic leakage of the bypass capacitor itself should be X 0 0 None considered if the unit is left in the Sleep mode for an X 1 0 Sleep extended period. After power-up, this capacitor must be X0 1 Nap recharged by the internal reference voltage and the on-chip X 1 1 Sleep 10kΩ series resistor. Under worst-case conditions (for ex- ample, the bypass capacitor is completely discharged), the = Signifies rising edge of RD pin. X = Don't care output data can be invalid for several hundred milliseconds. TABLE II. ADS7852 Power-Down Mode. CS t t 11 12 t 6 RD CLK t 13 t 14 BUSY t t 7 8 A1 A0 NOTE: Rising edge of 1st RD while A0 = 1 initiates power-down immediately. A1 must be LOW to enter Nap mode. FIGURE 3. Entering Nap Using RD and A0. CS t t 11 12 t 6 RD t 15 CLK t t 7 8 A1 A0 NOTE: Rising edge of 2nd RD while A0 = 0 places the ADS7852 in sample mode. A1 must be LOW to initiate wake-up. FIGURE 4. Initiating Wake-Up Using RD and A0. ADS7852 12 SBAS111B LAYOUT Test Point For optimum performance, care should be taken with the physical layout of the ADS7852 circuitry. This is particularly V CC t Waveform 2, t true if the CLK input is approaching the maximum throughput 3kΩ dis en D OUT rate. t Waveform 1 dis 100pF The basic SAR architecture is sensitive to glitches or sudden C LOAD changes on the power supply, reference, ground connections, and digital inputs that occur just prior to latching the output Load Circuit for t and t dis en of the analog comparator. Thus, driving any single conversion for an n-bit SAR converter, there are n “windows” in which large external transient voltages can affect the conversion result. Such glitches might originate from switching power V CS/SHDN IH supplies, nearby digital logic, or high power devices. The degree of error in the digital output depends on the reference D voltage, layout, and the exact timing of the external event. OUT 90% (1) Waveform 1 This error can change if the external event changes in times t dis with respect to the CLK input. D OUT With this effect in mind, power to the ADS7852 should be 10% (2) Waveform 2 clean and well bypassed. A 0.1μF ceramic bypass capacitor Voltage Waveforms for t dis should be placed as close to the device as possible. In addition, a 1μF to 10μF capacitor is recommended. If NOTES: (1) Waveform 1 is for an output with internal needed, an even larger capacitor and a 5Ω or 10Ω series conditions such that the output is HIGH unless disabled resistor may be used to low pass filter a noisy supply. The by the output control. (2) Waveform 2 is for an output with internal conditions such that the output is LOW ADS7852 draws very little current from an external reference unless disabled by the output control. on average as the reference voltage is internally buffered. However, glitches from the conversion process appear at the FIGURE 5. Timing Diagram and Test Circuits for Param- V input and the reference source must be able to handle REF eters in Figure 2. this. Whether the reference is internal or external, the V REF pin should be bypassed with a 0.1μF capacitor. An additional larger capacitor may also be used, if desired. If the reference In addition to using the address pins in conjunction with RD, voltage is external and originates from an op amp, make sure the power-down mode can also be terminated implicitly by it can drive the bypass capacitor or capacitors without starting a new conversion (for example, taking WR LOW oscillation. while CS is LOW). If it is desired to keep the ADS7852 in a power-down state for a period that is greater than dictated The GND pin should be connected to a clean ground point. In by the sampling rate, the convert signal driving the WR pin many cases, this will be the “analog” ground. Avoid connections must be disabled. which are too near the grounding point of a microcontroller or digital signal processor. If needed, run a ground trace directly The typical supply current of the ADS7852 is 2.6mA, with from the converter to the power supply entry point. The ideal a 5V supply and a 500kHz sampling rate. In the Nap mode, layout will include an analog ground plane dedicated to the the typical supply current is 600μA. In the Sleep mode, the converter and associated analog circuitry. current is typically reduced to 10μA. ADS7852 13 SBAS111B PACKAGE OPTION ADDENDUM www.ti.com 3-Oct-2003 PACKAGING INFORMATION ORDERABLE DEVICE STATUS(1) PACKAGE TYPE PACKAGE DRAWING PINS PACKAGE QTY ADS7852Y/250 ACTIVE TQFP PBS 32 250 ADS7852Y/2K ACTIVE TQFP PBS 32 2000 ADS7852YB/250 ACTIVE TQFP PBS 32 250 ADS7852YB/2K ACTIVE TQFP PBS 32 2000 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. MECHANICAL DATA MPQF027 – NOVEMBER 1995 PBS (S-PQFP-G32) PLASTIC QUAD FLATPACK 0,23 0,50 0,08 M 0,17 24 17 25 16 32 9 0,13 NOM 1 8 3,50 TYP Gage Plane 5,05 SQ 4,95 0,25 7,10 SQ 0,10 MIN 6,90 0°–7° 0,70 1,05 0,40 0,95 Seating Plane 0,08 1,20 MAX 4087735/A 11/95 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. 1 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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