VIPer100/SP ® - VIPer100A/ASP SMPS PRIMARY I.C. TYPE V I R DSS n DS(on) VIPer100/SP 620V 3 A 2.5 Ω VIPer100A/ASP 700V 3 A 2.8 Ω 10 � ADJUSTABLE SWITCHING FREQUENCY UP PENTAWATT HV PENTAWATT HV TO 200 kHz 1 (022Y) PowerSO-10™ � CURRENT MODE CONTROL � SOFT START AND SHUT DOWN CONTROL � AUTOMATIC BURST MODE OPERATION IN DESCRIPTION STAND-BY CONDITION ABLE TO MEET VIPer100™/100A, made using VIPower M0 “BLUE ANGEL” NORM (<1w TOTAL POWER Technology, combines on the same silicon chip a CONSUMPTION) state-of-the-art PWM circuit together with an optimized high voltage avalanche rugged Vertical � INTERNALLY TRIMMED ZENER REFERENCE Power MOSFET (620V or 700V / 3A). � UNDERVOLTAGE LOCK-OUT WITH Typical applications cover off line power supplies HYSTERESIS with a secondary power capability of 50 W in wide � INTEGRATED START-UP SUPPLY range condition and 100W in single range or with doubler configuration. It is compatible from both � AVALANCHE RUGGED primary or secondary regulation loop despite � OVERTEMPERATURE PROTECTION using around 50% less components when � LOW STAND-BY CURRENT compared with a discrete solution. Burst mode operation is an additional feature of this device, � ADJUSTABLE CURRENT LIMITATION offering the possibility to operate in stand-by mode without extra components. BLOCK DIAGRAM OSC DRAIN ON/OFF OSCILLATOR SECURITY PWM LATCH LATCH S FF UVLO VDD R/S Q R1 Q FF LOGIC S R2 R3 OVERTEMP. DETECTOR 0.5V _ + + 0.5 V + 1.7 μ s 1 V/A 250 ns _ DELAY _ BLANKING CURRENT ERROR AMPLIFIER _ AMPLIFIER 13 V + 4.5 V COMP SOURCE May 2003 1/23 1 FC00231 VIPer100/SP - VIPer100A/ASP ABSOLUTE MAXIMUM RATING Symbol Parameter Value Unit Continuous Drain-Source Voltage (T =25 to 125°C) j V for VIPer100/SP -0.3 to 620 V DS for VIPer100A/ASP -0.3 to 700 V I Maximum Current Internally limited A D V Supply Voltage 0 to 15 V DD V Voltage Range Input 0 to V V OSC DD V Voltage Range Input 0 to 5 V COMP I Maximum Continuous Current ± 2mA COMP V Electrostatic Discharge (R =1.5kΩ; C=100pF) 4000 V esd Avalanche Drain-Source Current, Repetitive or Not Repetitive (Tc=100°C; Pulse width limited by T max; δ < 1%) j I 2 A D(AR) for VIPer100/SP 1.4 A for VIPer100A/ASP P Power Dissipation at T =25ºC82W tot c T Junction Operating Temperature Internally limited °C j T Storage Temperature -65 to 150 °C stg THERMAL DATA Symbol Parameter PENTAWATT HV PowerSO-10™ (*) Unit R Thermal Resistance Junction-case Max 1.4 1.4 °C/W thj-case R Thermal Resistance Ambient-case Max 60 50 °C/W thj-amb. (*) When mounted using the minimum recommended pad size on FR-4 board. CONNECTION DIAGRAMS (Top View) PENTAWATT HV PENTAWATT HV (022Y) PowerSO-10™ CURRENT AND VOLTAGE CONVENTIONS IDD ID VDD DRAIN IOSC - OSC + 13V COMP SOURCE VDD DS V ICOMP OSC V VCOMP FC00020 2/23 1 VIPer100/SP - VIPer100A/ASP ORDERING NUMBERS PENTAWATT HV PENTAWATT HV (022Y) PowerSO-10™ VIPer100 VIPer100 (022Y) VIPer100SP VIPer100A VIPer100A (022Y) VIPer100ASP PINS FUNCTIONAL DESCRIPTION DRAIN PIN: Integrated Power MOSFET drain pin. It provides source, and can easily be connected to the internal bias current during start-up via an output of an optocoupler. Note that any integrated high voltage current source which is overvoltage due to regulation loop failure is still switched off during normal operation. The device detected by the error amplifier through the V DD is able to handle an unclamped current during its voltage, which cannot overpass 13V. The normal operation, assuring self protection against output voltage will be somewhat higher than the voltage surges, PCB stray inductance, and nominal one, but still under control. allowing a snubberless operation for low output power. COMP PIN: This pin provides two functions : SOURCE Pin: Power MOSFET source pin. Primary side circuit - It is the output of the error transconductance common ground connection. amplifier, and allows for the connection of a compensation network to provide the desired transfer function of the regulation loop. Its VDD Pin: bandwidth can be easily adjusted to the This pin provides two functions : needed value with usual components value. As stated above, secondary regulation - It corresponds to the low voltage supply of the configurations are also implemented through control part of the circuit. If V goes below 8V, the COMP pin. DD the start-up current source is activated and the output power MOSFET is switched off until the - When the COMP voltage is going below 0.5V, V voltage reaches 11V. During this phase, DD the shut-down of the circuit occurs, with a zero the internal current consumption is reduced, duty cycle for the power MOSFET. This feature the V pin is sourcing a current of about 2mA DD can be used to switch off the converter, and is and the COMP pin is shorted to ground. After automatically activated by the regulation loop that, the current source is shut down, and the (whatever is the configuration) to provide a device tries to start up by switching again. burst mode operation in case of negligible output power or open load condition. - This pin is also connected to the error amplifier, in order to allow primary as well as secondary OSC PIN: regulation configurations. In case of primary An R -C network must be connected on that pin to t t regulation, an internal 13V trimmed reference define the switching frequency. Note that despite voltage is used to maintain V at 13V. For DD the connection of R to V , no significant t DD secondary regulation, a voltage between 8.5V frequency change occurs for V varying from 8V DD and 12.5V will be put on V pin by transformer DD to 15V. It provides also a synchronisation design, in order to stuck the output of the capability, when connected to an external transconductance amplifier to the high state. frequency source. The COMP pin behaves as a constant current 3/23 1 VIPer100/SP - VIPer100A/ASP AVALANCHE CHARACTERISTICS Symbol Parameter Max Value Unit Avalanche Current, Repetitive or Not Repetitive (pulse widht limited by T max; δ < 1%) j I 2 A D(AR) for VIPer100/SP 1.4 A for VIPer100A/ASP (see fig.12) Single Pulse Avalanche Energy E 60 mJ (AR) (starting T =25ºC, I =I ) (see fig.12) j D D(ar) ELECTRICAL CHARACTERISTICS (T =25°C; V =13V, unless otherwise specified) j DD POWER SECTION Symbol Parameter Test Conditions Min Typ Max Unit I =1mA; V =0V D COMP BV Drain-Source Voltage for VIPer100/SP 620 V DSS for VIPer100A/ASP (see fig.5) 700 V V =0V; T =125°C COMP j I Off-State Drain Current V =620V for VIPer100/SP 1 mA DSS DS V =700V for VIPer100A/ASP DS 1 mA I =2A D 2.0 2.5 Ω for VIPer100/SP 2.3 2.8 Ω Static Drain-Source for VIPer100A/ASP R DS(on) On Resistance I =2A; T =100°C D j for VIPer100/SP 4.5 Ω for VIPer100A/ASP 5.0 Ω I =0.2A; V =300V (1) 100 ns D IN t Fall Time f (See fig. 3) I =0.4A; V =300V (1) 50 ns D IN t Rise Time r (See fig. 3) C Output Capacitance V =25V 150 pF oss DS (1) On Inductive Load, Clamped. SUPPLY SECTION Symbol Parameter Test Conditions Min Typ Max Unit -2 mA Start-Up Charging V =5V; VDS=35V DD I DDch Current (see fig. 2 and fig. 15) 12 16 mA Operating Supply Current V =12V; F =0kHz DD SW I DD0 (see fig. 2) I Operating Supply Current V =12V; F =100kHz 15.5 mA DD1 DD sw I Operating Supply Current V =12V; F =200kHz 19 mA DD2 DD sw V Undervoltage Shutdown (See fig. 2) 7.5 8 9 V DDoff V Undervoltage Reset (See fig. 2) 11 12 V DDon V Hysteresis Start-up (See fig. 2) 2.4 3 V DDhyst 4/23 VIPer100/SP - VIPer100A/ASP ELECTRICAL CHARACTERISTICS (continued) OSCILLATOR SECTION Symbol Parameter Test Conditions Min Typ Max Unit R =8.2KΩ; C =2.4nF T T 90 100 110 kHz Oscillator Frequency V =9 to 15V; DD F SW Total Variation with R ± 1%; C ± 5% T T (see fig. 6 and fig. 9) V Oscillator Peak Voltage 7.1 V OSCIH V Oscillator Valley Voltage 3.7 V OSCIL ERROR AMPLIFIER SECTION Symbol Parameter Test Conditions Min Typ Max Unit V V Regulation Point I =0mA (see fig. 1) 12.6 13 13.4 V DDREG DD COMP ΔV Total Variation T =0 to 100°C 2 % DDreg j 150 kHz From Input =V to Output = V DD COMP G Unity Gain Bandwidth BW COMP pin is open (see fig. 10) A Open Loop Voltage Gain COMP pin is open (see fig. 10) 45 52 dB VOL G DC Transconductance V =2.5V (see fig. 1) 1.1 1.5 1.9 mA/V m COMP V Output Low Level I =-400μA; V =14V 0.2 V COMPLO COMP DD V Output High Level I =400μA; V =12V 4.5 V COMPHI COMP DD Output Low Current I V =2.5V; V =14V -600 μA COMPLO COMP DD Capability Output High Current I V =2.5V; V =12V 600 μA COMPHI COMP DD Capability PWM COMPARATOR SECTION Symbol Parameter Test Conditions Min Typ Max Unit H ΔV / ΔI V =1 to 3 V 0.711.3 V/A ID COMP DPEAK COMP V V Offset I =10mA 0.5 V COMPoff COMP DPEAK I Peak Current Limitation V =12V; COMP pin open 3 4 5.3 A Dpeak DD Current Sense Delay to t I =1A 250 ns d D Turn-Off t Blanking Time 250 360 ns b t Minimum On Time 350 1200 ns on(min) SHUTDOWN AND OVERTEMPERATURE SECTION Symbol Parameter Test Conditions Min Typ Max Unit V Restart Threshold (see fig. 4) 0.5 V COMPth t Disable Set Up Time (see fig. 4) 1.7 5 μs DISsu Thermal Shutdown T (See fig. 8) 140 170 °C tsd Temperature Thermal Shutdown T (See fig. 8) 40 °C hyst Hysteresis 5/23 VIPer100/SP - VIPer100A/ASP Figure 1: V Regulation Point Figure 2: Undervoltage Lockout DD ICOMP IDD Slope = Gm in mA/V ICOMPHI IDD0 VDD VDS= 35 V VDDhyst 0 Fsw = 0 VDD VDDoff VDDon ICOMPLO IDDch VDDreg FC00150 FC00170 Figure 3: Transition Time Figure 4: Shut Down Action VOSC I D t VCOMP tDISsu 10% Ipeak t V DS VCOMPth t D 90% V ID 10% VD t t tf tr ENABLE ENABLE FC00160 DISABLE FC00060 Figure 5: Breakdown Voltage Vs. Temperature Figure 6: Typical Frequency Variation FC00180 FC00190 1.15 1 (%) BVDSS (Normalized) 0 1.1 -1 1.05 -2 -3 1 -4 -5 0.95 0 20406080 100120140 0 20406080 100 120 Temperature (°C) Temperature (°C) 6/23 VIPer100/SP - VIPer100A/ASP Figure 7: Start-Up Waveforms Figure 8: Overtemperature Protection T J T tsc T -T tsd hyst t V dd V ddon V ddoff t I d t V comp t SC10191 7/23 VIPer100/SP - VIPer100A/ASP Figure 9: Oscillator For R >1.2KΩ t VDD Rt and OSC C ≥ 15nF if F ≤ 40KHz t SW 2.3 550  -- --- --- --- - --- --- --- --- --- --- --- - CLK F= ⋅ 1 – SW  R C R – 150 t t t Ct FC00050 Ct Forbidden area 880 Ct(nF) = Fsw(kHz) 22nF 15nF Forbidden area 40kHz Fsw Oscillator frequency vs Rt and Ct F FC C00 0003 030 0 1,000 Ct = 1.5 nF 500 Ct = 2.7 nF 300 Ct = 4.7 nF 200 Ct = 10 nF 100 50 30 1 2 3 5 10 20 30 50 Rt (kΩ) 8/23 1 ~360Ω Frequency (kHz) VIPer100/SP - VIPer100A/ASP Figure 10: Error Amplifier Frequency Response FC00200 60 RCOMP = +∞ RCOMP = 270k 40 RCOMP = 82k RCOMP = 27k RCOMP = 12k 20 0 (20) 0.001 0.01 0.1 1 10 100 1,000 Frequency (kHz) Figure 11: Error Amplifier Phase Response FC00210 200 RCOMP = + ∞ RCOMP = 270k 150 RCOMP = 82k RCOMP = 27k 100 RCOMP = 12k 50 0 (50) 0.001 0.01 0.1 1 10 100 1,000 Frequency (kHz) 9/23 1 Phase (°) Voltage Gain (dB) VIPer100/SP - VIPer100A/ASP Figure 12: Avalanche Test Circuit L1 1mH 23 VDD DRAIN Q1 2 x STHV102FI in parallel - 1 R1 OSC 13V BT1 + 0 to 20V 47 COMP SOURCE GENERATOR INPUT 500us PULSE 54 C1 U1 BT2 VIPer100 47uF 12V 16V R2 R3 1k 100 FC00195 10/23 1 VIPer100/SP - VIPer100A/ASP Figure 13: Off Line Power Supply With Auxiliary Supply Feedback F1 BR1 TR2 C1 TR1 D2 L2 AC IN +Vcc D1 R9 C2 C7 C9 R1 C3 GND D3 C10 R7 C4 R2 VDD DRAIN - U1 OSC VIPer100 + 13V COMP SOURCE C5 C6 C11 R3 FC00081 Figure 14: Off Line Power Supply With Optocoupler Feedback F1 BR1 TR2 C1 TR1 D2 L2 AC IN +Vcc D1 R9 C2 C7 C9 R1 C3 GND D3 C10 R7 C4 R2 VDD DRAIN - U1 OSC VIPer100 13V + COMP SOURCE C5 C6 C11 R6 ISO1 R3 R4 C8 U2 R5 FC00091 11/23 1 VIPer100/SP - VIPer100A/ASP OPERATION DESCRIPTION: F is the normal switching frequency. SW I is the minimum controllable current, STBY corresponding to the minimum on time that the CURRENT MODE TOPOLOGY: device is able to provide in normal operation. This The current mode control method, like the one current can be computed as : integrated in the VIPer100/100A uses two control () t + tV loops - an inner current control loop and an outer b d IN - --- --- --- --- --- --- --- --- -- --- - - I = loop for voltage control. When the Power STBY L P MOSFET output transistor is on, the inductor current (primary side of the transformer) is t + t is the sum of the blanking time and of the b d monitored with a SenseFET technique and propagation time of the internal current sense and converted into a voltage V proportional to this comparator, and represents roughly the minimum S current. When V reaches V (the amplified S COMP on time of the device. Note that P may be STBY output voltage error) the power switch is switched affected by the efficiency of the converter at low off. Thus, the outer voltage control loop defines load, and must include the power drawn on the the level at which the inner loop regulates peak primary auxiliary voltage. current through the power switch and the primary As soon as the power goes below this limit, the winding of the transformer. auxiliary secondary voltage starts to increase Excellent open loop D.C. and dynamic line above the 13V regulation level forcing the output regulation is ensured due to the inherent input voltage of the transconductance amplifier to low voltage feedforward characteristic of the current state (V < V ). This situation leads to COMP COMPth mode control. This results in an improved line the shutdown mode where the power switch is regulation, instantaneous correction to line maintained in the off state, resulting in missing changes and better stability for the voltage cycles and zero duty cycle. As soon as V gets DD regulation loop. back to the regulation level and the V COMPth threshold is reached, the device operates again. Current mode topology also ensures good The above cycle repeats indefinitely, providing a limitation in the case of short circuit. During a first burst mode of which the effective duty cycle is phase the output current increases slowly much lower than the minimum one when in normal following the dynamic of the regulation loop. Then operation. The equivalent switching frequency is it reaches the maximum limitation current also lower than the normal one, leading to a internally set and finally stops because the power reduced consumption on the input mains lines. supply on V is no longer correct. For specific DD This mode of operation allows the VIPer100/100A applications the maximum peak current internally to meet the new German "Blue Angel" Norm with set can be overridden by externally limiting the less than 1W total power consumption for the voltage excursion on the COMP pin. An integrated system when working in stand-by. The output blanking filter inhibits the PWM comparator output voltage remains regulated around the normal for a short time after the integrated Power level, with a low frequency ripple corresponding to MOSFET is switched on. This function prevents the burst mode. The amplitude of this ripple is low, anomalous or premature termination of the because of the output capacitors and of the low switching pulse in the case of current spikes output current drawn in such conditions.The caused by primary side capacitance or secondary normal operation resumes automatically when the side rectifier reverse recovery time. power get back to higher levels than P . STBY STAND-BY MODE HIGH VOLTAGE START-UP CURRENT Stand-by operation in nearly open load condition SOURCE automatically leads to a burst mode operation An integrated high voltage current source provides allowing voltage regulation on the secondary side. a bias current from the DRAIN pin during the start- The transition from normal operation to burst up phase. This current is partially absorbed by mode operation happens for a power P given STBY internal control circuits which are placed into a by : standby mode with reduced consumption and also 1 2 provided to the external capacitor connected to the -- - P = L I F STBY STBY P SW 2 V pin. As soon as the voltage on this pin DD reaches the high voltage threshold V of the DDon Where: UVLO logic, the device turns into active mode and L is the primary inductance of the transformer. P starts switching. 12/23 VIPer100/SP - VIPer100A/ASP The start up current generator is switched off, and where: the converter should normally provide the needed I is the consumption current on the V pin DD DD current on the V pin through the auxiliary DD when switching. Refer to specified I and I 2 DD1 DD winding of the transformer, as shown on figure 15. values. In case of abnormal condition where the auxiliary t is the start up time of the converter when the SS winding is unable to provide the low voltage supply device begins to switch. Worst case is generally at current to the V pin (i.e. short circuit on the DD full load. output of the converter), the external capacitor V is the voltage hysteresis of the UVLO DDhyst discharges itself down to the low threshold voltage logic. Refer to the minimum specified value. V of the UVLO logic, and the device get back DDoff to the inactive state where the internal circuits are Soft start feature can be implemented on the in standby mode and the start up current source is COMP pin through a simple capacitor which will be activated. The converter enters a endless start up also used as the compensation network. In this cycle, with a start-up duty cycle defined by the case, the regulation loop bandwidth is rather low, ratio of charging current towards discharging when because of the large value of this capacitor. In the VIPer100/100A tries to start. This ratio is fixed case a large regulation loop bandwidth is by design to 2 to 15, which gives a 12% start up mandatory, the schematics of figure 16 can be duty cycle while the power dissipation at start up is used. It mixes a high performance compensation approximately 0.6 W, for a 230 Vrms input voltage. network together with a separate high value soft This low value of start-up duty cycle prevents the start capacitor. Both soft start time and regulation stress of the output rectifiers and of the loop bandwidth can be adjusted separately. transformer when in short circuit. If the device is intentionally shut down by putting The external capacitor C on the V pin must the COMP pin to ground, the device is also VDD DD be sized according to the time needed by the performing start-up cycles, and the V voltage is DD converter to start up, when the device starts oscillating between V and V . DDon DDoff switching. This time t depends on many SS This voltage can be used for supplying external parameters, among which transformer design, functions, provided that their consumption doesn’t output capacitors, soft start feature and exceed 0.5mA. Figure 17 shows a typical compensation network implemented on the COMP application of this function, with a latched shut pin. The following formula can be used for defining down. Once the "Shutdown" signal has been the minimum capacitor needed: activated, the device remains in the off state until I t the input voltage is removed. DD SS -- --- --- --- --- --- --- --- -- - C > VDD V DDhyst Figure 15: Behaviour of the high voltage current source at start-up 3 mA VDD 2 mA DRAIN VDD VDDon 1 mA 15 mA 15 mA VDDoff CVDD Ref. t UNDERVOLTAGE Auxiliary primary LOCK OUT LOGIC winding VIPer100 SOURCE Start up duty cycle ~ 12% FC00100 13/23 VIPer100/SP - VIPer100A/ASP TRANSCONDUCTANCE ERROR AMPLIFIER achieve different compensation laws. A capacitor will provide an integrator function, thus eliminating The VIPer100/100A includes a transconductance the DC static error, and a resistance in series error amplifier. Transconductance Gm is the leads to a flat gain at higher frequency, insuring a change in output current (I ) versus change in COMP correct phase margin. This configuration is input voltage (V ). Thus: DD illustrated on figure 18. ∂I COMP ------------------------ G = m ∂V As shown in figure 18 an additional noise filtering DD capacitor of 2.2 nF is generally needed to avoid The output impedance Z at the output of this COMP any high frequency interference. amplifier (COMP pin) can be defined as: It can be also interesting to implement a slope compensation when working in continuous mode ∂V ∂V COMP 1 COMP with duty cycle higher than 50%. Figure 19 shows --------------------------- --------- --------------------------- Z == × COMP ∂I G ∂V such a configuration. Note that R1 and C2 build COMP DD m the classical compensation network, and Q1 is injecting the slope compensation with the correct This last equation shows that the open loop gain polarity from the oscillator sawtooth. A can be related to G and Z : VOL m COMP A = G x Z VOL m COMP EXTERNAL CLOCK SYNCHRONIZATION: where G value for VIPer100/100A is 1.5 mA/V m The OSC pin provides a synchronisation typically. capability, when connected to an external G is well defined by specification, but Z and m COMP frequency source. Figure 20 shows one possible therefore A are subject to large tolerances. An VOL schematic to be adapted depending the specific impedance Z can be connected between the needs. If the proposed schematic is used, the COMP pin and ground in order to define more pulse duration must be kept at a low value (500ns accurately the transfer function F of the error is sufficient) for minimizing consumption. The amplifier, according to the following equation, very optocoupler must be able to provide 20mA through similar to the one above: the optotransistor. F = Gm x Z(S) (S) The error amplifier frequency response is reported PRIMARY PEAK CURRENT LIMITATION in figure 10 for different values of a simple The primary I current and, as resulting resistance connected on the COMP pin. The DPEAK effect, the output power can be limited using the unloaded transconductance error amplifier shows simple circuit shown in figure 21. The circuit based an internal Z of about 330 KΩ. More complex COMP on Q1, R and R clamps the voltage on the impedance can be connected on the COMP pin to 1 2 Figure 16: Mixed Soft Start and Compensation Figure 17: Latched Shut Down D2 U1 D3 VIPER100 U1 VDD DRAIN VIPER100 R1 - VDD DRAIN OSC R3 13V + Q2 - OSC COMP SOURCE 13V + D1 AUXILIARY COMP SOURCE WINDING R3 R2 C4 R1 R2 R4 + C3 +C2 C1 Shutdown D1 Q1 FC00131 FC00110 14/23 VIPer100/SP - VIPer100A/ASP COMP pin in order to limit the primary peak OVER-TEMPERATURE PROTECTION: current of the device to a value: Over-temperature protection is based on chip – temperature sensing. The minimum junction V 0.5 COMP - --- --- --- --- -- --- --- --- --- --- --- --- - I = temperature at which over-temperature cut-out DPEAK H occurs is 140ºC while the typical value is 170ºC. ID The device is automatically restarted when the where: junction temperature decreases to the restart temperature threshold that is typically 40ºC below R + R 1 2 V = 0.6 × --- --- --- --- --- --- --- - the shutdown value (see figure 8). COMP R 2 The suggested value for R +R is in the range of 1 2 220KΩ. Figure 18: Typical Compensation Network Figure 19: Slope Compensation U1 VIPER100 VDD DRAIN R2 R1 U1 VIPER100 - OSC VDD DRAIN 13V + - OSC COMP SOURCE 13V + COMP SOURCE C2 R1 C2 Q1 C3 C1 C1 R3 FC00141 FC00121 Figure 20: External Clock Sinchronisation Figure 21: Current Limitation Circuit Example U1 VIPER100 VDD DRAIN - U1 OSC VIPER100 13V + VDD DRAIN COM P SOURCE - OSC 13V + COMP SOURCE R1 10 kΩ Q1 R2 FC00220 FC00240 15/23 VIPer100/SP - VIPer100A/ASP Figure 22: Input Voltage Surges Protection D1 R1 (Optional) R2 39R Au xilliary winding DRAIN VDD C2 - C1 OSC Bulk capacitor + 22nF 13V COMP SOURCE VIPerXX0 ELECTRICAL OVER STRESS RUGGEDNESS The VIPer may be submitted to electrical over can overpass the V pin absolute maximum DD stress caused by violent input voltage surges or rating voltage value. Such events may trigger the lightning. Following the enclosed Layout V internal protection circuitry which could be DD Considerations chapter rules is the most of the damaged by the strong discharge current of the time sufficient to prevent catastrophic damages, V bulk capacitor. The simple RC filter shown in DD however in some cases the voltage surges figure 22 can be implemented to improve the coupled through the transformer auxiliary winding application immunity to such surges. 16/23 VIPer100/SP - VIPer100A/ASP Figure 23: Recommended Layout T1 D1 DU\GRQVHFR7 C7 D2DGORQGUILOLQJDWH R1 VDD DRAIN - C1 OSC C5 + 13V L COMP SOURCE ULGJHEGHVLRG U1 VIPerXX0 R2 C6 C2 C3 ISO1 C4 FC00500 LAYOUT CONSIDERATIONS - To use different tracks for low level signals and Some simple rules insure a correct running of power ones. The interferences due to a mixing switching power supplies. They may be classified of signal and power may result in instabilities into two categories: and/or anomalous behaviour of the device in - To minimise power loops: the way the switched case of violent power surge (Input overvoltages, power current must be carefully analysed and output short circuits...). the corresponding paths must present the In case of VIPer, these rules apply as shown on smallest inner loop area as possible. This figure 23. The loops C1-T1-U1, C5-D2-T1, C7-D1- avoids radiated EMC noises, conducted EMC T1 must be minimised. C6 must be as close as noises by magnetic coupling, and provides a possible from T1. The signal components C2, better efficiency by eliminating parasitic ISO1, C3 and C4 are using a dedicated track to be inductances, especially on secondary side. connected directly to the source of the device. 17/23 1 )URPQSXW VIPer100/SP - VIPer100A/ASP PowerSO-10™ MECHANICAL DATA mm. inch DIM. MIN. TYP MAX. MIN. TYP. MAX. A 3.35 3.65 0.132 0.144 A (*) 3.4 3.6 0.134 0.142 A1 0.00 0.10 0.000 0.004 B 0.40 0.60 0.016 0.024 B (*) 0.37 0.53 0.014 0.021 C 0.35 0.55 0.013 0.022 C (*) 0.23 0.32 0.009 0.0126 D 9.40 9.60 0.370 0.378 D1 7.40 7.60 0.291 0.300 E 9.30 9.50 0.366 0.374 E2 7.20 7.60 0.283 300 E2 (*) 7.30 7.50 0.287 0.295 E4 5.90 6.10 0.232 0.240 E4 (*) 5.90 6.30 0.232 0.248 e 1.27 0.050 F 1.25 1.35 0.049 0.053 F (*) 1.20 1.40 0.047 0.055 H 13.80 14.40 0.543 0.567 H (*) 13.85 14.35 0.545 0.565 h 0.50 0.002 L 1.20 1.80 0.047 0.070 L (*) 0.80 1.10 0.031 0.043 α 0º 8º 0º 8º α (*) 2º 8º 2º 8º (*) Muar only POA P013P B 0.10 A B 10 HE E2 E4 1 SEATING PLANE eB DETAIL "A" A C 0.25 D = = h D1 = = SEATING PLANE A F A1 A1 L DETAIL "A" P095A α 18/23 VIPer100/SP - VIPer100A/ASP PENTAWATT HV MECHANICAL DATA mm. inch DIM. MIN. TYP MAX. MIN. TYP. MAX. A 4.30 4.80 0.169 0.189 C 1.17 1.37 0.046 0.054 D 2.40 2.80 0.094 0.11 E 0.35 0.55 0.014 0.022 F 0.60 0.80 0.024 0.031 G1 4.91 5.21 0.193 0.205 G2 7.49 7.80 0.295 0.307 H1 9.30 9.70 0.366 0.382 H2 10.40 0.409 10.05 H3 10.40 0.396 0.409 L 15.60 17.30 6.14 0.681 L1 14.60 15.22 0.575 0.599 L2 21.20 21.85 0.835 0.860 L3 22.20 22.82 0.874 0.898 L5 2.60 3 0.102 0.118 L6 15.10 15.80 0.594 0.622 L7 6 6.60 0.236 0.260 M 2.50 3.10 0.098 0.122 M1 4.50 5.60 0.177 0.220 R 0.50 0.02 V4 90° (typ) Diam 3.65 3.85 0.144 0.152 P023H3 19/23 1 1 H2 A DIA H3 C H1 L5 L7 L6 L1 L L3 D V4 R E F Resin between leads M M1 G1 G2 VIPer100/SP - VIPer100A/ASP PENTAWATT HV 022Y (VERTICAL HIGH PITCH) MECHANICAL DATA mm. inch DIM. MIN. TYP MAX. MIN. TYP. MAX. A 4.30 4.80 0.169 0.189 C 1.17 1.37 0.046 0.054 D 2.40 2.80 0.094 0.110 E 0.35 0.55 0.014 0.022 F 0.60 0.80 0.024 0.031 G1 4.91 5.21 0.193 0.205 G2 7.49 7.80 0.295 0.307 H1 9.30 9.70 0.366 0.382 H2 10.40 0.409 H3 10.05 10.40 0.396 0.409 L 16.42 17.42 0.646 0.686 L1 14.60 15.22 0.575 0.599 L3 20.52 21.52 0.808 0.847 L5 2.60 3.00 0.102 0.118 L6 15.10 15.80 0.594 0.622 L7 6.00 6.60 0.236 0.260 M 2.50 3.10 0.098 0.122 M1 5.00 5.70 0.197 0.224 R 0.50 0.020 V4 90° 90° Diam. 3.70 3.90 0.146 0.154 20/23 1 VIPer100/SP - VIPer100A/ASP PowerSO-10™ SUGGESTED PAD LAYOUT TUBE SHIPMENT (no suffix) 14.6 - 14.9 CASABLANCA MUAR B 10.8 - 1 1 C 6.3 0 C A A 0.67 - 0.73 B 1 10 0.54 - 0.6 9 2 All dimensions are in mm. 3 8 9.5 7 4 1.27 Base Q.ty Bulk Q.ty Tube length (± 0.5) A B C (± 0.1) 5 6 Casablanca 50 1000 532 10.4 16.4 0.8 Muar 50 1000 532 4.9 17.2 0.8 TAPE AND REEL SHIPMENT (suffix “13TR”) REEL DIMENSIONS Base Q.ty 600 Bulk Q.ty 600 A (max) 330 B (min) 1.5 C (± 0.2) 13 F 20.2 G (+ 2 / -0) 24.4 N (min) 60 T (max) 30.4 All dimensions are in mm. TAPE DIMENSIONS According to Electronic Industries Association (EIA) Standard 481 rev. A, Feb. 1986 Tape width W 24 Tape Hole Spacing P0 (± 0.1) 4 Component Spacing P 24 Hole Diameter D (± 0.1/-0) 1.5 Hole Diameter D1 (min) 1.5 Hole Position F (± 0.05) 11.5 Compartment Depth K (max) 6.5 Hole Spacing P1 (± 0.1) 2 All dimensions are in mm. End Start Top No components Components No components cover 500mm min tape Empty components pockets 500mm min saled with cover tape. User direction of feed 21/23 1 1 VIPer100/SP - VIPer100A/ASP PENTAWATT HV TUBE SHIPMENT (no suffix) Base Q.ty 50 Bulk Q.ty 1000 B Tube length (± 0.5) 532 A 18 B 33.1 C (± 0.1) 1 C All dimensions are in mm. A 22/23 1 VIPer100/SP - VIPer100A/ASP Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may results from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a trademark of STMicroelectronics  2003 STMicroelectronics - Printed in ITALY- All Rights Reserved. STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A. http://www.st.com 23/23 1