4 Mbit LPC Firmware Flash SST49LF004B SST49LF004B4Mb LPC Firmware memory Data Sheet FEATURES: • SST49LF004B: 512K x8 (4 Mbit)Two Operational Modes Conforms to Intel LPC Interface Specification 1.1 – Low Pin Count (LPC) interface mode for in-system operation – Supports Single-Byte LPC Memory and – Parallel Programming (PP) mode for fast Firmware Memory Cycle Types production programming Flexible Erase Capability LPC Interface Mode – Uniform 4 KByte sectors – 5-signal LPC bus interface supporting byte Read – Uniform 64 KByte overlay blocks and Write – Chip-Erase for PP Mode Only – 33 MHz clock frequency operation Single 3.0-3.6V Read and Write Operations – WP# and TBL# pins provide hardware write Superior Reliability protect for entire chip and/or top Boot Block – Block Locking Registers for individual block – Endurance: 100,000 Cycles (typical) write-lock and lock-down protection – Greater than 100 years Data Retention – JEDEC Standard SDP Command Set Low Power Consumption – Data# Polling and Toggle Bit for End-of-Write – Active Read Current: 6 mA (typical) detection – Standby Current: 10 µA (typical) – 5 GPI pins for system design flexibility Fast Sector-Erase/Byte-Program Operation – 4 ID pins for multi-chip selection – Sector-Erase Time: 18 ms (typical)Parallel Programming (PP) Mode – Block-Erase Time: 18 ms (typical) – 11-pin multiplexed address and 8-pin data – Chip-Erase Time: 70 ms (typical) I/O interface – Byte-Program Time: 14 µs (typical) – Supports fast programming in-system on – Chip Rewrite Time: 8 seconds (typical) programmer equipment CMOS and PCI I/O Compatibility Packages Available – 32-lead PLCC – 40-lead TSOP (10mm x 20mm) PRODUCT DESCRIPTION The SST49LF004B flash memory device is designed to pared with alternative approaches. The SST49LF004B interface with host controllers (chipsets) that support a low- device significantly improves performance and reliability, pin-count (LPC) interface for BIOS applications. The while lowering power consumption. The SST49LF004B SST49LF004B device complies with Intel’s LPC Interface device writes (Program or Erase) with a single 3.0-3.6V Specification 1.1, supporting single-byte Firmware Memory power supply. and LPC Memory cycle types. The SST49LF004B provides a maximum Byte-Program The SST49LF004B is backward compatible to the time of 20 µsec. The entire memory can be erased and SST49LF00xA Firmware Hub and the SST49LF0x0A LPC programmed byte-by-byte in 8 seconds when using status Flash. In this document, FWH mode in the SST49LF00xA detection features such as Toggle Bit or Data# Polling to specification is referenced as the Firmware Memory Read/ indicate the completion of Program operation. To protect Write cycle and LPC mode in the SST49LF0x0A specifica- against inadvertent writes, the SST49LF004B device has tion is referenced as the LPC Memory Read/Write cycle. on-chip hardware and software write protection schemes. It Two interface modes are supported by the SST49LF004B: is offered with a typical endurance of 100,000 cycles. Data LPC mode (Firmware Memory and LPC Memory cycle retention is rated at greater than 100 years. types) for in-system operations and Parallel Programming The SST49LF004B uses less energy during Erase and (PP) mode to interface with programming equipment. Program than alternative flash memory technologies. The The SST49LF004B flash memory device is manufactured total energy consumed is a function of the applied voltage, with SST’s proprietary, high-performance SuperFlash tech- current and time of application. Since for any given voltage nology. The split-gate cell design and thick-oxide tunneling range the SuperFlash technology uses less current to pro- injector attain greater reliability and manufacturability com- ©2003 Silicon Storage Technology, Inc. The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc. S71232-02-000 12/03 Intel is a registered trademark of Intel Corporation. 1 These specifications are subject to change without notice. 4 Mbit LPC Firmware Flash SST49LF004B Data Sheet gram and has a shorter erase time, the total energy con- or hardware does not have to be calibrated or correlated to sumed during any Erase or Program operation is less than the cumulative number of Erase cycles as is necessary alternative flash memory technologies. with alternative flash memory technologies, whose Erase and Program times increase with accumulated Erase/Pro- The SuperFlash technology provides fixed Erase and Pro- gram cycles. gram times, independent of the number of Erase/Program cycles that have occurred. This means the system software TABLE OF CONTENTS PRODUCT DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 LIST OF FIGURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 LIST OF TABLES. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 FUNCTIONAL BLOCKS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 PIN ASSIGNMENTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 PIN DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Input/Output Communications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Input Communication Frame. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Interface Mode Select. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Identification Inputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 General Purpose Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Write Protect / Top Block Lock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Row / Column Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Output Enable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Write Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 No Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 DEVICE MEMORY MAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 DESIGN CONSIDERATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 PRODUCT IDENTIFICATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 MODE SELECTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 ©2003 Silicon Storage Technology, Inc. S71232-02-000 12/03 2 4 Mbit LPC Firmware Flash SST49LF004B Data Sheet LPC MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Device Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Firmware Memory Read Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Firmware Memory Write Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 LPC Memory Read Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 LPC Memory Write Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Abort Mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Response to Invalid Fields for Firmware Memory Cycle. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Response to Invalid Fields for LPC Memory Cycle. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Multiple Device Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Write Operation Status Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 PARALLEL PROGRAMMING MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Device Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Write Operation Status Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Data Protection (PP Mode). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 SOFTWARE COMMAND SEQUENCE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 ELECTRICAL SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 AC Characteristics (LPC Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 AC Characteristics (PP Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 PRODUCT ORDERING INFORMATION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 PACKAGING DIAGRAMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 ©2003 Silicon Storage Technology, Inc. S71232-02-000 12/03 3 4 Mbit LPC Firmware Flash SST49LF004B Data Sheet LIST OF FIGURES FIGURE 1: Pin Assignments for 32-lead PLCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 FIGURE 2: Pin Assignments for 40-lead TSOP (10mm x 20mm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 FIGURE 3: Device Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 FIGURE 4: Firmware Memory Read Cycle Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 FIGURE 5: Firmware Memory Write Cycle Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 FIGURE 6: LPC Memory Read Cycle Waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 FIGURE 7: LPC Memory Write Cycle Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 FIGURE 8: LCLK Waveform (LPC Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 FIGURE 9: Output Timing Parameters (LPC Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 FIGURE 10: Input Timing Parameters (LPC Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 FIGURE 11: Reset Timing Diagram (LPC Mode). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 FIGURE 12: Reset Timing Diagram (PP Mode). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 FIGURE 13: Read Cycle Timing Diagram (PP Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 FIGURE 14: Write Cycle Timing Diagram (PP Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 FIGURE 15: Data# Polling Timing Diagram (PP Mode). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 FIGURE 16: Toggle Bit Timing Diagram (PP Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 FIGURE 17: Byte-Program Timing Diagram (PP Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 FIGURE 18: Sector-Erase Timing Diagram (PP Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 FIGURE 19: Block-Erase Timing Diagram (PP Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 FIGURE 20: Chip-Erase Timing Diagram (PP Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 FIGURE 21: Software ID Entry and Read (PP Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 FIGURE 22: Software ID Exit (PP Mode). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 FIGURE 23: AC Input/Output Reference Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 FIGURE 24: A Test Load Example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 ©2003 Silicon Storage Technology, Inc. S71232-02-000 12/03 4 4 Mbit LPC Firmware Flash SST49LF004B Data Sheet LIST OF TABLES TABLE 1: Pin Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 TABLE 2: Product Identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 TABLE 3: Firmware and LPC Memory Cycles START Field Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 TABLE 4: Firmware Memory Read Cycle Field Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 TABLE 5: Firmware Memory Write Cycle. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 TABLE 6: LPC Memory Read Cycle Field Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 TABLE 7: LPC Memory Write Cycle Field Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 TABLE 8: Firmware Memory Multiple Device Selection Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 TABLE 9: LPC Memory Multiple Device Selection Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 TABLE 10: Block Locking Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 TABLE 11: Block Locking Register Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 TABLE 12: Operation Modes Selection (PP Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 TABLE 13: Software Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 TABLE 14: DC Operating Characteristics (All Interfaces) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 TABLE 15: Recommended System Power-up Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 TABLE 16: Pin Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 TABLE 17: Reliability Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 TABLE 18: Clock Timing Parameters (LPC Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 TABLE 19: Read/Write Cycle Timing Parameters (LPC Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 TABLE 20: AC Input/Output Specifications (LPC Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 TABLE 21: Interface Measurement Condition Parameters (LPC Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . 28 TABLE 22: Reset Timing Parameters (LPC Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 TABLE 23: Reset Timing Parameters (PP Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 TABLE 24: Read Cycle Timing Parameters (PP Mode). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 TABLE 25: Program/Erase Cycle Timing Parameters (PP Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 TABLE 26: Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 ©2003 Silicon Storage Technology, Inc. S71232-02-000 12/03 5 4 Mbit LPC Firmware Flash SST49LF004B Data Sheet FUNCTIONAL BLOCKS FUNCTIONAL BLOCK DIAGRAM TBL# WP# INIT# SuperFlash X-Decoder Memory LAD[3:0] LCLK FWH/LPC Address Buffers & Latches LFRAME# Interface Y-Decoder ID[3:0] GPI[4:0] R/C# I/O Buffers and Data Latches Control Logic A[10:0] Programmer DQ[7:0] Interface OE# WE# MODE RST# 1232 ILL B1.0 ©2003 Silicon Storage Technology, Inc. S71232-02-000 12/03 6 4 Mbit LPC Firmware Flash SST49LF004B Data Sheet PIN ASSIGNMENTS 4 3 2 1 32 31 30 A7(GPI1) 5 29 MODE (MODE) A6 (GPI0) 6 28 V (V ) SS SS 7 27 A5 (WP#) NC 8 26 A4 (TBL#) NC 32-lead PLCC A3 (ID3) 9 25 V (V ) DD DD Top View A2 (ID2) 10 24 OE# (INIT#) A1 (ID1) 11 23 WE# (LFRAME#) A0 (ID0) 12 22 NC DQ0 (LAD0) 13 21 DQ7 (RES) 14 15 16 17 18 19 20 1232 32-plcc P1.0 ( ) Designates LPC Mode FIGURE 1: PIN ASSIGNMENTS FOR 32-LEAD PLCC NC (NC) 1 40 V SS MODE (MODE) 2 39 V DD NC (NC) 3 38 (LFRAME#) WE# NC (NC) 4 37 (INIT#) OE# NC (NC) 5 36 (NC) NC NC (NC) 6 35 (RES) DQ7 A10 (GPI4) 7 34 (RES) DQ6 NC (NC) 8 33 (RES) DQ5 Standard Pinout R/C# (LCLK) 9 32 (RES) DQ4 V 10 31 (NC) NC DD Top View NC (NC) 11 30 V SS RST# (RST#) 12 29 V SS Die Up NC (NC) 13 28 (LAD3) DQ3 NC (NC) 14 27 (LAD2) DQ2 A9 (GPI3) 15 26 (LAD1) DQ1 16 25 A8 (GPI2) (LAD0) DQ0 17 24 A7 (GPI1) (ID0) A0 18 23 A6 (GPI0) (ID1) A1 19 22 (ID2) A2 A5 (WP#) 20 21 (ID3) A3 A4 (TBL#) 1232 40-tsop P2.0 ( ) Designates LPC Mode FIGURE 2: PIN ASSIGNMENTS FOR 40-LEAD TSOP (10MM X 20MM) ©2003 Silicon Storage Technology, Inc. S71232-02-000 12/03 7 DQ1 (LAD1) A8 (GPI2) DQ2 (LAD2) A9 (GPI3) V (V ) RST# (RST#) SS SS DQ3 (LAD3) NC DQ4 (RES) V (V ) DD DD R/C# (LCLK) DQ5 (RES) A10 (GPI4) DQ6 (RES) 4 Mbit LPC Firmware Flash SST49LF004B Data Sheet PIN DESCRIPTIONS TABLE 1: PIN DESCRIPTION Interface 1 Symbol Pin Name Type PP LPC Functions LCLK Clock I X To provide a clock input to the control unit LAD[3:0] Address and I/O X To provide LPC bus information such as addresses and command Data inputs/outputs data. LFRAME# Frame I X To indicate start of a data transfer operation; also used to abort an LPC cycle in progress. MODE Interface I X X This pin determines which interface is operational. When held high, program- Mode Select mer mode is enabled and when held low, LPC mode is enabled. This pin must be set at power-up or before returning from reset and must not change during device operation. This pin must be held high (V ) for PP mode and low (V ) IH IL for LPC mode. This pin is internally pulled-down with a resistor between 20- 100 KΩ. RST# Reset I X X To reset the operation of the device INIT# Initialize I X This is the second reset pin for in-system use. This pin functions identically to RST#. ID[3:0] Identification I X These four pins are part of the mechanism that allows multiple parts to be Inputs attached to the same bus. The strapping of these pins is used to identify the component. The boot device must have ID[3:0]=0000, all subsequent devices should use sequential count-up strapping. These pins are internally pulled-down with a resistor between 20-100 KΩ. GPI[4:0] General I X These individual inputs can be used for additional board flexibility. The state of Purpose Inputs these pins can be read through LPC registers. These inputs should be at their desired state before the start of the LPC clock cycle during which the read is attempted, and should remain in place until the end of the Read cycle. Unused GPI pins must not be floated. TBL# Top Block Lock I X When low, prevents programming to the boot block sectors at the top of the device memory. When TBL# is high it disables hardware write protection for the top block sectors. This pin cannot be left unconnected. WP# Write Protect I X When low, prevents programming to all but the highest addressable blocks. When WP# is high it disables hardware write protection for these blocks. This pin cannot be left unconnected. R/C# Row/Column I X Select for the Programming interface, this pin determines whether the Select address pins are pointing to the row addresses, or to the column addresses. -A Address I X Inputs for low-order addresses during Read and Write operations. Addresses A 10 0 are internally latched during a Write cycle. For the programming interface, these addresses are latched by R/C# and share the same pins as the high- order address inputs. DQ -DQ Data I/O X To output data during Read cycles and receive input data during Write cycles. 7 0 Data is internally latched during a Write cycle. The outputs are in tri-state when OE# is high. OE# Output Enable I X To gate the data output buffers. WE# Write Enable I X To control the Write operations. RES Reserved X These pins must be left unconnected. V Power Supply PWR X X To provide power supply (3.0-3.6V) DD V Ground PWR X X Circuit ground (0V reference) SS NC No Connection N/A N/A Unconnected pins. T1.0 1232 1. I = Input, O = Output ©2003 Silicon Storage Technology, Inc. S71232-02-000 12/03 8 4 Mbit LPC Firmware Flash SST49LF004B Data Sheet Clock General Purpose Inputs The LCLK pin accepts a clock input from the host controller. The General Purpose Inputs (GPI[4:0]) can be used as dig- ital inputs for the CPU to read. The GPI register holds the values on these pins. The data on the GPI pins must be Input/Output Communications stable before the start of a GPI register Read and remain The LAD[3:0] pins are used to serially communicate cycle stable until the Read cycle is complete. The pins must be information such as cycle type, cycle direction, ID selection, driven low, V , or high, V but not left unconnected (float). IL IH address, data, and sync fields. Write Protect / Top Block Lock Input Communication Frame The Top Boot Lock (TBL#) and Write Protect (WP#) pins The LFRAME# pin is used to indicate start of a LPC bus are provided for hardware write protection of device mem- cycle. The pin is also used to abort an LPC bus cycle in ory in the SST49LF004B. The TBL# pin is used to write pro- progress. tect 64 KByte at the highest memory address range for the SST49LF004B. WP# pin write protects the remaining sec- Interface Mode Select tors in the flash memory. An active low signal at the TBL# pin prevents Program and Erase operations of the top boot The MODE pin is used to set the interface mode. If the block. When TBL# pin is held high, the hardware write pro- mode pin is set to logic high, the device is in PP mode. If tection of the top boot block is disabled. The WP# pin the mode pin is set low, the device is in the LPC mode. The serves the same function for the remaining blocks of the mode selection pin must be configured prior to device oper- device memory. The TBL# and WP# pins write protection ation. The mode pin is internally pulled down if the pin is left functions operate independently of one another. Both TBL# unconnected. and WP# pins must be set to their required protection states prior to starting a Program or Erase operation. A logic level Reset change occurring at the TBL# or WP# pin during a Program A V on INIT# or RST# pin initiates a device reset. INIT# or Erase operation could cause unpredictable results. IL and RST# pins have the same function internally. It is required to drive INIT# or RST# pins low during a system Row / Column Select reset to ensure proper CPU initialization. During a Read The R/C# pin is used to control the multiplex address operation, driving INIT# or RST# pins low deselects the inputs in Parallel Programming (PP) mode. The column device and places the output drivers, LAD[3:0], in a high addresses are mapped to the higher internal addresses impedance state. The reset signal must be held low for a (A ), and the row addresses are mapped to the lower 18-11 minimum of time T . A reset latency occurs if a reset pro- RSTP internal address (A ). 10-0 cedure is performed during a Program or Erase operation. See Table 22 and Table 23, Reset Timing Parameters, for more information. A device reset during an active Program Output Enable or Erase operation will abort the operation and memory The OE# pin is used to gate the output data buffers in PP contents may become invalid due to data being altered or mode. corrupted from an incomplete Erase or Program operation. Write Enable Identification Inputs The WE# pin is used to control the write operations in PP These pins are part of a mechanism that allows multiple mode. devices to be attached to the same bus. The strapping of these pins is used to identify the component. The boot No Connection device must have ID[3:0] = 0; all subsequent devices should use sequential count-up strapping. These pins are These pins are not connected internally. internally pulled-down with a resistor between 20-100 KΩ. ©2003 Silicon Storage Technology, Inc. S71232-02-000 12/03 9 4 Mbit LPC Firmware Flash SST49LF004B Data Sheet DEVICE MEMORY MAP 7FFFFH Boot Block TBL# Block 7 70000H 6FFFFH Block 6 60000H 5FFFFH Block 5 50000H 4FFFFH Block 4 40000H 3FFFFH Block 3 WP# 30000H 2FFFFH Block 2 20000H 1FFFFH Block 1 10000H 4 KByte Sector 15 0F000H 0EFFFH Block 0 03000H (64 KByte) 4 KByte Sector 2 02000H 4 KByte Sector 1 01000H 4 KByte Sector 0 00000H 1232 F02.0 FIGURE 3: DEVICE MEMORY MAP DESIGN CONSIDERATIONS PRODUCT IDENTIFICATION SST recommends a high frequency 0.1 µF ceramic capac- The Product Identification mode identifies the device as the itor to be placed as close as possible between V and SST49LF004B and manufacturer as SST. DD V less than 1 cm away from the V pin of the device. SS DD Additionally, a low frequency 4.7 µF electrolytic capacitor TABLE 2: PRODUCT IDENTIFICATION from V to V should be placed within 1 cm of the V DD SS DD Address Data pin. If a socket is used for programming purposes, an addi- 1 PP Mode LPC Mode tional 1-10 µF should be added next to each socket. Manufacturer’s ID 0000H FFBC 0000H BFH The RST# and INIT# pins must remain stable at V for the IH Device ID entire duration of an Erase or Program operation. WP# 2 SST49LF004B 0001H FFBC 0001H 60H must remain stable at V for the entire duration of the IH T2.0 1232 Erase and Program operations for non-Boot Block sectors. 1. Address shown in this column is for boot device only. To write data to the top Boot Block sectors, the TBL# pin Address locations should appear elsewhere in the 4 must also remain stable at V for the entire duration of the GByte system memory map depending on ID strapping IH values on ID[3:0] pins when multiple LPC memory Erase and Program operations. devices are used in a system. 2. The device ID for SST49LF004B is the same as SST49LF004A. ©2003 Silicon Storage Technology, Inc. S71232-02-000 12/03 10 4 Mbit LPC Firmware Flash SST49LF004B Data Sheet MODE SELECTION LPC MODE The SST49LF004B flash memory device operates in two Device Operation distinct interface modes: the LPC mode and the Parallel Programming (PP) mode. In LPC mode, communication The LPC mode uses a 5-signal communication interface between the Host and the SST49LF004B occurs via the 4- consisting of one control line, LFRAME#, which is driven by bit I/O communication signals, LAD[3:0], and LFRAME#. In the host to start or abort a bus cycle, and a 4-bit data bus, PP mode, the device is controlled via the 11 addresses, LAD[3:0], which is used to communicate cycle type, cycle A -A , and 8 I/O, DQ -DQ , signals. The address inputs direction, ID selection, address, data and sync fields. The 10 0 7 0 are multiplexed in row and column selected by control sig- device enters standby mode when LFRAME# is high and nal R/C# pin. The row addresses are mapped to the lower no internal operation is in progress. internal addresses (A ), and the column addresses are 10-0 The SST49LF004B supports both single-byte Firmware mapped to the higher internal addresses (A ). See Fig- 18-11 Memory Read/Write cycles and single-byte LPC Memory ure 3, Device Memory Map, for address assignments. Read/Write cycles as defined in Intel’s Low-Pin-Count Interface Specification, Revision 1.1. The host drives LFRAME# low for one or more clock cycles to initiate an LPC cycle. The last latched value of LAD[3:0] before LFRAME# is the START value. The START value deter- mines whether the SST49LF004B will respond to a Firm- ware Memory Read/Write cycle or a LPC Memory Read/ Write cycle as defined in Table 3. TABLE 3: FIRMWARE AND LPC MEMORY CYCLES START FIELD DEFINITION START Value Definition 0000 Start of an LPC memory cycle. The direction (Read or Write) is determined by the second field of the LPC cycle. 1101 Start of a Firmware Memory Read cycle 1110 Start of a Firmware Memory Write cycle T3.0 1232 See following sections for details of Firmware Memory and LPC Memory cycle types. JEDEC standard SDP (Soft- ware Data Protection) Program and Erase command sequences are used to initiate Firmware and LPC Memory Program and Erase operations. See Table 12 for a listing of Program and Erase commands. Chip-Erase is only available in PP mode. ©2003 Silicon Storage Technology, Inc. S71232-02-000 12/03 11 4 Mbit LPC Firmware Flash SST49LF004B Data Sheet Firmware Memory Read Cycle TABLE 4: FIRMWARE MEMORY READ CYCLE FIELD DEFINITIONS Clock Field Field Contents LAD[3:0] 1 Cycle Name LAD[3:0] Direction Comments 1 START 1101 IN LFRAME# must be active (low) for the device to respond. Only the last field latched before LFRAME# transitions high will be recognized. The START field contents (1101b) indi- cate a Firmware Memory Read cycle. 2 IDSEL 0000 to 1111 IN Indicates which SST49LF004B device should respond. If the IDSEL (ID select) field matches the value of ID[3:0], the device will respond to the LPC bus cycle. 3-9 MADDR YYYY IN These seven clock cycles make up the 28-bit memory address. YYYY is one nibble of the entire address. Addresses are transferred most-significant nibble first. 10 MSIZE 0000 (1 Byte) IN The MSIZE field indicates how many bytes will be trans- ferred during multi-byte operations. The SST49LF004B only supports single-byte operation. MSIZE=0000b 11 TAR0 1111 IN then Float In this clock cycle, the master (Intel ICH) has driven the bus to all ‘1’s and then floats the bus, prior to the next clock cycle. This is the first part of the bus “turnaround cycle.” 12 TAR1 1111 (float) Float then The SST49LF004B takes control of the bus during this OUT cycle. 13 RSYNC 0000 (READY) OUT During this clock cycle, the device generates a “ready sync” (RSYNC) indicating that the device has received the input data. 14 DATA ZZZZ OUT ZZZZ is the least-significant nibble of the data byte. 15 DATA ZZZZ OUT ZZZZ is the most-significant nibble of the data byte. 16 TAR0 1111 OUT then In this clock cycle, the SST49LF004B drives the bus to all Float ones and then floats the bus prior to the next clock cycle. This is the first part of the bus “turnaround cycle.” 17 TAR1 1111 (float) Float then IN The host resumes control of the bus during this cycle. T4.0 1232 1. Field contents are valid on the rising edge of the present clock cycle. LCLK LFRAME# MSIZE TAR0 TAR1 RSYNC DATA Start IDSEL MADDR 1101b 0000b A[27:24] A[23:20] A[19:16] A[15:12] A[11:8] A[7:4] A[3:0] 0000b 1111b Tri-State 0000b D[3:0] D[7:4] TAR LAD[3:0] 1232 F03.0 FIGURE 4: FIRMWARE MEMORY READ CYCLE WAVEFORM ©2003 Silicon Storage Technology, Inc. S71232-02-000 12/03 12 4 Mbit LPC Firmware Flash SST49LF004B Data Sheet Firmware Memory Write Cycle TABLE 5: FIRMWARE MEMORY WRITE CYCLE Clock Field Field Contents LAD[3:0] 1 Cycle Name LAD[3:0] Direction Comments 1 START 1110 IN LFRAME# must be active (low) for the device to respond. Only the last field latched before LFRAME# transitions high will be recognized. The START field contents (1110b) indicate a Firmware Memory Write cycle. 2 IDSEL 0000 to 1111 IN Indicates which SST49LF004B device should respond. If the IDSEL (ID select) field matches the value of ID[3:0], the device will respond to the mem- ory cycle. 3-9 MADDR YYYY IN These seven clock cycles make up the 28-bit memory address. YYYY is one nibble of the entire address. Addresses are transferred most-significant nibble first. 10 MSIZE 0000 (1 Byte) IN The MSIZE field indicates how many bytes will be transferred during multi-byte operations. The device only supports single-byte writes. MSIZE=0000b 11 DATA ZZZZ IN ZZZZ is the least-significant nibble of the data byte. 12 DATA ZZZZ IN ZZZZ is the most-significant nibble of the data byte. 13 TAR0 1111 IN then Float In this clock cycle, the host drives the bus to all '1's and then floats the bus prior to the next clock cycle. This is the first part of the bus “turnaround cycle.” 14 TAR1 1111 (float) Float then OUT The SST49LF004B takes control of the bus during this cycle. 15 RSYNC 0000 OUT During this clock cycle, the device generates a “ready sync” (RSYNC) indicating that the device has received the input data. 16 TAR0 1111 OUT then Float In this clock cycle, the SST49LF004B drives the bus to all '1's and then floats the bus prior to the next clock cycle. This is the first part of the bus “turnaround cycle.” 17 TAR1 1111 (float) Float then IN The host resumes control of the bus during this cycle. T5.0 1232 1. Field contents are valid on the rising edge of the present clock cycle. LCLK LFRAME# Start IDSEL MADDR MSIZE DATA TAR0 TAR1 RSYNC 1110b 0000b A[27:24] A[23:20] A[19:16] A[15:12] A[11:8] A[7:4] A[3:0] 0000b D[3:0] D[7:4] 1111b Tri-State 0000b TAR LAD[3:0] 1232 F04.0 FIGURE 5: FIRMWARE MEMORY WRITE CYCLE WAVEFORM ©2003 Silicon Storage Technology, Inc. S71232-02-000 12/03 13 4 Mbit LPC Firmware Flash SST49LF004B Data Sheet LPC Memory Read Cycle TABLE 6: LPC MEMORY READ CYCLE FIELD DEFINITIONS Clock Field Field Contents LAD[3:0] 1 Cycle Name LAD[3:0] Direction Comments 1 START 0000 IN LFRAME# must be active (low) for the device to respond. Only the last field latched before LFRAME# transitions high will be recognized. The START field contents (0000b) indicate an LPC Memory cycle. 2 CYCTYPE 010X IN Indicates the type of LPC Memory cycle. Bits 3:2 must be “01b” for + DIR memory cycle. Bit 1 indicates the type of transfer “0” for Read. Bit 0 is reserved. 3-10 ADDR YYYY IN Address Phase for Memory Cycle. LPC protocol supports a 32- bit address phase. YYYY is one nibble of the entire address. Addresses are transferred most-significant nibble first. 11 TAR0 1111 IN In this clock cycle, the host drives the bus to all 1s and then then Float floats the bus. This is the first part of the bus “turnaround cycle.” 12 TAR1 1111 (float) Float The SST49LF004B takes control of the bus during this cycle. then OUT 13 SYNC 0000 OUT The SST49LF004B outputs the value 0000b indicating that it has received data. 14 DATA ZZZZ OUT ZZZZ is the least-significant nibble of the data byte. 15 DATA ZZZZ OUT ZZZZ is the most-significant nibble of the data byte. 16 TAR0 1111 IN In this clock cycle, the host drives the bus to all 1s and then then Float floats the bus. This is the first part of the bus “turnaround cycle.” 17 TAR1 1111 (float) Float The SST49LF004B takes control of the bus during this cycle. then OUT T6.0 1232 1. Field contents are valid on the rising edge of the present clock cycle. LCLK LFRAME# CYCTYPE + Start Address TAR0 TAR1 Sync Data DIR 0000b 010Xb A[19:16] A[15:12] A[11:8] A[7:4] A[3:0] 1111b Tri-State 0000b D[3:0] D[7:4] TAR A[31:28] A[27:24] A[23:20] LAD[3:0] 1 Clock 1 Clock Load Address in 8 Clocks 2 Clocks 1 Clock Data Out 2 Clocks 1232 F05.1 FIGURE 6: LPC MEMORY READ CYCLE WAVEFORM ©2003 Silicon Storage Technology, Inc. S71232-02-000 12/03 14 4 Mbit LPC Firmware Flash SST49LF004B Data Sheet LPC Memory Write Cycle TABLE 7: LPC MEMORY WRITE CYCLE FIELD DEFINITIONS Clock Field Field Contents LAD[3:0] 1 Cycle Name LAD[3:0] Direction Comments 1 START 0000 IN LFRAME# must be active (low) for the device to respond. Only the last field latched before LFRAME# transitions high will be recognized. The START field contents (0000b) indicate an LPC Memory cycle. 2 CYCTYPE + 011X IN Indicates the type of LPC Memory cycle. Bits 3:2 DIR must be “01b” for memory cycle. Bit 1 indicates the type of transfer “1” for Write. Bit 0 is reserved. 3-10 ADDR YYYY IN Address Phase for Memory Cycle. LPC protocol sup- ports a 32-bit address phase. YYYY is one nibble of the entire address. Addresses are transferred most significant nibble first. 11 DATA ZZZZ IN ZZZZ is the least-significant nibble of the data byte. 12 DATA ZZZZ IN ZZZZ is the most-significant nibble of the data byte. 13 TAR0 1111 IN In this clock cycle, the host drives the bus to all '1's and then floats the bus. This is the first part of the bus “turn- around cycle.” 14 TAR1 1111 (float) Float then OUT The SST49LF004B takes control of the bus during this cycle. 15 SYNC 0000 OUT The SST49LF004B outputs the values 0000, indicating that it has received data or a flash command. 16 TAR0 1111 OUT then Float In this clock cycle, the SST49LF004B drives the bus to all '1's and then floats the bus. This is the first part of the bus “turnaround cycle.” 17 TAR1 1111 (float) Float then IN Host resumes control of the bus during this cycle. T7.0 1232 1. Field contents are valid on the rising edge of the present clock cycle. LCLK LFRAME# CYCTYPE + Start Address Data Data TAR0 TAR1 Sync DIR TAR 0000b 011Xb A[31:28] A[27:24] A[23:20] A[19:16] A[15:12] A[11:8] A[7:4] A[3:0] D[3:0] D[7:4] 1111b Tri-State 0000b LAD[3:0] 1 Clock 1 Clock Load Address in 8 Clocks Load Data in 2 Clocks 2 Clocks 1 Clock 1232 F06.1 FIGURE 7: LPC MEMORY WRITE CYCLE WAVEFORM ©2003 Silicon Storage Technology, Inc. S71232-02-000 12/03 15 4 Mbit LPC Firmware Flash SST49LF004B Data Sheet Abort Mechanism Response to Invalid Fields for LPC Memory Cycle If LFRAME# is driven low for one or more clock cycles after the start of a bus cycle, the cycle will be terminated. The ID mismatch: ID information is included in the address bits host may drive LAD[3:0] with '1111b' (ABORT nibble) to of every LPC Memory cycle. Address bits A , A :A are 23 21 19 return the interface to ready mode. The ABORT only used to select the device with proper IDs. The affects the current bus cycle. For a multi-cycle command SST49LF004B will compare the ID bits in the address field sequence, such as the Erase or Program SDP commands, with ID[3:0]. If the ID bits in the address do not correspond ABORT doesn't interrupt the entire command sequence, to the hardware ID pins the device will ignore the cycle. See only the current bus cycle of the command sequence. The Multiple Device Selection section for details. host can re-send the bus cycle for the aborted command Address out of range: The address sequence is 8 fields and continue the SDP command sequence after the device long (32 bits). Address bits A , A :A are used to select 23 21 19 is ready again. the device with proper IDs. The SST49LF004B responds to address range FFFFFFFFH to FF800000H and Response to Invalid Fields for Firmware 000FFFFFH to 000E0000H during LPC memory cycle Memory Cycle transfers. Address A has the special function of directing 22 reads and writes to the flash core (A =1) or to the register The SST49LF004B will not explicitly indicate that it has 22 space (A =0). received invalid field sequences. The response to specific 22 invalid fields or sequences is as follows: Once valid START, CYCTYPE + DIR, and address range (including ID bits) are received, the SST49LF004B will ID mismatch: If the IDSEL field does not match ID[3:0], always complete the bus cycle. However, if the device is the device will ignore the cycle. See Multiple Device Selec- busy performing a flash Erase or Program operation, no tion section for details. new internal Write command (memory Write or register Write) will be executed. As long as the states of LAD[3:0] Address out of range: The address sequence is 7 and LFRAME# are known, the response of the fields long (28 bits) for Firmware Memory bus cycles, but SST49LF004B to signals received during the LPC cycle only A and A :A will be decoded by SST49LF004B. 22 18 0 should be predictable. Address A has the special function of directing reads and 22 writes to the flash core (A =1) or to the register space 22 (A =0). 22 Invalid MSIZE field: If the device receives an invalid MSIZE field during a Firmware Memory Read or Write cycle, the device will reset and no operation will be attempted. The SST49LF004B will not generate any kind of response in this situation. Invalid size fields for a Firm- ware Memory cycle are any data other than 0000b. Once valid START, IDSEL, and MSIZE fields are received, the SST49LF004B will always complete the bus cycle. However, if the device is busy performing a flash Erase or Program operation, no new Write command (memory write or register write) will be executed. ©2003 Silicon Storage Technology, Inc. S71232-02-000 12/03 16 4 Mbit LPC Firmware Flash SST49LF004B Data Sheet Multiple Device Selection for LPC Memory Cycle Multiple Device Selection For LPC Memory Read/Write cycles, ID information is Multiple LPC flash devices may be strapped to increase included in the address bits of every cycle. The ID bits in memory densities in a system. The four ID pins, ID[3:0], the address field are the inverse of the hardware strapping. allow up to 16 devices to be attached to the same bus by The address bits (A , A :A ) are used to select the using different ID strapping in a system. BIOS support, bus 23 21 19 device with proper IDs. See Table 9 for multiple device loading, or the attaching bridge may limit this number. The selection configurations. The SST49LF004B will compare boot device must have an ID of 0000b (determined by these bits with ID[3:0]’s strapping values. If there is a mis- ID[3:0]); subsequent devices use incremental numbering. match, the device will ignore the remainder of the cycle. Equal density must be used with multiple devices. Multiple Device Selection for TABLE 9: LPC MEMORY MULTIPLE DEVICE Firmware Memory Cycle SELECTION CONFIGURATION For Firmware Memory Read/Write cycles, hardware strap- Device # ID[3:0] A A :A 23, 21 19 ping values on ID[3:0] must match the values in IDSEL 0 (Boot device) 0000 1111 field. See Table 8 for multiple device selection configura- 1 0001 1110 tions. The SST49LF004B will compare the IDSEL field with 2 0010 1101 ID[3:0]'s strapping values. If there is a mismatch, the device 3 0011 1100 will ignore the reminder of the cycle. 4 0100 1011 5 0101 1010 TABLE 8: FIRMWARE MEMORY MULTIPLE DEVICE SELECTION CONFIGURATION 6 0110 1001 7 0111 1000 Device # ID[3:0] IDSEL 8 1000 0111 0 (Boot device) 0000 0000 9 1001 0110 1 0001 0001 10 1010 0101 2 0010 0010 11 1011 0100 3 0011 0011 12 1100 0011 4 0100 0100 13 1101 0010 5 0101 0101 14 1110 0001 6 0110 0110 15 1111 0000 7 0111 0111 T9.0 1232 8 1000 1000 9 1001 1001 10 1010 1010 11 1011 1011 12 1100 1100 13 1101 1101 14 1110 1110 15 1111 1111 T8.0 1232 ©2003 Silicon Storage Technology, Inc. S71232-02-000 12/03 17 4 Mbit LPC Firmware Flash SST49LF004B Data Sheet isters appear at their respective address location in the 4 Write Operation Status Detection GByte system memory map. Unused register locations will The SST49LF004B device provides two software means to read as 00H. Any attempt to read or write any register dur- detect the completion of a Write (Program or Erase) cycle, ing an internal Write operation will be ignored. in order to optimize the system Write cycle time. The soft- ware detection includes two status bits: Data# Polling, D[7], General Purpose Inputs Register and Toggle Bit, D[6]. The End-of-Write detection mode is The GPI_REG (General Purpose Inputs Register) passes incorporated into the Firmware Memory and LPC Memory the state of GPI[4:0] to the outputs. It is recommended that Read cycles. The actual completion of the nonvolatile write the GPI[4:0] pins are in the desired state before LFRAME# is asynchronous with the system. Therefore, either a Data# is brought low for the beginning of the bus cycle, and remain Polling or Toggle Bit read may be simultaneous with the in that state until the end of the cycle. There is no default completion of the Write cycle. If this occurs, the system value since this is a pass-through register. The GPI register may possibly get an erroneous result, i.e., valid data may for the boot device appears at FFBC0100H in the 4 GByte appear to conflict with either D[7] or D[6]. In order to prevent system memory map, and will appear elsewhere if the spurious rejection, if an erroneous result occurs, the soft- device is not the boot device. The register is not available to ware routine should include a loop to read the accessed be read when the device is in Erase/Program operation. location an additional two (2) times. If both reads are valid, then the device has completed the Write cycle, otherwise Block Locking Registers the rejection is valid. SST49LF004B provides software controlled lock protection Data# Polling through a set of Block Locking registers. The Block Locking registers are Read/Write registers and are accessible When the SST49LF004B device is in the internal Program through standard addressable memory locations specified operation, any attempt to read D[7] will produce the com- in Table 10 and Table 11. Unused register locations will plement of the true data. Once the Program operation is read as 00H. completed, D[7] will produce true data. Note that even though D[7] may have valid data immediately following the Write Lock: The Write-Lock bit, bit 0, controls the lock completion of an internal Write operation, the remaining state. The default Write status of all blocks after power up is data outputs may still be invalid. Valid data will appear on write locked. When bit 0 of the Block Locking register is set, the entire data bus in subsequent successive Read cycles Program and Erase operations for the corresponding block after an interval of 1 µs. During an internal Erase operation, are prevented. Clearing the Write-Lock bit will unprotect the any attempt to read D[7] will produce a '0'. Once the inter- block. The Write-Lock bit must be cleared prior to starting a nal Erase operation is completed, D[7] will produce a '1'. Program or Erase operation since it is sampled at the Proper status will not be given using Data# Polling if the beginning of the operation. The Write-Lock bit functions in address is in the invalid range. conjunction with the hardware Write Lock pin TBL# for the top Boot Block. When TBL# is low, it overrides the software Toggle Bit locking scheme. The top Boot Block Locking register does During the internal Program or Erase operation, any consec- not indicate the state of the TBL# pin. The Write-Lock bit utive attempts to read D[6] will produce alternating 0s and functions in conjunction with the hardware WP# pin for 1s, i.e., toggling between 0 and 1. When the internal Pro- blocks 0 to 6. When WP# is low, it overrides the software gram or Erase operation is completed, the toggling will stop. locking scheme. The Block Locking registers do not indi- Note that even though D[6] may have valid data immediately cate the state of the WP# pin. following the completion of an internal Write operation, the remaining data outputs may still be invalid. Valid data will Lock Down: The Lock-Down bit, bit 1, controls the Block appear on the entire data bus in subsequent successive Locking registers. The default Lock Down status of all Read cycles after an interval of 1 µs. Proper status will not be blocks upon power-up is not locked down. Once the Lock- given using Toggle Bit if the address is in the invalid range. Down bit is set, any future attempted changes to that Block Locking register will be ignored. The Lock-Down bit is only Registers cleared upon a device reset with RST# or INIT# or power down. Current Lock Down status of a particular block can There are three types of registers available on the be determined by reading the corresponding Lock-Down SST49LF004B, the General Purpose Inputs register, Block bit. Locking registers, and the JEDEC ID registers. These reg- ©2003 Silicon Storage Technology, Inc. S71232-02-000 12/03 18 4 Mbit LPC Firmware Flash SST49LF004B Data Sheet TABLE 10: BLOCK LOCKING REGISTERS Protected Memory Memory Map Register Block Size Address Package Register Address T_BLOCK_LK 64K 07FFFFH - 070000H FFBF0002H T_MINUS01_LK 64K 06FFFFH - 060000H FFBE0002H T_MINUS02_LK 64K 05FFFFH - 050000H FFBD0002H T_MINUS03_LK 64K 04FFFFH - 040000H FFBC0002H T_MINUS04_LK 64K 03FFFFH - 030000H FFBB0002H T_MINUS05_LK 64K 02FFFFH - 020000H FFBA0002H T_MINUS06_LK 64K 01FFFFH - 010000H FFB90002H T_MINUS07_LK 64K 00FFFFH - 000000H FFB80002H T10.0 1232 TABLE 11: BLOCK LOCKING REGISTER BITS Reserved Bit [7..2] Lock-Down Bit [1] Write-Lock Bit [0] Lock Status 000000 0 0 Full Access 000000 0 1 Write Locked (Default State at Power-Up) 000000 1 0 Locked Open (Full Access Locked Down) 000000 1 1 Write Locked Down T11.0 1232 JEDEC ID Registers The JEDEC ID registers provide access to the manufac- turer and device ID information with a single Read cycle. The JEDEC ID registers for the boot device appear at FFBC0000H and FFBC0001H in the 4 GByte system memory map, and will appear elsewhere if the device is not the boot device. Registers are not available for read when the device is in Erase/Program operation. Refer to Table 2 for product identification information. ©2003 Silicon Storage Technology, Inc. S71232-02-000 12/03 19 4 Mbit LPC Firmware Flash SST49LF004B Data Sheet PARALLEL PROGRAMMING MODE Block-Erase Operation Device Operation The Block-Erase Operation allows the system to erase any Commands are used to initiate the memory operation func- of the 8 uniform 64 KByte blocks. The Block- Erase opera- tions of the device. The data portion of the software com- tion is initiated by executing a six-byte command load mand sequence is latched on the rising edge of WE#. sequence for Software Data Protection with Block-Erase During the software command sequence the row address command (50H) and block address (BA) in the last bus is latched on the falling edge of R/C# and the column cycle. The internal Block-Erase operation begins after the address is latched on the rising edge of R/C#. sixth WE# pulse. The End-of-Erase can be determined using either Data# Polling or Toggle Bit methods. See Fig- Read ure 19 for timing waveforms. Any commands written during The Read operation of the SST49LF004B device is con- the Block- Erase operation will be ignored. trolled by OE#. OE# is the output control and is used to gate data from the output pins. Refer to the Read cycle tim- Chip-Erase Operation ing diagram, Figure 13, for further details. The SST49LF004B device provides a Chip-Erase opera- tion only in PP mode, which allows the user to erase the Reset entire memory array to the '1's state. This is useful when A V on RST# pin initiates a device reset. IL the entire device must be quickly erased. The Chip-Erase operation is initiated by executing a six- byte Software Data Byte-Program Operation Protection command sequence with Chip- Erase com- The SST49LF004B device is programmed on a byte-by- mand (10H) with address 5555H in the last bus cycle. The byte basis. Before programming, one must ensure that the internal Erase operation begins with the rising edge of the byte that is being programmed is fully erased. The Byte- sixth WE#. During the internal Erase operation, the only Program operation is initiated by executing a four-byte com- valid reads are Toggle Bit or Data# Polling. See Table 13 for mand load sequence for Software Data Protection with the command sequence, Figure 20 for timing diagram. Any address (PA) and data in the last bus cycle. During the commands written during the Chip-Erase operation will be Byte-Program operation, the row address (A -A ) is 10 0 ignored. latched on the falling edge of R/C# and the column Address (A -A ) is latched on the rising edge of R/C#. 21 11 Write Operation Status Detection The data bus is latched on the rising edge of WE#. The The SST49LF004B device provides two software means to Program operation, once initiated, will be completed, within detect the completion of a Write (Program or Erase) cycle, 20 µs. See Figure 17 for timing waveforms. During the Pro- in order to optimize the system Write cycle time. The soft- gram operation, the only valid reads are Data# Polling and ware detection includes two status bits: Data# Polling Toggle Bit. During the internal Program operation, the host (DQ ) and Toggle Bit (DQ ). The End-of-Write detection is free to perform additional tasks. Any commands written 7 6 mode is enabled after the rising edge of WE# which ini- during the internal Program operation will be ignored. tiates the internal Program or Erase operation. Sector-Erase Operation The actual completion of the nonvolatile write is asynchro- The Sector-Erase operation allows the system to erase the nous with the system; therefore, either a Data# Polling or device on a sector-by-sector basis. The sector architecture Toggle Bit read may be simultaneous with the completion is based on uniform sector size of 4 KByte. The Sector- of the Write cycle. If this occurs, the system may possibly Erase operation is initiated by executing a six-byte com- get an erroneous result, i.e., valid data may appear to con- mand load sequence for Software Data Protection with flict with either DQ or DQ . In order to prevent spurious 7 6 Sector-Erase command (30H) and sector address (SA) in rejection, if an erroneous result occurs, the software routine the last bus cycle. The internal Erase operation begins after should include a loop to read the accessed location an the sixth WE# pulse. The End-of-Erase can be determined additional two (2) times. If both reads are valid, the device using either Data# Polling or Toggle Bit methods. See Fig- has completed the Write cycle, otherwise the rejection is ure 18 for Sector-Erase timing waveforms. Any commands valid. written during the Sector-Erase operation will be ignored. ©2003 Silicon Storage Technology, Inc. S71232-02-000 12/03 20 4 Mbit LPC Firmware Flash SST49LF004B Data Sheet TABLE 12: OPERATION MODES SELECTION (PP MODE) Mode RST# OE# WE# DQ Address Read V V V D A IH IL IH OUT IN Program V V V D A IH IH IL IN IN 1 Erase V V V X Sector or Block address, IH IH IL XXH for Chip-Erase Reset V XX High Z X IL Write Inhibit V V V High Z/D X IH IL IH OUT Product Identification V V V Manufacturer’s ID (BFH) A - A = V , A = V IH IL IH 18 1 IL 0 IL Device ID (60H) A - A = V , A = V 18 1 IL 0 IH T12.0 1232 1. X can be V or V , but no other value. IL IH Data# Polling (DQ ) 7 Data Protection (PP Mode) When the SST49LF004B device is in the internal Program The SST49LF004B device provides both hardware and operation, any attempt to read DQ will produce the com- 7 software features to protect nonvolatile data from inadvert- plement of the true data. Once the Program operation is ent writes. completed, DQ will produce true data. Note that even 7 though DQ may have valid data immediately following the 7 Hardware Data Protection completion of an internal Write operation, the remaining Noise/Glitch Protection: A WE# pulse of less than 5 ns will data outputs may still be invalid. Valid data will appear on not initiate a Write cycle. the entire data bus in subsequent successive Read cycles after an interval of 1 µs. During an internal Erase operation, V Power Up/Down Detection: The Write operation is DD any attempt to read DQ will produce a '0'. Once the inter- inhibited when V is less than 1.5V. 7 DD nal Erase operation is completed, DQ will produce a '1'. 7 Write Inhibit Mode: Forcing OE# low, WE# high will inhibit Data# Polling is valid after the rising edge of the fourth WE# the Write operation. This prevents inadvertent writes during pulse for the Program operation. For Sector-Erase, Block- power-up or power-down. Erase, or Chip-Erase, the Data# Polling is valid after the ris- ing edge of the sixth WE# pulse. See Figure 15 for Data# Software Data Protection (SDP) Polling timing diagram. Proper status will not be given using The SST49LF004B provides the JEDEC approved Soft- Data# Polling if the address is in the invalid range. ware Data Protection scheme for all data alteration opera- tion, i.e., Program and Erase. Any Program operation Toggle Bit (DQ ) 6 requires the inclusion of a series of three-byte sequence. During the internal Program or Erase operation, any con- The three-byte load sequence is used to initiate the Pro- secutive attempts to read DQ will produce alternating '0's 6 gram operation, providing optimal protection from inadvert- and '1's, i.e., toggling between 0 and 1. When the internal ent Write operations, e.g., during the system power-up or Program or Erase operation is completed, the toggling will power down. Any Erase operation requires the inclusion of stop. The device is then ready for the next operation. The a five-byte load sequence. Toggle Bit is valid after the rising edge of the fourth WE# pulse for Program operation. For Sector-Erase, Block- Erase or Chip-Erase, the Toggle Bit is valid after the rising edge of the sixth WE# pulse. See Figure 16 for Toggle Bit timing diagram. ©2003 Silicon Storage Technology, Inc. S71232-02-000 12/03 21 4 Mbit LPC Firmware Flash SST49LF004B Data Sheet SOFTWARE COMMAND SEQUENCE TABLE 13: SOFTWARE COMMAND SEQUENCE 1 1 1 1 1 1 1st 2nd 3rd 4th 5th 6th Cycle Cycle Cycle Cycle Cycle Cycle Command 2 2 2 2 2 2 Sequence Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data 3 YYYY 5555H AAH YYYY 2AAAH 55H YYYY 5555H A0H PA Data Byte-Program 4 YYYY 5555H AAH YYYY 2AAAH 55H YYYY 5555H 80H YYYY 5555H AAH YYYY 2AAAH 55H SAX 30H Sector-Erase 5 YYYY 5555H AAH YYYY 2AAAH 55H YYYY 5555H 80H YYYY 5555H AAH YYYY 2AAAH 55H BA 50H X Block-Erase 6 YYYY 5555H AAH YYYY 2AAAH 55H YYYY 5555H 80H YYYY 5555H AAH YYYY 2AAAH 55H YYYY 5555H 10H Chip-Erase 7 YYYY 5555H AAH YYYY 2AAAH 55H YYYY 5555H 90H Read ID Software ID Entry XXXX XXXXH F0H Software 8 ID Exit YYYY 5555H AAH YYYY 2AAAH 55H YYYY 5555H F0H Software 8 ID Exit T13.0 1232 1. LPC mode use consecutive Write cycles to complete a command sequence; PP mode use consecutive bus cycles to complete a command sequence. 2. YYYY = A[31:16]. In LPC mode, during SDP command sequence, YYYY must be within valid memory address range, see Address out of range section for details. In PP mode, YYYY can be V or V , but no other value. IL IH 3. PA = Program Byte address 4. SA for Sector-Erase Address X 5. BA for Block-Erase Address X 6. Chip-Erase is supported in PP mode only 7. SST Manufacturer’s ID = BFH, is read with A -A = 0. 18 0 SST49LF004B Device ID = 60H, is read with A -A = 0, A = 1. 18 1 0 8. Both Software ID Exit operations are equivalent ©2003 Silicon Storage Technology, Inc. S71232-02-000 12/03 22 4 Mbit LPC Firmware Flash SST49LF004B Data Sheet ELECTRICAL SPECIFICATIONS The AC and DC specifications for the LPC interface signals (LA0[3:0], LFRAME, LCLCK and RST#) are defined in Sec- tion 4.2.2.4 of the PCI local bus specification, Rev. 2.1. Refer to Table 14 for the DC voltage and current specifications. Refer to Tables 18 through 24 for the AC timing specifications for Clock, Read, Write, and Reset operations. Absolute Maximum Stress Ratings (Applied conditions greater than those listed under “Absolute Maximum Stress Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these conditions or conditions greater than those defined in the operational sections of this data sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.) Temperature Under Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55°C to +125°C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C D.C. Voltage on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to V +0.5V DD Transient Voltage (<20 ns) on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -2.0V to V +2.0V DD Package Power Dissipation Capability (Ta=25°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0W Surface Mount Lead Soldering Temperature (3 Seconds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240°C 1 Output Short Circuit Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA 1. Outputs shorted for no more than one second. No more than one output shorted at a time. OPERATING RANGE Range Ambient Temp V DD Commercial 0°C to +85°C 3.0-3.6V AC CONDITIONS OF TEST Input Rise/Fall Time . . . . . . . . . . . . . . . 3 ns Output Load . . . . . . . . . . . . . . . . . . . . . C = 30 pF L See Figures 23 and 24 ©2003 Silicon Storage Technology, Inc. S71232-02-000 12/03 23 4 Mbit LPC Firmware Flash SST49LF004B Data Sheet DC Characteristics TABLE 14: DC OPERATING CHARACTERISTICS (ALL INTERFACES) Limits Symbol Parameter Min Max Units Test Conditions 1 I Active V Current LCLK (LPC mode) and Address Input (PP mode)=V /V DD DD ILT IHT at f=33 MHz (LPC mode) or 1/ (PP mode) TRC min All other inputs=V or V IL IH Read 12 mA All outputs = open, V =V Max DD DD 2 Write 30 mA See Note 2 I Standby V Current 100µA LCLK (LPC mode) and Address Input (PP mode)=V /V SB DD ILT IHT at f=33 MHz (LPC mode) or 1/ (PP mode) (LPC Interface) TRC min LFRAME#=0.9 V , f=33 MHz, CE#=0.9 V , DD DD V =V Max, All other inputs ≥ 0.9 V or ≤ 0.1 V DD DD DD DD 3 I Input Current for Mode 10 mA LCLK (LPC mode) and Address Input (PP mode)=V /V RY ILT IHT and at f=33 MHz (LPC mode) or 1/ (PP mode) TRC min ID[3:0] pins LFRAME#=V , f=33 MHz, V =V Max IL DD DD All other inputs ≥ 0.9 V or ≤ 0.1 V DD DD I Input Leakage Current for 200µA V =GND to V , V =V Max I IN DD DD DD Mode and ID[3:0] pins I Input Leakage Current 1µA V =GND to V , V =V Max LI IN DD DD DD I Output Leakage Current 1µA V =GND to V , V =V Max LO OUT DD DD DD V INIT# Input High Voltage 1.1 V +0.5 V V =V Max IHI DD DD DD V INIT# Input Low Voltage -0.5 0.4 V V =V Min ILI DD DD V Input Low Voltage -0.5 0.3 V VV =V Min IL DD DD DD V Input High Voltage 0.5 V V +0.5 V V =V Max IH DD DD DD DD V Output Low Voltage 0.1 V V OL DD V Output High Voltage 0.9 V V OH DD T14.2 1232 1. I active while a Read or Write (Program or Erase) operation is in progress. DD 2. For PP mode: OE# = WE# = V ; For LPC mode: f = 1/T min, LFRAME# = V . IH RC IH 3. The device is in Ready mode when no activity is on the LPC bus. TABLE 15: RECOMMENDED SYSTEM POWER-UP TIMINGS Symbol Parameter Minimum Units 1 T Power-up to Read Operation 100µs PU-READ 1 T Power-up to Write Operation 100µs PU-WRITE T15.0 1232 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter TABLE 16: PIN CAPACITANCE (V =3.3V, Ta=25 °C, f=1 Mhz, other pins open) DD Parameter Description Test Condition Maximum 1 C I/O Pin Capacitance V =0V 12 pF I/O I/O 1 C Input Capacitance V =0V 12 pF IN IN T16.0 1232 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. ©2003 Silicon Storage Technology, Inc. S71232-02-000 12/03 24 4 Mbit LPC Firmware Flash SST49LF004B Data Sheet TABLE 17: RELIABILITY CHARACTERISTICS Minimum Symbol Parameter Specification Units Test Method 1 N Endurance 10,000 Cycles JEDEC Standard A117 END 1 T Data Retention 100 Years JEDEC Standard A103 DR 1 I Latch Up 100 + I mA JEDEC Standard 78 LTH DD T17.0 1232 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. TABLE 18: CLOCK TIMING PARAMETERS (LPC MODE) Symbol Parameter Min Max Units T LCLK Cycle Time 30 ns CYC T LCLK High Time 11 ns HIGH T LCLK Low Time 11 ns LOW - LCLK Slew Rate (peak-to-peak) 1 4 V/ns - RST# or INIT# Slew Rate 50 mV/ns T18.0 1232 T cyc T high 0.6 V DD T low 0.5 V DD 0.4 V p-to-p DD 0.4 V DD (minimum) 0.3 V DD 0.2 V DD 1232 F07.0 FIGURE 8: LCLK WAVEFORM (LPC MODE) ©2003 Silicon Storage Technology, Inc. S71232-02-000 12/03 25 4 Mbit LPC Firmware Flash SST49LF004B Data Sheet AC Characteristics (LPC Mode) TABLE 19: READ/WRITE CYCLE TIMING PARAMETERS, V =3.0-3.6V (LPC MODE) DD Symbol Parameter Min Max Units T Clock Cycle Time 30 ns CYC T Data Set Up Time to Clock Rising 7 ns SU T Clock Rising to Data Hold Time 0 ns DH 1 T Clock Rising to Data Valid 2 11 ns VAL T Byte Programming Time 20 µs BP T Sector-Erase Time 25 ms SE T Block-Erase Time 25 ms BE T Clock Rising to Active (Float to Active Delay) 2 ns ON T Clock Rising to Inactive (Active to Float Delay) 28 ns OFF T19.0 1232 1. Minimum and maximum times have different loads. See PCI spec TABLE 20: AC INPUT/OUTPUT SPECIFICATIONS (LPC MODE) Symbol Parameter Min Max Units Conditions I (AC) Switching Current High -12 V mA 0 < V ≤ 0.3V OH DD OUT DD -17.1(V -V ) mA 0.3V < V < 0.9V DD OUT DD OUT DD 1 Equation C 0.7V < V < V DD OUT DD (Test Point) -32 V mA V = 0.7V DD OUT DD 1 I (AC) Switching Current Low 16 V Equation D mA V >V ≥ 0.6V OL DD DD OUT DD 26.7 V mA 0.6V > V > 0.1V OUT DD OUT DD 0.18V > V > 0 DD OUT (Test Point) 38 V mA V = 0.18V DD OUT DD I Low Clamp Current -25+(V +1)/0.015 mA -3 < V ≤ -1 CL IN IN I High Clamp Current 25+(V -V -1)/0.015 mA V +4 > V ≥ V +1 CH IN DD DD IN DD slewr Output Rise Slew Rate 1 4 V/ns 0.2V -0.6V load DD DD slewf Output Fall Slew Rate 1 4 V/ns 0.6V -0.2V load DD DD T20.0 1232 1. See PCI spec. ©2003 Silicon Storage Technology, Inc. S71232-02-000 12/03 26 4 Mbit LPC Firmware Flash SST49LF004B Data Sheet V TH V LCLK TEST V TL T VAL LAD [3:0] (Valid Output Data) LAD [3:0] (Float Output Data) T ON T OFF 1232 F09.0 FIGURE 9: OUTPUT TIMING PARAMETERS (LPC MODE) V TH V LCLK TEST V TL T SU T DH LAD [3:0] Inputs V MAX Valid (Valid Input Data) 1232 F10.0 FIGURE 10: INPUT TIMING PARAMETERS (LPC MODE) ©2003 Silicon Storage Technology, Inc. S71232-02-000 12/03 27 4 Mbit LPC Firmware Flash SST49LF004B Data Sheet TABLE 21: INTERFACE MEASUREMENT CONDITION PARAMETERS (LPC MODE) Symbol Value Units 1 V 0.6 V V TH DD 1 V 0.2 V V TL DD V 0.4 V V TEST DD 1 V 0.4 V V MAX DD Input Signal Edge Rate 1 V/ns T21.0 1232 1. The input test environment is done with 0.1 V of overdrive over V and V . Timing parameters must be met with no more over- DD IH IL drive than this. V specifies the maximum peak-to-peak waveform allowed for measuring input timing. Production testing may use MAX different voltage values, but must correlate results back to these parameters. TABLE 22: RESET TIMING PARAMETERS, V =3.0-3.6V (LPC MODE) DD Symbol Parameter Min Max Units T V stable to Reset Low 1 ms PRST DD T Clock Stable to Reset Low 100 µs KRST T RST# Pulse Width 100 ns RSTP T RST# Low to Output Float 48 ns RSTF 1 T RST# High to LFRAME# Low 1 µs RST T RST# Low to reset during Sector-/Block-Erase or Program 10µs RSTE T22.0 1232 1. There will be a latency due to T if a reset procedure is performed during a Program or Erase operation, RSTE V DD T PRST CLK T KRST T RSTP RST#/INIT# Sector-/Block-Erase T RSTE or Program operation aborted T RST T RSTF LAD[3:0] LFRAME# 1232 F08.0 FIGURE 11: RESET TIMING DIAGRAM (LPC MODE) ©2003 Silicon Storage Technology, Inc. S71232-02-000 12/03 28 4 Mbit LPC Firmware Flash SST49LF004B Data Sheet TABLE 23: RESET TIMING PARAMETERS, V =3.0-3.6V (PP MODE) DD Symbol Parameter Min Max Units T V stable to Reset Low 1 ms PRST DD T RST# Pulse Width 100 ns RSTP T RST# Low to Output Float 48 ns RSTF 1 T RST# High to Row Address Setup 1 µs RST T RST# Low to reset during Sector-/Block-Erase or Program 10µs RSTE T RST# Low to reset during Chip-Erase 50 µs RSTC T23.0 1232 1. There will be a reset latency of T or T if a reset procedure is performed during a programming or erase operational. RSTE RSTC V T DD PRST Row Address Addresses R/C# T RSTP RST# Sector-/Block-Erase T RSTE or Program operation aborted T Chip-Erase RSTC aborted T RST T RSTF DQ 7-0 1232 F11.0 FIGURE 12: RESET TIMING DIAGRAM (PP MODE) ©2003 Silicon Storage Technology, Inc. S71232-02-000 12/03 29 4 Mbit LPC Firmware Flash SST49LF004B Data Sheet AC Characteristics (PP Mode) TABLE 24: READ CYCLE TIMING PARAMETERS, V =3.0-3.6V (PP MODE) DD Symbol Parameter Min Max Units T Read Cycle Time 270 ns RC T RST# High to Row Address Setup 1µs RST T R/C# Address Set-up Time 45 ns AS T R/C# Address Hold Time 45 ns AH T Address Access Time 120 ns AA T Output Enable Access Time 60 ns OE T OE# Low to Active Output 0 ns OLZ T OE# High to High-Z Output 35 ns OHZ T Output Hold from Address Change 0 ns OH T24.0 1232 TABLE 25: PROGRAM/ERASE CYCLE TIMING PARAMETERS, V =3.0-3.6V (PP MODE) DD Symbol Parameter Min Max Units T RST# High to Row Address Setup 1µs RST T R/C# Address Setup Time 45 ns AS T R/C# Address Hold Time 45 ns AH T R/C# to Write Enable High Time 50 ns CWH T OE# High Setup Time 20 ns OES T OE# High Hold Time 20 ns OEH T OE# to Data# Polling Delay 60 ns OEP T OE# to Toggle Bit Delay 60 ns OET T WE# Pulse Width 100 ns WP T WE# Pulse Width High 100 ns WPH T Data Setup Time 50 ns DS T Data Hold Time 5 ns DH T Software ID Access and Exit Time 150 ns IDA T Byte Programming Time 20µs BP T Sector-Erase Time 25 ms SE T Block-Erase Time 25 ms BE T Chip-Erase Time 100 ms SCE T25.0 1232 ©2003 Silicon Storage Technology, Inc. S71232-02-000 12/03 30 4 Mbit LPC Firmware Flash SST49LF004B Data Sheet RST# T RST T RC Row Address Column Address Row Address Column Address Addresses T T T T AS AH AS AH R/C# V IH WE# T AA T OH OE# T T OE OHZ T OLZ High-Z High-Z Data Valid DQ 7-0 1232 F12.0 FIGURE 13: READ CYCLE TIMING DIAGRAM (PP MODE) T RST RST# Addresses Row Address Column Address T T T T AS AH AS AH R/C# T T CWH OEH OE# T OES T T WPH WP WE# T DH T DS DQ Data Valid 7-0 1232 F13.0 FIGURE 14: WRITE CYCLE TIMING DIAGRAM (PP MODE) ©2003 Silicon Storage Technology, Inc. S71232-02-000 12/03 31 4 Mbit LPC Firmware Flash SST49LF004B Data Sheet Addresses Row Column R/C# WE# OE# T OEP DQ D D# D# D 7 1232 F15.0 FIGURE 15: DATA# POLLING TIMING DIAGRAM (PP MODE) Row Column Addresses R/C# WE# OE# T OET DQ D D 6 1232 F15.0 FIGURE 16: TOGGLE BIT TIMING DIAGRAM (PP MODE) ©2003 Silicon Storage Technology, Inc. S71232-02-000 12/03 32 4 Mbit LPC Firmware Flash SST49LF004B Data Sheet A 14-0 (Internal A ) 5555 2AAA 5555 BA MS-0 R/C# OE# WE# Internal Program Starts AA 55 A0 DATA DQ 7-0 BA = Byte-Program Address A = Most Significant Address 1232 F16.0 MS FIGURE 17: BYTE-PROGRAM TIMING DIAGRAM (PP MODE) A 14-0 (Internal A ) 5555 2AAA 5555 5555 2AAA SA MS-0 X R/C# OE# WE# Internal Erase Starts AA 55 80 AA 55 30 DQ 7-0 SA = Sector Address 1232 F17.0 X FIGURE 18: SECTOR-ERASE TIMING DIAGRAM (PP MODE) ©2003 Silicon Storage Technology, Inc. S71232-02-000 12/03 33 4 Mbit LPC Firmware Flash SST49LF004B Data Sheet A 14-0 (Internal A ) 5555 2AAA 5555 5555 2AAA BA MS-0 X R/C# OE# WE# Internal Erase Starts AA 55 80 AA 55 50 DQ 7-0 BA = Block Address 1232 F18.0 X FIGURE 19: BLOCK-ERASE TIMING DIAGRAM (PP MODE) A 14-0 (Internal A ) 5555 2AAA 5555 5555 2AAA 5555 MS-0 R/C# OE# WE# Internal Erase Starts AA 55 80 AA 55 10 DQ 7-0 1232 F19.0 FIGURE 20: CHIP-ERASE TIMING DIAGRAM (PP MODE) ©2003 Silicon Storage Technology, Inc. S71232-02-000 12/03 34 4 Mbit LPC Firmware Flash SST49LF004B Data Sheet A 14-0 (Internal A ) 5555 2AAA 5555 0000 0001 MS-0 R/C# OE# T WP WE# T T AA IDA T WPH 55 Device ID AA 90 BF DQ 7-0 1232 F20.0 FIGURE 21: SOFTWARE ID ENTRY AND READ (PP MODE) A 14-0 (Internal A ) 5555 2AAA 5555 MS-0 R/C# OE# T IDA WE# AA 55 F0 DQ 7-0 1232 F21.0 FIGURE 22: SOFTWARE ID EXIT (PP MODE) ©2003 Silicon Storage Technology, Inc. S71232-02-000 12/03 35 4 Mbit LPC Firmware Flash SST49LF004B Data Sheet V IHT V V INPUT REFERENCE POINTS OT OUTPUT IT V ILT 1232 F22.0 AC test inputs are driven at V (0.9 V ) for a logic “1” and V (0.1 V ) for a logic “0”. Measurement reference IHT DD ILT DD points for inputs and outputs are V (0.5 V ) and V (0.5 V ). Input rise and fall times (10% ↔ 90%) are <5 ns. IT DD OT DD Note: V - V Test IT INPUT V - V Test OT OUTPUT V - V HIGH Test IHT INPUT V - V LOW Test ILT INPUT FIGURE 23: AC INPUT/OUTPUT REFERENCE WAVEFORMS TO TESTER TO DUT C L 1232 F23.0 FIGURE 24: A TEST LOAD EXAMPLE ©2003 Silicon Storage Technology, Inc. S71232-02-000 12/03 36 4 Mbit LPC Firmware Flash SST49LF004B Data Sheet PRODUCT ORDERING INFORMATION Device Speed Suffix1 Suffix2 SST49LF004B- XXX -XX -XXX Environmental Attribute E = non-Pb Package Modifier H = 32 leads I = 40 leads Package Type N = PLCC E = TSOP (type 1, die up, 10mm x 20mm) Operating Temperature C = Commercial = 0°C to +85°C Minimum Endurance 4 = 10,000 cycles Serial Access Clock Frequency 33 = 33 MHz Device Density 004 = 4 Mbit Voltage Range L = 3.0-3.6V Product Series 49 = LPC Firmware Memories Valid combinations for SST49LF004B SST49LF004B-33-4C-EI SST49LF004B-33-4C-NH SST49LF004B-33-4C-EIE SST49LF004B-33-4C-NHE Note: Valid combinations are those products in mass production or will be in mass production. Consult your SST sales representative to confirm availability of valid combinations and to determine availability of new combinations. ©2003 Silicon Storage Technology, Inc. S71232-02-000 12/03 37 4 Mbit LPC Firmware Flash SST49LF004B Data Sheet PACKAGING DIAGRAMS TOP VIEW SIDE VIEW BOTTOM VIEW .495 .485 .112 .453 Optional .106 .447 Pin #1 .048 .029 .020 R. .040 Identifier x 30˚ R. .042 .023 23 1 2 MAX. .030 .042 .021 .048 .013 .400 .595 .553 .530 .032 BSC .585 .547 .490 .026 .050 BSC .015 Min. .095 .075 .050 .032 BSC .140 .026 .125 Note: 1. Complies with JEDEC publication 95 MS-016 AE dimensions, although some dimensions may be more stringent. 2. All linear dimensions are in inches (max/min). 3. Dimensions do not include mold flash. Maximum allowable mold flash is .008 inches. 32-plcc-NH-3 4. Coplanarity: 4 mils. 32-LEAD PLASTIC LEAD CHIP CARRIER (PLCC) SST PACKAGE CODE: NH ©2003 Silicon Storage Technology, Inc. S71232-02-000 12/03 38 4 Mbit LPC Firmware Flash SST49LF004B Data Sheet 1.05 0.95 Pin # 1 Identifier 0.50 BSC 0.27 10.10 0.17 9.90 0.15 18.50 0.05 18.30 DETAIL 1.20 max. 0.70 0.50 20.20 19.80 0˚- 5˚ 0.70 Note: 1. Complies with JEDEC publication 95 MO-142 CD dimensions, 0.50 although some dimensions may be more stringent. 2. All linear dimensions are in millimeters (max/min). 1mm 3. Coplanarity: 0.1 mm 4. Maximum allowable mold flash is 0.15 mm at the package ends, and 0.25 mm between leads. 40-tsop-EI-7 40-LEAD THIN SMALL OUTLINE PACKAGE (TSOP) 10MM X 20MM SST PACKAGE CODE: EI TABLE 26: REVISION HISTORY Number Description Date 00Initial release Jan 2003 01Added a footnote to Table 2 on page 10 Jun 2003 Removed the CE# signal from Figures 6 and 7 Changes to Table 14 on page 24 – Changed V values IHI – Updated the I Test Conditions DD 022004 Data Book Dec 2003 Updated status to “Data Sheet” Silicon Storage Technology, Inc.  1171 Sonora Court  Sunnyvale, CA 94086  Telephone 408-735-9110  Fax 408-735-9036 www.SuperFlash.com or www.sst.com ©2003 Silicon Storage Technology, Inc. S71232-02-000 12/03 39