2 Mbit (256K x8) Page-Write EEPROM SST29EE020 / SST29LE020 / SST29VE020 SST29EE / LE / VE0202Mb Page-Write flash memories Data Sheet FEATURES: • Single Voltage Read and Write OperationsLatched Address and Data – 4.5-5.5V for SST29EE020Automatic Write Timing – 3.0-3.6V for SST29LE020 – Internal V Generation PP – 2.7-3.6V for SST29VE020 End of Write Detection Superior Reliability – Toggle Bit – Endurance: 100,000 Cycles (typical) – Data# Polling – Greater than 100 years Data Retention Hardware and Software Data Protection Low Power Consumption Product Identification can be accessed via – Active Current: 20 mA (typical) for 5V and Software Operation 10 mA (typical) for 3.0/2.7V TTL I/O Compatibility – Standby Current: 10 µA (typical) JEDEC Standard Fast Page-Write Operation – Flash EEPROM Pinouts and command sets – 128 Bytes per Page, 2048 Pages Packages Available – Page-Write Cycle: 5 ms (typical) – Complete Memory Rewrite: 10 sec (typical) – 32-lead PLCC – Effective Byte-Write Cycle Time: 39 µs (typical) – 32-lead TSOP (8mm x 20mm) – 32-pin PDIPFast Read Access Time – 4.5-5.5V operation: 120 ns – 3.0-3.6V operation: 200 ns – 2.7-3.6V operation: 200 ns PRODUCT DESCRIPTION The SST29EE/LE/VE020 are 256K x8 CMOS Page-Write The SST29EE/LE/VE020 are suited for applications EEPROM manufactured with SST’s proprietary, high per- that require convenient and economical updating of formance CMOS SuperFlash technology. The split-gate program, configuration, or data memory. For all sys- cell design and thick oxide tunneling injector attain better tem applications, the SST29EE/LE/VE020 significantly reliability and manufacturability compared with alternate improve performance and reliability, while lowering approaches. The SST29EE/LE/VE020 write with a single power consumption. The SST29EE/LE/VE020 power supply. Internal Erase/Program is transparent to the improve flexibility while lowering the cost for program, user. The SST29EE/LE/VE020 conform to JEDEC stan- data, and configuration storage applications. dard pinouts for byte-wide memories. To meet high density, surface mount requirements, the Featuring high performance Page-Write, the SST29EE/LE/ SST29EE/LE/VE020 are offered in 32-lead PLCC and VE020 provide a typical Byte-Write time of 39 µsec. The 32-lead TSOP packages. A 600-mil, 32-pin PDIP pack- entire memory, i.e., 256 KByte, can be written page-by- age is also available. See Figures 1, 2, and 3 for pinouts. page in as little as 10 seconds, when using interface fea- tures such as Toggle Bit or Data# Polling to indicate the Device Operation completion of a Write cycle. To protect against inadvertent The SST Page-Write EEPROM offers in-circuit electrical write, the SST29EE/LE/VE020 have on-chip hardware and write capability. The SST29EE/LE/VE020 does not require Software Data Protection schemes. Designed, manufac- separate Erase and Program operations. The internally tured, and tested for a wide spectrum of applications, the timed Write cycle executes both erase and program trans- SST29EE/LE/VE020 are offered with a guaranteed Page- parently to the user. The SST29EE/LE/VE020 have indus- Write endurance of 10,000 cycles. Data retention is rated at try standard optional Software Data Protection, which SST greater than 100 years. recommends always to be enabled. The SST29EE/LE/ VE020 are compatible with industry standard EEPROM pinouts and functionality. ©2003 Silicon Storage Technology, Inc. The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc. S71062-07-000 3/03 307 SSF is a trademark of Silicon Storage Technology, Inc. 1 These specifications are subject to change without notice. 2 Mbit Page-Write EEPROM SST29EE020 / SST29LE020 / SST29VE020 Data Sheet consists of a specific three-byte load sequence that allows Read writing to the selected page and will leave the SST29EE/ The Read operations of the SST29EE/LE/VE020 are con- LE/VE020 protected at the end of the Page-Write. The trolled by CE# and OE#, both have to be low for the system page-load cycle consists of loading 1 to 128 Bytes of data to obtain data from the outputs. CE# is used for device into the page buffer. The internal Write cycle consists of the selection. When CE# is high, the chip is deselected and T time-out and the write timer operation. During the BLCO only standby power is consumed. OE# is the output control Write operation, the only valid reads are Data# Polling and and is used to gate data from the output pins. The data bus Toggle Bit. is in high impedance state when either CE# or OE# is high. Refer to the Read cycle timing diagram for further details The Page-Write operation allows the loading of up to 128 (Figure 4). bytes of data into the page buffer of the SST29EE/LE/ VE020 before the initiation of the internal Write cycle. Dur- ing the internal Write cycle, all the data in the page buffer is Write written simultaneously into the memory array. Hence, the The Page-Write to the SST29EE/LE/VE020 should always Page-Write feature of SST29EE/LE/VE020 allow the entire use the JEDEC Standard Software Data Protection (SDP) memory to be written in as little as 10 seconds. During the three-byte command sequence. The SST29EE/LE/VE020 internal Write cycle, the host is free to perform additional contain the optional JEDEC approved Software Data Pro- tasks, such as to fetch data from other locations in the sys- tection scheme. SST recommends that SDP always be tem to set up the write to the next page. In each Page-Write enabled, thus, the description of the Write operations will operation, all the bytes that are loaded into the page buffer be given using the SDP enabled format. The three-byte must have the same page address, i.e. A through A . Any 7 16 SDP Enable and SDP Write commands are identical; byte not loaded with user data will be written to FFH. therefore, any time a SDP Write command is issued, See Figures 5 and 6 for the Page-Write cycle timing dia- Software Data Protection is automatically assured. The grams. If after the completion of the three-byte SDP load first time the three-byte SDP command is given, the device sequence or the initial byte-load cycle, the host loads a sec- becomes SDP enabled. Subsequent issuance of the same ond byte into the page buffer within a byte-load cycle time command bypasses the data protection for the page being (T ) of 100 µs, the SST29EE/LE/VE020 will stay in the written. At the end of the desired Page-Write, the entire BLC page-load cycle. Additional bytes are then loaded consecu- device remains protected. For additional descriptions, tively. The page-load cycle will be terminated if no addi- please see the application notes The Proper Use of tional byte is loaded into the page buffer within 200 µs JEDEC Standard Software Data Protection and Protecting (T ) from the last byte-load cycle, i.e., no subsequent Against Unintentional Writes When Using Single Power BLCO WE# or CE# high-to-low transition after the last rising edge Supply Flash Memories. of WE# or CE#. Data in the page buffer can be changed by The Write operation consists of three steps. Step 1 is the a subsequent byte-load cycle. The page-load period can three-byte load sequence for Software Data Protection. continue indefinitely, as long as the host continues to load Step 2 is the byte-load cycle to a page buffer of the the device within the byte-load cycle time of 100 µs. The SST29EE/LE/VE020. Steps 1 and 2 use the same timing page to be loaded is determined by the page address of for both operations. Step 3 is an internally controlled Write the last byte loaded. cycle for writing the data loaded in the page buffer into the memory array for nonvolatile storage. During both the SDP Software Chip-Erase three-byte load sequence and the byte-load cycle, the addresses are latched by the falling edge of either CE# or The SST29EE/LE/VE020 provide a Chip-Erase operation, WE#, whichever occurs last. The data is latched by the ris- which allows the user to simultaneously clear the entire ing edge of either CE# or WE#, whichever occurs first. The memory array to the “1” state. This is useful when the entire internal Write cycle is initiated by the T timer after the device must be quickly erased. BLCO rising edge of WE# or CE#, whichever occurs first. The The Software Chip-Erase operation is initiated by using a Write cycle, once initiated, will continue to completion, typi- specific six-byte load sequence. After the load sequence, cally within 5 ms. See Figures 5 and 6 for WE# and CE# the device enters into an internally timed cycle similar to the controlled Page-Write cycle timing diagrams and Figures Write cycle. During the Erase operation, the only valid read 15 and 17 for flowcharts. is Toggle Bit. See Table 4 for the load sequence, Figure 10 The Write operation has three functional cycles: the Soft- for timing diagram, and Figure 19 for the flowchart. ware Data Protection load sequence, the page-load cycle, and the internal Write cycle. The Software Data Protection ©2003 Silicon Storage Technology, Inc. S71062-07-000 3/03 307 2 2 Mbit Page-Write EEPROM SST29EE020 / SST29LE020 / SST29VE020 Data Sheet Write Operation Status Detection Hardware Data Protection The SST29EE/LE/VE020 provide two software means to Noise/Glitch Protection: A WE# or CE# pulse of less than 5 detect the completion of a Write cycle, in order to optimize ns will not initiate a Write cycle. the system Write cycle time. The software detection V Power Up/Down Detection: The Write operation is DD includes two status bits: Data# Polling (DQ ) and Toggle Bit 7 inhibited when V is less than 2.5V. DD (DQ ). The end of write detection mode is enabled after the 6 rising WE# or CE# whichever occurs first, which initiates Write Inhibit Mode: Forcing OE# low, CE# high, or WE# the internal Write cycle. high will inhibit the Write operation. This prevents inadvert- ent writes during power-up or power-down. The actual completion of the nonvolatile write is asynchro- nous with the system; therefore, either a Data# Polling or Software Data Protection (SDP) Toggle Bit read may be simultaneous with the completion of the Write cycle. If this occurs, the system may possibly The SST29EE/LE/VE020 provide the JEDEC approved get an erroneous result, i.e., valid data may appear to con- optional Software Data Protection scheme for all data alter- flict with either DQ or DQ . In order to prevent spurious 7 6 ation operations, i.e., Write and Chip-Erase. With this rejection, if an erroneous result occurs, the software routine scheme, any Write operation requires the inclusion of a should include a loop to read the accessed location an series of three-byte load operations to precede the data additional two (2) times. If both reads are valid, then the loading operation. The three-byte load sequence is used to device has completed the Write cycle, otherwise the rejec- initiate the Write cycle, providing optimal protection from tion is valid. inadvertent Write operations, e.g., during the system power-up or power-down. The SST29EE/LE/VE020 are shipped with the Software Data Protection disabled. Data# Polling (DQ ) 7 When the SST29EE/LE/VE020 are in the internal Write The software protection scheme can be enabled by apply- cycle, any attempt to read DQ of the last byte loaded dur- ing a three-byte sequence to the device, during a page- 7 ing the byte-load cycle will receive the complement of the load cycle (Figures 5 and 6). The device will then be auto- true data. Once the Write cycle is completed, DQ will matically set into the data protect mode. Any subsequent 7 show true data. Note that even though DQ may have valid Write operation will require the preceding three-byte 7 data immediately following the completion of an internal sequence. See Table 4 for the specific software command Write operation, the remaining data outputs may still be codes and Figures 5 and 6 for the timing diagrams. To set invalid: valid data on the entire data bus will appear in sub- the device into the unprotected mode, a six-byte sequence sequent successive Read cycles after an interval of 1 µs. is required. See Table 4 for the specific codes and Figure 9 See Figure 7 for Data# Polling timing diagram and Figure for the timing diagram. If a Write is attempted while SDP is 16 for a flowchart. enabled the device will be in a non-accessible state for ~300µs. SST recommends Software Data Protection always be enabled. See Figure 17 for flowcharts. Toggle Bit (DQ ) 6 The SST29EE/LE/VE020 Software Data Protection is a During the internal Write cycle, any consecutive attempts to global command, protecting all pages in the entire memory read DQ will produce alternating ‘0’s and ‘1’s, i.e., toggling 6 array once enabled (or disabled). Therefore using SDP for between 0 and 1. When the Write cycle is completed, the a single Page-Write will enable SDP for the entire array. toggling will stop. The device is then ready for the next Single pages by themselves cannot be SDP enabled or operation. See Figure 8 for Toggle Bit timing diagram and disabled. Figure 16 for a flowchart. The initial read of the Toggle Bit will typically be a “1”. Single power supply reprogrammable nonvolatile memo- ries may be unintentionally altered. SST strongly recom- Data Protection mends that Software Data Protection (SDP) always be enabled. The SST29EE/LE/VE020 should be programmed The SST29EE/LE/VE020 provide both hardware and soft- using the SDP command sequence. SST recommends the ware features to protect nonvolatile data from inadvertent SDP Disable Command Sequence not be issued to the writes. device prior to writing. ©2003 Silicon Storage Technology, Inc. S71062-07-000 3/03 307 3 2 Mbit Page-Write EEPROM SST29EE020 / SST29LE020 / SST29VE020 Data Sheet Please refer to the following Application Notes for more TABLE 1: PRODUCT IDENTIFICATION information on using SDP: Address Data Protecting Against Unintentional Writes When Manufacturer’s ID 0000H BFH Using Single Power Supply Flash Memories Device ID The Proper Use of JEDEC Standard Software SST29EE020 0001H 10H Data Protection SST29LE020 0001H 12H SST29VE020 0001H 12H Product Identification T1.3 307 The Product Identification mode identifies the device as the SST29EE/LE/VE020 and manufacturer as SST. Product Identification Mode Exit This mode is accessed via software. For details, see In order to return to the standard Read mode, the Software Table 4, Figure 11 for the software ID entry and read Product Identification mode must be exited. Exiting is timing diagram, and Figure 18 for the ID entry com- accomplished by issuing the Software ID Exit (reset) opera- mand sequence flowchart. tion, which returns the device to the Read operation. The Reset operation may also be used to reset the device to the Read mode after an inadvertent transient condition that apparently causes the device to behave abnormally, e.g., not read correctly. See Table 4 for software command codes, Figure 12 for timing waveform, and Figure 18 for a flowchart. FUNCTIONAL BLOCK DIAGRAM SuperFlash X-Decoder Memory A - A 17 0 Address Buffer & Latches Y-Decoder and Page Latches CE# Control Logic OE# I/O Buffers and Data Latches WE# DQ - DQ 7 0 307 ILL B1.1 ©2003 Silicon Storage Technology, Inc. S71062-07-000 3/03 307 4 2 Mbit Page-Write EEPROM SST29EE020 / SST29LE020 / SST29VE020 Data Sheet 4 3 2 1 32 31 30 A7 5 29 A14 A6 6 28 A13 A5 7 27 A8 8 26 A4 A9 32-lead PLCC A3 9 25 A11 Top View A2 10 24 OE# 11 23 A1 A10 A0 12 22 CE# DQ0 13 21 DQ7 14 15 16 17 18 19 20 307 ILL F02.3 FIGURE 1: PIN ASSIGNMENTS FOR 32-LEAD PLCC A11 1 32 OE# A9 2 31 A10 A8 3 30 CE# A13 4 29 DQ7 A14 5 28 DQ6 Standard Pinout A17 6 27 DQ5 WE# DQ4 7 26 Top View V 8 25 DQ3 DD NC 9 24 V SS Die Up A16 10 23 DQ2 A15 11 22 DQ1 A12 12 21 DQ0 A7 13 20 A0 A6 14 19 A1 A5 15 18 A2 A4 16 17 A3 307 ILL F01.2 FIGURE 2: PIN ASSIGNMENTS FOR 32-LEAD TSOP NC 1 32 V DD A16 2 31 WE# A15 3 30 A17 4 29 A12 A14 A7 5 28 A13 32-pin A6 6 27 A8 A5 7 PDIP 26 A9 A4 8 25 A11 Top View A3 9 24 OE# A2 10 23 A10 A1 11 22 CE# A0 12 21 DQ7 DQ0 13 20 DQ6 14 19 DQ1 DQ5 DQ2 15 18 DQ4 V 16 17 DQ3 SS 307 ILL F19.0 FIGURE 3: PIN ASSIGNMENTS FOR 32-PIN PDIP ©2003 Silicon Storage Technology, Inc. S71062-07-000 3/03 307 5 DQ1 A12 A15 DQ2 V A16 SS DQ3 NC V DQ4 DD DQ5 WE# DQ6 A17 2 Mbit Page-Write EEPROM SST29EE020 / SST29LE020 / SST29VE020 Data Sheet TABLE 2: PIN DESCRIPTION Symbol Pin Name Functions A -A Row Address Inputs To provide memory addresses. Row addresses define a page for a Write cycle. 17 7 A -A Column Address Inputs Column Addresses are toggled to load page data 6 0 DQ -DQ Data Input/output To output data during Read cycles and receive input data during Write cycles. 7 0 Data is internally latched during a Write cycle. The outputs are in tri-state when OE# or CE# is high. CE# Chip Enable To activate the device when CE# is low. OE# Output Enable To gate the data output buffers. WE# Write Enable To control the Write operations. V Power Supply To provide: 5.0V supply (4.5-5.5V) for SST29EE020 DD 3.0V supply (3.0-3.6V) for SST29LE020 2.7V supply (2.7-3.6V) for SST29VE020 V Ground SS NC No Connection Unconnected pins. T2.2 307 TABLE 3: OPERATION MODES SELECTION Mode CE# OE# WE# DQ Address Read V V V D A IL IL IH OUT IN Page-Write V V V D A IL IH IL IN IN 1 Standby V X XHigh Z X IH Write Inhibit X V XHigh Z/ D X IL OUT XX V High Z/ D X IH OUT Software Chip-Erase V V V D A See Table 4 IL IH IL IN IN, Product Identification Software Mode V V V Manufacturer’s ID (BFH) See Table 4 IL IH IL 2 Device ID SDP Enable Mode V V V See Table 4 IL IH IL SDP Disable Mode V V V See Table 4 IL IH IL T3.3 307 1. X can be V or V , but no other value IL IH 2. Device ID = 10H for SST29EE020 and 12H for SST29LE/VE020 ©2003 Silicon Storage Technology, Inc. S71062-07-000 3/03 307 6 2 Mbit Page-Write EEPROM SST29EE020 / SST29LE020 / SST29VE020 Data Sheet TABLE 4: SOFTWARE COMMAND SEQUENCE Command 1st Bus 2nd Bus 3rd Bus 4th Bus 5th Bus 6th Bus Sequence Write Cycle Write Cycle Write Cycle Write Cycle Write Cycle Write Cycle 1 1 1 1 1 1 Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data 2 Software 5555H AAH 2AAAH 55H 5555H A0H Addr Data Data Protect Enable & Page-Write 3 Software Chip-Erase 5555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H 5555H 10H 4,5 Software ID Entry 5555H AAH 2AAAH 55H 5555H 90H Software ID Exit 5555H AAH 2AAAH 55H 5555H F0H Alternate 5555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H 5555H 60H 6 Software ID Entry T4.2 307 1. Address format A -A (Hex), Address A can be V or V , but no other value. 14 0 15 IL IH 2. Page-Write consists of loading up to 128 Bytes (A -A ) 6 0 3. The software Chip-Erase function is not supported by the industrial temperature part. Please contact SST if you require this function for an industrial temperature part. 4. The device does not remain in Software Product ID Mode if powered down. 5. With A -A = 0; SST Manufacturer’s ID = BFH, is read with A = 0, 14 1 0 SST29EE020 Device ID = 10H, is read with A = 1 0 SST29LE/VE020 Device ID = 12H, is read with A = 1 0 6. Alternate six-byte Software Product ID Command Code Note: This product supports both the JEDEC standard three-byte command code sequence and SST’s original six-byte command code sequence. For new designs, SST recommends that the three-byte command code sequence be used. ©2003 Silicon Storage Technology, Inc. S71062-07-000 3/03 307 7 2 Mbit Page-Write EEPROM SST29EE020 / SST29LE020 / SST29VE020 Data Sheet Absolute Maximum Stress Ratings (Applied conditions greater than those listed under “Absolute Maximum Stress Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these conditions or conditions greater than those defined in the operational sections of this data sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.) Temperature Under Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55°C to +125°C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C D. C. Voltage on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.5V to V +0.5V DD Transient Voltage (<20 ns) on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-2.0V to V +2.0V DD Voltage on A Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 14.0V 9 Package Power Dissipation Capability (Ta = 25°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0W Through Hold Lead Soldering Temperature (10 Seconds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300°C Surface Mount Lead Soldering Temperature (3 Seconds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240°C 1 Output Short Circuit Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA 1. Outputs shorted for no more than one second. No more than one output shorted at a time. OPERATING RANGE FOR SST29EE020 Range Ambient Temp V DD Commercial 0°C to +70°C 4.5-5.5V Industrial -40°C to +85°C 4.5-5.5V OPERATING RANGE FOR SST29LE020 Range Ambient Temp V DD Commercial 0°C to +70°C 3.0-3.6V Industrial -40°C to +85°C 3.0-3.6V OPERATING RANGE FOR SST29VE020 Range Ambient Temp V DD Commercial 0°C to +70°C 2.7-3.6V Industrial -40°C to +85°C 2.7-3.6V AC CONDITIONS OF TEST Input Rise/Fall Time . . . . . . . . . . . . . . 10 ns Output Load . . . . . . . . . . . . . . . . . . . . . 1 TTL Gate and C = 100 pF L See Figures 13 and 14 ©2003 Silicon Storage Technology, Inc. S71062-07-000 3/03 307 8 2 Mbit Page-Write EEPROM SST29EE020 / SST29LE020 / SST29VE020 Data Sheet TABLE 5: DC OPERATING CHARACTERISTICS V = 4.5-5.5V FOR SST29EE020 DD Limits Symbol Parameter Min Max Units Test Conditions I Power Supply Current Address input=V /V at f=1/T Min, DD ILT IHT, RC V =V Max DD DD Read 30 mA CE#=OE#=V , WE#=V , all I/Os open IL IH Program and Erase 50 mA CE#=WE#=V , OE#=V , V =V Max IL IH DD DD I Standby V Current 3 mA CE#=OE#=WE#=V , V =V Max SB1 DD IH DD DD (TTL input) I Standby V Current 50 µA CE#=OE#=WE#=V -0.3V, V =V Max SB2 DD DD DD DD (CMOS input) I Input Leakage Current 1 µA V =GND to V , V =V Max LI IN DD DD DD I Output Leakage Current 10 µA V =GND to V , V =V Max LO OUT DD DD DD V Input Low Voltage 0.8 V V =V Min IL DD DD V Input High Voltage 2.0 V V =V Max IH DD DD V Output Low Voltage 0.4 V I =2.1 mA, V =V Min OL OL DD DD V Output High Voltage 2.4 V I =-400 µA, V =V Min OH OH DD DD T5.3 307 TABLE 6: DC OPERATING CHARACTERISTICS V = 3.0-3.6V FOR SST29LE020 AND 2.7-3.6V FOR SST29VE020 DD Limits Symbol Parameter Min Max Units Test Conditions I Power Supply Current Address input=V /V at f=1/T Min, DD ILT IHT, RC V =V Max DD DD Read 12 mA CE#=OE#=V , WE#=V , all I/Os open IL IH Program and Erase 15 mA CE#=WE#=V , OE#=V , V =V Max IL IH DD DD I Standby V Current 1 mA CE#=OE#=WE#=V , V =V Max SB1 DD IH DD DD (TTL input) I Standby V Current 15 µA CE#=OE#=WE#=V -0.3V, V =V Max SB2 DD DD DD DD (CMOS input) I Input Leakage Current 1 µA V =GND to V , V =V Max LI IN DD DD DD I Output Leakage Current 10 µA V =GND to V , V =V Max LO OUT DD DD DD V Input Low Voltage 0.8 V V =V Min IL DD DD V Input High Voltage 2.0 V V =V Max IH DD DD V Output Low Voltage 0.4 V I =100 µA, V =V Min OL OL DD DD V Output High Voltage 2.4 V I =-100 µA, V =V Min OH OH DD DD T6.3 307 ©2003 Silicon Storage Technology, Inc. S71062-07-000 3/03 307 9 2 Mbit Page-Write EEPROM SST29EE020 / SST29LE020 / SST29VE020 Data Sheet TABLE 7: RECOMMENDED SYSTEM POWER-UP TIMINGS Symbol Parameter Minimum Units 1 T Power-up to Read Operation 100 µs PU-READ 1 T Power-up to Write Operation 5 ms PU-WRITE T7.1 307 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. TABLE 8: CAPACITANCE (Ta = 25°C, f=1 Mhz, other pins open) Parameter Description Test Condition Maximum 1 C I/O Pin Capacitance V = 0V 12 pF I/O I/O 1 C Input Capacitance V = 0V 6 pF IN IN T8.0 307 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. TABLE 9: RELIABILITY CHARACTERISTICS Symbol Parameter Minimum Specification Units Test Method 1 N Endurance 10,000 Cycles JEDEC Standard A117 END 1 T Data Retention 100 Years JEDEC Standard A103 DR 1 I Latch Up 100 mA JEDEC Standard 78 LTH T9.5 307 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. ©2003 Silicon Storage Technology, Inc. S71062-07-000 3/03 307 10 2 Mbit Page-Write EEPROM SST29EE020 / SST29LE020 / SST29VE020 Data Sheet AC CHARACTERISTICS TABLE 10: READ CYCLE TIMING PARAMETERS FOR SST29EE020 SST29EE020-120 Symbol Parameter Min Max Units T Read Cycle Time 120 ns RC T Chip Enable Access Time 120 ns CE T Address Access Time 120 ns AA T Output Enable Access Time 50 ns OE 1 T CE# Low to Active Output 0 ns CLZ 1 T OE# Low to Active Output 0 ns OLZ 1 T CE# High to High-Z Output 30 ns CHZ 1 T OE# High to High-Z Output 30 ns OHZ 1 T Output Hold from Address Change 0 ns OH T10.5 307 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. TABLE 11: READ CYCLE TIMING PARAMETERS FOR SST29LE020 SST29LE020-200 Symbol Parameter Min Max Units T Read Cycle Time 200 ns RC T Chip Enable Access Time 200 ns CE T Address Access Time 200 ns AA T Output Enable Access Time 100 ns OE 1 T CE# Low to Active Output 0 ns CLZ 1 T OE# Low to Active Output 0 ns OLZ 1 T CE# High to High-Z Output 50 ns CHZ 1 T OE# High to High-Z Output 50 ns OHZ 1 T Output Hold from Address Change 0 ns OH T11.2 307 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. TABLE 12: READ CYCLE TIMING PARAMETERS FOR SST29VE020 SST29VE020-200 Symbol Parameter Min Max Units T Read Cycle Time 200 ns RC T Chip Enable Access Time 200 ns CE T Address Access Time 200 ns AA T Output Enable Access Time 100 ns OE 1 T CE# Low to Active Output 0 ns CLZ 1 T OE# Low to Active Output 0 ns OLZ 1 T CE# High to High-Z Output 50 ns CHZ 1 T OE# High to High-Z Output 50 ns OHZ 1 T Output Hold from Address Change 0 ns OH T12.2 307 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. ©2003 Silicon Storage Technology, Inc. S71062-07-000 3/03 307 11 2 Mbit Page-Write EEPROM SST29EE020 / SST29LE020 / SST29VE020 Data Sheet TABLE 13: PAGE-WRITE CYCLE TIMING PARAMETERS SST29EE020 SST29LE/VE020 Symbol Parameter Min Max Min Max Units T Write Cycle (Erase and Program) 10 10 ms WC T Address Setup Time 0 0 ns AS T Address Hold Time 50 70 ns AH T WE# and CE# Setup Time 0 0 ns CS T WE# and CE# Hold Time 0 0 ns CH T OE# High Setup Time 0 0 ns OES T OE# High Hold Time 0 0 ns OEH T CE# Pulse Width 70 120 ns CP T WE# Pulse Width 70 120 ns WP T Data Setup Time 35 50 ns DS 1 T Data Hold Time 0 0 ns DH 1 T Byte Load Cycle Time 0.05 100 0.05 100 µs BLC 1 T Byte Load Cycle Time 200 200 µs BLCO 1 T Software ID Access and Exit Time 10 10 µs IDA T Software Chip-Erase 20 20 ms SCE T13.5 307 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. ©2003 Silicon Storage Technology, Inc. S71062-07-000 3/03 307 12 2 Mbit Page-Write EEPROM SST29EE020 / SST29LE020 / SST29VE020 Data Sheet T RC T AA ADDRESS A 17-0 T CE CE# T OE OE# T T OHZ OLZ V IH WE# T CHZ T OH T CLZ HIGH-Z HIGH-Z DATA VALID DATA VALID DQ 7-0 307 ILL F03.0 FIGURE 4: READ CYCLE TIMING DIAGRAM Three-Byte Sequence for T AH Enabling SDP T AS ADDRESS A 5555 2AAA 5555 17-0 T T CS CH CE# T T OES OEH OE# T WP T T BLCO BLC WE# T DH DQ AA 55 A0 DATA VALID 7-0 T WC T SW0 SW1 SW2 DS BYTE 0 BYTE 1 BYTE 127 307 ILL F04.1 FIGURE 5: WE# CONTROLLED PAGE-WRITE CYCLE TIMING DIAGRAM ©2003 Silicon Storage Technology, Inc. S71062-07-000 3/03 307 13 2 Mbit Page-Write EEPROM SST29EE020 / SST29LE020 / SST29VE020 Data Sheet Three-Byte Sequence for T AH Enabling SDP T AS ADDRESS A 17-0 5555 2AAA 5555 T CP T T BLC BLCO CE# T T OES OEH OE# T T CS CH WE# T DH DQ AA 55 A0 7-0 DATA VALID T WC T SW0 SW1 SW2 DS BYTE 0 BYTE 1 BYTE 127 307 ILL F05.1 FIGURE 6: CE# CONTROLLED PAGE-WRITE CYCLE TIMING DIAGRAM ADDRESS A 17-0 T CE CE# T OES T OEH OE# T OE WE# DQ D D# D# D 7 T + T WC BLCO 307 ILL F06.0 FIGURE 7: DATA# POLLING TIMING DIAGRAM ©2003 Silicon Storage Technology, Inc. S71062-07-000 3/03 307 14 2 Mbit Page-Write EEPROM SST29EE020 / SST29LE020 / SST29VE020 Data Sheet ADDRESS A 17-0 T CE CE# T OEH T OES T OE OE# WE# DQ 6 T + T WC BLCO TWO READ CYCLES WITH SAME OUTPUTS 307 ILL F07.1 FIGURE 8: TOGGLE BIT TIMING DIAGRAM Six-Byte Sequence for Disabling Software Data Protection T WC ADDRESS A 5555 2AAA 5555 5555 2AAA 5555 14-0 DQ AA 55 80 AA 55 20 7-0 CE# OE# T T BLCO WP WE# T BLC SW0 SW1 SW2 SW3 SW4 SW5 307 ILL F08.1 FIGURE 9: SOFTWARE DATA PROTECT DISABLE TIMING DIAGRAM ©2003 Silicon Storage Technology, Inc. S71062-07-000 3/03 307 15 2 Mbit Page-Write EEPROM SST29EE020 / SST29LE020 / SST29VE020 Data Sheet Six-Byte Code for Software Chip-Erase T SCE ADDRESS A 5555 2AAA 5555 5555 2AAA 5555 14-0 DQ AA 55 80 AA 55 10 7-0 CE# OE# T T BLCO WP WE# T BLC SW0 SW1 SW2 SW3 SW4 SW5 307 ILL F09.2 FIGURE 10: SOFTWARE CHIP-ERASE TIMING DIAGRAM Three-Byte Sequence for Software ID Entry ADDRESS A 5555 2AAA 5555 0000 0001 14-0 T AA DQ AA 55 90 BF DEVICE ID 7-0 T IDA CE# OE# T WP WE# T BLC DEVICE ID = 10H for SST29EE020 SW0 SW1 SW2 = 12H for SST29LE020/29VE020 307 ILL F10.2 FIGURE 11: SOFTWARE ID ENTRY AND READ ©2003 Silicon Storage Technology, Inc. S71062-07-000 3/03 307 16 2 Mbit Page-Write EEPROM SST29EE020 / SST29LE020 / SST29VE020 Data Sheet Three-Byte Sequence for Software ID Exit and Reset ADDRESS A 5555 2AAA 5555 14-0 DQ AA 55 F0 7-0 T IDA CE# OE# T WP WE# T BLC SW0 SW1 SW2 307 ILL F11.0 FIGURE 12: SOFTWARE ID EXIT AND RESET ©2003 Silicon Storage Technology, Inc. S71062-07-000 3/03 307 17 2 Mbit Page-Write EEPROM SST29EE020 / SST29LE020 / SST29VE020 Data Sheet V IHT V V HT HT INPUT REFERENCE POINTS OUTPUT V V LT LT V ILT 307 ILL F12.1 AC test inputs are driven at V (2.4 V) for a logic “1” and V (0.4 V) for a logic “0”. Measurement reference points for IHT ILT inputs and outputs are V (2.0 V) and V (0.8 V). Input rise and fall times (10% ↔ 90%) are <10 ns. HT LT Note: V - V Test HT HIGH V - V Test LT LOW V - V HIGH Test IHT INPUT V - V LOW Test ILT INPUT FIGURE 13: AC INPUT/OUTPUT REFERENCE WAVEFORMS V DD TO TESTER R L HIGH TO DUT C L R L LOW 307 ILL F13.1 FIGURE 14: A TEST LOAD EXAMPLE ©2003 Silicon Storage Technology, Inc. S71062-07-000 3/03 307 18 2 Mbit Page-Write EEPROM SST29EE020 / SST29LE020 / SST29VE020 Data Sheet Start Software Data See Figure 17 Protect Write Command Set Page Address Set Byte Address = 0 Load Byte Data Increment Byte Address By 1 Byte No Address = 128? Yes Wait T BLCO Wait for end of Write (T , WC Data# Polling bit or Toggle bit operation) Write Completed 307 ILL F14.1 FIGURE 15: WRITE ALGORITHM ©2003 Silicon Storage Technology, Inc. S71062-07-000 3/03 307 19 2 Mbit Page-Write EEPROM SST29EE020 / SST29LE020 / SST29VE020 Data Sheet Internal Timer Toggle Bit Data# Polling Page-Write Page-Write Page-Write Initiated Initiated Initiated Read DQ 7 Read a byte Wait T WC (Data for last from page byte loaded) Write No Read same Completed Is DQ = 7 byte true data? Yes No Write Does DQ 6 Completed match? Yes Write Completed 307 ILL F15.1 FIGURE 16: WAIT OPTIONS ©2003 Silicon Storage Technology, Inc. S71062-07-000 3/03 307 20 2 Mbit Page-Write EEPROM SST29EE020 / SST29LE020 / SST29VE020 Data Sheet Software Data Protect Enable Software Data Protect Command Sequence Disable Command Sequence Write data: AAH Write data: AAH Address: 5555H Address: 5555H Write data: 55H Write data: 55H Address: 2AAAH Address: 2AAAH Write data: A0H Write data: 80H Address: 5555H Address: 5555H Optional Page Load Load 0 to Write data: AAH Operation 128 Bytes of Address: 5555H page data Write data: 55H Address: 2AAAH Wait T BLCO Write data: 20H Address: 5555H Wait T WC Wait T BLCO SDP Enabled Wait T WC SDP Disabled 307 ILL F16.1 FIGURE 17: SOFTWARE DATA PROTECTION FLOWCHARTS ©2003 Silicon Storage Technology, Inc. S71062-07-000 3/03 307 21 2 Mbit Page-Write EEPROM SST29EE020 / SST29LE020 / SST29VE020 Data Sheet Software Product ID Entry Software Product ID Exit & Command Sequence Reset Command Sequence Write data: AAH Write data: AAH Address: 5555H Address: 5555H Write data: 55H Write data: 55H Address: 2AAAH Address: 2AAAH Write data: 90H Write data: F0H Address: 5555H Address: 5555H Pause 10 µs Pause 10 µs Return to normal Read Software ID operation 307 ILL F17.1 FIGURE 18: SOFTWARE PRODUCT COMMAND FLOWCHARTS ©2003 Silicon Storage Technology, Inc. S71062-07-000 3/03 307 22 2 Mbit Page-Write EEPROM SST29EE020 / SST29LE020 / SST29VE020 Data Sheet Software Chip-Erase Command Sequence Write data: AAH Address: 5555H Write data: 55H Address: 2AAAH Write data: 80H Address: 5555H Write data: AAH Address: 5555H Write data: 55H Address: 2AAAH Write data: 10H Address: 5555H Wait T SCE Chip-Erase to FFH 307 ILL F18.2 FIGURE 19: SOFTWARE CHIP-ERASE COMMAND CODES ©2003 Silicon Storage Technology, Inc. S71062-07-000 3/03 307 23 2 Mbit Page-Write EEPROM SST29EE020 / SST29LE020 / SST29VE020 Data Sheet PRODUCT ORDERING INFORMATION Device Speed Suffix1 Suffix2 SST29xE020 - XXX -XX -XX Package Modifier H = 32 leads or pins Package Type E = TSOP (type 1, die up, 8mm x 20mm) N = PLCC P = PDIP Temperature Range C = Commercial = 0°C to +70°C I = Industrial = -40°C to +85°C Minimum Endurance 4 = 10,000 cycles Read Access Speed 200 = 200 ns 120 = 120 ns Function E = Page-Write Voltage E = 4.5-5.5V L = 3.0-3.6V V = 2.7-3.6V Valid combinations for SST29EE020 SST29EE020-120-4C-NH SST29EE020-120-4C-EH SST29EE020-120-4C-PH SST29EE020-120-4I-NH SST29EE020-120-4I-EH Valid combinations for SST29LE020 SST29LE020-200-4C-NH SST29LE020-200-4C-EH SST29LE020-200-4I-NH SST29LE020-200-4I-EH Valid combinations for SST29VE020 SST29VE020-200-4C-NH SST29VE020-200-4C-EH SST29VE020-200-4I-NH SST29VE020-200-4I-EH Note: Valid combinations are those products in mass production or will be in mass production. Consult your SST sales representative to confirm availability of valid combinations and to determine availability of new combinations. Note: The software Chip-Erase function is not supported by the industrial temperature part. Please contact SST if you require this function for an industrial temperature part. Non-Pb:Many devices in this data sheet are also offered in non-Pb (no lead added) packages. The non-Pb part number is simply the standard part number with the letter “E” added to the end of the package code. The non-Pb package codes corresponding to the packages listed above are NHE and EHE. ©2003 Silicon Storage Technology, Inc. S71062-07-000 3/03 307 24 2 Mbit Page-Write EEPROM SST29EE020 / SST29LE020 / SST29VE020 Data Sheet PACKAGING DIAGRAMS TOP VIEW SIDE VIEW BOTTOM VIEW .495 .485 .112 Optional .453 .106 Pin #1 .447 .048 .029 .040 Identifier .020 R. x 30˚ R. .042 .023 .030 23 1 2 MAX. .042 .021 .048 .013 .400 .530 .595 .553 .032 BSC .490 .585 .547 .026 .050 BSC .015 Min. .095 .075 .050 BSC .032 .140 .026 .125 Note: 1. Complies with JEDEC publication 95 MS-016 AE dimensions, although some dimensions may be more stringent. 2. All linear dimensions are in inches (max/min). 3. Dimensions do not include mold flash. Maximum allowable mold flash is .008 inches. 32-plcc-NH-3 4. Coplanarity: 4 mils. 32-LEAD PLASTIC LEAD CHIP CARRIER (PLCC) SST PACKAGE CODE: NH ©2003 Silicon Storage Technology, Inc. S71062-07-000 3/03 307 25 2 Mbit Page-Write EEPROM SST29EE020 / SST29LE020 / SST29VE020 Data Sheet 1.05 0.95 Pin # 1 Identifier 0.50 BSC 8.10 0.27 7.90 0.17 0.15 18.50 0.05 18.30 DETAIL 1.20 max. 0.70 0.50 20.20 19.80 0˚- 5˚ 0.70 0.50 Note: 1.Complies with JEDEC publication 95 MO-142 BD dimensions, although some dimensions may be more stringent. 1mm 2.All linear dimensions are in millimeters (max/min). 3.Coplanarity: 0.1 mm 32-tsop-EH-7 4.Maximum allowable mold flash is 0.15 mm at the package ends, and 0.25mm between leads. 32-LEAD THIN SMALL OUTLINE PACKAGE (TSOP) 8MM X 20MM SST PACKAGE CODE: EH ©2003 Silicon Storage Technology, Inc. S71062-07-000 3/03 307 26 2 Mbit Page-Write EEPROM SST29EE020 / SST29LE020 / SST29VE020 Data Sheet 32 C L 1 Pin #1 Identifier .625 .600 .550 .530 1.655 .075 7˚ 1.645 .065 4 PLCS. Base .200 Plane .170 Seating Plane .050 0˚ .015 .012 15˚ .008 .150 .120 .100 BSC .022 .080 .065 .600 BSC .016 .070 .045 Note: 1. Complies with JEDEC publication 95 MO-015 AP dimensions, although some dimensions may be more stringent. 2. All linear dimensions are in inches (max/min). 3. Dimensions do not include mold flash. Maximum allowable mold flash is .010 inches. 32-pdip-PH-3 32-PIN PLASTIC DUAL IN-LINE PINS (PDIP) SST PACKAGE CODE: PH TABLE 14: REVISION HISTORY Number Description Date 06 May 20022002 Data Book 07 Mar 2003WH package is no longer offered Removed 150 ns Read Access Time for SST29EE020 Removed 250 ns Read Access Time for SST29LE020 and SST29VE020 Clarified I Write to be Program and Erase in Tables 5 and 6 on page 9 DD Silicon Storage Technology, Inc.  1171 Sonora Court  Sunnyvale, CA 94086  Telephone 408-735-9110  Fax 408-735-9036 www.SuperFlash.com or www.sst.com ©2003 Silicon Storage Technology, Inc. S71062-07-000 3/03 307 27