1 Mbit / 2 Mbit / 4 Mbit (x8) Multi-Purpose Flash SST39SF010A / SST39SF020A / SST39SF040 SST39SF010A / 020A / 0405.0V 1Mb / 2Mb / 4Mb (x8) MPF memories Data Sheet FEATURES: • Organized as 128K x8 / 256K x8 / 512K x8Fast Erase and Byte-Program Single 4.5-5.5V Read and Write Operations – Sector-Erase Time: 18 ms (typical) – Chip-Erase Time: 70 ms (typical) Superior Reliability – Byte-Program Time: 14 µs (typical) – Endurance: 100,000 Cycles (typical) – Chip Rewrite Time: – Greater than 100 years Data Retention 2 seconds (typical) for SST39SF010A Low Power Consumption 4 seconds (typical) for SST39SF020A (typical values at 14 MHz) 8 seconds (typical) for SST39SF040 – Active Current: 10 mA (typical)End-of-Write Detection – Standby Current: 30 µA (typical) – Toggle Bit Sector-Erase Capability – Data# Polling – Uniform 4 KByte sectorsTTL I/O Compatibility Fast Read Access Time:JEDEC Standard – 55 ns – Flash EEPROM Pinouts and command sets – 70 ns Packages Available Latched Address and Data – 32-lead PLCC Automatic Write Timing – 32-lead TSOP (8mm x 14mm) – 32-pin PDIP – Internal V Generation PP All devices are RoHS compliant All non-Pb (lead-free) devices are RoHS compliant PRODUCT DESCRIPTION The SST39SF010A/020A/040 are CMOS Multi-Purpose function of the applied voltage, current, and time of applica- Flash (MPF) manufactured with SST’s proprietary, high tion. Since for any given voltage range, the SuperFlash performance CMOS SuperFlash technology. The split-gate technology uses less current to program and has a shorter cell design and thick oxide tunneling injector attain better erase time, the total energy consumed during any Erase or reliability and manufacturability compared with alternate Program operation is less than alternative flash technolo- approaches. The SST39SF010A/020A/040 devices write gies. These devices also improve flexibility while lowering (Program or Erase) with a 4.5-5.5V power supply. The the cost for program, data, and configuration storage appli- SST39SF010A/020A/040 devices conform to JEDEC stan- cations. dard pinouts for x8 memories. The SuperFlash technology provides fixed Erase and Pro- Featuring high performance Byte-Program, the gram times, independent of the number of Erase/Program SST39SF010A/020A/040 devices provide a maximum cycles that have occurred. Therefore the system software Byte-Program time of 20 µsec. These devices use Toggle or hardware does not have to be modified or de-rated as is Bit or Data# Polling to indicate the completion of Program necessary with alternative flash technologies, whose Erase operation. To protect against inadvertent write, they have and Program times increase with accumulated Erase/Pro- on-chip hardware and Software Data Protection schemes. gram cycles. Designed, manufactured, and tested for a wide spectrum of To meet high density, surface mount requirements, the applications, these devices are offered with a guaranteed SST39SF010A/020A/040 are offered in 32-lead PLCC and typical endurance of 100,000 cycles. Data retention is rated 32-lead TSOP packages. A 600 mil, 32-pin PDIP is also at greater than 100 years. available. See Figures 2, 3, and 4 for pin assignments. The SST39SF010A/020A/040 devices are suited for appli- cations that require convenient and economical updating of program, configuration, or data memory. For all system applications, they significantly improve performance and reliability, while lowering power consumption. They inher- ently use less energy during erase and program than alter- native flash technologies. The total energy consumed is a ©2010 Silicon Storage Technology, Inc. The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc. S71147-09-000 01/10 MPF is a trademark of Silicon Storage Technology, Inc. 1 These specifications are subject to change without notice. 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39SF010A / SST39SF020A / SST39SF040 Data Sheet Device Operation Commands are used to initiate the memory operation func- is latched on the rising edge of the sixth WE# pulse. The tions of the device. Commands are written to the device internal Erase operation begins after the sixth WE# pulse. using standard microprocessor write sequences. A com- The End-of-Erase can be determined using either Data# mand is written by asserting WE# low while keeping CE# Polling or Toggle Bit methods. See Figure 10 for timing low. The address bus is latched on the falling edge of WE# waveforms. Any commands written during the Sector- or CE#, whichever occurs last. The data bus is latched on Erase operation will be ignored. the rising edge of WE# or CE#, whichever occurs first. Chip-Erase Operation Read The SST39SF010A/020A/040 provide Chip-Erase opera- The Read operation of the SST39SF010A/020A/040 is tion, which allows the user to erase the entire memory controlled by CE# and OE#, both have to be low for the array to the “1s” state. This is useful when the entire device system to obtain data from the outputs. CE# is used for must be quickly erased. device selection. When CE# is high, the chip is dese- The Chip-Erase operation is initiated by executing a six- lected and only standby power is consumed. OE# is the byte Software Data Protection command sequence with output control and is used to gate data from the output Chip-Erase command (10H) with address 5555H in the last pins. The data bus is in high impedance state when byte sequence. The internal Erase operation begins with either CE# or OE# is high. Refer to the Read cycle timing the rising edge of the sixth WE# or CE#, whichever occurs diagram (Figure 5) for further details. first. During the internal Erase operation, the only valid read is Toggle Bit or Data# Polling. See Table 4 for the command Byte-Program Operation sequence, Figure 11 for timing diagram, and Figure 19 for the flowchart. Any commands written during the Chip- The SST39SF010A/020A/040 are programmed on a byte- Erase operation will be ignored. by-byte basis. Before programming, the sector where the byte exists must be fully erased. The Program operation is accomplished in three steps. The first step is the three-byte Write Operation Status Detection load sequence for Software Data Protection. The second The SST39SF010A/020A/040 provide two software means step is to load byte address and byte data. During the Byte- to detect the completion of a Write (Program or Erase) Program operation, the addresses are latched on the falling cycle, in order to optimize the system Write cycle time. The edge of either CE# or WE#, whichever occurs last. The software detection includes two status bits: Data# Polling data is latched on the rising edge of either CE# or WE#, (DQ ) and Toggle Bit (DQ ). The End-of-Write detection 7 6 whichever occurs first. The third step is the internal Pro- mode is enabled after the rising edge of WE# which ini- gram operation which is initiated after the rising edge of the tiates the internal Program or Erase operation. fourth WE# or CE#, whichever occurs first. The Program operation, once initiated, will be completed, within 20 µs. The actual completion of the nonvolatile write is asynchro- See Figures 6 and 7 for WE# and CE# controlled Program nous with the system; therefore, either a Data# Polling or operation timing diagrams and Figure 16 for flowcharts. Toggle Bit read may be simultaneous with the completion During the Program operation, the only valid reads are of the Write cycle. If this occurs, the system may possibly Data# Polling and Toggle Bit. During the internal Program get an erroneous result, i.e., valid data may appear to con- operation, the host is free to perform additional tasks. Any flict with either DQ or DQ . In order to prevent spurious 7 6 commands written during the internal Program operation rejection, if an erroneous result occurs, the software routine will be ignored. should include a loop to read the accessed location an additional two (2) times. If both reads are valid, then the device has completed the Write cycle, otherwise the rejec- Sector-Erase Operation tion is valid. The Sector-Erase operation allows the system to erase the device on a sector-by-sector basis. The sector architecture is based on uniform sector size of 4 KByte. The Sector- Erase operation is initiated by executing a six-byte com- mand load sequence for Software Data Protection with Sector-Erase command (30H) and sector address (SA) in the last bus cycle. The sector address is latched on the fall- ing edge of the sixth WE# pulse, while the command (30H) ©2010 Silicon Storage Technology, Inc. S71147-09-000 01/10 2 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39SF010A / SST39SF020A / SST39SF040 Data Sheet Data# Polling (DQ ) Software Data Protection (SDP) 7 When the SST39SF010A/020A/040 are in the internal Pro- The SST39SF010A/020A/040 provide the JEDEC gram operation, any attempt to read DQ will produce the approved Software Data Protection scheme for all data 7 complement of the true data. Once the Program operation alteration operations, i.e., Program and Erase. Any Pro- is completed, DQ will produce true data. Note that even gram operation requires the inclusion of a series of three- 7 though DQ may have valid data immediately following the byte sequence. The three-byte load sequence is used to 7 completion of an internal Write operation, the remaining initiate the Program operation, providing optimal protection data outputs may still be invalid: valid data on the entire from inadvertent Write operations, e.g., during the system data bus will appear in subsequent successive Read power-up or power-down. Any Erase operation requires the cycles after an interval of 1 µs. During internal Erase opera- inclusion of six-byte load sequence. The SST39SF010A/ tion, any attempt to read DQ will produce a ‘0’. Once the 020A/040 devices are shipped with the Software Data Pro- 7 internal Erase operation is completed, DQ will produce a tection permanently enabled. See Table 4 for the specific 7 ‘1’. The Data# Polling is valid after the rising edge of fourth software command codes. During SDP command WE# (or CE#) pulse for Program operation. For Sector- or sequence, invalid commands will abort the device to read Chip-Erase, the Data# Polling is valid after the rising edge mode, within T RC. of sixth WE# (or CE#) pulse. See Figure 8 for Data# Polling timing diagram and Figure 17 for a flowchart. Product Identification The Product Identification mode identifies the device as the Toggle Bit (DQ ) 6 SST39SF040, SST39SF010A, or SST39SF020A and During the internal Program or Erase operation, any con- manufacturer as SST. This mode may be accessed by soft- secutive attempts to read DQ will produce alternating 0s ware operations. Users may wish to use the software Prod- 6 and 1s, i.e., toggling between 0 and 1. When the internal uct Identification operation to identify the part (i.e., using the Program or Erase operation is completed, the toggling will device ID) when using multiple manufacturers in the same stop. The device is then ready for the next operation. The socket. For details, Table 4 for software operation, Figure Toggle Bit is valid after the rising edge of fourth WE# (or 12 for the software ID entry and read timing diagram and CE#) pulse for Program operation. For Sector- or Chip- Figure 18 for the ID entry command sequence flowchart. Erase, the Toggle Bit is valid after the rising edge of sixth WE# (or CE#) pulse. See Figure 9 for Toggle Bit timing dia- TABLE 1: Product Identification gram and Figure 17 for a flowchart. Address Data Manufacturer’s ID 0000H BFH Data Protection Device ID The SST39SF010A/020A/040 provide both hardware and SST39SF010A 0001H B5H software features to protect nonvolatile data from inadvert- SST39SF020A 0001H B6H ent writes. SST39SF040 0001H B7H T1.2 1147 Hardware Data Protection Noise/Glitch Protection: A WE# or CE# pulse of less than 5 Product Identification Mode Exit/Reset ns will not initiate a Write cycle. In order to return to the standard Read mode, the Software Product Identification mode must be exited. Exit is accom- V Power Up/Down Detection: The Write operation is DD plished by issuing the Exit ID command sequence, which inhibited when V is less than 2.5V. DD returns the device to the Read operation. Please note that Write Inhibit Mode: Forcing OE# low, CE# high, or WE# the software reset command is ignored during an internal high will inhibit the Write operation. This prevents inadvert- Program or Erase operation. See Table 4 for software com- ent writes during power-up or power-down. mand codes, Figure 13 for timing waveform and Figure 18 for a flowchart. ©2010 Silicon Storage Technology, Inc. S71147-09-000 01/10 3 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39SF010A / SST39SF020A / SST39SF040 Data Sheet SuperFlash X-Decoder Memory Memory Address Address Buffers & Latches Y-Decoder CE# I/O Buffers and Data Latches Control Logic OE# WE# DQ - DQ 7 0 1147 B1.2 FIGURE 1: Functional Block Diagram SST39SF040 SST39SF020A SST39SF010A SST39SF010A SST39SF020A SST39SF040 4 3 2 1 32 31 30 A7 A7 A7 5 29 A14 A14 A14 A6 A6 A6 6 28 A13 A13 A13 7 27 A5 A5 A5 A8 A8 A8 A4 A4 A4 8 26 A9 A9 A9 32-lead PLCC A3 A3 A3 9 25 A11 A11 A11 Top View 10 24 A2 A2 A2 OE# OE# OE# A1 A1 A1 11 23 A10 A10 A10 A0 A0 A0 12 22 CE# CE# CE# 13 21 DQ0 DQ0 DQ0 DQ7 DQ7 DQ7 14 15 16 17 18 19 20 1147 32-plcc P2.4 FIGURE 2: Pin Assignments for 32-lead PLCC ©2010 Silicon Storage Technology, Inc. S71147-09-000 01/10 4 SST39SF040 SST39SF020A SST39SF010A SST39SF010A SST39SF020A SST39SF040 DQ1 DQ1 DQ1 A12 A12 A12 DQ2 DQ2 DQ2 A15 A15 A15 V V V A16 A16 A16 SS SS SS DQ3 DQ3 DQ3 NC NC A18 DQ4 DQ4 DQ4 V V V DD DD DD DQ5 DQ5 DQ5 WE# WE# WE# DQ6 DQ6 DQ6 NC A17 A17 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39SF010A / SST39SF020A / SST39SF040 Data Sheet SST39SF040 SST39SF020A SST39SF010A SST39SF010A SST39SF020A SST39SF040 A11 A11 A11 1 32 OE# OE# OE# A9 A9 A9 2 31 A10 A10 A10 A8 A8 A8 3 30 CE# CE# CE# A13 A13 A13 4 29 DQ7 DQ7 DQ7 A14 A14 A14 DQ6 DQ6 DQ6 5 28 Standard Pinout A17 A17 NC 6 27 DQ5 DQ5 DQ5 WE# WE# WE# 7 26 DQ4 DQ4 DQ4 Top View V V V 8 25 DQ3 DQ3 DQ3 DD DD DD A18 NC NC 9 24 V V V SS SS SS Die Up A16 A16 A16 10 23 DQ2 DQ2 DQ2 A15 A15 A15 11 22 DQ1 DQ1 DQ1 A12 A12 A12 12 21 DQ0 DQ0 DQ0 A7 A7 A7 13 20 A0 A0 A0 A6 A6 A6 14 19 A1 A1 A1 A5 A5 A5 A2 A2 A2 15 18 A4 A4 A4 16 17 A3 A3 A3 1147 32-tsop P1.1 FIGURE 3: Pin Assignments for 32-lead TSOP (8mm x 14mm) SST39SF040 SST39SF020A SST39SF010A SST39SF010A SST39SF020A SST39SF040 1 32 A18 NC NC V V V DD DD DD A16 A16 A16 2 31 WE# WE# WE# A15 A15 A15 3 30 NC A17 A17 A12 A12 A12 4 29 A14 A14 A14 A7 A7 A7 5 28 A13 A13 A13 32-pin A6 A6 A6 6 27 A8 A8 A8 A5 A5 A5 7 PDIP 26 A9 A9 A9 A4 A4 A4 8 25 A11 A11 A11 Top View A3 A3 A3 9 24 OE# OE# OE# A2 A2 A2 10 23 A10 A10 A10 11 22 A1 A1 A1 CE# CE# CE# A0 A0 A0 12 21 DQ7 DQ7 DQ7 DQ0 DQ0 DQ0 13 20 DQ6 DQ6 DQ6 DQ1 DQ1 DQ1 14 19 DQ5 DQ5 DQ5 DQ2 DQ2 DQ2 15 18 DQ4 DQ4 DQ4 V V V 16 17 DQ3 DQ3 DQ3 SS SS SS 1147 32-pdip P3.2 FIGURE 4: Pin Assignments for 32-pin PDIP ©2010 Silicon Storage Technology, Inc. S71147-09-000 01/10 5 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39SF010A / SST39SF020A / SST39SF040 Data Sheet TABLE 2: Pin Description Symbol Pin Name Functions 1 A -A Address Inputs To provide memory addresses. MS 0 During Sector-Erase A -A address lines will select the sector. MS 12 DQ -DQ Data Input/output To output data during Read cycles and receive input data during Write cycles. 7 0 Data is internally latched during a Write cycle. The outputs are in tri-state when OE# or CE# is high. CE# Chip Enable To activate the device when CE# is low. OE# Output Enable To gate the data output buffers. WE# Write Enable To control the Write operations. V Power Supply To provide 5.0V supply (4.5-5.5V) DD V Ground SS NC No Connection Unconnected pins. T2.2 1147 1. A = Most significant address MS A = A for SST39SF010A, A for SST39SF020A, and A for SST39SF040 MS 16 17 18 TABLE 3: Operation Modes Selection Mode CE# OE# WE# DQ Address Read V V V D A IL IL IH OUT IN Program V V V D A IL IH IL IN IN 1 Erase V V V X Sector address, IL IH IL XXH for Chip-Erase Standby V X X High Z X IH Write Inhibit X V X High Z/ D X IL OUT XX V High Z/ D X IH OUT Product Identification Software Mode V V V See Table 4 IL IL IH T3.3 1147 1. X can be V or V , but no other value. IL IH ©2010 Silicon Storage Technology, Inc. S71147-09-000 01/10 6 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39SF010A / SST39SF020A / SST39SF040 Data Sheet TABLE 4: Software Command Sequence Command 1st Bus 2nd Bus 3rd Bus 4th Bus 5th Bus 6th Bus Sequence Write Cycle Write Cycle Write Cycle Write Cycle Write Cycle Write Cycle 1 1 1 1 1 1 Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data 2 Byte-Program 5555H AAH 2AAAH 55H 5555H A0H BA Data 3 Sector-Erase 5555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H SA 30H X Chip-Erase 5555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H 5555H 10H 4,5 Software ID Entry 5555H AAH 2AAAH 55H 5555H 90H 6 Software ID Exit XXH F0H 6 Software ID Exit 5555H AAH 2AAAH 55H 5555H F0H T4.2 1147 1. Address format A -A (Hex), Addresses A -A can be V or V , but no other value, for the Command sequence. 14 0 MS 15 IL IH A = Most significant address MS A = A for SST39SF010A, A for SST39SF020A, and A for SST39SF040 MS 16 17 18 2. BA = Program Byte address 3. SA for Sector-Erase; uses A -A address lines X MS 12 4. The device does not remain in Software Product ID mode if powered down. 5. With A -A = 0; SST Manufacturer’s ID = BFH, is read with A = 0, MS 1 0 SST39SF010A Device ID = B5H, is read with A = 1 0 SST39SF020A Device ID = B6H, is read with A = 1 0 SST39SF040 Device ID = B7H, is read with A = 1 0 6. Both Software ID Exit operations are equivalent Absolute Maximum Stress Ratings (Applied conditions greater than those listed under “Absolute Maximum Stress Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these conditions or conditions greater than those defined in the operational sections of this data sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.) Temperature Under Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55°C to +125°C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C D. C. Voltage on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.5V to V +0.5V DD Transient Voltage (<20 ns) on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-2.0V to V +2.0V DD Voltage on A Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 13.2V 9 Package Power Dissipation Capability (Ta = 25°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0W Through Hold Lead Soldering Temperature (10 Seconds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300°C Surface Mount Lead Soldering Temperature (3 Seconds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240°C 1 Output Short Circuit Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA 1. Outputs shorted for no more than one second. No more than one output shorted at a time. Operating Range Range Ambient Temp V DD Commercial 0°C to +70°C 4.5-5.5V Industrial -40°C to +85°C 4.5-5.5V AC Conditions of Test Input Rise/Fall Time . . . . . . . . . . . . . . 5 ns Output Load . . . . . . . . . . . . . . . . . . . . . C = 30 pF for 55 ns L Output Load . . . . . . . . . . . . . . . . . . . . . C = 100 pF for 70 ns L See Figures 14 and 15 ©2010 Silicon Storage Technology, Inc. S71147-09-000 01/10 7 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39SF010A / SST39SF020A / SST39SF040 Data Sheet 1 TABLE 5: DC Operating Characteristics V = 4.5-5.5V DD Limits Symbol Parameter Min Max Units Test Conditions I Power Supply Current Address input=V /V , at f=1/T Min DD ILT IHT RC V =V Max DD DD 2 Read 25 mA CE#=V , OE#=WE#=V , all I/Os open IL IH Program and Erase 35 mA CE#=WE#=V , OE#=V IL IH I Standby V Current 3mA CE#=V , V =V Max SB1 DD IH DD DD (TTL input) I Standby V Current 100 µA CE#=V , V =V Max SB2 DD IHC DD DD (CMOS input) I Input Leakage Current 1 µA V =GND to V , V =V Max LI IN DD DD DD I Output Leakage Current 10 µA V =GND to V , V =V Max LO OUT DD DD DD V Input Low Voltage 0.8 V V =V Min IL DD DD V Input High Voltage 2.0 V V =V Max IH DD DD V Input High Voltage (CMOS) V -0.3 V V =V Max IHC DD DD DD V Output Low Voltage 0.4 V I =2.1 mA, V =V Min OL OL DD DD V Output High Voltage 2.4 V I =-400 µA, V =V Min OH OH DD DD T5.10 1147 1. Typical conditions for the Active Current shown on the front data sheet page are average values at 25°C (room temperature), and V = 5V for SF devices. Not 100% tested. DD 2. Values are for 70 ns conditions. See the Multi-Purpose Flash Power Rating application note for further information. TABLE 6: Recommended System Power-up Timings Symbol Parameter Minimum Units 1 T Power-up to Read Operation 100 µs PU-READ 1 T Power-up to Program/Erase Operation 100 µs PU-WRITE T6.1 1147 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. TABLE 7: Capacitance (Ta = 25°C, f=1 Mhz, other pins open) Parameter Description Test Condition Maximum 1 C I/O Pin Capacitance V = 0V 12 pF I/O I/O 1 C Input Capacitance V = 0V 6 pF IN IN T7.0 1147 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. TABLE 8: Reliability Characteristics Symbol Parameter Minimum Specification Units Test Method 1,2 N Endurance 10,000 Cycles JEDEC Standard A117 END 1 T Data Retention 100 Years JEDEC Standard A103 DR 1 I Latch Up 100 + I mA JEDEC Standard 78 LTH DD T8.2 1147 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. 2. N endurance rating is qualified as a 10,000 cycle minimum for the whole device. A sector- or block-level rating would result in a END higher minimum specification. ©2010 Silicon Storage Technology, Inc. S71147-09-000 01/10 8 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39SF010A / SST39SF020A / SST39SF040 Data Sheet AC CHARACTERISTICS TABLE 9: Read Cycle Timing Parameters V = 4.5-5.5V DD SST39SF010A/020A/040-55 SST39SF010A/020A/040-70 Symbol Parameter Min Max Min Max Units T Read Cycle Time 55 70 ns RC T Chip Enable Access Time 55 70 ns CE T Address Access Time 55 70 ns AA T Output Enable Access Time 30 35 ns OE 1 T CE# Low to Active Output 0 0 ns CLZ 1 T OE# Low to Active Output 0 0 ns OLZ 1 T CE# High to High-Z Output 15 25 ns CHZ 1 T OE# High to High-Z Output 15 25 ns OHZ 1 T Output Hold from Address Change 0 0 ns OH T9.4 1147 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. TABLE 10: Program/Erase Cycle Timing Parameters Symbol Parameter Min Max Units T Byte-Program Time 20 µs BP T Address Setup Time 0 ns AS T Address Hold Time 30 ns AH T WE# and CE# Setup Time 0 ns CS T WE# and CE# Hold Time 0 ns CH T OE# High Setup Time 0 ns OES T OE# High Hold Time 10 ns OEH T CE# Pulse Width 40 ns CP T WE# Pulse Width 40 ns WP 1 T WE# Pulse Width High 30 ns WPH 1 T CE# Pulse Width High 30 ns CPH T Data Setup Time 40 ns DS 1 T Data Hold Time 0 ns DH 1 T Software ID Access and Exit Time 150 ns IDA T Sector-Erase 25 ms SE T Chip-Erase 100 ms SCE T10.1 1147 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. ©2010 Silicon Storage Technology, Inc. S71147-09-000 01/10 9 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39SF010A / SST39SF020A / SST39SF040 Data Sheet T T RC AA ADDRESS A MS-0 T CE CE# T OE OE# T T OHZ OLZ V IH WE# T T T CLZ OH CHZ HIGH-Z HIGH-Z DQ DATA VALID DATA VALID 7-0 1147 F03.1 Note: A = Most significant address MS A = A for SST39SF010A, A for SST39SF020A, and A for SST39SF040 MS 16 17 18 FIGURE 5: Read Cycle Timing Diagram INTERNAL PROGRAM OPERATION STARTS T BP 5555 2AAA 5555 ADDR ADDRESS A MS-0 T AH T T DH WP WE# T T T AS DS WPH OE# T CH CE# T CS DQ AA 55 A0 DATA 7-0 SW0 SW1 SW2 BYTE 1147 F04.1 (ADDR/DATA) Note: A = Most significant address MS A = A for SST39SF010A, A for SST39SF020A, and A for SST39SF040 MS 16 17 18 FIGURE 6: WE# Controlled Program Cycle Timing Diagram ©2010 Silicon Storage Technology, Inc. S71147-09-000 01/10 10 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39SF010A / SST39SF020A / SST39SF040 Data Sheet INTERNAL PROGRAM OPERATION STARTS T BP 5555 2AAA 5555 ADDR ADDRESS A MS-0 T AH T DH T CP CE# T T DS CPH T AS OE# T CH WE# T CS DQ AA 55 A0 DATA 7-0 SW0 SW1 SW2 BYTE 1147 F05.1 (ADDR/DATA) Note: A = Most significant address MS A = A for SST39SF010A, A for SST39SF020A, and A for SST39SF040 MS 16 17 18 FIGURE 7: CE# Controlled Program Cycle Timing Diagram ADDRESS A MS-0 T CE CE# T T OEH OES OE# T OE WE# DQ DD# D# D 7 1147 F06.1 Note: A = Most significant address MS A = A for SST39SF010A, A for SST39SF020A, and A for SST39SF040 MS 16 17 18 FIGURE 8: Data# Polling Timing Diagram ©2010 Silicon Storage Technology, Inc. S71147-09-000 01/10 11 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39SF010A / SST39SF020A / SST39SF040 Data Sheet ADDRESS A MS-0 T CE CE# T OEH T OES T OE OE# WE# Note DQ 6 TWO READ CYCLES WITH SAME OUTPUTS Note: Toggle bit output is always high first. A = Most significant address 1147 F07.1 MS A = A for SST39SF010A, A for SST39SF020A, and A for SST39SF040 MS 16 17 18 FIGURE 9: Toggle Bit Timing Diagram T SIX-BYTE CODE FOR SECTOR-ERASE SE 5555 2AAA 5555 5555 2AAA SA ADDRESS A X MS-0 CE# OE# T WP WE# DQ AA 55 80 AA 55 30 7-0 SW0 SW1 SW2 SW3 SW4 SW5 1147 F08.1 Note: This device also supports CE# controlled Sector-Erase operation. The WE# and CE# signals are interchageable as long as minimum timings are met. (See Table 10) SA = Sector Address X A = Most significant address MS A = A for SST39SF010A, A for SST39SF020A, and A for SST39SF040 MS 16 17 18 FIGURE 10: WE# Controlled Sector-Erase Timing Diagram ©2010 Silicon Storage Technology, Inc. S71147-09-000 01/10 12 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39SF010A / SST39SF020A / SST39SF040 Data Sheet T SIX-BYTE CODE FOR CHIP-ERASE SCE 5555 2AAA 5555 5555 2AAA 5555 ADDRESS A MS-0 CE# OE# T WP WE# AA 55 80 AA 55 10 DQ 7-0 SW0 SW1 SW2 SW3 SW4 SW5 1147 F17.1 Note: This device also supports CE# controlled Chip-Erase operation. The WE# and CE# signals are interchageable as long as minimum timings are met. (See Table 10) SA = Sector Address X A = Most significant address MS A = A for SST39SF010A, A for SST39SF020A, and A for SST39SF040 MS 16 17 18 FIGURE 11: WE# Controlled Chip-Erase Timing Diagram Three-byte Sequence for Software ID Entry ADDRESS A 5555 2AAA 5555 0000 0001 14-0 CE# OE# T IDA T WP WE# T WPH T AA AA 55 90 BF Device ID DQ 7-0 SW0 SW1 SW2 1147 F09.2 Device ID = B5H for SST39SF010A, B6H for SST39SF020A, and B7H for SST39SF040 FIGURE 12: Software ID Entry and Read ©2010 Silicon Storage Technology, Inc. S71147-09-000 01/10 13 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39SF010A / SST39SF020A / SST39SF040 Data Sheet THREE-BYTE SEQUENCE FOR SOFTWARE ID EXIT AND RESET 5555 2AAA 5555 ADDRESS A 14-0 DQ AA 55 F0 7-0 T IDA CE# OE# T WP WE# T WHP SW0 SW1 SW2 1147 F10.0 FIGURE 13: Software ID Exit and Reset ©2010 Silicon Storage Technology, Inc. S71147-09-000 01/10 14 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39SF010A / SST39SF020A / SST39SF040 Data Sheet V IHT V V INPUT REFERENCE POINTS OUTPUT IT OT V ILT 1147 F11.1 AC test inputs are driven at V (3.0V) for a logic “1” and V (0V) for a logic “0”. Measurement reference points for inputs IHT ILT and outputs are V (1.5V) and V (1.5V). Input rise and fall times (10% ↔ 90%) are <5 ns. IT OT Note: V - V Test IT INPUT V - V Test OT OUTPUT V - V HIGH Test IHT INPUT V - V LOW Test ILT INPUT FIGURE 14: AC Input/Output Reference Waveforms V DD TO TESTER R HIGH L TO DUT C R L L LOW 1147 F12.0 FIGURE 15: A Test Load Example ©2010 Silicon Storage Technology, Inc. S71147-09-000 01/10 15 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39SF010A / SST39SF020A / SST39SF040 Data Sheet Start Load data: AAH Address: 5555H Load data: 55H Address: 2AAAH Load data: A0H Address: 5555H Load Byte Address/Byte Data Wait for end of Program (T , BP Data# Polling bit, or Toggle bit operation) Program Completed 1147 F13.1 FIGURE 16: Byte-Program Algorithm ©2010 Silicon Storage Technology, Inc. S71147-09-000 01/10 16 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39SF010A / SST39SF020A / SST39SF040 Data Sheet Toggle Bit Data# Polling Internal Timer Byte Byte Byte Program/Erase Program/Erase Program/Erase Initiated Initiated Initiated Read DQ Read byte 7 Wait T , BP T T SCE, or SE Read same No Is DQ = 7 byte true data? Program/Erase Completed Yes No Does DQ 6 Program/Erase match? Completed Yes Program/Erase Completed 1147 F14.0 FIGURE 17: Wait Options ©2010 Silicon Storage Technology, Inc. S71147-09-000 01/10 17 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39SF010A / SST39SF020A / SST39SF040 Data Sheet Software Product ID Entry Software Product ID Exit & Command Sequence Reset Command Sequence Load data: AAH Load data: AAH Load data: F0H Address: 5555H Address: 5555H Address: XXH Load data: 55H Load data: 55H Wait T IDA Address: 2AAAH Address: 2AAAH Load data: 90H Load data: F0H Return to normal Address: 5555H Address: 5555H operation Wait T Wait T IDA IDA Return to normal Read Software ID operation 1147 F15.1 FIGURE 18: Software Product Command Flowcharts ©2010 Silicon Storage Technology, Inc. S71147-09-000 01/10 18 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39SF010A / SST39SF020A / SST39SF040 Data Sheet Chip-Erase Sector-Erase Command Sequence Command Sequence Load data: AAH Load data: AAH Address: 5555H Address: 5555H Load data: 55H Load data: 55H Address: 2AAAH Address: 2AAAH Load data: 80H Load data: 80H Address: 5555H Address: 5555H Load data: AAH Load data: AAH Address: 5555H Address: 5555H Load data: 55H Load data: 55H Address: 2AAAH Address: 2AAAH Load data: 10H Load data: 30H Address: 5555H Address: SA X Wait T Wait T SCE SE Chip erased Sector erased to FFH to FFH 1147 F16.1 FIGURE 19: Erase Command Sequence ©2010 Silicon Storage Technology, Inc. S71147-09-000 01/10 19 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39SF010A / SST39SF020A / SST39SF040 Data Sheet PRODUCT ORDERING INFORMATION SST 39 SF 010A - 70 - 4C - NH E XX XXXXXX -XX -XX - XXX X Environmental Attribute E = non-Pb Package Modifier H = 32 pins or leads Package Type N = PLCC P = PDIP W = TSOP (type 1, die up, 8mm x 14mm) Temperature Range C = Commercial = 0°C to +70°C I = Industrial = -40°C to +85°C Minimum Endurance 4 = 10,000 cycles Read Access Speed 55 = 55 ns 70 = 70 ns Version A = Special Feature Version Device Density 040 = 4 Mbit 020 = 2 Mbit 010 = 1 Mbit Voltage S = 4.5-5.5V Product Series 39 = Multi-Purpose Flash ©2010 Silicon Storage Technology, Inc. S71147-09-000 01/10 20 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39SF010A / SST39SF020A / SST39SF040 Data Sheet Valid combinations for SST39SF010A SST39SF010A-55-4C-NHE SST39SF010A-55-4C-WHE SST39SF010A-70-4C-NHE SST39SF010A-70-4C-WHE SST39SF010A-70-4C-PHE SST39SF010A-55-4I-NHE SST39SF010A-55-4I-WHE SST39SF010A-70-4I-NHE SST39SF010A-70-4I-WHE Valid combinations for SST39SF020A SST39SF020A-55-4C-NHE SST39SF020A-55-4C-WHE SST39SF020A-70-4C-NHE SST39SF020A-70-4C-WHE SST39SF020A-70-4C-PHE SST39SF020A-55-4I-NHE SST39SF020A-55-5I-WHE SST39SF020A-70-4I-NHE SST39SF020A-70-4I-WHE Valid combinations for SST39SF040 SST39SF040-55-4C-NHE SST39SF040-55-4C-WHE SST39SF040-70-4C-NHE SST39SF040-70-4C-WHE SST39SF040-70-4C-PHE SST39SF040-55-4I-NHE SST39SF040-55-4I-WHE SST39SF040-70-4I-NHE SST39SF040-70-4I-WHE Note: Valid combinations are those products in mass production or will be in mass production. Consult your SST sales representative to confirm availability of valid combinations and to determine availability of new combinations. ©2010 Silicon Storage Technology, Inc. S71147-09-000 01/10 21 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39SF010A / SST39SF020A / SST39SF040 Data Sheet PACKAGING DIAGRAMS TOP VIEW SIDE VIEW BOTTOM VIEW .495 .485 .112 .453 Optional .106 .447 Pin #1 .048 .029 .020 R. .040 Identifier x 30˚ R. .042 .023 23 1 2 MAX. .030 .042 .021 .048 .013 .400 .530 .595 .553 .032 BSC .490 .585 .547 .026 .050 BSC .015 Min. .095 .075 .050 .032 BSC .140 .026 .125 Note: 1. Complies with JEDEC publication 95 MS-016 AE dimensions, although some dimensions may be more stringent. 2. All linear dimensions are in inches (max/min). 3. Dimensions do not include mold flash. Maximum allowable mold flash is .008 inches. 32-plcc-NH-3 4. Coplanarity: 4 mils. FIGURE 20: 32-lead Plastic Lead Chip Carrier (PLCC) SST Package Code: NH ©2010 Silicon Storage Technology, Inc. S71147-09-000 01/10 22 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39SF010A / SST39SF020A / SST39SF040 Data Sheet 1.05 0.95 Pin # 1 Identifier 0.50 BSC 8.10 0.27 7.90 0.17 0.15 12.50 0.05 12.30 DETAIL 1.20 max. 0.70 0.50 14.20 13.80 0˚- 5˚ 0.70 0.50 Note: 1. Complies with JEDEC publication 95 MO-142 BA dimensions, although some dimensions may be more stringent. 32-tsop-WH-7 1mm 2. All linear dimensions are in millimeters (max/min). 3. Coplanarity: 0.1 mm 4. Maximum allowable mold flash is 0.15 mm at the package ends, and 0.25 mm between leads. FIGURE 21: 32-lead Thin Small Outline Package (TSOP) 8mm x 14mm SST Package Code: WH ©2010 Silicon Storage Technology, Inc. S71147-09-000 01/10 23 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39SF010A / SST39SF020A / SST39SF040 Data Sheet 32 C L 1 Pin #1 Identifier .625 .600 .550 .530 1.655 .075 7˚ 1.645 .065 4 PLCS. Base .200 Plane .170 Seating Plane .050 0˚ .015 .012 15˚ .008 .150 .120 .100 BSC .022 .080 .600 BSC .065 .016 .070 .045 Note: 1. Complies with JEDEC publication 95 MO-015 AP dimensions, although some dimensions may be more stringent. 2. All linear dimensions are in inches (max/min). 3. Dimensions do not include mold flash. Maximum allowable mold flash is .010 inches. 32-pdip-PH-3 FIGURE 22: 32-pin Plastic Dual In-line Pins (PDIP) SST Package Code: PH ©2010 Silicon Storage Technology, Inc. S71147-09-000 01/10 24 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39SF010A / SST39SF020A / SST39SF040 Data Sheet TABLE 11: Revision History Number Description Date 022002 Data Book May 2002 03Changes to Table 5 on page 8 Mar 2003 – Added footnote for MPF power usage and Typical conditions – Clarified the Test Conditions for Power Supply Current and Read parameters – Clarified I Write to be Program and Erase DD 04Document status changed from “Preliminary Specification” to “Data Sheet” Oct 2003 Changed I Program and Erase max values from 25 to 35 in Table 5 on page 8 DD 05 Nov 20032004 Data Book Added non-Pb MPNs and removed footnote (See page 21) 06Corrected Revision History for Version 04: Aug 2004 I max value was incorrectly stated as 30 mA instead of 35 mA DD 07Removed leaded parts from valid combinations. See PSN-D0PB0001 Mar 2009 08Changed endurance from 10,000 to 100,000 in Product Description, page 1 Sep 2009 09End of Life for all 45 ns valid combinations. See S71147(02). Jan 2010 Added replacement 55 ns valid combinations Silicon Storage Technology, Inc. 1171 Sonora Court Sunnyvale, CA 94086 Telephone 408-735-9110 Fax 408-735-9036 www.SuperFlash.com or www.sst.com ©2010 Silicon Storage Technology, Inc. S71147-09-000 01/10 25