2 Mbit (256K x8) Page-Mode EEPROM SST29EE020 / SST29LE020 / SST29VE020 SST29EE020 / SST29LE020 / SST29VE0202 Mb Page-Mode flash memories Data Sheet FEATURES: • Single Voltage Read and Write OperationsLatched Address and Data – 5.0V-only for SST29EE020Automatic Write Timing – 3.0-3.6V for SST29LE020 – Internal V Generation PP – 2.7-3.6V for SST29VE020 End of Write Detection Superior Reliability – Toggle Bit – Endurance: 100,000 Cycles (typical) – Data# Polling – Greater than 100 years Data Retention Hardware and Software Data Protection Low Power Consumption Product Identification can be accessed via – Active Current: 20 mA (typical) for 5V and Software Operation 10 mA (typical) for 3.0/2.7V TTL I/O Compatibility – Standby Current: 10 µA (typical) JEDEC Standard Fast Page-Write Operation – Flash EEPROM Pinouts and command sets – 128 Bytes per Page, 2048 Pages Packages Available – Page-Write Cycle: 5 ms (typical) – Complete Memory Rewrite: 10 sec (typical) – 32-lead PLCC – Effective Byte-Write Cycle Time: 39 µs (typical) – 32-lead TSOP (8mm x 14mm, 8mm x 20mm) – 32-pin PDIPFast Read Access Time – 5.0V-only operation: 120 and 150 ns – 3.0-3.6V operation: 200 and 250 ns – 2.7-3.6V operation: 200 and 250 ns PRODUCT DESCRIPTION The SST29EE/LE/VE020 are 256K x8 CMOS Page-Write The SST29EE/LE/VE020 are suited for applications that EEPROM manufactured with SST’s proprietary, high per- require convenient and economical updating of program, formance CMOS SuperFlash technology. The split-gate configuration, or data memory. For all system applications, cell design and thick oxide tunneling injector attain better the SST29EE/LE/VE020 significantly improve performance reliability and manufacturability compared with alternate and reliability, while lowering power consumption. The approaches. The SST29EE/LE/VE020 write with a single SST29EE/LE/VE020 improve flexibility while lowering the power supply. Internal Erase/Program is transparent to the cost for program, data, and configuration storage applica- user. The SST29EE/LE/VE020 conform to JEDEC stan- tions. dard pinouts for byte-wide memories. To meet high density, surface mount requirements, the Featuring high performance Page-Write, the SST29EE/LE/ SST29EE/LE/VE020 are offered in 32-lead PLCC and 32- VE020 provide a typical Byte-Write time of 39 µsec. The lead TSOP packages. A 600-mil, 32-pin PDIP package is entire memory, i.e., 256 KBytes, can be written page-by- also available. See Figures 1, 2, and 3 for pinouts. page in as little as 10 seconds, when using interface fea- tures such as Toggle Bit or Data# Polling to indicate the Device Operation completion of a Write cycle. To protect against inadvertent The SST Page-Mode EEPROM offers in-circuit electrical write, the SST29EE/LE/VE020 have on-chip hardware and write capability. The SST29EE/LE/VE020 does not require Software Data Protection schemes. Designed, manufac- separate Erase and Program operations. The internally tured, and tested for a wide spectrum of applications, the timed Write cycle executes both erase and program trans- SST29EE/LE/VE020 are offered with a guaranteed Page- parently to the user. The SST29EE/LE/VE020 have indus- Write endurance of 10,000 cycles. Data retention is rated at try standard optional Software Data Protection, which SST greater than 100 years. recommends always to be enabled. The SST29EE/LE/ VE020 are compatible with industry standard EEPROM pinouts and functionality. ©2001 Silicon Storage Technology, Inc. The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc. S71062-06-000 6/01 307 SSF is a trademark of Silicon Storage Technology, Inc. 1 These specifications are subject to change without notice. 2 Mbit Page-Mode EEPROM SST29EE020 / SST29LE020 / SST29VE020 Data Sheet consists of a specific three-byte load sequence that allows Read writing to the selected page and will leave the SST29EE/ The Read operations of the SST29EE/LE/VE020 are con- LE/VE020 protected at the end of the Page-Write. The trolled by CE# and OE#, both have to be low for the system page load cycle consists of loading 1 to 128 Bytes of data to obtain data from the outputs. CE# is used for device into the page buffer. The internal Write cycle consists of the selection. When CE# is high, the chip is deselected and T time-out and the write timer operation. During the BLCO only standby power is consumed. OE# is the output control Write operation, the only valid reads are Data# Polling and and is used to gate data from the output pins. The data bus Toggle Bit. is in high impedance state when either CE# or OE# is high. Refer to the Read cycle timing diagram for further details The Page-Write operation allows the loading of up to 128 (Figure 4). bytes of data into the page buffer of the SST29EE/LE/ VE020 before the initiation of the internal Write cycle. Dur- ing the internal Write cycle, all the data in the page buffer is Write written simultaneously into the memory array. Hence, the The Page-Write to the SST29EE/LE/VE020 should always Page-Write feature of SST29EE/LE/VE020 allow the entire use the JEDEC Standard Software Data Protection (SDP) memory to be written in as little as 10 seconds. During the three-byte command sequence. The SST29EE/LE/VE020 internal Write cycle, the host is free to perform additional contain the optional JEDEC approved Software Data Pro- tasks, such as to fetch data from other locations in the sys- tection scheme. SST recommends that SDP always be tem to set up the write to the next page. In each Page-Write enabled, thus, the description of the write operations will be operation, all the bytes that are loaded into the page buffer given using the SDP enabled format. The three-byte SDP must have the same page address, i.e. A through A . Any 7 16 Enable and SDP Write commands are identical; therefore, byte not loaded with user data will be written to FFH. any time a SDP Write command is issued, Software Data See Figures 5 and 6 for the Page-Write cycle timing dia- Protection is automatically assured. The first time the three- grams. If after the completion of the three-byte SDP load byte SDP command is given, the device becomes SDP sequence or the initial byte-load cycle, the host loads a sec- enabled. Subsequent issuance of the same command ond byte into the page buffer within a byte-load cycle time bypasses the data protection for the page being written. At (T ) of 100 µs, the SST29EE/LE/VE020 will stay in the the end of the desired Page-Write, the entire device BLC page load cycle. Additional bytes are then loaded consecu- remains protected. For additional descriptions, please see tively. The page load cycle will be terminated if no addi- the application notes The Proper Use of JEDEC Standard tional byte is loaded into the page buffer within 200 µs Software Data Protection and Protecting Against Uninten- (T ) from the last byte-load cycle, i.e., no subsequent tional Writes When Using Single Power Supply Flash BLCO WE# or CE# high-to-low transition after the last rising edge Memories. of WE# or CE#. Data in the page buffer can be changed by The Write operation consists of three steps. Step 1 is the a subsequent byte-load cycle. The page load period can three-byte load sequence for Software Data Protection. continue indefinitely, as long as the host continues to load Step 2 is the byte-load cycle to a page buffer of the the device within the byte-load cycle time of 100 µs. The SST29EE/LE/VE020. Steps 1 and 2 use the same timing page to be loaded is determined by the page address of for both operations. Step 3 is an internally controlled Write the last byte loaded. cycle for writing the data loaded in the page buffer into the memory array for nonvolatile storage. During both the SDP Software Chip-Erase three-byte load sequence and the byte-load cycle, the addresses are latched by the falling edge of either CE# or The SST29EE/LE/VE020 provide a Chip-Erase operation, WE#, whichever occurs last. The data is latched by the ris- which allows the user to simultaneously clear the entire ing edge of either CE# or WE#, whichever occurs first. The memory array to the “1” state. This is useful when the entire internal Write cycle is initiated by the T timer after the device must be quickly erased. BLCO rising edge of WE# or CE#, whichever occurs first. The The Software Chip-Erase operation is initiated by using a Write cycle, once initiated, will continue to completion, typi- specific six-byte load sequence. After the load sequence, cally within 5 ms. See Figures 5 and 6 for WE# and CE# the device enters into an internally timed cycle similar to the controlled Page-Write cycle timing diagrams and Figures Write cycle. During the Erase operation, the only valid read 15 and 17 for flowcharts. is Toggle Bit. See Table 4 for the load sequence, Figure 10 The Write operation has three functional cycles: the Soft- for timing diagram, and Figure 19 for the flowchart. ware Data Protection load sequence, the page load cycle, and the internal Write cycle. The Software Data Protection ©2001 Silicon Storage Technology, Inc. S71062-06-000 6/01 307 2 2 Mbit Page-Mode EEPROM SST29EE020 / SST29LE020 / SST29VE020 Data Sheet Write Inhibit Mode: Forcing OE# low, CE# high, or WE# Write Operation Status Detection high will inhibit the Write operation. This prevents inadvert- The SST29EE/LE/VE020 provide two software means to ent writes during power-up or power-down. detect the completion of a Write cycle, in order to optimize the system Write cycle time. The software detection Software Data Protection (SDP) includes two status bits: Data# Polling (DQ ) and Toggle Bit 7 (DQ ). The end of write detection mode is enabled after the 6 The SST29EE/LE/VE020 provide the JEDEC approved rising WE# or CE# whichever occurs first, which initiates optional Software Data Protection scheme for all data alter- the internal Write cycle. ation operations, i.e., Write and Chip-Erase. With this scheme, any Write operation requires the inclusion of a The actual completion of the nonvolatile write is asynchro- series of three byte-load operations to precede the data nous with the system; therefore, either a Data# Polling or loading operation. The three byte-load sequence is used to Toggle Bit read may be simultaneous with the completion initiate the Write cycle, providing optimal protection from of the Write cycle. If this occurs, the system may possibly inadvertent write operations, e.g., during the system power- get an erroneous result, i.e., valid data may appear to con- up or power-down. The SST29EE/LE/VE020 are shipped flict with either DQ or DQ . In order to prevent spurious 7 6 with the Software Data Protection disabled. rejection, if an erroneous result occurs, the software routine should include a loop to read the accessed location an The software protection scheme can be enabled by apply- additional two (2) times. If both reads are valid, then the ing a three-byte sequence to the device, during a page- device has completed the Write cycle, otherwise the rejec- load cycle (Figures 5 and 6). The device will then be auto- tion is valid. matically set into the data protect mode. Any subsequent Write operation will require the preceding three-byte sequence. See Table 4 for the specific software command Data# Polling (DQ ) 7 codes and Figures 5 and 6 for the timing diagrams. To set When the SST29EE/LE/VE020 are in the internal Write the device into the unprotected mode, a six-byte sequence cycle, any attempt to read DQ of the last byte loaded dur- 7 is required. See Table 4 for the specific codes and Figure 9 ing the byte-load cycle will receive the complement of the for the timing diagram. If a write is attempted while SDP is true data. Once the Write cycle is completed, DQ will 7 enabled the device will be in a non-accessible state for show true data. The device is then ready for the next opera- ~300µs. SST recommends Software Data Protection tion. See Figure 7 for Data# Polling timing diagram and Fig- always be enabled. See Figure 17 for flowcharts. ure 16 for a flowchart. The SST29EE/LE/VE020 Software Data Protection is a global command, protecting all pages in the entire memory Toggle Bit (DQ ) 6 array once enabled (or disabled). Therefore using SDP for During the internal Write cycle, any consecutive attempts to a single Page-Write will enable SDP for the entire array. read DQ will produce alternating 0s and 1s, i.e., toggling 6 Single pages by themselves cannot be SDP enabled or between 0 and 1. When the Write cycle is completed, the disabled. toggling will stop. The device is then ready for the next Single power supply reprogrammable nonvolatile memo- operation. See Figure 8 for Toggle Bit timing diagram and ries may be unintentionally altered. SST strongly recom- Figure 16 for a flowchart. The initial read of the Toggle Bit mends that Software Data Protection (SDP) always be will typically be a “1”. enabled. The SST29EE/LE/VE020 should be programmed using the SDP command sequence. SST recommends the Data Protection SDP Disable Command Sequence not be issued to the The SST29EE/LE/VE020 provide both hardware and soft- device prior to writing. ware features to protect nonvolatile data from inadvertent Please refer to the following Application Notes for more writes. information on using SDP: Protecting Against Unintentional Writes When Hardware Data Protection Using Single Power Supply Flash Memories Noise/Glitch Protection: A WE# or CE# pulse of less than 5 The Proper Use of JEDEC Standard Software ns will not initiate a Write cycle. Data Protection V Power Up/Down Detection: The Write operation is DD inhibited when V is less than 2.5V. DD ©2001 Silicon Storage Technology, Inc. S71062-06-000 6/01 307 3 2 Mbit Page-Mode EEPROM SST29EE020 / SST29LE020 / SST29VE020 Data Sheet Product Identification Product Identification Mode Exit The product identification mode identifies the device as the In order to return to the standard read mode, the Software SST29EE/LE/VE020 and manufacturer as SST. This mode Product Identification mode must be exited. Exiting is is accessed via software. For details, see Table 4, Figure accomplished by issuing the Software ID Exit (reset) opera- 11 for the software ID entry and read timing diagram, and tion, which returns the device to the Read operation. The Figure 18 for the ID entry command sequence flowchart. Reset operation may also be used to reset the device to the Read mode after an inadvertent transient condition that apparently causes the device to behave abnormally, e.g., TABLE 1: PRODUCT IDENTIFICATION not read correctly. See Table 4 for software command Address Data codes, Figure 12 for timing waveform, and Figure 18 for a Manufacturer’s ID 0000H BFH flowchart. Device ID SST29EE020 0001H 10H SST29LE020 0001H 12H SST29VE020 0001H 12H T1.3 307 FUNCTIONAL BLOCK DIAGRAM SuperFlash X-Decoder Memory A - A 17 0 Address Buffer & Latches Y-Decoder and Page Latches CE# Control Logic OE# I/O Buffers and Data Latches WE# DQ - DQ 7 0 307 ILL B1.1 4 3 2 1 32 31 30 5 29 A7 A14 A6 6 28 A13 A5 7 27 A8 8 26 A4 A9 32-lead PLCC A3 9 25 A11 Top View A2 10 24 OE# A1 11 23 A10 12 22 A0 CE# DQ0 13 21 DQ7 14 15 16 17 18 19 20 307 ILL F02.3 FIGURE 1: PIN ASSIGNMENTS FOR 32-LEAD PLCC ©2001 Silicon Storage Technology, Inc. S71062-06-000 6/01 307 4 DQ1 A12 A15 DQ2 V A16 SS DQ3 NC V DQ4 DD DQ5 WE# DQ6 A17 2 Mbit Page-Mode EEPROM SST29EE020 / SST29LE020 / SST29VE020 Data Sheet A11 1 32 OE# A9 2 31 A10 A8 CE# 3 30 A13 4 29 DQ7 A14 5 28 DQ6 A17 6 Standard Pinout 27 DQ5 WE# 7 26 DQ4 Top View V 8 25 DQ3 DD NC 9 24 V SS Die Up A16 10 23 DQ2 A15 11 22 DQ1 A12 12 21 DQ0 A7 A0 13 20 A6 14 19 A1 A5 15 18 A2 A4 16 17 A3 307 ILL F01.2 FIGURE 2: PIN ASSIGNMENTS FOR 32-LEAD TSOP NC 1 32 V DD A16 2 31 WE# A15 3 30 A17 A12 4 29 A14 A7 5 28 A13 32-pin 6 27 A6 A8 7 PDIP 26 A5 A9 A4 8 25 A11 Top View A3 9 24 OE# A2 10 23 A10 A1 11 22 CE# A0 12 21 DQ7 DQ0 13 20 DQ6 DQ1 14 19 DQ5 DQ2 15 18 DQ4 16 17 V DQ3 SS 307 ILL F19.0 FIGURE 3: PIN ASSIGNMENTS FOR 32-PIN PDIP TABLE 2: PIN DESCRIPTION Symbol Pin Name Functions A -A Row Address Inputs To provide memory addresses. Row addresses define a page for a Write cycle. 17 7 A -A Column Address Inputs Column Addresses are toggled to load page data 6 0 DQ -DQ Data Input/output To output data during Read cycles and receive input data during Write cycles. 7 0 Data is internally latched during a Write cycle. The outputs are in tri-state when OE# or CE# is high. CE# Chip Enable To activate the device when CE# is low. OE# Output Enable To gate the data output buffers. WE# Write Enable To control the Write operations. V Power Supply To provide: 5.0V supply (±10%) for SST29EE020 DD 3.0V supply (3.0-3.6V) for SST29LE020 2.7V supply (2.7-3.6V) for SST29VE020 V Ground SS NC No Connection Unconnected pins. T2.2 307 ©2001 Silicon Storage Technology, Inc. S71062-06-000 6/01 307 5 2 Mbit Page-Mode EEPROM SST29EE020 / SST29LE020 / SST29VE020 Data Sheet TABLE 3: OPERATION MODES SELECTION Mode CE# OE# WE# DQ Address Read V V V D A IL IL IH OUT IN Page-Write V V V D A IL IH IL IN IN 1 Standby V X XHigh Z X IH Write Inhibit X V XHigh Z/ D X IL OUT XX V High Z/ D X IH OUT Software Chip-Erase V V V D A See Table 4 IL IH IL IN IN, Product Identification Software Mode V V V Manufacturer’s ID (BFH) See Table 4 IL IH IL 2 Device ID SDP Enable Mode V V V See Table 4 IL IH IL SDP Disable Mode V V V See Table 4 IL IH IL T3.3 307 1. X can be V or V , but no other value IL IH 2. Device ID = 10H for SST29EE020 and 12H for SST29LE/VE020 TABLE 4: SOFTWARE COMMAND SEQUENCE Command 1st Bus 2nd Bus 3rd Bus 4th Bus 5th Bus 6th Bus Sequence Write Cycle Write Cycle Write Cycle Write Cycle Write Cycle Write Cycle 1 1 1 1 1 1 Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data 2 Software 5555H AAH 2AAAH 55H 5555H A0H Addr Data Data Protect Enable & Page-Write Software 5555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H 5555H 20H Data Protect Disable 3 Software Chip-Erase 5555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H 5555H 10H 4,5 Software ID Entry 5555H AAH 2AAAH 55H 5555H 90H Software ID Exit 5555H AAH 2AAAH 55H 5555H F0H Alternate 5555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H 5555H 60H 6 Software ID Entry T4.2 307 1. Address format A -A (Hex), Address A can be V or V , but no other value. 14 0 15 IL IH 2. Page-Write consists of loading up to 128 Bytes (A -A ) 6 0 3. The software Chip-Erase function is not supported by the industrial temperature part. Please contact SST if you require this function for an industrial temperature part. 4. The device does not remain in Software Product ID Mode if powered down. 5. With A -A =0; SST Manufacturer’s ID= BFH, is read with A = 0, 14 1 0 SST29EE020 Device ID = 10H, is read with A = 1 0 SST29LE/VE020 Device ID = 12H, is read with A = 1 0 6. Alternate six-byte Software Product ID Command Code Note: This product supports both the JEDEC standard three-byte command code sequence and SST’s original six-byte command code sequence. For new designs, SST recommends that the three-byte command code sequence be used. ©2001 Silicon Storage Technology, Inc. S71062-06-000 6/01 307 6 2 Mbit Page-Mode EEPROM SST29EE020 / SST29LE020 / SST29VE020 Data Sheet Absolute Maximum Stress Ratings (Applied conditions greater than those listed under “Absolute Maximum Stress Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these conditions or conditions greater than those defined in the operational sections of this data sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.) Temperature Under Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55°C to +125°C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C D. C. Voltage on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.5V to V + 0.5V DD Transient Voltage (<20 ns) on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . .-1.0V to V + 1.0V DD Voltage on A Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 14.0V 9 Package Power Dissipation Capability (Ta = 25°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0W Through Hold Lead Soldering Temperature (10 Seconds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300°C Surface Mount Lead Soldering Temperature (3 Seconds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240°C 1 Output Short Circuit Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA 1. Outputs shorted for no more than one second. No more than one output shorted at a time. OPERATING RANGE FOR SST29EE020 Range Ambient Temp V DD Commercial 0°C to +70°C5.0V±10% Industrial -40°C to +85°C5.0V±10% OPERATING RANGE FOR SST29LE020 Range Ambient Temp V DD Commercial 0°C to +70°C 3.0-3.6V Industrial -40°C to +85°C 3.0-3.6V OPERATING RANGE FOR SST29VE020 Range Ambient Temp V DD Commercial 0°C to +70°C 2.7-3.6V Industrial -40°C to +85°C 2.7-3.6V AC CONDITIONS OF TEST Input Rise/Fall Time . . . . . . . . . . . . . . 10 ns Output Load . . . . . . . . . . . . . . . . . . . . . 1 TTL Gate and C = 100 pF L See Figures 13 and 14 ©2001 Silicon Storage Technology, Inc. S71062-06-000 6/01 307 7 2 Mbit Page-Mode EEPROM SST29EE020 / SST29LE020 / SST29VE020 Data Sheet TABLE 5: DC OPERATING CHARACTERISTICS V = 5.0V±10% FOR SST29EE020 DD Limits Symbol Parameter Min Max Units Test Conditions I Power Supply Current Address input=V /V , at f=1/T Min, DD IL IH RC V =V Max DD DD Read 30 mA CE#=OE#=V , WE#=V , all I/Os open IL IH Write 50 mA CE#=WE#=V , OE#=V , V =V Max IL IH DD DD I Standby V Current 3 mA CE#=OE#=WE#=V , V =V Max SB1 DD IH DD DD (TTL input) I Standby V Current 50 µA CE#=OE#=WE#=V -0.3V, V =V Max SB2 DD DD DD DD (CMOS input) I Input Leakage Current 1µA V =GND to V , V =V Max LI IN DD DD DD I Output Leakage Current 10 µA V =GND to V , V =V Max LO OUT DD DD DD V Input Low Voltage 0.8 V V =V Min IL DD DD V Input High Voltage 2.0 V V =V Max IH DD DD V Output Low Voltage 0.4 V I =2.1 mA, V =V Min OL OL DD DD V Output High Voltage 2.4 V I =-400 µA, V =V Min OH OH DD DD T5.2 307 TABLE 6: DC OPERATING CHARACTERISTICS V = 3.0-3.6V FOR SST29LE020 AND 2.7-3.0V FOR SST29VE020 DD Limits Symbol Parameter Min Max Units Test Conditions I Power Supply Current Address input=V /V , at f=1/T Min, DD IL IH RC V =V Max DD DD Read 12 mA CE#=OE#=V , WE#=V , all I/Os open IL IH Write 15 mA CE#=WE#=V , OE#=V , V =V Max IL IH DD DD I Standby V Current 1 mA CE#=OE#=WE#=V , V =V Max SB1 DD IH DD DD (TTL input) I Standby V Current 15 µA CE#=OE#=WE#=V -0.3V, V =V Max SB2 DD DD DD DD (CMOS input) I Input Leakage Current 1µA V =GND to V , V =V Max LI IN DD DD DD I Output Leakage Current 10 µA V =GND to V , V =V Max LO OUT DD DD DD V Input Low Voltage 0.8 V V =V Min IL DD DD V Input High Voltage 2.0 V V =V Max IH DD DD V Output Low Voltage 0.4 V I =100 µA, V =V Min OL OL DD DD V Output High Voltage 2.4 V I =-100 µA, V =V Min OH OH DD DD T6.2 307 ©2001 Silicon Storage Technology, Inc. S71062-06-000 6/01 307 8 2 Mbit Page-Mode EEPROM SST29EE020 / SST29LE020 / SST29VE020 Data Sheet TABLE 7: RECOMMENDED SYSTEM POWER-UP TIMINGS Symbol Parameter Minimum Units 1 T Power-up to Read Operation 100 µs PU-READ 1 T Power-up to Write Operation 5 ms PU-WRITE T7.1 307 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. TABLE 8: CAPACITANCE (Ta = 25°C, f=1 Mhz, other pins open) Parameter Description Test Condition Maximum 1 C I/O Pin Capacitance V = 0V 12 pF I/O I/O 1 C Input Capacitance V = 0V 6 pF IN IN T8.0 307 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. TABLE 9: RELIABILITY CHARACTERISTICS Symbol Parameter Minimum Specification Units Test Method 1 N Endurance 10,000 Cycles JEDEC Standard A117 END 1 T Data Retention 100 Years JEDEC Standard A103 DR 1 I Latch Up 100 mA JEDEC Standard 78 LTH T9.5 307 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. ©2001 Silicon Storage Technology, Inc. S71062-06-000 6/01 307 9 2 Mbit Page-Mode EEPROM SST29EE020 / SST29LE020 / SST29VE020 Data Sheet AC CHARACTERISTICS TABLE 10: READ CYCLE TIMING PARAMETERS FOR SST29EE020 SST29EE020-120 SST29EE020-150 Symbol Parameter Min Max Min Max Units T Read Cycle Time 120 150 ns RC T Chip Enable Access Time 120 150 ns CE T Address Access Time 120 150 ns AA T Output Enable Access Time 50 60 ns OE 1 T CE# Low to Active Output 0 0 ns CLZ 1 T OE# Low to Active Output 0 0 ns OLZ 1 T CE# High to High-Z Output 30 30 ns CHZ 1 T OE# High to High-Z Output 30 30 ns OHZ 1 T Output Hold from Address Change 0 0 ns OH T10.4 307 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. TABLE 11: READ CYCLE TIMING PARAMETERS FOR SST29LE020 SST29LE020-200 SST29LE020-250 Symbol Parameter MinMax MinMax Units T Read Cycle Time 200 250 ns RC T Chip Enable Access Time 200 250 ns CE T Address Access Time 200 250 ns AA T Output Enable Access Time 100 120 ns OE 1 T CE# Low to Active Output 0 0 ns CLZ 1 T OE# Low to Active Output 0 0 ns OLZ 1 T CE# High to High-Z Output 50 50 ns CHZ 1 T OE# High to High-Z Output 50 50 ns OHZ 1 T Output Hold from Address Change 0 0 ns OH T11.1 307 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. TABLE 12: READ CYCLE TIMING PARAMETERS FOR SST29VE020 SST29VE020-200 SST29VE020-250 Symbol Parameter MinMax MinMax Units T Read Cycle Time 200 250 ns RC T Chip Enable Access Time 200 250 ns CE T Address Access Time 200 250 ns AA T Output Enable Access Time 100 120 ns OE 1 T CE# Low to Active Output 0 0 ns CLZ 1 T OE# Low to Active Output 0 0 ns OLZ 1 T CE# High to High-Z Output 50 50 ns CHZ 1 T OE# High to High-Z Output 50 50 ns OHZ 1 T Output Hold from Address Change 0 0 ns OH T12.1 307 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. ©2001 Silicon Storage Technology, Inc. S71062-06-000 6/01 307 10 2 Mbit Page-Mode EEPROM SST29EE020 / SST29LE020 / SST29VE020 Data Sheet TABLE 13: PAGE-WRITE CYCLE TIMING PARAMETERS SST29EE020 SST29LE/VE020 Symbol Parameter Min Max Min Max Units T Write Cycle (Erase and Program) 10 10 ms WC T Address Setup Time 0 0 ns AS T Address Hold Time 50 70 ns AH T WE# and CE# Setup Time 0 0 ns CS T WE# and CE# Hold Time 0 0 ns CH T OE# High Setup Time 0 0 ns OES T OE# High Hold Time 0 0 ns OEH T CE# Pulse Width 70 120 ns CP T WE# Pulse Width 70 120 ns WP T Data Setup Time 35 50 ns DS 1 T Data Hold Time 0 0 ns DH 1 T Byte Load Cycle Time 0.05 100 0.05 100µs BLC 1 T Byte Load Cycle Time 200 200µs BLCO 1 T Software ID Access and Exit Time 10 10 µs IDA T Software Chip-Erase 20 20 ms SCE T13.5307 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. ©2001 Silicon Storage Technology, Inc. S71062-06-000 6/01 307 11 2 Mbit Page-Mode EEPROM SST29EE020 / SST29LE020 / SST29VE020 Data Sheet T RC T AA ADDRESS A 17-0 T CE CE# T OE OE# T T OHZ OLZ V IH WE# T CHZ T OH T CLZ HIGH-Z HIGH-Z DATA VALID DATA VALID DQ 7-0 307 ILL F03.0 FIGURE 4: READ CYCLE TIMING DIAGRAM Three-Byte Sequence for T AH Enabling SDP T AS ADDRESS A 5555 2AAA 5555 17-0 T T CS CH CE# T T OES OEH OE# T WP T T BLCO BLC WE# T DH DQ AA 55 A0 DATA VALID 7-0 T WC T SW0 SW1 SW2 DS BYTE 0 BYTE 1 BYTE 127 307 ILL F04.1 FIGURE 5: WE# CONTROLLED PAGE-WRITE CYCLE TIMING DIAGRAM ©2001 Silicon Storage Technology, Inc. S71062-06-000 6/01 307 12 2 Mbit Page-Mode EEPROM SST29EE020 / SST29LE020 / SST29VE020 Data Sheet Three-Byte Sequence for T AH Enabling SDP T AS ADDRESS A 5555 2AAA 5555 17-0 T CP T T BLCO BLC CE# T T OES OEH OE# T T CS CH WE# T DH DQ AA 55 A0 DATA VALID 7-0 T WC T SW0 SW1 SW2 DS BYTE 0 BYTE 1 BYTE 127 307 ILL F05.1 FIGURE 6: CE# CONTROLLED PAGE-WRITE CYCLE TIMING DIAGRAM ADDRESS A 17-0 T CE CE# T OES T OEH OE# T OE WE# DQ D D D# D# 7 T + T WC BLCO 307 ILL F06.0 FIGURE 7: DATA# POLLING TIMING DIAGRAM ©2001 Silicon Storage Technology, Inc. S71062-06-000 6/01 307 13 2 Mbit Page-Mode EEPROM SST29EE020 / SST29LE020 / SST29VE020 Data Sheet ADDRESS A 17-0 T CE CE# T OEH T OES T OE OE# WE# DQ 6 T + T WC BLCO TWO READ CYCLES WITH SAME OUTPUTS 307 ILL F07.1 FIGURE 8: TOGGLE BIT TIMING DIAGRAM Six-Byte Sequence for Disabling Software Data Protection T WC ADDRESS A 5555 2AAA 5555 5555 2AAA 5555 14-0 DQ AA 55 80 AA 55 20 7-0 CE# OE# T T BLCO WP WE# T BLC SW0 SW1 SW2 SW3 SW4 SW5 307 ILL F08.1 FIGURE 9: SOFTWARE DATA PROTECT DISABLE TIMING DIAGRAM ©2001 Silicon Storage Technology, Inc. S71062-06-000 6/01 307 14 2 Mbit Page-Mode EEPROM SST29EE020 / SST29LE020 / SST29VE020 Data Sheet Six-Byte Code for Software Chip-Erase T SCE ADDRESS A 5555 2AAA 5555 5555 2AAA 5555 14-0 DQ AA 55 80 AA 55 10 7-0 CE# OE# T T BLCO WP WE# T BLC SW0 SW1 SW2 SW3 SW4 SW5 307 ILL F09.2 FIGURE 10: SOFTWARE CHIP-ERASE TIMING DIAGRAM Three-Byte Sequence for Software ID Entry ADDRESS A 5555 2AAA 5555 0000 0001 14-0 T AA DQ AA 55 90 BF DEVICE ID 7-0 T IDA CE# OE# T WP WE# T BLC DEVICE ID = 10H for SST29EE020 SW0 SW1 SW2 = 12H for SST29LE020/29VE020 307 ILL F10.2 FIGURE 11: SOFTWARE ID ENTRY AND READ ©2001 Silicon Storage Technology, Inc. S71062-06-000 6/01 307 15 2 Mbit Page-Mode EEPROM SST29EE020 / SST29LE020 / SST29VE020 Data Sheet Three-Byte Sequence for Software ID Exit and Reset ADDRESS A 5555 2AAA 5555 14-0 DQ AA 55 F0 7-0 T IDA CE# OE# T WP WE# T BLC SW0 SW1 SW2 307 ILL F11.0 FIGURE 12: SOFTWARE ID EXIT AND RESET ©2001 Silicon Storage Technology, Inc. S71062-06-000 6/01 307 16 2 Mbit Page-Mode EEPROM SST29EE020 / SST29LE020 / SST29VE020 Data Sheet V IHT V V HT HT INPUT REFERENCE POINTS OUTPUT V V LT LT V ILT 307 ILL F12.1 AC test inputs are driven at V (2.4 V) for a logic “1” and V (0.4 V) for a logic “0”. Measurement reference points for IHT ILT inputs and outputs are V (2.0 V) and V (0.8 V). Input rise and fall times (10% ↔ 90%) are <10 ns. HT LT Note: V - V Test HT HIGH V - V Test LT LOW V - V HIGH Test IHT INPUT V - V LOW Test ILT INPUT FIGURE 13: AC INPUT/OUTPUT REFERENCE WAVEFORMS TEST LOAD EXAMPLE V DD TO TESTER R L HIGH TO DUT C R L L LOW 307 ILL F13.1 FIGURE 14: A TEST LOAD EXAMPLE ©2001 Silicon Storage Technology, Inc. S71062-06-000 6/01 307 17 2 Mbit Page-Mode EEPROM SST29EE020 / SST29LE020 / SST29VE020 Data Sheet Start Software Data See Figure 17 Protect Write Command Set Page Address Set Byte Address = 0 Load Byte Data Increment Byte Address By 1 Byte No Address = 128? Yes Wait T BLCO Wait for end of Write (T , WC Data# Polling bit or Toggle bit operation) Write Completed 307 ILL F14.1 FIGURE 15: WRITE ALGORITHM ©2001 Silicon Storage Technology, Inc. S71062-06-000 6/01 307 18 2 Mbit Page-Mode EEPROM SST29EE020 / SST29LE020 / SST29VE020 Data Sheet Internal Timer Toggle Bit Data# Polling Page-Write Page-Write Page-Write Initiated Initiated Initiated Read DQ 7 Read a byte Wait T WC (Data for last from page byte loaded) Write No Read same Completed Is DQ = 7 byte true data? Yes No Write Does DQ 6 Completed match? Yes Write Completed 307 ILL F15.1 FIGURE 16: WAIT OPTIONS ©2001 Silicon Storage Technology, Inc. S71062-06-000 6/01 307 19 2 Mbit Page-Mode EEPROM SST29EE020 / SST29LE020 / SST29VE020 Data Sheet Software Data Protect Enable Software Data Protect Command Sequence Disable Command Sequence Write data: AAH Write data: AAH Address: 5555H Address: 5555H Write data: 55H Write data: 55H Address: 2AAAH Address: 2AAAH Write data: A0H Write data: 80H Address: 5555H Address: 5555H Optional Page Load Load 0 to Write data: AAH Operation 128 Bytes of Address: 5555H page data Write data: 55H Address: 2AAAH Wait T BLCO Write data: 20H Address: 5555H Wait T WC Wait T BLCO SDP Enabled Wait T WC SDP Disabled 307 ILL F16.1 FIGURE 17: SOFTWARE DATA PROTECTION FLOWCHARTS ©2001 Silicon Storage Technology, Inc. S71062-06-000 6/01 307 20 2 Mbit Page-Mode EEPROM SST29EE020 / SST29LE020 / SST29VE020 Data Sheet Software Product ID Entry Software Product ID Exit & Command Sequence Reset Command Sequence Write data: AAH Write data: AAH Address: 5555H Address: 5555H Write data: 55H Write data: 55H Address: 2AAAH Address: 2AAAH Write data: 90H Write data: F0H Address: 5555H Address: 5555H Pause 10 µs Pause 10 µs Return to normal Read Software ID operation 307 ILL F17.1 FIGURE 18: SOFTWARE PRODUCT COMMAND FLOWCHARTS ©2001 Silicon Storage Technology, Inc. S71062-06-000 6/01 307 21 2 Mbit Page-Mode EEPROM SST29EE020 / SST29LE020 / SST29VE020 Data Sheet Software Chip-Erase Command Sequence Write data: AAH Address: 5555H Write data: 55H Address: 2AAAH Write data: 80H Address: 5555H Write data: AAH Address: 5555H Write data: 55H Address: 2AAAH Write data: 10H Address: 5555H Wait T SCE Chip-Erase to FFH 307 ILL F18.2 FIGURE 19: SOFTWARE CHIP-ERASE COMMAND CODES ©2001 Silicon Storage Technology, Inc. S71062-06-000 6/01 307 22 2 Mbit Page-Mode EEPROM SST29EE020 / SST29LE020 / SST29VE020 Data Sheet PRODUCT ORDERING INFORMATION Device Speed Suffix1 Suffix2 SST29xE020 - XXX -XX -XX Package Modifier H = 32 leads or pins Numeric = Die modifier Package Type N = PLCC W = TSOP (die up) (8mm x 14mm) E = TSOP (die up) (8mm x 20mm) P = PDIP U = Unencapsulated die Temperature Range C = Commercial = 0°C to +70°C I = Industrial = -40°C to +85°C Minimum Endurance 4 = 10,000 cycles Read Access Speed 250 = 250 ns 200 = 200 ns 150 = 150 ns 120 = 120 ns Voltage E = 5.0V-only L = 3.0-3.6V V = 2.7-3.6V ©2001 Silicon Storage Technology, Inc. S71062-06-000 6/01 307 23 2 Mbit Page-Mode EEPROM SST29EE020 / SST29LE020 / SST29VE020 Data Sheet Valid combinations for SST29EE020 SST29EE020-120-4C-NH SST29EE020-120-4C-WH SST29EE020-120-4C-EH SST29EE020-120-4C-PH SST29EE020-120-4I-NH SST29EE020-120-4I-WH SST29EE020-120-4I-EH SST29EE020-150-4C-U2 Valid combinations for SST29LE020 SST29LE020-200-4C-NH SST29LE020-200-4C-WH SST29LE020-200-4C-EH SST29LE020-200-4I-NH SST29LE020-200-4I-WH SST29LE020-200-4I-EH SST29LE020-250-4C-U2 Valid combinations for SST29VE020 SST29VE020-200-4C-NH SST29VE020-200-4C-WH SST29VE020-200-4C-EH SST29VE020-200-4I-NH SST29VE020-200-4I-WH SST29VE020-200-4I-EH SST29VE020-250-4C-U2 Note: Valid combinations are those products in mass production or will be in mass production. Consult your SST sales representative to confirm availability of valid combinations and to determine availability of new combinations. Note: The software Chip-Erase function is not supported by the industrial temperature part. Please contact SST, if you require this function for an industrial temperature part. ©2001 Silicon Storage Technology, Inc. S71062-06-000 6/01 307 24 2 Mbit Page-Mode EEPROM SST29EE020 / SST29LE020 / SST29VE020 Data Sheet PACKAGING DIAGRAMS TOP VIEW SIDE VIEW BOTTOM VIEW .485 .495 .106 .447 Optional .112 .453 Pin #1 Identifier .042 .023 .030 .020 R. x 30˚ R. .048 MAX. .029 .040 23 1 2 .042 .013 .048 .021 .400 .490 .585 .547 .026 BSC .530 .595 .553 .032 .050 BSC. .015 Min. .075 .095 .050 BSC. .026 .125 .032 .140 Note: 1. Complies with JEDEC publication 95 MS-016 AE dimensions, although some dimensions may be more stringent. 2. All linear dimensions are in inches (min/max). 3. Dimensions do not include mold flash. Maximum allowable mold flash is .008 inches. 4. Coplanarity: 4 mils. 32.PLCC.NH-ILL.2 32-LEAD PLASTIC LEAD CHIP CARRIER (PLCC) SST PACKAGE CODE: NH 1.05 0.95 Pin # 1 Identifier .50 BSC .270 8.10 .170 7.90 0.15 12.50 0.05 12.30 0.70 0.50 14.20 13.80 32.TSOP-WH-ILL.4 Note: 1. Complies with JEDEC publication 95 MO-142 BA dimensions, although some dimensions may be more stringent. 2. All linear dimensions are in millimeters (min/max). 3. Coplanarity: 0.1 (±.05) mm. 4. Maximum allowable mold flash is 0.15mm at the package ends, and 0.25mm between leads. 32-LEAD THIN SMALL OUTLINE PACKAGE (TSOP) 8MM X 14MM SST PACKAGE CODE: WH ©2001 Silicon Storage Technology, Inc. S71062-06-000 6/01 307 25 2 Mbit Page-Mode EEPROM SST29EE020 / SST29LE020 / SST29VE020 Data Sheet 1.05 Pin # 1 Identifier 0.95 .50 BSC .27 8.10 .17 7.90 0.15 18.50 0.05 18.30 0.70 0.50 20.20 19.80 32.TSOP-EH-ILL.4 Note: 1. Complies with JEDEC publication 95 MO-142 BD dimensions, although some dimensions may be more stringent. 2. All linear dimensions are in millimeters (min/max). 3. Coplanarity: 0.1 (±.05) mm. 4. Maximum allowable mold flash is 0.15mm at the package ends, and 0.25mm between leads. 32-LEAD THIN SMALL OUTLINE PACKAGE (TSOP) 8MM X 20MM SST PACKAGE CODE: EH 32 C L .600 .625 1 Pin #1 Identifier .530 .550 1.645 .065 7˚ 1.655 .075 4 PLCS. .170 Base Plane .200 Seating Plane .015 0˚ .050 15˚ .008 .012 .120 .150 .070 .045 .016 .100 BSC .600 BSC .080 .065 .022 Note: 1. Complies with JEDEC publication 95 MO-015 AP dimensions, although some dimensions may be more stringent. 2. All linear dimensions are in inches (min/max). 32.pdipPH-ILL.2 3. Dimensions do not include mold flash. Maximum allowable mold flash is .010 inches. 32-PIN PLASTIC DUAL-IN-LINE PACKAGE (PDIP) SST PACKAGE CODE: PH Silicon Storage Technology, Inc. • 1171 Sonora Court • Sunnyvale, CA 94086 • Telephone 408-735-9110 • Fax 408-735-9036 www.SuperFlash.com or www.ssti.com ©2001 Silicon Storage Technology, Inc. S71062-06-000 6/01 307 26