1 Megabit (128K x 8) Page Mode EEPROM SST29EE010, SST29LE010, SST29VE010 Data Sheet FEATURES: • Single Voltage Read and Write Operations • Fast Read Access Time – 5.0V-only for the 29EE010 1 – 5.0V-only operation: 90 and 120 ns – 3.0V-only for the 29LE010 – 3.0V-only operation: 150 and 200 ns – 2.7V-only for the 29VE010 – 2.7V-only operation: 200 and 250 ns • Superior Reliability • Latched Address and Data 2 – Endurance: 100,000 Cycles (typical) • Automatic Write Timing – Greater than 100 years Data Retention – Internal V Generation pp 3 • Low Power Consumption • End of Write Detection – Active Current: 20 mA (typical) for 5V and – Toggle Bit 10 mA (typical) for 3.0/2.7V – Data# Polling – Standby Current: 10 μA (typical) 4 • Hardware and Software Data Protection • Fast Page-Write Operation • TTL I/O Compatibility – 128 Bytes per Page, 1024 Pages 5 – Page-Write Cycle: 5 ms (typical) • JEDEC Standard Byte-wide EEPROM Pinouts – Complete Memory Rewrite: 5 sec (typical) – Effective Byte-write Cycle Time: 39 μs • Packages Available (typical) 6 – 32-Pin TSOP (8x20 & 8x14 mm) – 32-Lead PLCC – 32 Pin Plastic DIP 7 applications, the 29EE010/29LE010/29VE010 signifi- PRODUCT DESCRIPTION cantly improve performance and reliability, while lower- 8 ing power consumption, when compared with floppy disk The 29EE010/29LE010/29VE010 are 128K x 8 CMOS or EPROM approaches. The 29EE010/29LE010/ page mode EEPROMs manufactured with SST’s propri- 29VE010 improve flexibility while lowering the cost for etary, high performance CMOS SuperFlash technology. 9 program, data, and configuration storage applications. The split gate cell design and thick oxide tunneling injector attain better reliability and manufacturability To meet high density, surface mount requirements, the compared with alternate approaches. The 29EE010/ 10 29EE010/29LE010/29VE010 are offered in 32-pin 29LE010/29VE010 write with a single power supply. TSOP and 32-lead PLCC packages. A 600-mil, 32-pin Internal Erase/Program is transparent to the user. The PDIP package is also available. See Figures 1 and 2 for 29EE010/29LE010/29VE010 conform to JEDEC stan- pinouts. 11 dard pinouts for byte-wide memories. Device Operation Featuring high performance page write, the 29EE010/ The SST page mode EEPROM offers in-circuit electrical 29LE010/29VE010 provide a typical byte-write time of 12 write capability. The 29EE010/29LE010/29VE010 does 39 μsec. The entire memory, i.e., 128K bytes, can be not require separate erase and program operations. The written page by page in as little as 5 seconds, when using internally timed write cycle executes both erase and interface features such as Toggle Bit or Data# Polling to 13 program transparently to the user. The 29EE010/ indicate the completion of a write cycle. To protect 29LE010/29VE010 have industry standard optional against inadvertent write, the 29EE010/29LE010/ Software Data Protection, which SST recommends al- 29VE010 have on-chip hardware and software data 14 ways to be enabled. The 29EE010/29LE010/29VE010 protection schemes. Designed, manufactured, and are compatible with industry standard EEPROM pinouts tested for a wide spectrum of applications, the 29EE010/ and functionality. 29LE010/29VE010 are offered with a guaranteed page- 15 4 3 write endurance of 10 or 10 cycles. Data retention is Read rated at greater than 100 years. The Read operations of the 29EE010/29LE010/ 16 The 29EE010/29LE010/29VE010 are suited for applica- 29VE010 are controlled by CE# and OE#, both have to tions that require convenient and economical updating of be low for the system to obtain data from the outputs. program, configuration, or data memory. For all system CE# is used for device selection. When CE# is high, the © 1998 Silicon Storage Technology, Inc. The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc. These specifications are subject to change without notice. 304-04 12/97 1 1 Megabit Page Mode EEPROM SST29EE010, SST29LE010, SST29VE010 chip is deselected and only standby power is consumed. leave the 29EE010/29LE010/29VE010 protected at the OE# is the output control and is used to gate data from end of the page write. The page load cycle consists of the output pins. The data bus is in high impedance state loading 1 to 128 bytes of data into the page buffer. The when either CE# or OE# is high. Refer to the read cycle internal write cycle consists of the T time-out and the BLCO timing diagram for further details (Figure 3). write timer operation. During the Write operation, the only valid reads are Data# Polling and Toggle Bit. Write The Page-Write operation allows the loading of up to 128 The Page Write to the SST29EE010/29LE010/29VE010 bytes of data into the page buffer of the 29EE010/ should always use the JEDEC Standard Software Data 29LE010/29VE010 before the initiation of the internal Protection (SDP) 3-byte command sequence. The write cycle. During the internal write cycle, all the data in 29EE010/29LE010/29VE010 contain the optional the page buffer is written simultaneously into the memory JEDEC approved Software Data Protection scheme. array. Hence, the page-write feature of 29EE010/ SST recommends that SDP always be enabled, thus, the 29LE010/29VE010 allow the entire memory to be written description of the Write operations will be given using the in as little as 5 seconds. During the internal write cycle, SDP enabled format. The 3-byte SDP Enable and SDP the host is free to perform additional tasks, such as to Write commands are identical; therefore, any time a fetch data from other locations in the system to set up the SDP Write command is issued, software data protec- write to the next page. In each Page-Write operation, all tion is automatically assured. The first time the 3-byte the bytes that are loaded into the page buffer must have SDP command is given, the device becomes SDP en- the same page address, i.e. A through A . Any byte not 7 16 abled. Subsequent issuance of the same command loaded with user data will be written to FF. bypasses the data protection for the page being written. At the end of the desired page write, the entire device See Figures 4 and 5 for the page-write cycle timing remains protected. For additional descriptions, please diagrams. If after the completion of the 3-byte SDP load see the application notes on “The Proper Use of JEDEC sequence or the initial byte-load cycle, the host loads a Standard Software Data Protection” and “Protecting second byte into the page buffer within a byte-load cycle Against Unintentional Writes When Using Single Power time (T ) of 100 μs, the 29EE010/29LE010/29VE010 BLC Supply Flash Memories” in this data book. will stay in the page load cycle. Additional bytes are then loaded consecutively. The page load cycle will be termi- The Write operation consists of three steps. Step 1 is the nated if no additional byte is loaded into the page buffer three byte load sequence for Software Data Protection. within 200 μs (T ) from the last byte-load cycle, i.e., BLCO Step 2 is the byte-load cycle to a page buffer of the no subsequent WE# or CE# high-to-low transition after 29EE010/29LE010/29VE010. Steps 1 and 2 use the the last rising edge of WE# or CE#. Data in the page same timing for both operations. Step 3 is an internally buffer can be changed by a subsequent byte-load cycle. controlled write cycle for writing the data loaded in the The page load period can continue indefinitely, as long page buffer into the memory array for nonvolatile stor- as the host continues to load the device within the byte- age. During both the SDP 3-byte load sequence and the load cycle time of 100 μs. The page to be loaded is byte-load cycle, the addresses are latched by the falling determined by the page address of the last byte loaded. edge of either CE# or WE#, whichever occurs last. The data is latched by the rising edge of either CE# or WE#, Software Chip-Erase whichever occurs first. The internal write cycle is initiated The 29EE010/29LE010/29VE010 provide a Chip-Erase by the T timer after the rising edge of WE# or CE#, BLCO operation, which allows the user to simultaneously clear whichever occurs first. The write cycle, once initiated, will the entire memory array to the “1” state. This is useful continue to completion, typically within 5 ms. See Fig- when the entire device must be quickly erased. ures 4 and 5 for WE# and CE# controlled page write cycle timing diagrams and Figures 14 and 16 for flowcharts. The Software Chip-Erase operation is initiated by using a specific six byte-load sequence. After the load se- The Write operation has three functional cycles: the quence, the device enters into an internally timed cycle Software Data Protection load sequence, the page load similar to the write cycle. During the erase operation, the cycle, and the internal write cycle. The Software Data only valid read is Toggle Bit. See Table 4 for the load Protection consists of a specific three byte load se- sequence, Figure 9 for timing diagram, and Figure 18 for quence that allows writing to the selected page and will the flowchart. © 1998 Silicon Storage Technology, Inc. 304-04 12/97 2 1 Megabit Page Mode EEPROM SST29EE010, SST29LE010, SST29VE010 Write Operation Status Detection Hardware Data Protection The 29EE010/29LE010/29VE010 provide two software Noise/Glitch Protection: A WE# or CE# pulse of less than means to detect the completion of a write cycle, in order 5 ns will not initiate a write cycle. 1 to optimize the system write cycle time. The software V Power Up/Down Detection: The write operation is CC detection includes two status bits: Data# Polling (DQ ) 7 inhibited when V is less than 2.5V. CC and Toggle Bit (DQ ). The end of write detection mode is 6 2 enabled after the rising WE# or CE# whichever occurs Write Inhibit Mode: Forcing OE# low, CE# high, or WE# first, which initiates the internal write cycle. high will inhibit the write operation. This prevents inad- vertent writes during power-up or power-down. The actual completion of the nonvolatile write is asyn- 3 chronous with the system; therefore, either a Data# Software Data Protection (SDP) Polling or Toggle Bit read may be simultaneous with the The 29EE010/29LE010/29VE010 provide the JEDEC completion of the write cycle. If this occurs, the system 4 approved optional software data protection scheme for may possibly get an erroneous result, i.e., valid data may all data alteration operations, i.e., Write and Chip erase. appear to conflict with either DQ or DQ . In order to 7 6 With this scheme, any write operation requires the inclu- prevent spurious rejection, if an erroneous result occurs, sion of a series of three byte-load operations to precede 5 the software routine should include a loop to read the the data loading operation. The three byte-load se- accessed location an additional two (2) times. If both quence is used to initiate the write cycle, providing reads are valid, then the device has completed the write optimal protection from inadvertent write operations, 6 cycle, otherwise the rejection is valid. e.g., during the system power-up or power-down. The 29EE010/29LE010/29VE010 are shipped with the soft- Data# Polling (DQ ) 7 ware data protection disabled. 7 When the 29EE010/29LE010/29VE010 are in the inter- nal write cycle, any attempt to read DQ of the last byte The software protection scheme can be enabled by 7 loaded during the byte-load cycle will receive the com- applying a three-byte sequence to the device, during a 8 plement of the true data. Once the write cycle is com- page-load cycle (Figures 4 and 5). The device will then pleted, DQ will show true data. The device is then ready be automatically set into the data protect mode. Any 7 for the next operation. See Figure 6 for Data# Polling subsequent write operation will require the preceding 9 timing diagram and Figure 15 for a flowchart. three-byte sequence. See Table 4 for the specific soft- ware command codes and Figures 4 and 5 for the timing Toggle Bit (DQ ) diagrams. To set the device into the unprotected mode, 6 10 During the internal write cycle, any consecutive attempts a six-byte sequence is required. See Table 4 for the to read DQ will produce alternating 0’s and 1’s, i.e. specific codes and Figure 8 for the timing diagram. If a 6 toggling between 0 and 1. When the write cycle is write is attempted while SDP is enabled the device will be completed, the toggling will stop. The device is then in a non-accessible state for ~ 300 μs. SST recommends 11 ready for the next operation. See Figure 7 for Toggle Bit Software Data Protection always be enabled. See Figure timing diagram and Figure 15 for a flowchart. The initial 16 for flowcharts. read of the Toggle Bit will typically be a “1”. 12 The 29EE010/29LE010/29VE010 Software Data Pro- tection is a global command, protecting (or unprotecting) Data Protection all pages in the entire memory array once enabled (or The 29EE010/29LE010/29VE010 provide both hard- 13 disabled). Therefore using SDP for a single page write ware and software features to protect nonvolatile data will enable SDP for the entire array. Single pages by from inadvertent writes. themselves cannot be SDP enabled or disabled. 14 15 16 © 1998 Silicon Storage Technology, Inc. 304-04 12/97 3 1 Megabit Page Mode EEPROM SST29EE010, SST29LE010, SST29VE010 Single power supply reprogrammable nonvolatile multiple manufacturers in the same socket. For details, memories may be unintentionally altered. SST strongly see Table 3 for hardware operation or Table 4 for recommends that Software Data Protection (SDP) al- software operation, Figure 10 for the software ID entry ways be enabled. The 29EE010/29LE010/29VE010 and read timing diagram and Figure 17 for the ID entry should be programmed using the SDP command se- command sequence flowchart. The manufacturer and quence. SST recommends the SDP Disable Command device codes are the same for both operations. Sequence not be issued to the device prior to writing. TABLE 1: PRODUCT IDENTIFICATION TABLE Please refer to the following Application Notes located at Byte Data the back of this databook for more information on using Manufacturer’s Code 0000 H BF H SDP: 29EE010 Device Code 0001 H 07 H • Protecting Against Unintentional Writes When Using 29LE010 Device Code 0001 H 08 H Single Power Supply Flash Memories 29VE010 Device Code 0001 H 08 H • The Proper Use of JEDEC Standard Software Data 304 PGM T1.1 Protection Product Identification Mode Exit Product Identification In order to return to the standard read mode, the Soft- The product identification mode identifies the device as ware Product Identification mode must be exited. Exiting the 29EE010/29LE010/29VE010 and manufacturer as is accomplished by issuing the Software ID Exit (reset) SST. This mode may be accessed by hardware or operation, which returns the device to the read operation. software operations. The hardware operation is typically The Reset operation may also be used to reset the used by a programmer to identify the correct algorithm device to the read mode after an inadvertent transient for the 29EE010/29LE010/29VE010. Users may wish to condition that apparently causes the device to behave use the software product identification operation to iden- abnormally, e.g. not read correctly. See Table 4 for tify the part (i.e. using the device code) when using software command codes, Figure 11 for timing wave- form and Figure 17 for a flowchart. FUNCTIONAL BLOCK DIAGRAM OF SST 29EE010/29LE010/29VE010 1,048,576 Bit EEPROM X-Decoder Cell Array A - A Address buffer & Latches 16 0 Y-Decoder and Page Latches CE# OE# Control Logic I/O Buffers and Data Latches WE# DQ - DQ 7 0 304 MSW B1.0 © 1998 Silicon Storage Technology, Inc. 304-04 12/97 4 1 Megabit Page Mode EEPROM SST29EE010, SST29LE010, SST29VE010 A11 OE# 1 32 A9 2 A10 31 A8 3 30 CE# 1 A13 4 29 DQ7 A14 Standard Pinout DQ6 5 28 NC 6 DQ5 27 WE# 7 DQ4 26 Top View Vcc 8 25 DQ3 2 NC 9 24 Vss A16 10 DQ2 23 A15 11 DQ1 22 A12 12 Die up 21 DQ0 A7 3 13 20 A0 A6 14 A1 19 A5 15 A2 18 A4 16 17 A3 304 MSW F01.1 4 FIGURE 1: PIN ASSIGNMENTS FOR 32-PIN TSOP PACKAGES 5 NC 1 A15 NC WE# 32 Vcc 6 A12 A16 Vcc NC A16 2 31 WE# A15 3 30 NC A12 4 29 A14 4 3 2 1 32 31 30 A14 A7 29 A7 5 5 28 A13 7 A6 28 A13 6 27 A8 A6 6 A5 7 26 A9 27 A8 A5 7 32-Pin PDIP A4 8 25 A11 A9 A4 8 26 A3 Top View 9 24 OE# 32-Lead PLCC 25 A11 A3 9 8 A2 10 23 A10 OE# 24 A2 10 Top View A1 11 22 CE# 23 A10 A1 11 A0 12 21 DQ7 DQ0 22 CE# 13 20 DQ6 A0 12 9 DQ1 14 19 DQ5 DQ7 21 DQ0 13 DQ2 15 DQ4 14 15 16 17 18 19 20 18 Vss 16 17 DQ3 DQ1 Vss DQ4 DQ6 10 DQ2 DQ3 DQ5 304 MSW F02.1 FIGURE 2: PIN ASSIGNMENTS FOR 32-PIN PLASTIC DIPS AND 32-LEAD PLCCS 11 TABLE 2: PIN DESCRIPTION Symbol Pin Name Functions 12 A -A Row Address Inputs To provide memory addresses. Row addresses define a page for a 16 7 write cycle. A -A Column Address Column Addresses are toggled to load page data. 6 0 13 Inputs DQ -DQ Data Input/output To output data during read cycles and receive input data during write 7 0 cycles. Data is internally latched during a write cycle. The outputs are in 14 tri-state when OE# or CE# is high. CE# Chip Enable To activate the device when CE# is low. OE# Output Enable To gate the data output buffers. 15 WE# Write Enable To control the write operations Vcc Power Supply To provide 5-volt supply (± 10%) for the 29EE010, 3-volt supply (3.0-3.6V) for the 29LE010 and 2.7-volt supply (2.7-3.6V) for the 29VE010 16 Vss Ground NC No Connection Unconnected pins. 304 PGM T2.0 © 1998 Silicon Storage Technology, Inc. 304-04 12/97 5 1 Megabit Page Mode EEPROM SST29EE010, SST29LE010, SST29VE010 TABLE 3: OPERATION MODES SELECTION Mode CE# OE# WE# DQ Address Read VIL VIL VIH DOUT AIN Page Write V V V D A IL IH IL IN IN Standby V X X High Z X IH Write Inhibit X V X High Z/ D X IL OUT Write Inhibit X X V High Z/ D X IH OUT Software Chip Erase V V V D A , See Table 4 IL IH IL IN IN Product Identification Hardware Mode V V V Manufacturer Code (BF) A - A = V , A = V , A = V IL IL IH 16 1 IL 9 H 0 IL Device Code (see notes) A - A = V , A = V , A = V 16 1 IL 9 H 0 IH Software Mode V V V See Table 4 IL IH IL SDP Enable Mode V V V See Table 4 IL IH IL SDP Disable Mode V V V See Table 4 IL IH IL 304 PGM T3.0 TABLE 4: SOFTWARE COMMAND CODES Command 1st Bus 2nd Bus 3rd Bus 4th Bus 5th Bus 6th Bus Sequence Write Cycle Write Cycle Write Cycle Write Cycle Write Cycle Write Cycle (1) (1) (1) (1) (1) (1) Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data (2) Software Data 5555H AAH 2AAAH 55H 5555H A0H Addr Data Protect Enable & Page Write Software Data 5555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H 5555H 20H Protect Disable Software Chip 5555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H 5555H 10H Erase Software ID Entry 5555H AAH 2AAAH 55H 5555H 90H Software ID Exit 5555H AAH 2AAAH 55H 5555H F0H Alternate Software 5555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H 5555H 60H (3) ID Entry 304 PGM T4.1 (1) Notes: Address format A -A (Hex), Addresses A and A are a “Don’t Care”. 14 0 15 16 (2) Page Write consists of loading up to 128 bytes (A - A ). 6 0 (3) Alternate 6 byte software Product-ID Command Code (4) The software chip erase function is not supported by the industrial temperature part. Please contact SST, if you require this function for an industrial temperature part. Notes for Software Product ID Command Code: 1. With A -A =0; SST Manufacturer Code = BFH, is read with A = 0, 14 1 0 29EE010 Device Code = 07H, is read with A = 1. 0 29LE010/29VE010 Device Code = 08H, is read with A = 1. 0 2. The device does not remain in Software Product ID Mode if powered down. © 1998 Silicon Storage Technology, Inc. 304-04 12/97 6 1 Megabit Page Mode EEPROM SST29EE010, SST29LE010, SST29VE010 Absolute Maximum Stress Ratings (Applied conditions greater than those listed under “Absolute Maximum Stress Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these conditions or conditions greater than those defined in the operational sections of this data sheet is not implied. 1 Exposure to absolute maximum stress rating conditions may affect device reliability.) Temperature Under Bias ................................................................................................................. -55°C to +125°C 2 Storage Temperature ...................................................................................................................... -65°C to +150°C D. C. Voltage on Any Pin to Ground Potential ............................................................................. -0.5V to V + 0.5V CC Transient Voltage (<20 ns) on Any Pin to Ground Potential......................................................... -1.0V to V + 1.0V CC 3 Voltage on A9 Pin to Ground Potential ................................................................................................ -0.5V to 14.0V Package Power Dissipation Capability (Ta = 25°C) ........................................................................................... 1.0W Through Hole Lead Soldering Temperature (10 Seconds) .............................................................................. 300°C 4 Surface Mount Lead Soldering Temperature (3 Seconds) ............................................................................... 240°C (1) Output Short Circuit Current ....................................................................................................................... 100 mA (1) Note: Outputs shorted for no more than one second. No more than one output shorted at a time. 5 6 29EE010 OPERATING RANGE AC CONDITIONS OF TEST Range Ambient Temp V CC Input Rise/Fall Time ......... 10 ns Commercial 0°C to +70°C 5V±10% 7 Output Load ..................... 1 TTL Gate and C = 100 pF L Industrial -40°C to +85°C 5V±10% See Figures 12 and 13 29LE010 OPERATING RANGE 8 Range Ambient Temp V CC Commercial 0°C to +70°C 3.0V to 3.6V 9 Industrial -40°C to +85°C 3.0V to 3.6V 29VE010 OPERATING RANGE 10 Range Ambient Temp V CC Commercial 0°C to +70°C 2.7V to 3.6V Industrial -40°C to +85°C 2.7V to 3.6V 11 12 13 14 15 16 © 1998 Silicon Storage Technology, Inc. 304-04 12/97 7 1 Megabit Page Mode EEPROM SST29EE010, SST29LE010, SST29VE010 TABLE 5: 29EE010 DC OPERATING CHARACTERISTICS VCC = 5V±10% Limits Symbol Parameter Min Max Units Test Conditions I Power Supply Current CE#=OE#=V WE#=V , all I/Os open, CC IL, IH Read 30 mA Address input = V /V , at f=1/T Min., IL IH RC VCC=VCC Max Write 50 mA CE#=WE#=V OE#=V V =V Max. IL, IH, CC CC I Standby V Current 3 mA CE#=OE#=WE#=V V =V Max. SB1 CC IH, CC CC (TTL input) ISB2 Standby VCC Current 50 μA CE#=OE#=WE#=VCC -0.3V. (CMOS input) V = V Max. CC CC I Input Leakage Current 1 μA V =GND to V , V = V Max. LI IN CC CC CC I Output Leakage Current 10 μA V =GND to V , V = V Max. LO OUT CC CC CC VIL Input Low Voltage 0.8 V VCC = VCC Max. V Input High Voltage 2.0 V V = V Max. IH CC CC V Output Low Voltage 0.4 V I = 2.1 mA, V = V Min. OL OL CC CC V Output High Voltage 2.4 V I = -400μA, V = V Min. OH OH CC CC V Supervoltage for A 11.6 12.4 V CE# = OE# =V , WE# = V H 9 IL IH I Supervoltage Current 100 μA CE# = OE# = V , WE# = V , H IL IH for A A = V Max. 9 9 H 304 PGM T5.0 TABLE 6: 29LE010/29VE010 DC OPERATING CHARACTERISTICS V = 3.0-3.6 FOR 29LE010, V = 2.7-3.6 FOR 29VE010 CC CC Limits Symbol Parameter Min Max Units Test Conditions I Power Supply Current CE#=OE#=V WE#=V , all I/Os open, CC IL, IH Read 12 mA Address input = V /V , at f=1/T Min., IL IH RC V =V Max CC CC Write 15 mA CE#=WE#=V OE#=V V =V Max. IL, IH, CC CC I Standby V Current 1 mA CE#=OE#=WE#=V V =V Max. SB1 CC IH, CC CC (TTL input) I Standby V Current 15 μA CE#=OE#=WE#=V -0.3V. SB2 CC CC (CMOS input) V = V Max. CC CC I Input Leakage Current 1 μA V =GND to V , V = V Max. LI IN CC CC CC I Output Leakage Current 10 μA V =GND to V , V = V Max. LO OUT CC CC CC V Input Low Voltage 0.8 V V = V Max. IL CC CC V Input High Voltage 2.0 V V = V Max. IH CC CC V Output Low Voltage 0.4 V I = 100 μA, V = V Min. OL OL CC CC V Output High Voltage 2.4 V I = -100 μA, V = V Min. OH OH CC CC V Supervoltage for A 11.6 12.4 V CE# = OE# =V , WE# = V H 9 IL IH I Supervoltage Current 100 μA CE# = OE# = V , WE# = V , H IL IH for A A = V Max. 9 9 H 304 PGM T6.0 © 1998 Silicon Storage Technology, Inc. 304-04 12/97 8 1 Megabit Page Mode EEPROM SST29EE010, SST29LE010, SST29VE010 TABLE 7: POWER-UP TIMINGS Symbol Parameter Maximum Units (1) T Power-up to Read Operation 100 μs PU-READ 1 (1) T Power-up to Write Operation 5 ms PU-WRITE 304 PGM T7.0 2 TABLE 8: CAPACITANCE (T = 25 °C, f=1 MHz, other pins open) a Parameter Description Test Condition Maximum 3 (1) C I/O Pin Capacitance V 0V 12 pF I/O I/O = (1) C Input Capacitance V 0V 6 pF IN IN = 304 PGM T8.0 4 (1) Note: This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. 5 TABLE 9: RELIABILITY CHARACTERISTICS Symbol Parameter Minimum Specification Units Test Method 6 (2) N Endurance 10,000 Cycles MIL-STD-883, Method 1033 END (1) T Data Retention 100 Years JEDEC Standard A103 DR 7 (1) V ESD Susceptibility 1000 Volts JEDEC Standard A114 ZAP_HBM Human Body Model (1) V ESD Susceptibility 200 Volts JEDEC Standard A115 ZAP_MM 8 Machine Model (1) I Latch Up 100 mA JEDEC Standard 78 LTH 304 PGM T9.1 9 (1) Note: This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. (2) See Ordering Information for desired type. 10 11 12 13 14 15 16 © 1998 Silicon Storage Technology, Inc. 304-04 12/97 9 1 Megabit Page Mode EEPROM SST29EE010, SST29LE010, SST29VE010 AC CHARACTERISTICS TABLE 10: 29EE010 READ CYCLE TIMING PARAMETERS 29EE010-90 29EE010-120 Symbol Parameter Min Max Min Max Units T Read Cycle time 90 120 ns RC T Chip Enable Access Time 90 120 ns CE T Address Access Time 90 120 ns AA T Output Enable Access Time 40 50 ns OE (1) T CE# Low to Active Output 0 0 ns CLZ (1) T OE# Low to Active Output 0 0 ns OLZ (1) T CE# High to High-Z Output 30 30 ns CHZ (1) T OE# High to High-Z Output 30 30 ns OHZ (1) T Output Hold from Address 0 0 ns OH Change 304 PGM T10.1 TABLE 11: 29LE010 READ CYCLE TIMING PARAMETERS 29LE010-150 29LE010-200 Symbol Parameter Min Max Min Max Units T Read Cycle time 150 200 ns RC T Chip Enable Access Time 150 200 ns CE T Address Access Time 150 200 ns AA T Output Enable Access Time 60 100 ns OE (1) T CE# Low to Active Output 0 0 ns CLZ (1) T OE# Low to Active Output 0 0 ns OLZ (1) T CE# High to High-Z Output 30 50 ns CHZ (1) T OE# High to High-Z Output 30 50 ns OHZ (1) T Output Hold from Address Change 0 0 ns OH 304 PGM T11.0 TABLE 12: 29VE010 READ CYCLE TIMING PARAMETERS 29VE010-200 29VE010-250 Symbol Parameter Min Max Min Max Units T Read Cycle time 200 250 ns RC T Chip Enable Access Time 200 250 ns CE T Address Access Time 200 250 ns AA TOE Output Enable Access Time 100 120 ns (1) T CE# Low to Active Output 0 0 ns CLZ (1) T OE# Low to Active Output 0 0 ns OLZ (1) T CE# High to High-Z Output 50 50 ns CHZ (1) T OE# High to High-Z Output 50 50 ns OHZ (1) T Output Hold from Address Change 0 0 ns OH 304 PGM T12.0 © 1998 Silicon Storage Technology, Inc. 304-04 12/97 10 1 Megabit Page Mode EEPROM SST29EE010, SST29LE010, SST29VE010 TABLE 13: PAGE-WRITE CYCLE TIMING PARAMETERS 29EE010 29LE/VE010 Symbol Parameter Min Max Min Max Units 1 T Write Cycle (erase and program) 10 10 ms WC T Address Setup Time 0 0 ns AS 2 T Address Hold Time 50 70 ns AH TCS WE# and CE# Setup Time 0 0 ns T WE# and CE# Hold Time 0 0 ns CH 3 T OE# High Setup Time 0 0 ns OES T OE# High Hold Time 0 0 ns OEH 4 T CE# Pulse Width 70 120 ns CP T WE# Pulse Width 70 120 ns WP TDS Data Setup Time 35 50 ns 5 T Data Hold Time 0 0 ns DH (1) T Byte Load Cycle Time 0.05 100 0.05 100 μs BLC (1) 6 T Byte Load Cycle Time 200 200 μs BLCO T Software ID Access and Exit Time 10 10 μs IDA T Software Chip Erase 20 20 ms SCE 7 304 PGM T13.1 (1) Note: This parameter is measured only for initial qualification and after the design or process change that could affect this parameter. 8 9 10 11 12 13 14 15 16 © 1998 Silicon Storage Technology, Inc. 304-04 12/97 11 1 Megabit Page Mode EEPROM SST29EE010, SST29LE010, SST29VE010 304 AC F03.0 FIGURE 3: READ CYCLE TIMING DIAGRAM 304 AC F04.0 FIGURE 4: WE# CONTROLLED PAGE WRITE CYCLE TIMING DIAGRAM © 1998 Silicon Storage Technology, Inc. 304-04 12/97 12 1 Megabit Page Mode EEPROM SST29EE010, SST29LE010, SST29VE010 1 2 3 4 5 6 304 AC F05.0 7 FIGURE 5: CE# CONTROLLED PAGE WRITE CYCLE TIMING DIAGRAM 8 9 10 11 12 13 14 15 304 AC F06.0 16 FIGURE 6: DATA# POLLING TIMING DIAGRAM © 1998 Silicon Storage Technology, Inc. 304-04 12/97 13 1 Megabit Page Mode EEPROM SST29EE010, SST29LE010, SST29VE010 304 AC F07.0 FIGURE 7: TOGGLE BIT TIMING DIAGRAM 304 AC F08.0 FIGURE 8: SOFTWARE DATA PROTECT DISABLE TIMING DIAGRAM © 1998 Silicon Storage Technology, Inc. 304-04 12/97 14 1 Megabit Page Mode EEPROM SST29EE010, SST29LE010, SST29VE010 1 2 3 4 5 6 304 AC F09.0 7 FIGURE 9: SOFTWARE CHIP ERASE TIMING DIAGRAM 8 9 10 DEVICE CODE 11 12 13 14 DEVICE CODE = 07 for 29EE010 15 = 08 for 29LE010/29VE010 304 AC F10.0 16 FIGURE 10: SOFTWARE ID ENTRY AND READ © 1998 Silicon Storage Technology, Inc. 304-04 12/97 15 1 Megabit Page Mode EEPROM SST29EE010, SST29LE010, SST29VE010 304 AC F11.0 FIGURE 11: SOFTWARE ID EXIT AND RESET © 1998 Silicon Storage Technology, Inc. 304-04 12/97 16 1 Megabit Page Mode EEPROM SST29EE010, SST29LE010, SST29VE010 1 2.4 2.0 2.0 OUTPUT INPUT REFERENCE POINTS 0.8 0.8 2 0.4 304 MSW F12.0 3 AC test inputs are driven at V (2.4 V ) for a logic “1” and V (0.4 V ) for a logic “0”. Measurement reference OH TTL OL TTL points for inputs and outputs are V (2.0 V ) and V (0.8 V ). Inputs rise and fall times (10% ↔ 90%) are <10 IH TTL IL TTL ns. 4 FIGURE 12: AC INPUT/OUTPUT REFERENCE WAVEFORMS 5 6 7 TEST LOAD EXAMPLE 8 V CC TO TESTER 9 R L HIGH 10 TO DUT 11 C L R L LOW 12 13 304 MSW F13.0 14 FIGURE 13: TEST LOAD EXAMPLE 15 16 © 1998 Silicon Storage Technology, Inc. 304-04 12/97 17 1 Megabit Page Mode EEPROM SST29EE010, SST29LE010, SST29VE010 Start Software Data Software Data See Figure 16 Pr Prote otectc W t W rite rite Command Command Set Page Address Set Byte Address = 0 Load Byte Data Increment Byte Address By 1 Byte No Address = 128 ? Yes Wait T Wait TBLCO BLCO Wait for end of Wait for end of Write (T , Data Write ( WC T , WC # Polling bit or Toggle bit or Data # P Toggo le ll b ing bi it t operation) operation) Write Completed Figure 14: Write Algorithm 304 MSW F14.0 FIGURE 14: WRITE ALGORITHM © 1998 Silicon Storage Technology, Inc. 304-04 12/97 18 1 Megabit Page Mode EEPROM SST29EE010, SST29LE010, SST29VE010 Data# Polling Internal Timer Toggle Bit 1 2 Page Write Page Write Page Write Initiated Initiated Initiated 3 Read DQ 4 7 Read a byte Wait T WC (Data for last from page byte loaded) 5 6 Write Read same Completed No Is DQ = 7 byte 7 true data? Yes 8 No Does DQ 6 Write 9 Completed match? Yes 10 Write 11 Completed 12 304 MSW F15.0 FIGURE 15: WAIT OPTIONS 13 14 15 16 © 1998 Silicon Storage Technology, Inc. 304-04 12/97 19 1 Megabit Page Mode EEPROM SST29EE010, SST29LE010, SST29VE010 Software Data Protect Enable Software Data Protect Command Sequence Disable Command Sequence Write data: AA Write data: AA Address: 5555 Address: 5555 Write data: 55 Write data: 55 Address: 2AAA Address: 2AAA Write data: 80 Write data: A0 Address: 5555 Address: 5555 Write data: AA Load 0 to Optional Page Load Address: 5555 Operation 128 Bytes of page data Write data: 55 Address: 2AAA Wait T BLCO Write data: 20 Address: 5555 Wait T WC Wait T BLCO SDP Enabled Wait T WC SDP Disabled 304 MSW F16.0 FIGURE 16: SOFTWARE DATA PROTECTION FLOWCHARTS © 1998 Silicon Storage Technology, Inc. 304-04 12/97 20 1 Megabit Page Mode EEPROM SST29EE010, SST29LE010, SST29VE010 1 Software Product ID Entry Software Product ID Exit & Command Sequence Reset Command Sequence 2 Write data: AA Write data: AA Address: 5555 Address: 5555 3 4 Write data: 55 Write data: 55 Address: 2AAA Address: 2AAA 5 6 Write data: 90 Write data: F0 Address: 5555 Address: 5555 7 8 Pause 10 μs Pause 10 μs 9 Return to normal Read Software ID operation 10 11 304 MSW F17.0 12 FIGURE 17: SOFTWARE PRODUCT COMMAND FLOWCHARTS 13 14 15 16 © 1998 Silicon Storage Technology, Inc. 304-04 12/97 21 1 Megabit Page Mode EEPROM SST29EE010, SST29LE010, SST29VE010 Software Chip-Erase Command Sequence Write data: AA Address: 5555 Write data: 55 Address: 2AAA Write data: 80 Address: 5555 Write data: AA Address: 5555 Write data: 55 Address: 2AAA Write data: 10 Address: 5555 Wait T SCE Chip Erase to FFH 304 MSW F18.0 FIGURE 18: SOFTWARE CHIP ERASE COMMAND CODES © 1998 Silicon Storage Technology, Inc. 304-04 12/97 22 1 Megabit Page Mode EEPROM SST29EE010, SST29LE010, SST29VE010 PRODUCT ORDERING INFORMATION 1 Device Speed Suffix1 Suffix2 SST29XE010 - XXX - XX - XX 2 Package Modifier H = 32 leads 3 Numeric = Die modifier Package Type 4 P = PDIP N = PLCC E = TSOP (die up) 8x20 mm 5 W = TSOP (die up) 8x14 mm U = Unencapsulated die 6 Operating Temperature C = Commercial = 0° to 70°C I = Industrial = -40° to 85°C 7 Minimum Endurance 3 = 1000 cycles 8 4 = 10,000 cycles Read Access Speed 9 250 = 250 ns 200 = 200 ns 150 = 150 ns 10 120 = 120 ns 90 = 90 ns 11 Voltage E = 5V-only L = 3V-only 12 V = 2.7V-only 13 14 15 16 © 1998 Silicon Storage Technology, Inc. 304-04 12/97 23 1 Megabit Page Mode EEPROM SST29EE010, SST29LE010, SST29VE010 29EE010 Valid combinations SST29EE010- 90-4C- EH SST29EE010- 90-4C- NH SST29EE010- 90-4C- PH SST29EE010-120-4C- EH SST29EE010-120-4C- NH SST29EE010-120-4C- PH SST29EE010- 90-4C- WH SST29EE010-120-4C- WH SST29EE010- 90-4I-EH SST29EE010- 90-4I-NH SST29EE010-120-4I-EH SST29EE010-120-4I-NH SST29EE010-120-4C-U2 29LE010 Valid combinations SST29LE010-150-4C- EH SST29LE010-150-4C- NH SST29LE010-150-4C- PH SST29LE010-200-4C- EH SST29LE010-200-4C- NH SST29LE010-200-4C- PH SST29LE010-150-4C- WH SST29LE010-200-4C- WH SST29LE010-150-4I-EH SST29LE010-150-4I-NH SST29LE010-200-4C-U2 29VE010 Valid combinations SST29VE010-200-4C- EH SST29VE010-200-4C- NH SST29VE010-200-4C- PH SST29VE010-250-4C- EH SST29VE010-250-4C- NH SST29VE010-250-4C- PH SST29VE010-200-4C-WH SST29VE010-250-4C-WH SST29VE010-200-4I-EH SST29VE010-200-4I-NH SST29VE010-250-4C-U2 Example:Valid combinations are those products in mass production or will be in mass production. Consult your SST sales representative to confirm availability of valid combinations and to determine availability of new combinations. Note: The software chip erase function is not supported by the industrial temperature part. Please contact SST, if you require this function for an industrial temperature part. © 1998 Silicon Storage Technology, Inc. 304-04 12/97 24 1 Megabit Page Mode EEPROM SST29EE010, SST29LE010, SST29VE010 PACKAGING DIAGRAMS 1 2 3 4 5 6 32pn PDIP PH AC.2 Note: 1. Complies with JEDEC publication 95 MO-015 AP dimensions, although some dimensions may be more stringent. 7 2. All linear dimensions are in inches (min/max). 3. Dimensions do not include mold flash. Maximum allowable mold flash is .010 inches. 32-LEAD PLASTIC DUAL-IN-LINE PACKAGE (PDIP) 8 SST PACKAGE CODE: PH 9 10 11 12 13 14 32pn PLCC NH AC.2 15 Note: 1. Complies with JEDEC publication 95 MS-016 AE dimensions, although some dimensions may be more stringent. 2. All linear dimensions are in inches (min/max). 3. Dimensions do not include mold flash. Maximum allowable mold flash is .008 inches. 16 32-LEAD PLASTIC LEAD CHIP CARRIER (PLCC) SST PACKAGE CODE: NH © 1998 Silicon Storage Technology, Inc. 304-04 12/97 25 1 Megabit Page Mode EEPROM SST29EE010, SST29LE010, SST29VE010 Note: 1. Complies with JEDEC publication 95 MO-142 BA dimensions, although some dimensions may be more stringent. 2. All linear dimensions are in metric (min/max). 3. Coplanarity: 0.1 (±.05) mm. 32pn TSOP WH AC.3 32-LEAD THIN SMALL OUTLINE PACKAGE (TSOP) SST PACKAGE CODE: WH Note: 1. Complies with JEDEC publication 95 MO-142 BD dimensions, although some dimensions may be more stringent. 2. All linear dimensions are in metric (min/max). 3. Coplanarity: 0.1 (±.05) mm. 32pn TSOP EH AC.4 32-LEAD THIN SMALL OUTLINE PACKAGE (TSOP) SST PACKAGE CODE: EH © 1998 Silicon Storage Technology, Inc. 304-04 12/97 26 1 Megabit Page Mode EEPROM SST29EE010, SST29LE010, SST29VE010 SST Area Offices Canada - Toronto U.S.A. - California (408) 523-7722 Kaltron Components Inc. (905) 405-6276 U.S.A. - Florida (813) 771-8819 Canada - Ottawa U.S.A. - Florida (941) 505-8893 Kaltron Components Inc. (819) 457-1225 U.S.A. - Massachusetts (978) 356-3845 1 Canada - Montreal Japan - Yokohama (81) 45-471-1851 Kaltron Components Inc. (514) 696-6589 Europe - UK (44) 1784-490455 Canada - B.C. Thorson Pacific, Inc. (604) 294-3999 North American Sales Representatives 2 Puerto Rico MEC/Caribe (787) 746-9897 Alabama Elcom, Inc. (205) 830-4001 International Sales Representatives & Distributors Arizona 3 QuadRep, Inc. (602) 839-2102 Australia California ACD (61) 3-762 7644 Northern Belgium Premier Technical Sales (408) 736-2260 Memec Brussels (32) 2778-9850 4 Southern China QuadRep, Inc., San Diego (619) 775-1188 Actron Technology Co., Ltd. (86) 21-6482-8021 QuadRep, Inc., Irvine (714) 727-4222 Denmark Colorado Berendsen Components A/S (45) 39-57-71-10 5 QuadRep, Inc. (303) 771-6886 Ireland Florida Memec Ireland LTD (353) 61 411842 MEC Corporation - Central/East Coast (904) 427-7236 Finland MEC Corporation - South/East Coast (954) 426-8944 OXXO OY AB (358) 9-5842 600 MEC Corporation - West Coast (813) 393-5011 6 France Georgia RepDesign (33) 1 46 23 7990 Elcom, Inc. (770) 447-8200 A2M (33) 1 46 23 7900 Iowa Germany Oasis Sales Corporation (319) 377-8738 7 Endrich Bauelemente Idaho Vertriebs GMBH (49) 7452-60070 QuadRep, Inc. (208) 939-9626 Metronik GmbH (49) 89-61108-0 Illinois Hong Kong Oasis Sales Corporation - Northern (847) 640-1850 8 Actron Technology Co., Ltd. (852) 2727-3978 Rush & West Associates - Southern (314) 965-3322 Serial System (HK) Ltd. (852) 2950-0820 Kansas Israel Rush & West Associates (913) 764-2700 Elina Electronics (972) 3-649 8543 Massachusetts 9 Italy S-J Associates (978) 670-8899 Carla Gavazzi Cefra SpA (39) 2-4801.2355 Minnesota Japan Cahill, Schmitz & Cahill (612) 646-7217 Asahi Electronics Co., Ltd. (81) 3-3350-5418 Missouri Asahi Electronics Co., Ltd. (81) 93-511-6471 10 Rush & West Associates (314) 965-3322 Hakuto Co., Ltd. (81) 3-3355-7615 North Carolina MICROTEK Inc. (81) 3-5300-5525 Elcom, Inc. - Charlotte (704) 543-1229 Ryoden Trading Co., Ltd. (81) 3-5396-6206 Elcom, Inc. - Raleigh (919) 743-5200 Silicon Technology Co., Ltd. (81) 3-3795-6461 11 New Jersey Korea S-J Associates (609) 866-1234 Bigshine Korea Co., Ltd. (82) 2-832-8881 New Mexico Netherlands QuadRep, Inc. (505) 332-2417 Memec Benelux (31) 40-265-9399 New York 12 Singapore S-J Associates - NYC (516) 536-4242 Serial System Ltd. (65) 286-1812 S-J Associates - Upstate (716) 924-1720 South Africa Ohio KH Distributors (27) 11 845-5011 Great Lakes - Columbus (614) 885-6700 13 Spain Great Lakes - Cleveland (216) 349-2700 Tekelec Espana S.A. (34) 13 20 41 60 Oregon Sweden Thorson Pacific, Inc. (503) 293-9001 Pelcon Electronics AB (46) 8.795 98 70 Texas Switzerland 14 Tech. Mktg, Inc. - Carrollton (972) 387-3601 Leading Technology (41) 277-21 7-446 Tech. Mktg, Inc. - Houston (713) 783-4497 Taiwan, R.O.C. Tech. Mktg, Inc. - Austin (512) 343-6976 Award Software (886) 22-555-0880 Utah PCT Limited (886) 22-698-0098 15 QuadRep, Inc. (801) 521-4717 Tonsam Corporation (886) 22-651-0011 Virginia United Kingdom S-J Associates (703) 533-2233 Ambar Components, Ltd. (44) 1844-261144 Washington 16 Thorson Pacific, Inc. (425) 603-9393 Wisconsin Oasis Sales Corporation (414) 782-6660 Revised 3-12-98 Silicon Storage Technology, Inc. • 1171 Sonora Court • Sunnyvale, CA 94086 • Telephone 408-735-9110 • Fax 408-735-9036 www.SuperFlash.com or www.ssti.com • Literature FaxBack 888-221-1178, International 732-544-2873 © 1998 Silicon Storage Technology, Inc. 304-04 12/97 27