NBC12429 3.3V/5V�Programmable PLL Synthesized Clock Generator 25 MHz to 400 MHz http://onsemi.com The NBC12429 is a general purpose, PLL based synthesized clock source. The VCO will operate over a frequency range of 200 MHz to MARKING DIAGRAMS 400 MHz. The VCO frequency is sent to the N-output divider, where it can be configured to provide division ratios of 1, 2, 4, or 8. The VCO 128 and output frequency can be programmed using the parallel or serial interfaces to the configuration logic. Output frequency steps of 1.0 MHz can be achieved using a 16 MHz crystal, depending on the NBC12429 output dividers. The PLL loop filter is fully integrated and does not AWLYYWW require any external components. PLCC-28 FN SUFFIX • Best-in-Class Output Jitter Performance, ±20 ps Peak-to-Peak CASE 776 • 25 MHz to 400 MHz Programmable Differential PECL Outputs • Fully Integrated Phase-Lock-Loop with Internal Loop Filter • Parallel Interface for Programming Counter and Output Dividers During Power-Up • Minimal Frequency Overshoot NBC12429 • Serial 3-Wire Programming Interface AWLYYWW LQFP-32 FA SUFFIX • Crystal Oscillator Interface 32 CASE 873A • Operating Range: V = 3.135 V to 5.25 V CC 1 • CMOS and TTL Compatible Control Inputs • Drop-in Replacement for Motorola MC12429 A = Assembly Location WL = Wafer Lot YY = Year WW = Work Week ORDERING INFORMATION Device Package Shipping NBC12429FN PLCC-28 37 Units/Rail NBC12429FNR2 PLCC-28 500 Tape & Reel NBC12429FA LQFP-32 250 Units/Tray NBC12429FAR2 LQFP-32 2000 Tape & Reel  Semiconductor Components Industries, LLC, 2003 1 Publication Order Number: January, 2003 - Rev. 2 NBC12429/D NBC12429 +3.3 or 5.0 V 1 PLL_V CC 1 MHz F REF PHASE � 16 DETECTOR +3.3 or 5.0 V VCO V 21, 25 CC 4 XTAL1 24 F 9-BIT � M � N OUT 10-20 MHz OSC 23 COUNTER (1, 2, 4, 8) F OUT 200-400 5 XTAL2 MHz 20 TEST 6 OE LATCH LATCH 28 S_LOAD LATCH 7 P_LOAD 01 01 27 S_DATA 2- BIT SR 3- BIT SR 9- BIT SR 26 S_CLOCK 8 � 16 17, 18 22, 19 9 2 M[8:0] N[1:0] Figure 1. NBC12429 Block Diagram (28-Lead PLCC) 25 24 23 22 21 20 19 18 S_CLOCK 26 N[1] 32 31 30 29 28 27 26 25 24 N/C S_CLOCK 1 17 27 S_DATA N[0] N[1] S_DATA 2 23 S_LOAD 28 16 M[8] S_LOAD 22 N[0] 3 4 21 M[8] PLL_V 1 15 PLL_V M[7] CC CC 20 5 PLL_V M[7] CC 2 14 NC M[6] 6 19 M[6] N/C 3 7 18 13 NC M[5] N/C M[5] 17 8 XTAL1 M[4] 4 XTAL1 12 M[4] 9 10 11 1213 1415 16 56 7 8 9 10 11 Figure 2. 28-Lead PLCC (Top View) Figure 3. 32-Lead LQFP (Top View) http://onsemi.com 2 XTAL2 V CC OE FOUT P_LOAD FOUT M[0] GND M[1] V CC M[2] TEST M[3] GND XTAL2 V CC OE F OUT F P_LOAD OUT M[0] GND M[1] V CC M[2] V CC M[3] TEST GND N/C NBC12429 The following gives a brief description of the functionality of the NBC12429 Inputs and Outputs. Unless explicitly stated, all inputs are CMOS/TTL compatible with either pull-up or pulldown resistors. The PECL outputs are capable of driving two series terminated 50 � transmission lines on the incident edge. PIN FUNCTION DESCRIPTION Pin Name Function Description INPUTS XTAL1, XTAL2 Crystal Inputs These pins form an oscillator when connected to an external series-resonant crystal. S_LOAD* CMOS/TTL Serial Latch Input This pin loads the configuration latches with the contents of the shift registers. The (Internal Pulldown Resistor) latches will be transparent when this signal is HIGH; thus, the data must be stable on the HIGH-to-LOW transition of S_LOAD for proper operation. S_DATA* CMOS/TTL Serial Data Input This pin acts as the data input to the serial configuration shift registers. (Internal Pulldown Resistor) S_CLOCK* CMOS/TTL Serial Clock Input This pin serves to clock the serial configuration shift registers. Data from S_DATA (Internal Pulldown Resistor) is sampled on the rising edge. P_LOAD** CMOS/TTL Parallel Latch Input This pin loads the configuration latches with the contents of the parallel inputs (Internal Pullup Resistor) .The latches will be transparent when this signal is LOW; therefore, the parallel data must be stable on the LOW-to-HIGH transition of P_LOAD for proper opera- tion. M[8:0]** CMOS/TTL PLL Loop Divider These pins are used to configure the PLL loop divider. They are sampled on the Inputs (Internal Pullup Resistor) LOW-to-HIGH transition of P_LOAD. M[8] is the MSB, M[0] is the LSB. N[1:0]** CMOS/TTL Output Divider Inputs These pins are used to configure the output divider modulus. They are sampled (Internal Pullup Resistor) on the LOW-to-HIGH transition of P_LOAD. OE** CMOS/TTL Output Enable Input Active HIGH Output Enable. The Enable is synchronous to eliminate possibility of (Internal Pullup Resistor) runt pulse generation on the FOUT output. OUTPUTS F , F PECL Differential Outputs These differential, positive-referenced ECL signals (PECL) are the outputs of the OUT OUT synthesizer. TEST CMOS/TTL Output The function of this output is determined by the serial configuration bits T[2:0]. POWER V Positive Supply for the Logic The positive supply for the internal logic and output buffer of the chip, and is con- CC nected to +3.3 V or +5.0 V. PLL_V Positive Supply for the PLL This is the positive supply for the PLL and is connected to +3.3 V or +5.0 V. CC GND Negative Power Supply These pins are the negative supply for the chip and are normally all connected to ground. * When left Open, these inputs will default LOW. ** When left Open, these inputs will default HIGH. http://onsemi.com 3 NBC12429 ATTRIBUTES Characteristics Value Internal Input Pulldown Resistor 75 k� Internal Input Pullup Resistor 37.5 k� ESD Protection Human Body Model > 2 kV Machine Model > 150 V Charged Device Model > 1 kV Moisture Sensitivity (Note 1) PLCC Level 1 LQFP Level 2 Flammability Rating Oxygen Index: 28 to 34 UL 94 V-0 @ 0.125 in Transistor Count 2035 Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 1. For additional information, see Application Note AND8003/D. MAXIMUM RATINGS (Note 2) Symbol Parameter Condition 1 Condition 2 Rating Unit V Positive Supply GND = 0 V - 6 V CC V Input Voltage GND = 0 V V � V 6 V I I CC I Output Current Continuous - 50 mA out Surge - 100 mA TA Operating Temperature Range - - 0 to +70 °C T Storage Temperature Range - - -65 to +150 °C stg � Thermal Resistance (Junction-to-Ambient) 0 LFPM 28 PLCC 63.5 °C/W JA 500 LFPM 28 PLCC 43.5 °C/W � Thermal Resistance (Junction-to-Case) std bd 28 PLCC 22 to 26 °C/W JC � Thermal Resistance (Junction-to-Ambient) 0 LFPM 32 LQFP 80 °C/W JA 500 LFPM 32 LQFP 55 °C/W � Thermal Resistance (Junction-to-Case) std bd 32 LQFP 12 to 17 °C/W JC T Wave Solder < 2 to 3 sec @ 248°C - 265 °C sol 2. Maximum Ratings are those values beyond which device damage may occur. http://onsemi.com 4 NBC12429 DC CHARACTERISTICS (V = 3.3 V ± 5%) CC 0°C 25°C 70°C Symbol Characteristic Condition Min Typ Max Min Typ Max Min Typ Max Unit V Input HIGH Voltage V = 3.3 V 2.0 - - 2.0 - - 2.0 - - V IH CC LVCMOS/ LVTTL V Input LOW Voltage V = 3.3 V - - 0.8 - - 0.8 - - 0.8 V IL CC LVCMOS/ LVTTL I Input Current - - 1.0 - - 1.0 - - 1.0 mA IN V Output HIGH Voltage I = -0.8 mA 2.5 - - 2.5 - - 2.5 - - V OH OH TEST V Output LOW Voltage I = 0.8 mA - - 0.4 - - 0.4 - - 0.4 V OL OL TEST V Output HIGH Voltage F V = 3.3 V 2.155 - 2.405 2.155 - 2.405 2.155 - 2.405 V OH OUT CC PECL F (Notes 3, 4) OUT V Output LOW Voltage F V = 3.3 V 1.355 - 1.605 1.355 - 1.605 1.355 - 1.605 V OL OUT CC PECL F (Notes 3, 4) OUT I Power Supply Current V 48 56 70 48 58 70 48 61 70 mA CC CC PLL_V 18 22 26 18 22 26 18 22 26 mA CC 3. F /F output levels will vary 1:1 with V variation. OUT OUT CC 4. F /F outputs are terminated through a 50 � resistor to V - 2.0 V. OUT OUT CC DC CHARACTERISTICS (V = 5.0 V ± 5%) CC 0°C 25°C 70°C Min Typ Max Min Typ Max Min Typ Max Symbol Characteristic Condition Unit V Input HIGH Voltage V = 5.0 V 2.0 - - 2.0 - - 2.0 - - V IH CC CMOS/ TTL V Input LOW Voltage V = 5.0 V - - 0.8 - - 0.8 - - 0.8 V IL CC CMOS/ TTL I Input Current - - 1.0 - - 1.0 - - 1.0 mA IN V Output HIGH Voltage TEST I = -0.8 mA 2.5 - - 2.5 - - 2.5 - - V OH OH V Output LOW Voltage TEST I = 0.8 mA - - 0.4 - - 0.4 - - 0.4 V OL OL V Output HIGH Voltage F V = 5.0 V 3.855 - 4.105 3.855 - 4.105 3.855 - 4.105 V OH OUT CC PECL F (Notes 5, 6) OUT V Output LOW Voltage F V = 5.0 V 3.055 - 3.305 3.055 - 3.305 3.055 - 3.305 V OL OUT CC PECL F (Notes 5, 6) OUT I Power Supply Current V 50 58 75 50 60 75 50 65 75 mA CC CC PLL_V 19 23 27 19 23 27 19 23 27 mA CC 5. F /F output levels will vary 1:1 with V variation. OUT OUT CC 6. F /F outputs are terminated through a 50 � resistor to V - 2.0 volts. OUT OUT CC http://onsemi.com 5 NBC12429 AC CHARACTERISTICS (V = 3.125 V to 5.25 V ± 5%; T = 0° to 70°C) (Note 8) CC A Symbol Characteristic Condition Min Max Unit F Maximum Input Frequency S_CLOCK (Note 7) - 10 MHz MAXI Xtal Oscillator 10 20 F Maximum Output Frequency VCO (Internal) 200 400 MHz MAXO F 25 400 OUT t Maximum PLL Lock Time - 10 ms LOCK t Cycle-to-Cycle Jitter (1 �) See Applications Section - �20 ps jitter t Setup Time S_DATA to S_CLOCK 20 - ns s S_CLOCK to S_LOAD 20 - M, N to P_LOAD 20 - t Hold Time S_DATA to S_CLOCK 20 - ns h M, N to P_LOAD 20 - t Minimum Pulse Width S_LOAD 50 - ns pwMIN P_LOAD 50 - DCO Output Duty Cycle 47.5 52.5 % t , t Output Rise/Fall F 20%-80% 175 425 ps r f OUT 7. 10 MHz is the maximum frequency to load the feedback divide registers. S_CLOCK can be switched at higher frequencies when used as a test clock in TEST_MODE 6. 8. F /F outputs are terminated through a 50 � resistor to V - 2.0 V. OUT OUT CC http://onsemi.com 6 NBC12429 FUNCTIONAL DESCRIPTION The internal oscillator uses the external quartz crystal as for the output driver and the internal logic is separated from the basis of its frequency reference. The output of the the power supply for the phase-locked loop to minimize reference oscillator is divided by 16 before being sent to the noise induced jitter. phase detector. With a 16 MHz crystal, this provides a The configuration logic has two sections: serial and reference frequency of 1 MHz. Although this data sheet parallel. The parallel interface uses the values at the M[8:0] illustrates functionality only for a 16 MHz crystal, Table 1, and N[1:0] inputs to configure the internal counters. any crystal in the 10-20 MHz range can be used, Table 3. Normally upon system reset, the P_LOAD input is held The VCO within the PLL operates over a range of 200 to LOW until sometime after power becomes valid. On the 400 MHz. Its output is scaled by a divider that is configured LOW-to-HIGH transition of P_LOAD, the parallel inputs by either the serial or parallel interfaces. The output of this are captured. The parallel interface has priority over the loop divider is also applied to the phase detector. serial interface. Internal pullup resistors are provided on the The phase detector and the loop filter force the VCO M[8:0] and N[1:0] inputs to reduce component count in the output frequency to be M times the reference frequency by application of the chip. adjusting the VCO control voltage. Note that for some The serial interface logic is implemented with a fourteen values of M (either too high or too low), the PLL will not bit shift register scheme. The register shifts once per rising achieve loop lock. edge of the S_CLOCK input. The serial input S_DATA must The output of the VCO is also passed through an output meet setup and hold timing as specified in the AC divider before being sent to the PECL output driver. This Characteristics section of this document. With P_LOAD output divider (N divider) is configured through either the held high, the configuration latches will capture the value of serial or the parallel interfaces and can provide one of four the shift register on the HIGH-to-LOW edge of the division ratios (1, 2, 4, or 8). This divider extends the S_LOAD input. See the programming section for more performance of the part while providing a 50% duty cycle. information. The output driver is driven differentially from the output The TEST output reflects various internal node values and divider and is capable of driving a pair of transmission lines is controlled by the T[2:0] bits in the serial data stream. See terminated into 50 � to V -2.0 V. The positive reference the programming section for more information. CC Table 1. Programming VCO Frequency Function Table ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ VCO 256 128 64 32 16 8 4 2 1 ÁÁÁÁÁÁÁÁÁÁ Freq Frequency encyÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ (MHz) M8 M7 M6 M5 M4 M3 M2 M1 M0 M Count* ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ 200 200 0 1 1 0 0 1 0 0 0 ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ 201 201 0 1 1 0 0 1 0 0 1 ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ 202 202 0 1 1 0 0 1 0 1 0 ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ 203 203 0 1 1 0 0 1 0 1 1 ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ • • • • • • • • • • • ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ • • • • • • • • • • • ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ • • • • • • • • • • • ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ 397 397 1 1 0 0 0 1 1 0 1 ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ 398 398 1 1 0 0 0 1 1 1 0 ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ 399 399 1 1 0 0 0 1 1 1 1 ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ 400 400 1 1 0 0 1 0 0 0 0 ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ *With 16 MHz crystal. http://onsemi.com 7 NBC12429 PROGRAMMING INTERFACE Programming the NBC12429 is accomplished by The input frequency and the selection of the feedback properly configuring the internal dividers to produce the divider M is limited by the VCO frequency range and desired frequency at the outputs. The output frequency can F . M must be configured to match the VCO frequency XTAL by represented by this formula: range of 200 to 400 MHz in order to achieve stable PLL operation. FOUT� (F � 16)� M� N (eq. 1) XTAL M � f � (f � 16) and (eq. 3) min VCOmin XTAL where F is the crystal frequency, M is the loop divider XTAL M � f � (f � 16) (eq. 4) max VCOmax XTAL modulus, and N is the output divider modulus. Note that it The value for M falls within the constraints set for PLL is possible to select values of M such that the PLL is unable stability. If the value for M fell outside of the valid range, a to achieve loop lock. To avoid this, always make sure that M different N value would be selected to move M in the is selected to be 200 ≤ M ≤ 400 for a 16 MHz input reference. appropriate direction. Assuming that a 16 MHz reference frequency is used the The M and N counters can be loaded either through a above equation reduces to: parallel or serial interface. The parallel interface is FOUT� M� N (eq. 2) controlled via the P_LOAD signal such that a LOW to HIGH Substituting the four values for N (1, 2, 4, 8) yields: transition will latch the information present on the M[8:0] and N[1:0] inputs into the M and N counters. When the Table 2. Programmable Output Divider Function Table P_LOAD signal is LOW, the input latches will be ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Output Frequency transparent and any changes on the M[8:0] and N[1:0] inputs Range (MHz)* N1 N0 N Divider F OUT will affect the F output pair. To use the serial port, the ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ OUT S_CLOCK signal samples the information on the S_DATA 0 0 �1 M 200-400 ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ line and loads it into a 14 bit shift register. Note that the 0 1 �2 M � 2 100-200 ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ P_LOAD signal must be HIGH for the serial load operation 1 0 �4 M � 4 50-100 ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ to function. The Test register is loaded with the first three 1 1 �8 M � 8 25-50 bits, the N register with the next two, and the M register with ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ the final nine bits of the data stream on the S_DATA input. *For crystal frequency of 16 MHz. ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ For each register, the most significant bit is loaded first (T2, The user can identify the proper M and N values for the N1, and M8). A pulse on the S_LOAD pin after the shift desired frequency from the above equations. The four output register is fully loaded will transfer the divide values into the counters. The HIGH to LOW transition on the S_LOAD frequency ranges established by N are 200-400 MHz, input will latch the new divide values into the counters. 100-200 MHz, 50-100 MHz and 25-50 MHz, respectively. Figures 4 and 5 illustrate the timing diagram for both a From these ranges, the user will establish the value of N parallel and a serial load of the NBC12429 synthesizer. required. The value of M can then be calculated based on M[8:0] and N[1:0] are normally specified once at equation 1. For example, if an output frequency of 131 MHz power-up through the parallel interface, and then possibly was desired, the following steps would be taken to identify again through the serial interface. This approach allows the the appropriate M and N values. 131 MHz falls within the application to come up at one frequency and then change or frequency range set by an N value of 2; thus, N [1:0] = 01. fine-tune the clock as the ability to control the serial For N = 2, F = M ÷ 2 and M = 2 x F . Therefore, OUT OUT interface becomes available. M = 131 x 2 = 262, so M[8:0] = 100000110. Following this The TEST output provides visibility for one of the several same procedure, a user can generate any whole frequency internal nodes as determined by the T[2:0] bits in the serial desired between 25 and 400 MHz. Note that for N > 2, fractional values of F can be realized. The size of the configuration stream. It is not configurable through the OUT programmable frequency steps (and thus, the indicator of parallel interface. The T2, T1, and T0 control bits are preset the fractional output frequencies achievable) will be equal to ‘000’ when P_LOAD is LOW so that the PECL F OUT to F ÷ 16 ÷ N. outputs are as jitter-free as possible. Any active signal on the XTAL For input reference frequencies other than 16 MHz, see TEST output pin will have detrimental affects on the jitter Table 3, which shows the usable VCO frequency and M of the PECL output pair. In normal operations, jitter divider range. specifications are only guaranteed if the TEST output is static. The serial configuration port can be used to select one of the alternate functions for this pin. http://onsemi.com 8 NBC12429 Table 3. NBC12429 Frequency Operating Range ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Output Frequency for F = XTAL VCO Frequency Range for a Crystal Frequency of: 16 MHz and for N = ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ M M[8:0] 10 12 14 16 18 20 1 2 4 8 ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ 160 010100000 200 ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ 170 010101010 212.5 180 010110100 202.5 225 190 010111110 213.75 237.5 200 011001000 200 225 250 200 100 50 25 210 011010010 210 236.25 262.5 210 105 52.5 26.25 220 011011100 220 247.5 275 220 110 55 27.5 230 011100110 201.25 230 258.75 287.5 230 115 57.5 28.75 240 011110000 210 240 270 300 240 120 60 30 250 011111010 218.75 250 281.25 312.5 250 125 62.5 31.25 260 100000100 227.5 260 292.5 325 260 130 65 32.5 270 100001110 202.5 236.25 270 303.75 337.5 270 135 67.5 33.75 280 100011000 210 245 280 315 350 280 140 70 35 290 100100010 217.5 253.75 290 326.25 362.5 290 145 72.5 36.25 300 100101100 225 262.5 300 337.5 375 300 150 75 37.5 310 100110110 232.5 271.25 310 348.75 387.5 310 155 77.5 38.75 320 101000000 200 240 280 320 360 400 320 160 80 40 330 101001010 206.25 247.5 288.75 330 371.25 330 165 82.5 41.25 340 101010100 212.5 255 297.5 340 382.5 340 170 85 42.5 350 101011110 218.75 262.5 306.25 350 393.75 350 175 87.5 43.75 360 101101000 225 270 315 360 360 180 90 45 370 101110010 231.25 277.5 323.75 370 370 185 92.5 46.25 380 101111100 237.5 285 332.5 380 380 190 95 47.5 390 110000110 243.75 292.5 341.25 390 390 195 97.5 48.75 400 110010000 250 300 350 400 400 200 100 50 410 110011010 256.25 307.5 358.75 420 110100100 262.5 315 367.5 430 110101110 268.75 322.5 376.25 440 110111000 275 330 385 450 111000010 281.25 337.5 393.75 460 111001100 287.5 345 470 111010110 293.75 352.5 480 111100000 300 360 490 111101010 306.25 367.5 500 111110100 312.5 375 510 111111110 318.75 382.5 http://onsemi.com 9 NBC12429 Most of the signals available on the TEST output pin are T2 T1 T0 TEST (Pin 20) useful only for performance verification of the NBC12429 0 0 0 SHIFT REGISTER OUT itself. However, the PLL bypass mode may be of interest at 0 0 1 HIGH the board level for functional debug. When T[2:0] is set to 0 1 0 F REF 110, the NBC12429 is placed in PLL bypass mode. In this 0 1 1 M COUNTER OUT 1 0 0 F mode the S_CLOCK input is fed directly into the M and N OUT 1 0 1 LOW dividers. The N divider drives the F differential pair and OUT 1 1 0 PLL BYPASS the M counter drives the TEST output pin. In this mode the 1 1 1 F � 4 OUT S_CLOCK input could be used for low speed board level functional test or debug. Bypassing the PLL and driving F directly gives the user more control on the test clocks OUT sent through the clock tree. Figure 6 shows the functional M[8:0] M, N setup of the PLL bypass mode. Because the S_CLOCK is a N[1:0] CMOS level the input frequency is limited to 250 MHz or less. This means the fastest the F pin can be toggled via P_LOAD OUT the S_CLOCK is 250 MHz as the minimum divide ratio of the N counter is 1. Note that the M counter output on the TEST output will not be a 50% duty cycle due to the way the Figure 4. Parallel Interface Timing Diagram divider is implemented. S_CLOCK T2 T1 T0 N1 N0 M8 M7 M6 M5 M4 M3 M2 M1 M0 S_DATA First Last S_LOAD Bit Bit Figure 5. Serial Interface Timing Diagram FREF VCO_CLK PLL 12429 MCNT 0 FOUT N � 1 (1, 2, 4, 8) (VIA ENABLE GATE) SCLOCK SEL_CLK M COUNTER FDIV4 7 MCNT LOW LATCH TEST FOUT TEST MUX MCNT Reset FREF SHIFT SDATA SLOAD HIGH 0 PLOAD REG T0 14- BIT T1 DECODE T2 • T2=T1=1, T0=0: Test Mode • SCLOCK is selected, MCNT is on TEST output, SCLOCK � N is on FOUT pin. PLOAD acts as reset for test pin latch. When latch reset, T2 data is shifted out TEST pin. Figure 6. Serial Test Clock Block Diagram http://onsemi.com 10 NBC12429 APPLICATIONS INFORMATION Using the On-Board Crystal Oscillator Power Supply Filtering The NBC12429 features a fully integrated on-board The NBC12429 is a mixed analog/digital product and as crystal oscillator to minimize system implementation costs. such, it exhibits some sensitivities that would not necessarily The oscillator is a series resonant, multivibrator type design be seen on a fully digital product. Analog circuitry is as opposed to the more common parallel resonant oscillator naturally susceptible to random noise, especially if this noise design. The series resonant design provides better stability is seen on the power supply pins. The NBC12429 provides and eliminates the need for large on chip capacitors. The separate power supplies for the digital circuitry (V ) and CC oscillator is totally self contained so that the only external the internal PLL (PLL_V ) of the device. The purpose of CC component required is the crystal. As the oscillator is this design technique is to try and isolate the high switching somewhat sensitive to loading on its inputs, the user is noise of the digital outputs from the relatively sensitive advised to mount the crystal as close to the NBC12429 as internal analog phase-locked loop. In a controlled possible to avoid any board level parasitics. To facilitate environment such as an evaluation board, this level of co-location, surface mount crystals are recommended, but isolation is sufficient. However, in a digital system not required. Because the series resonant design is affected environment where it is more difficult to minimize noise on by capacitive loading on the crystal terminals, loading the power supplies, a second level of isolation may be variation introduced by crystals from different vendors required. The simplest form of isolation is a power supply could be a potential issue. For crystals with a higher shunt filter on the PLL_V pin for the NBC12429. CC capacitance, it may be required to place a resistance across Figure 7 illustrates a typical power supply filter scheme. the terminals to suppress the third harmonic. Although The NBC12429 is most susceptible to noise with spectral typically not required, it is a good idea to layout the PCB content in the 1 KHz to 1 MHz range. Therefore, the filter with the provision of adding this external resistor. The should be designed to target this range. The key parameter resistor value will typically be between 500�� and 1 K�. that needs to be met in the final filter design is the DC voltage The oscillator circuit is a series resonant circuit and thus, drop that will be seen between the V supply and the CC for optimum performance, a series resonant crystal should PLL_V pin of the NBC12429. From the data sheet, the CC be used. Unfortunately, most crystals are characterized in a PLL_V current (the current sourced through the CC parallel resonant mode. Fortunately, there is no physical PLL_V pin) is typically 23 mA (27 mA maximum). CC difference between a series resonant and a parallel resonant Assuming that a minimum of 2.8 V must be maintained on crystal. The difference is purely in the way the devices are the PLL_V pin, very little DC voltage drop can be CC characterized. As a result, a parallel resonant crystal can be tolerated when a 3.3 V V supply is used. The resistor CC used with the NBC12429 with only a minor error in the shown in Figure 7 must have a resistance of 10-15 � to meet desired frequency. A parallel resonant mode crystal used in the voltage drop criteria. The RC filter pictured will provide a series resonant circuit will exhibit a frequency of a broadband filter with approximately 100:1 attenuation for oscillation a few hundred ppm lower than specified (a few noise whose spectral content is above 20 KHz. As the noise hundred ppm translates to kHz inaccuracies). In a general frequency crosses the series resonant point of an individual computer application, this level of inaccuracy is immaterial. capacitor, it’s overall impedance begins to look inductive Table 4 below specifies the performance requirements of the and thus increases with increasing frequency. The parallel crystals to be used with the NBC12429. capacitor combination shown ensures that a low impedance path to ground exists for frequencies well above the Table 4. Crystal Specifications bandwidth of the PLL. Parameter Value 3.3 V or 3.3 V or 5.0 V 5.0 V Crystal Cut Fundamental AT Cut Resonance Series Resonance* L=1000 �H R = 10-15 � Frequency Tolerance ±75 ppm at 25°C S R=15 � Frequency/Temperature Stability ±150 ppm 0 to 70°C PLL_V CC Operating Range 0 to 70°C 22 �F NBC12429 0.01 �F Shunt Capacitance 5-7 pF Equivalent Series Resistance (ESR) 50 to 80 � V CC Correlation Drive Level 100 �W 0.01 �F Aging 5 ppm/Yr (First 3 Years) * See accompanying text for series versus parallel resonant Figure 7. Power Supply Filter discussion. http://onsemi.com 11 NBC12429 between V A higher level of attenuation can be achieved by replacing and GND for the bypass capacitors. CC the resistor with an appropriate valued inductor. Figure 7 Combining good quality general purpose chip capacitors shows a 1000 �H choke. This value choke will show a with good PCB layout techniques will produce effective significant impedance at 10 KHz frequencies and above. capacitor resonances at frequencies adequate to supply the Because of the current draw and the voltage that must be instantaneous switching current for the NBC12429 outputs. maintained on the PLL_V pin, a low DC resistance It is imperative that low inductance chip capacitors are used. CC inductor is required (less than 15��). Generally, the It is equally important that the board layout not introduce resistor/capacitor filter will be cheaper, easier to implement, any of the inductance saved by using the leadless capacitors. and provide an adequate level of supply filtering. Thin interconnect traces between the capacitor and the The NBC12429 provides sub-nanosecond output edge power plane should be avoided and multiple large vias rates and therefore a good power supply bypassing scheme should be used to tie the capacitors to the buried power is a must. Figure 8 shows a representative board layout for planes. Fat interconnect and large vias will help to minimize the NBC12429. There exists many different potential board layout induced inductance and thus maximize the series layouts and the one pictured is but one. The important aspect resonant point of the bypass capacitors. of the layout in Figure 8 is the low impedance connections C1 C1 ÉÉÉÉÉÉ ÉÉÉÉÉÉ ÉÉÉÉÉÉ ÉÉÉÉÉÉ R1 ÉÉ 1 ÉÉ C3 C2 R1 = 10-15 � C1 = 0.01 �F C2 = 22 �F C3 = 0.1 �F Xtal = V CC ÉÉ ÉÉ = GND = Via Figure 8. PCB Board Layout for NBC12429 (28 PLCC) Note the dotted lines circling the crystal oscillator Although the NBC12429 has several design features to connection to the device. The oscillator is a series resonant minimize the susceptibility to power supply noise (isolated circuit and the voltage amplitude across the crystal is power and grounds and fully differential PLL), there still relatively small. It is imperative that no actively switching may be applications in which overall performance is being signals cross under the crystal as crosstalk energy coupled degraded due to system power supply noise. The power to these lines could significantly impact the jitter of the supply filter and bypass schemes discussed in this section device. Special attention should be paid to the layout of the should be adequate to eliminate power supply noise-related crystal to ensure a stable, jitter free interface between the problems in most designs. crystal and the on-board oscillator. Note the provisions for placing a resistor across the crystal oscillator terminals as discussed in the crystal oscillator section of this data sheet. http://onsemi.com 12 NBC12429 Jitter Performance of the NBC12429 Care must be taken that the measured edge is the edge Jitter is a common parameter associated with clock immediately following the trigger edge. These scopes can generation and distribution. Clock jitter can be defined as the also store a finite number of period durations and deviation in a clock’s output transition from its ideal post-processing software can analyze the data to find the position. maximum and minimum periods. Cycle-to-Cycle Jitter (short-term) is the period Recent hardware and software developments have variation between two adjacent cycles over a defined resulted in advanced jitter measurement techniques. The number of observed cycles. The number of cycles observed Tektronix TDS-series oscilloscopes have superb jitter is application dependent but the JEDEC specification is analysis capabilities on non-contiguous clocks with their 1000 cycles. histogram and statistics capabilities. The Tektronix TDSJIT2/3 Jitter Analysis software provides many key timing parameter measurements and will extend that capability by making jitter measurements on contiguous clock and data cycles from single-shot acquisitions. M1 by Amherst was used as well and both test methods T T 0 1 correlated. This test process can be correlated to earlier test methods T = T - T JITTER(cycle- cycle) 1 0 and is more accurate. All of the jitter data reported on the Figure 9. Cycle-to-Cycle Jitter NBC12429 was collected in this manner. Figure 11 shows the jitter as a function of the output frequency. The graph Peak-to-Peak Jitter is the difference between the shows that for output frequencies from 25 to 400 MHz the highest and lowest acquired value and is represented as the jitter falls within the �20 ps peak-to-peak specification. width of the Gaussian base. The general trend is that as the output frequency is increased, the output edge jitter will decrease. Figure 12 illustrates the RMS jitter performance of the NBC12429 across its specified VCO frequency range. Note that the jitter is a function of both the output frequency as RMS well as the VCO frequency. However, the VCO frequency or one Sigma shows a much stronger dependence. The data presented has Jitter not been compensated for trigger jitter. Long-Term Period Jitter is the maximum jitter observed at the end of a period’s edge when compared to the Typical Time Gaussian position of the perfect reference clock’s edge and is specified Distribution by the number of cycles over which the jitter is measured. The number of cycles used to look for the maximum jitter Figure 10. Peak-to-Peak Jitter varies by application but the JEDEC spec is 10,000 observed cycles. There are different ways to measure jitter and often they The NBC12429 exhibits long term and cycle-to-cycle are confused with one another. The typical method of jitter, which rivals that of SAW based oscillators. This jitter measuring jitter is to look at the timing signal with an performance comes with the added flexibility associated oscilloscope and observe the variations in period-to-period with a synthesizer over a fixed frequency oscillator. The or cycle-to-cycle. If the scope is set up to trigger on every jitter data presented should provide users with enough rising or falling edge, set to infinite persistence mode and information to determine the effect on their overall timing allowed to trace sufficient cycles, it is possible to determine budget. The jitter performance meets the needs of most the maximum and minimum periods of the timing signal. system designs while adding the flexibility of frequency Digital scopes can accumulate a large number of cycles, margining and field upgrades. These features are not create a histogram of the edge placements and record available with a fixed frequency SAW oscillator. peak-to-peak as well as standard deviations of the jitter. http://onsemi.com 13 Jitter Amplitude Peak-to-Peak Jitter (6 sigma) NBC12429 25 25 20 20 15 15 10 10 N = 8 N = 4 5 5 N = 1 N = 2 0 0 200 250 300 350 400 50 100 150 200 250 300 350 400 VCO FREQUENCY (MHz) OUTPUT FREQUENCY (MHz) Figure 12. RMS Jitter vs. Output Frequency Figure 11. RMS Jitter vs. VCO Frequency http://onsemi.com 14 RMS JITTER (ps) RMS JITTER (ps) NBC12429 S_DATA S_CLOCK t HOLD t SET- UP Figure 13. Set-Up and Hold S_DATA t HOLD t S_LOAD SET- UP Figure 14. Set-Up and Hold M[8:0] N[1:0] P_ LOAD t HOLD t SET- UP Figure 15. Set-Up and Hold F OUT F OUT Pulse Width t �pw PERIOD DCO� �PERIOD Figure 16. Output Duty Cycle http://onsemi.com 15 NBC12429 F OUT D Receiver Driver Device Device F D OUT 50 � 50 � V TT V V = - 2.0 V TT CC Figure 17. Typical Termination for Output Driver and Device Evaluation (See Application Note AND8020 - Termination of ECL Logic Devices.) http://onsemi.com 16 NBC12429 PACKAGE DIMENSIONS PLCC-28 FN SUFFIX PLASTIC PLCC PACKAGE CASE 776-02 ISSUE E M S S 0.007 (0.180) T L-M N B Y BRK -N- M S S U 0.007 (0.180) T L-M N D Z -L- -M- W D S S S 0.010 (0.250) T L-M N X G1 V 28 1 VIEW D-D M S S A 0.007 (0.180) T L-M N M S S 0.007 (0.180) T L-M N H Z M S S 0.007 (0.180) T L-M N R K1 C E 0.004 (0.100) G K SEATING -T- J PLANE M S S 0.007 (0.180) T L-M N F VIEW S G1 S S S 0.010 (0.250) T L-M N VIEW S NOTES: INCHES MILLIMETERS 1. DATUMS -L-, -M-, AND -N- DETERMINED DIM MIN MAX MIN MAX WHERE TOP OF LEAD SHOULDER EXITS A 0.485 0.495 12.32 12.57 PLASTIC BODY AT MOLD PARTING LINE. B 0.485 0.495 12.32 12.57 2. DIMENSION G1, TRUE POSITION TO BE C 0.165 0.180 4.20 4.57 MEASURED AT DATUM -T-, SEATING PLANE. 3. DIMENSIONS R AND U DO NOT INCLUDE E 0.090 0.110 2.29 2.79 MOLD FLASH. ALLOWABLE MOLD FLASH IS F 0.013 0.019 0.33 0.48 0.010 (0.250) PER SIDE. G 0.050 BSC 1.27 BSC 4. DIMENSIONING AND TOLERANCING PER H 0.026 0.032 0.66 0.81 ANSI Y14.5M, 1982. J 0.020 --- 0.51 --- 5. CONTROLLING DIMENSION: INCH. K 0.025 --- 0.64 --- 6. THE PACKAGE TOP MAY BE SMALLER THAN R 0.450 0.456 11.43 11.58 THE PACKAGE BOTTOM BY UP TO 0.012 U 0.450 0.456 11.43 11.58 (0.300). DIMENSIONS R AND U ARE V 0.042 0.048 1.07 1.21 DETERMINED AT THE OUTERMOST W 0.042 0.048 1.07 1.21 EXTREMES OF THE PLASTIC BODY X 0.042 0.056 1.07 1.42 EXCLUSIVE OF MOLD FLASH, TIE BAR Y --- 0.020 --- 0.50 BURRS, GATE BURRS AND INTERLEAD Z 2 10 2 10 FLASH, BUT INCLUDING ANY MISMATCH �� �� G1 0.410 0.430 10.42 10.92 BETWEEN THE TOP AND BOTTOM OF THE K1 0.040 --- 1.02 --- PLASTIC BODY. 7. DIMENSION H DOES NOT INCLUDE DAMBAR PROTRUSION OR INTRUSION. THE DAMBAR PROTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE GREATER THAN 0.037 (0.940). THE DAMBAR INTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE SMALLER THAN 0.025 (0.635). http://onsemi.com 17 NBC12429 PACKAGE DIMENSIONS LQFP-32 FA SUFFIX PLASTIC LQFP PACKAGE CASE 873A-02 ISSUE A 4X A A1 0.20 (0.008) AB T-U Z 32 25 1 AE -U- -T- P B V AE B1 DETAIL Y BASE V1 DETAIL Y 17 METAL 8 N ÉÉ 9 4X -Z- ÉÉ 0.20 (0.008) AC T-U Z 9 F D S1 ÉÉ S ÉÉ 8X M� J R DETAIL AD G SECTION AE-AE -AB- E C SEATING -AC- PLANE 0.10 (0.004) AC W Q� H K X DETAIL AD NOTES: MILLIMETERS INCHES 1. DIMENSIONING AND TOLERANCING PER ANSI DIM MIN MAX MIN MAX Y14.5M, 1982. A 7.000 BSC 0.276 BSC 2. CONTROLLING DIMENSION: MILLIMETER. A1 3.500 BSC 0.138 BSC 3. DATUM PLANE -AB- IS LOCATED AT BOTTOM OF B 7.000 BSC 0.276 BSC LEAD AND IS COINCIDENT WITH THE LEAD B1 3.500 BSC 0.138 BSC WHERE THE LEAD EXITS THE PLASTIC BODY AT C 1.400 1.600 0.055 0.063 THE BOTTOM OF THE PARTING LINE. 4. DATUMS -T-, -U-, AND -Z- TO BE DETERMINED D 0.300 0.450 0.012 0.018 AT DATUM PLANE -AB-. E 1.350 1.450 0.053 0.057 5. DIMENSIONS S AND V TO BE DETERMINED AT F 0.300 0.400 0.012 0.016 SEATING PLANE -AC-. G 0.800 BSC 0.031 BSC 6. DIMENSIONS A AND B DO NOT INCLUDE MOLD H 0.050 0.150 0.002 0.006 PROTRUSION. ALLOWABLE PROTRUSION IS J 0.090 0.200 0.004 0.008 0.250 (0.010) PER SIDE. DIMENSIONS A AND B K 0.500 0.700 0.020 0.028 DO INCLUDE MOLD MISMATCH AND ARE M 12 REF �� 12 REF DETERMINED AT DATUM PLANE -AB-. N 0.090 0.160 0.004 0.006 7. DIMENSION D DOES NOT INCLUDE DAMBAR P 0.400 BSC 0.016 BSC PROTRUSION. DAMBAR PROTRUSION SHALL Q 1 �� 5 1 � 5 � NOT CAUSE THE D DIMENSION TO EXCEED R 0.150 0.250 0.006 0.010 0.520 (0.020). 8. MINIMUM SOLDER PLATE THICKNESS SHALL BE S 9.000 BSC 0.354 BSC 0.0076 (0.0003). S1 4.500 BSC 0.177 BSC 9. EXACT SHAPE OF EACH CORNER MAY VARY V 9.000 BSC 0.354 BSC FROM DEPICTION. V1 4.500 BSC 0.177 BSC W 0.200 REF 0.008 REF X 1.000 REF 0.039 REF http://onsemi.com 18 -T-, -U-, -Z- GAUGE PLANE 0.250 (0.010) M 0.20 (0.008) AC T-U Z NBC12429 Notes http://onsemi.com 19 NBC12429 ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. PUBLICATION ORDERING INFORMATION Literature Fulfillment: JAPAN: ON Semiconductor, Japan Customer Focus Center Literature Distribution Center for ON Semiconductor 2-9-1 Kamimeguro, Meguro-ku, Tokyo, Japan 153-0051 P.O. Box 5163, Denver, Colorado 80217 USA Phone: 81-3-5773-3850 Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada Email: r14525@onsemi.com Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada ON Semiconductor Website: http://onsemi.com Email: ONlit@hibbertco.com For additional information, please contact your local N. American Technical Support: 800-282-9855 Toll Free USA/Canada Sales Representative. NBC12429/D http://onsemi.com 20