ON SEMICONDUCTOR CS5173EDR8

CS517x CS517x ALYW ALYW CS5171, CS5172, CS5173, CS5174 1.5 A 280 kHz/560 kHz Boost Regulators The CS5171/2/3/4 products are 280 kHz/560 kHz switching regulators with a high efficiency, 1.5 A integrated switch. These parts http://onsemi.com operate over a wide input voltage range, from 2.7 V to 30 V. The flexibility of the design allows the chips to operate in most power supply configurations, including boost, flyback, forward, inverting, and SEPIC. The ICs utilize current mode architecture, which allows excellent load and line regulation, as well as a practical means for SO−8 limiting current. Combining high frequency operation with a highly D SUFFIX integrated regulator circuit results in an extremely compact power CASE 751 supply solution. The circuit design includes provisions for features such as frequency synchronization, shutdown, and feedback controls PIN CONNECTIONS AND for either positive or negative voltage regulation. These parts are MARKING DIAGRAM pin−to−pin compatible with LT1372/1373. CS5171/3 1 8 V V C SW FB PGND Part Number Frequency Feedback Voltage Polarity Test AGND CS5171 280 kHz positive SS V CC CS5172 280 kHz negative CS5173 560 kHz positive CS5172/4 CS5174 560 kHz negative 1 8 V V C SW Test PGND Features NFB AGND • Integrated Power Switch: 1.5 A Guaranteed SS V CC • Wide Input Range: 2.7 V to 30 V • High Frequency Allows for Small Components x = 1, 2, 3, or 4 • Minimum External Components A = Assembly Location • Easy External Synchronization WL, L = Wafer Lot YY, Y = Year • Built in Overcurrent Protection WW, W = Work Week • Frequency Foldback Reduces Component Stress During an Overcurrent Condition • Thermal Shutdown with Hysteresis ORDERING INFORMATION • Regulates Either Positive or Negative Output Voltages See detailed ordering and shipping information in the package dimensions section on page 21 of this data sheet. • Shut Down Current: 50 �A Maximum • Pin−to−Pin Compatible with LT1372/1373 • Wide Temperature Range − Industrial Grade: −40°C to 125°C − Commercial Grade: 0°C to 125°C  Semiconductor Components Industries, LLC, 2004 1 Publication Order Number: January, 2004 − Rev. 19 CS5171/D CS5171, CS5172, CS5173, CS5174 R2 3.72 k D1 V OUT 8 1 V V SW 5 V C MBRS120T3 2 7 FB PGND C1 0.01 �F 3 6 AGND Test L1 45 + C3 SS V SS CC 22 �F 22 �H 3.3 V R3 R1 + C2 5 k 1.28 k 22 �F Figure 1. Applications Diagram MAXIMUM RATINGS* Rating Value Unit Junction Temperature Range, T −40 to +150 °C J Storage Temperature Range, T −65 to +150 °C STORAGE Package Thermal Resistance: Junction−to−Case, R 45 °C/W �JC 165 °C/W Junction−to−Ambient, R �JA Lead Temperature Soldering: Reflow (Note 1) 230 Peak °C ESD, Human Body Model 1.2 kV 1. 60 second maximum above 183°C. *The maximum package power dissipation must be observed. MAXIMUM RATINGS Pin Name Pin Symbol V V I I MAX MIN SOURCE SINK IC Power Input V 30 V −0.3 V N/A 200 mA CC Shutdown/Sync SS 30 V −0.3 V 1.0 mA 1.0 mA Loop Compensation V 6.0 V −0.3 V 10 mA 10 mA C Voltage Feedback Input FB 10 V −0.3 V 1.0 mA 1.0 mA (CS5171/3 only) Negative Feedback Input NFB −10 V 10 V 1.0 mA 1.0 mA (transient, 10 ms) (CS5172/4 only) Test Pin Test 6.0 V −0.3 V 1.0 mA 1.0 mA Power Ground PGND 0.3 V −0.3 V 4 A 10 mA Analog Ground AGND 0 V 0 V N/A 10 mA Switch Input V 40 V −0.3 V 10 mA 3.0 A SW http://onsemi.com 2 CS5171/3 CS5171, CS5172, CS5173, CS5174 ELECTRICAL CHARACTERISTICS (2.7 V< V < 30 V; Industrial Grade: −40°C < T < 125°C; CC J Commercial Grade: 0°C < T < 125°C; For all CS5171/2/3/4 specifications unless otherwise stated.) J Characteristic Test Conditions Min Typ Max Unit Positive and Negative Error Amplifiers FB Reference Voltage (CS5171/3 only) V tied to FB; measure at FB 1.246 1.276 1.300 V C NFB Reference Voltage (CS5172/4 only) V = 1.25 V −2.55 −2.45 −2.35 V C FB Input Current (CS5171/3 only) FB = V −1.0 0.1 1.0 �A REF NFB Input Current (CS5172/4 only) NFB = NV −16 −10 −5.0 �A REF FB Reference Voltage Line Regulation V = FB − 0.01 0.03 %/V C (CS5171/3 only) NFB Reference Voltage Line Regulation V = 1.25 V − 0.01 0.05 %/V C (CS5172/4 only) Positive Error Amp Transconductance I = ± 25 �A 300 550 800 �Mho VC Negative Error Amp Transconductance I = ± 5 �A 115 160 225 �Mho VC Positive Error Amp Gain Note 2 200 500 − V/V Negative Error Amp Gain Note 2 100 180 320 V/V V Source Current FB = 1.0 V or NFB = −1.9 V, V = 1.25 V 25 50 90 �A C C V Sink Current FB = 1.5 V or NFB = −3.1 V, V = 1.25 V 200 625 1500 �A C C V High Clamp Voltage FB = 1.0 V or NFB = −1.9 V; 1.5 1.7 1.9 V C V sources 25 �A C V Low Clamp Voltage FB = 1.5 V or NFB = −3.1 V, V sinks 25 �A 0.25 0.50 0.65 V C C V Threshold Reduce V from 1.5 V until switching stops 0.75 1.05 1.30 V C C Oscillator Base Operating Frequency CS5171/2, FB = 1 V or NFB = −1.9 V 230 280 310 kHz Reduced Operating Frequency CS5171/2, FB = 0 V or NFB = 0 V 30 52 120 kHz Maximum Duty Cycle CS5171/2 90 94 − % Base Operating Frequency CS5173/4, FB = 1 V or NFB = −1.9 V 460 560 620 kHz Reduced Operating Frequency CS5173/4, FB = 0 V or NFB = 0 V 60 104 160 kHz Maximum Duty Cycle CS5173/4 82 90 − % NFB Frequency Shift Threshold Frequency drops to reduced operating −0.80 −0.65 −0.50 V frequency FB Frequency Shift Threshold Frequency drops to reduced operating 0.36 0.40 0.44 V frequency Sync/ Shutdown Sync Range CS5171/2 320 − 500 kHz Sync Range CS5173/4 640 − 1000 kHz Sync Pulse Transition Threshold Rise time = 20 ns 2.5 − − V SS Bias Current SS = 0 V −15 −3.0 − �A SS = 3.0 V − 3.0 8.0 �A Shutdown Threshold − 0.50 0.85 1.20 V Shutdown Delay 2.7 V ≤ V ≤ 12 V 12 80 350 �s CC 12 V < V ≤ 30 V CC 12 36 200 �s 2. Guaranteed by design, not 100% tested in production. http://onsemi.com 3 CS5171, CS5172, CS5173, CS5174 ELECTRICAL CHARACTERISTICS (continued) (2.7 V< V < 30 V; Industrial Grade: −40°C < T < 125°C; CC J Commercial Grade: 0°C < T < 125°C; For all CS5171/2/3/4 specifications unless otherwise stated.) J Characteristic Test Conditions Min Typ Max Unit Power Switch Switch Saturation Voltage I = 1.5 A, (Note 3) − 0.8 1.4 V SWITCH I = 1.0 A, 0°C ≤ T ≤ 85°C SWITCH J − 0.55 − V I = 1.0 A, −40°C ≤ T ≤ 0°C SWITCH J − 0.75 − V I = 10 mA SWITCH − 0.09 0.45 V Switch Current Limit 50% duty cycle, Note 3 1.6 1.9 2.4 A 80% duty cycle, Note 3 1.5 1.7 2.2 A Minimum Pulse Width FB = 0 V or NFB = 0 V, I = 4.0 A, (Note 3) 200 250 300 ns SW �I / �IV 2.7 V ≤ V ≤ 12 V, 10 mA ≤ I ≤ 1.0 A − 10 30 mA/A CC SW CC SW 12 V < V ≤ 30 V, 10 mA ≤ I ≤ 1.0 A CC SW − − 100 mA/A 2.7 V ≤ V ≤ 12 V, 10 mA ≤ I ≤ 1.5 A, CC SW − 17 30 mA/A Note 3 12 V < V ≤ 30 V, 10 mA ≤ I ≤ 1.5 A, CC SW − − 100 mA/A Note 3 Switch Leakage V = 40 V, V = 0V − 2.0 100 �A SW CC General Operating Current I = 0 − 5.5 8.0 mA SW Shutdown Mode Current V < 0.8 V, SS = 0 V, 2.7 V ≤ V ≤ 12 V − 12 60 �A C CC V < 0.8 V, SS = 0 V, 12 V ≤ V ≤ 30 V − − 100 C CC Minimum Operation Input Voltage V switching, maximum I 10 mA − 2.45 2.70 V SW SW = Thermal Shutdown (Note 3) 150 180 210 °C Thermal Hysteresis (Note 3) − 25 − °C 3. Guaranteed by design, not 100% tested in production. PACKAGE PIN DESCRIPTION Package Pin Number 8 LEAD SO NARROW Pin Symbol Function 1 V Loop compensation pin. The V pin is the output of the error C C amplifier and is used for loop compensation, current limit and soft start. Loop compensation can be implemented by a simple RC network as shown in the application diagram on page 2 as R1 and C1. 2 (CS5171/3 only) FB Positive regulator feedback pin. This pin senses a positive output voltage and is referenced to 1.276 V. When the volt- age at this pin falls below 0.4 V, chip switching frequency reduces to 20% of the nominal frequency. 2 (CS5172/4 only) Test These pins are connected to internal test logic and should either be left floating or tied to ground. Connection to a volt- 3 (CS5171/3 only) age between 2 V and 6 V shuts down the internal oscillator and leaves the power switch running. 3 (CS5172/4 only) NFB Negative feedback pin. This pin senses a negative output voltage and is referenced to −2.5 V. When the voltage at this pin goes above −0.65 V, chip switching frequency reduces to 20% of the nominal frequency. 4 SS Synchronization and shutdown pin. This pin may be used to synchronize the part to nearly twice the base frequency. A TTL low will shut the part down and put it into low current mode. If synchronization is not used, this pin should be ei- ther tied high or left floating for normal operation. http://onsemi.com 4 CS5171, CS5172, CS5173, CS5174 PACKAGE PIN DESCRIPTION Package Pin Number 8 LEAD SO NARROW (continued) Pin Symbol Pin Symbol Function Function 5 V Input power supply pin. This pin supplies power to the part CC and should have a bypass capacitor connected to AGND. 6 AGND Analog ground. This pin provides a clean ground for the controller circuitry and should not be in the path of large currents. The output voltage sensing resistors should be connected to this ground pin. This pin is connected to the IC substrate. 7 PGND Power ground. This pin is the ground connection for the emitter of the power switching transistor. Connection to a good ground plane is essential. 8 V High current switch pin. This pin connects internally to the SW collector of the power switch. The open voltage across the power switch can be as high as 40 V. To minimize radiation, use a trace as short as practical. V CC Thermal Shutdown Shutdown 2.0 V V SW Regulator PWM Oscillator S Delay Q Switch Latch Driver Timer R Sync SS Frequency Shift 5:1 ×5 200 k Slope Compensation Negative 2.0 V Error Amp 63 m� 250 k NFB + PGND Ramp CS5172/4 Summer − only PWM Comparator −0.65 V Detector + − 0.4 V Detector FB − CS5171/3 + only Positive Error Amp 1.276 V AGND V C Figure 2. Block Diagram http://onsemi.com 5 CS5171, CS5172, CS5173, CS5174 TYPICAL PERFORMANCE CHARACTERISTICS 7.2 70 7.0 V = 30 V 60 CC V = 30 V CC 6.8 50 I = 1.5 A SW 6.6 40 V = 12 V 6.4 CC 30 V = 12 V 6.2 CC 20 6.0 V = 2.7 V 10 5.8 CC V = 2.7 V CC 5.6 0 0 50 100 0 50 100 Temperature (°C) Temperature (°C) Figure 3. I (No Switching) vs. Temperature Figure 4. �I / �IV vs. Temperature CC CC SW 1.9 1200 1000 −40 °C 1.8 800 85 °C 600 1.7 25 °C 400 1.6 200 1.5 0 500 1000 0 50 100 I (mA) SW Temperature (°C) Figure 6. Minimum Input Voltage vs. Temperature Figure 5. V vs. I CE(SAT) SW 285 570 565 280 560 555 275 550 270 545 540 265 535 530 260 525 520 255 0 50 100 0 50 100 Temperature (°C) Temperature (°C) Figure 8. Switching Frequency vs. Temperature Figure 7. Switching Frequency vs. Temperature (CS5173/4 only) (CS5171/2 only) http://onsemi.com 6 V (mV) Current (mA) CE(SAT) f (kHz) OSC f (kHz) OSC V (V) (mA/A) IN CS5171, CS5172, CS5173, CS5174 TYPICAL PERFORMANCE CHARACTERISTICS V = (12 V) CC V = (12 V) CC 100 100 −40°C 85°C 75 75 85°C −40°C 50 50 25°C 25 25 25°C 0 0 350 380 400 420 450 −550 −660 −725 V (mV) V (mV) NFB FB Figure 10. Switching Frequency vs. V Figure 9. Switching Frequency vs. V NFB FB (CS5172/4 only) (CS5171/3 only) 1.280 V = 12 V CC −2.42 1.278 V = 30 V CC −2.43 1.276 −2.44 1.274 −2.45 V = 2.7 V CC V = 12 V CC 1.272 V = 30 V CC −2.46 1.270 −2.47 V = 2.7 V CC 1.268 −2.48 0 50 100 0 50 100 Temperature (°C) Temperature (°C) Figure 11. Reference Voltage vs. Temperature Figure 12. Reference Voltage vs. Temperature (CS5171/3 only) (CS5172/4 only) 0.20 −7 −8 0.18 −9 0.16 V = 12 V CC −10 0.14 −11 0.12 −12 0.10 V = 2.7 V CC −13 0.08 −14 0 50 100 0 50 100 Temperature (°C) Temperature (°C) Figure 13. I vs. Temperature (CS5171/3 only) Figure 14. I vs. Temperature (CS5172/ 4 only) FB NFB http://onsemi.com 7 Voltage (V) I (�A) f (% of Typical) FB OSC Voltage (V) I (�A) NFB f (% of Typical) OSC CS5171, CS5172, CS5173, CS5174 TYPICAL PERFORMANCE CHARACTERISTICS 2.60 99 V = 30 V CC 98 V = 12 V CC 2.50 97 96 2.40 V = 2.7 V CC 95 V = 2.7 V CC 2.30 94 V = 12 V CC V = 30 V CC 93 2.20 0 50 100 0 50 100 Temperature (°C) Temperature (°C) Figure 16. Maximum Duty Cycle vs. Temperature Figure 15. Current Limit vs. Temperature 1.1 1.7 1.0 V High Clamp Voltage C 0.9 1.5 0.8 1.3 0.7 1.1 0.6 V Threshold C 0.9 0.5 0.4 0.7 0 50 100 0 50 100 Temperature (°C) Temperature (°C) Figure 18. Shutdown Threshold vs. Temperature Figure 17. V Threshold and High Clamp C Voltage vs. Temperature 160 40 25°C 140 V = 2.7 V CC 30 85°C 120 20 100 −40°C V = 12 V CC 10 80 V = 30 V CC 0 60 40 −10 0 50 100 1739 5 Temperature (°C) V (V) SS Figure 20. I vs. V Figure 19. Shutdown Delay vs. Temperature SS SS http://onsemi.com 8 Current (A) Delay (�s) Voltage (V) Voltage (V) I (�A) Duty Cycle (%) SS CS5171, CS5172, CS5173, CS5174 TYPICAL PERFORMANCE CHARACTERISTICS 600 −40°C 40 550 30 25°C 20 85°C 500 10 450 0 0 50 100 10 Temperature (°C) V (V) IN Figure 22. Error Amplifier Transconductance Figure 21. I vs. V During Shutdown CC IN vs. Temperature (CS5171/3 only) 100 190 180 170 60 160 150 20 140 130 −20 120 110 −60 100 −255 −175 −125 −75 −25 0 25 0 50 100 V − V (mV) Temperature (°C) REF FB Figure 24. Error Amplifier I vs. V Figure 23. Negative Error Amplifier OUT FB (CS5171/3 only) Transconductance vs. Temperature (CS5172/4 only) 2.6 100 2.5 80 60 2.4 40 2.3 20 0 2.2 −20 2.1 −40 −60 2.0 −200 −150 −100 −50 0 50 0 50 100 Temperature (°C) V − V (mV) REF NFB Figure 26. Switch Leakage vs. Temperature Figure 25. Error Amplifier I vs. V OUT NFB (CS5172/4 only) http://onsemi.com 9 g (�mho) m I (�A) I (�A) OUT CC g (�mho) Current (�A) m I (�A) OUT CS5171, CS5172, CS5173, CS5174 APPLICATIONS INFORMATION THEORY OF OPERATION The oscillator is trimmed to guarantee an 18% frequency Current Mode Control accuracy. The output of the oscillator turns on the power switch at a frequency of 280 kHz (CS5171/2) or 560 kHz V (CS5173/4), as shown in Figure 27. The power switch is CC Oscillator turned off by the output of the PWM Comparator. S Q L A TTL−compatible sync input at the SS pin is capable of − V C R + syncing up to 1.8 times the base oscillator frequency. As Power Switch D1 PWM V shown in Figure 28, in order to sync to a higher frequency, SW Comparator In Out C a positive transition turns on the power switch before the O R LOAD Driver output of the oscillator goes high, thereby resetting the X5 oscillator. The sync operation allows multiple power SUMMER 63 m� Slope Compensation supplies to operate at the same frequency. A sustained logic low at the SS pin will shut down the IC and reduce the supply current. Figure 27. Current Mode Control Scheme An additional feature includes frequency shift to 20% of the nominal frequency when either the NFB or FB pins The CS517x family incorporates a current mode control trigger the threshold. During power up, overload, or short scheme, in which the PWM ramp signal is derived from the circuit conditions, the minimum switch on−time is limited power switch current. This ramp signal is compared to the by the PWM comparator minimum pulse width. Extra output of the error amplifier to control the on−time of the switch off−time reduces the minimum duty cycle to protect power switch. The oscillator is used as a fixed−frequency external components and the IC itself. clock to ensure a constant operational frequency. The resulting control scheme features several advantages over As previously mentioned, this block also produces a ramp conventional voltage mode control. First, derived directly for the slope compensation to improve regulator stability. from the inductor, the ramp signal responds immediately to Error Amplifier line voltage changes. This eliminates the delay caused by the 200 k output filter and error amplifier, which is commonly found 2.0 V 250 k in voltage mode controllers. The second benefit comes from NFB + inherent pulse−by−pulse current limiting by merely CS5172/4 − clamping the peak switching current. Finally, since current negative error−amp V mode commands an output current rather than voltage, the C C1 120 pF filter offers only a single pole to the feedback loop. This 1M� 0.01 �F Voltage + allows both a simpler compensation and a higher 1.276 V Clamp R1 gain−bandwidth over a comparable voltage mode circuit. − 5 k� FB CS5171/3 Without discrediting its apparent merits, current mode positive error−amp control comes with its own peculiar problems, mainly, Figure 29. Error Amplifier Equivalent Circuit subharmonic oscillation at duty cycles over 50%. The For CS5172/4, the NFB pin is internally referenced to CS517x family solves this problem by adopting a slope −2.5 V with approximately a 250 k� input impedance. For compensation scheme in which a fixed ramp generated by CS5171/3, the FB pin is directly connected to the inverting the oscillator is added to the current ramp. A proper slope input of the positive error amplifier, whose non−inverting rate is provided to improve circuit stability without input is fed by the 1.276 V reference. Both amplifiers are sacrificing the advantages of current mode control. transconductance amplifiers with a high output impedance Oscillator and Shutdown of approximately 1 M�, as shown in Figure 29. The V pin C Sync is connected to the output of the error amplifiers and is Current internally clamped between 0.5 V and 1.7 V. A typical Ramp connection at the V pin includes a capacitor in series with C V SW a resistor to ground, forming a pole/zero for loop compensation. Figure 28. Timing Diagram of Sync and Shutdown An external shunt can be connected between the V pin C and ground to reduce its clamp voltage. Consequently, the current limit of the internal power transistor current is reduced from its nominal value. Switch Driver and Power Switch The switch driver receives a control signal from the logic section to drive the output power switch. The switch is http://onsemi.com 10 CS5171, CS5172, CS5173, CS5174 When the V grounded through emitter resistors (63 m� total) to the pin voltage rises above the threshold, the C PGND pin. PGND is not connected to the IC substrate so that internal power switch starts to switch and a voltage pulse can switching noise can be isolated from the analog ground. The be seen at the V pin. Detecting a low output voltage at the SW peak switching current is clamped by an internal circuit. The FB pin, the built−in frequency shift feature reduces the clamp current is guaranteed to be greater than 1.5 A and switching frequency to a fraction of its nominal value, varies with duty cycle due to slope compensation. The reducing the minimum duty cycle, which is otherwise power switch can withstand a maximum voltage of 40 V on limited by the minimum on−time of the switch. The peak the collector (V pin). The saturation voltage of the switch current during this phase is clamped by the internal current SW is typically less than 1 V to minimize power dissipation. limit. When the FB pin voltage rises above 0.4 V, the frequency Short Circuit Condition increases to its nominal value, and the peak current begins When a short circuit condition happens in a boost circuit, to decrease as the output approaches the regulation voltage. the inductor current will increase during the whole The overshoot of the output voltage is prevented by the switching cycle, causing excessive current to be drawn from active pull−on, by which the sink current of the error the input power supply. Since control ICs don’t have the amplifier is increased once an overvoltage condition is means to limit load current, an external current limit circuit detected. The overvoltage condition is defined as when the (such as a fuse or relay) has to be implemented to protect the FB pin voltage is 50 mV greater than the reference voltage. load, power supply and ICs. In other topologies, the frequency shift built into the IC COMPONENT SELECTION prevents damage to the chip and external components. This Frequency Compensation feature reduces the minimum duty cycle and allows the The goal of frequency compensation is to achieve transformer secondary to absorb excess energy before the desirable transient response and DC regulation while switch turns back on. ensuring the stability of the system. A typical compensation network, as shown in Figure 31, provides a frequency response of two poles and one zero. This frequency response is further illustrated in the Bode plot shown in Figure 32. I L V C V OUT R1 V CC CS5171 C2 C1 V C GND Figure 31. A Typical Compensation Network Figure 30. Startup Waveforms of Circuit Shown in The high DC gain in Figure 32 is desirable for achieving the Application Diagram. Load = 400 mA. DC accuracy over line and load variations. The DC gain of The CS517x can be activated by either connecting the a transconductance error amplifier can be calculated as V pin to a voltage source or by enabling the SS pin. CC follows: Startup waveforms shown in Figure 30 are measured in the Gain � G � R DC M O boost converter demonstrated in the Application Diagram where: on the page 2 of this document. Recorded after the input G = error amplifier transconductance; voltage is turned on, this waveform shows the various M R = error amplifier output resistance ≈ 1 M�. phases during the power up transition. O The low frequency pole, f is determined by the error When the V voltage is below the minimum supply CC P1, amplifier output resistance and C1 as: voltage, the V pin is in high impedance. Therefore, SW current conducts directly from the input power source to the 1 f � P1 output through the inductor and diode. Once V reaches 2�C1R CC O approximately 1.5 V, the internal power switch briefly turns The first zero generated by C1 and R1 is: on. This is a part of the CS517x’s normal operation. The 1 turn−on of the power switch accounts for the initial current f � Z1 2�C1R1 swing. http://onsemi.com 11 CS5171, CS5172, CS5173, CS5174 The phase lead provided by this zero ensures that the loop −V 2 V OUT has at least a 45° phase margin at the crossover frequency. Therefore, this zero should be placed close to the pole R P 200 k� generated in the power stage which can be identified at R1 frequency: R IN NFB + 1 250 k� f � P 2�C R O LOAD R2 − where: Negative Error−Amp C = equivalent output capacitance of the error amplifier O ≈120pF; Figure 33. Negative Error Amplifier and NFB Pin R = load resistance. LOAD The high frequency pole, f , can be placed at the output P2 It is shown that if R1 is less than 10 k, the deviation from filter’s ESR zero or at half the switching frequency. Placing the design target will be less than 0.1 V. If the tolerances of the pole at this frequency will cut down on switching noise. the negative voltage reference and NFB pin input current are The frequency of this pole is determined by the value of C2 considered, the possible offset of the output V varies OFFSET and R1: in the range of: 1 f � �0.0.5 (R1� R2) P2 2�C2R1 � � � (15�A� R1)� V OFFSET R2 One simple method to ensure adequate phase margin is to 0.0.5 (R1� R2) design the frequency response with a −20 dB per decade � � � � (5�A� R1) R2 slope, until unity−gain crossover. The crossover frequency should be selected at the midpoint between f and f where V Voltage Limit Z1 P2 SW the phase margin is maximized. In the boost topology, V pin maximum voltage is set by SW the maximum output voltage plus the output diode forward voltage. The diode forward voltage is typically 0.5 V for Schottky diodes and 0.8 V for ultrafast recovery diodes f P1 V � V �V SW(MAX) OUT(MAX) F f Z1 where: f P2 V = output diode forward voltage. F In the flyback topology, peak V voltage is governed by: SW V � V �(V �V )� N SW(MAX) CC(MAX) OUT F where: Frequency (LOG) N = transformer turns ratio, primary over secondary. Figure 32. Bode Plot of the Compensation Network When the power switch turns off, there exists a voltage Shown in Figure 31 spike superimposed on top of the steady−state voltage. Negative Voltage Feedback Usually this voltage spike is caused by transformer leakage Since the negative error amplifier has finite input inductance charging stray capacitance between the V and SW impedance as shown in Figure 33, its induced error has to be PGND pins. To prevent the voltage at the V pin from SW considered. If a voltage divider is used to scale down the exceeding the maximum rating, a transient voltage negative output voltage for the NFB pin, the equation for suppressor in series with a diode is paralleled with the calculating output voltage is: primary windings. Another method of clamping switch �2.5 (R1� R2) voltage is to connect a transient voltage suppressor between � � �V � �10�A� R1 OUT R2 the V pin and ground. SW http://onsemi.com 12 Gain (dB) DC Gain CS5171, CS5172, CS5173, CS5174 I Magnetic Component Selection I L IN When choosing a magnetic component, one must consider factors such as peak current, core and ferrite material, output voltage ripple, EMI, temperature range, physical size and cost. In boost circuits, the average inductor current is the + V C CC IN − product of output current and voltage gain (V /V ), OUT CC assuming 100% energy transfer efficiency. In continuous conduction mode, inductor ripple current is R ESR V (V � V ) CC OUT CC I � RIPPLE (f)(L)(V OUT) where: f = 280 kHz for CS5171/2 and 560 kHz for CS5173/4. Figure 35. Boost Circuit Effective Input Filter The peak inductor current is equal to average current plus half of the ripple current, which should not cause inductor The situation is different in a flyback circuit. The input saturation. The above equation can also be referenced when current is discontinuous and a significant pulsed current is selecting the value of the inductor based on the tolerance of seen by the input capacitors. Therefore, there are two the ripple current in the circuits. Small ripple current requirements for capacitors in a flyback regulator: energy provides the benefits of small input capacitors and greater storage and filtering. To maintain a stable voltage supply to output current capability. A core geometry like a rod or the chip, a storage capacitor larger than 20 �F with low ESR barrel is prone to generating high magnetic field radiation, is required. To reduce the noise generated by the inductor, but is relatively cheap and small. Other core geometries, insert a 1.0 �F ceramic capacitor between V and ground CC such as toroids, provide a closed magnetic loop to prevent as close as possible to the chip. EMI. Output Capacitor Selection Input Capacitor Selection In boost circuits, the inductor becomes part of the input filter, as shown in Figure 35. In continuous mode, the input current waveform is triangular and does not contain a large pulsed current, as shown in Figure 34. This reduces the requirements imposed on the input capacitor selection. V ripple During continuous conduction mode, the peak to peak OUT inductor ripple current is given in the previous section. As we can see from Figure 34, the product of the inductor current ripple and the input capacitor’s effective series resistance (ESR) determine the V ripple. In most CC I L applications, input capacitors in the range of 10 �F to 100 �F with an ESR less than 0.3 � work well up to a full 1.5 A switch current. Figure 36. Typical Output Voltage Ripple By examining the waveforms shown in Figure 36, we can see that the output voltage ripple comes from two major V ripple CC sources, namely capacitor ESR and the charging/discharging of the output capacitor. In boost circuits, when the power switch turns off, I flows into the I L IN output capacitor causing an instant �V = I × ESR. At the IN same time, current I − I charges the capacitor and L OUT increases the output voltage gradually. When the power I L switch is turned on, I is shunted to ground and I L OUT discharges the output capacitor. When the I ripple is small L enough, I can be treated as a constant and is equal to input L current I . Summing up, the output voltage peak−peak IN Figure 34. Boost Input Voltage and Current ripple can be calculated by: Ripple Waveforms http://onsemi.com 13 CS5171, CS5172, CS5173, CS5174 V (I � I (1� D) IN OUT) IN V � OUT(RIPPLE) (C (f) OUT) V CC I D OUT � � I � ESR IN (C )(f) R2 OUT The equation can be expressed more conveniently in V C terms of V , V and I for design purposes as CC OUT OUT D1 follows: I (V � V ) OUT OUT CC 1 V � � OUT(RIPPLE) (C )(f) (C )(f) OUT OUT R3 (I )(V )(ESR) OUT OUT � R1 V CC C1 The capacitor RMS ripple current is: � 2 2 C2 I � (I � I ) (1� D)�(I ) (D) RIPPLE IN OUT OUT V � V OUT CC � � I OUT V CC Figure 37. Current Limiting using a Diode Clamp Another solution to the current limiting problem is to Although the above equations apply only for boost externally measure the current through the switch using a circuits, similar equations can be derived for flyback sense resistor. Such a circuit is illustrated in Figure 38. circuits. Reducing the Current Limit In some applications, the designer may prefer a lower V CC limit on the switch current than 1.5 A. An external shunt can be connected between the V pin and ground to reduce its C clamp voltage. Consequently, the current limit of the V PGND AGND C internal power transistor current is reduced from its nominal V IN value. The voltage on the V pin can be evaluated with the C equation R1 C1 V � I R A C SW E V R2 C2 Q1 where: C3 R = .063�, the value of the internal emitter resistor; E Output R A = 5 V/V, the gain of the current sense amplifier. Ground SENSE V Since R and A cannot be changed by the end user, the Figure 38. Current Limiting using a Current Sense E V only available method for limiting switch current below 1.5 Resistor A is to clamp the V pin at a lower voltage. If the maximum The switch current is limited to C switch or inductor current is substituted into the equation V BE(Q1) I � above, the desired clamp voltage will result. SWITCH(PEAK) R SENSE A simple diode clamp, as shown in Figure 37, clamps the where: V voltage to a diode drop above the voltage on resistor R3. C V = the base−emitter voltage drop of Q1, typically Unfortunately, such a simple circuit is not generally BE(Q1) 0.65 V. acceptable if V is loosely regulated. IN http://onsemi.com 14 − + CS5171, CS5172, CS5173, CS5174 The improved circuit does not require a regulated voltage The dashed box contains the normal compensation to operate properly. Unfortunately, a price must be paid for circuitry to limit the bandwidth of the error amplifier. this convenience in the overall efficiency of the circuit. The Resistors R2 and R3 form a voltage divider off of the V SW designer should note that the input and output grounds are pin. In normal operation, V looks similar to a square SW no longer common. Also, the addition of the current sense wave, and is dependent on the converter topology. Formulas resistor, R , results in a considerable power loss which for calculating V in the boost and flyback topologies are SENSE SW increases with the duty cycle. Resistor R2 and capacitor C3 given in the section “V Voltage Limit.” The voltage on SW form a low−pass filter to remove noise. V charges capacitor C3 when the switch is off, causing SW the voltage at the V pin to shift upwards. When the switch Subharmonic Oscillation C turns on, C3 discharges through R3, producing a negative Subharmonic oscillation (SHM) is a problem found in slope at the V pin. This negative slope provides the slope current−mode control systems, where instability results C compensation. when duty cycle exceeds 50%. SHM only occurs in The amount of slope compensation added by this circuit switching regulators with a continuous inductor current. is This instability is not harmful to the converter and usually �(1�D) does not affect the output voltage regulation. SHM will R f �I 3 SW R C f 3 3 SW � �� �� � � V 1� e increase the radiated EM noise from the converter and can SW �T R �R (1� D)R A 2 3 E V cause, under certain circumstances, the inductor to emit where: high−frequency audible noise. �I/�T = the amount of slope compensation added (A/s); SHM is an easily remedied problem. The rising slope of V = the voltage at the switch node when the transistor the inductor current is supplemented with internal “slope SW is turned off (V); compensation” to prevent any duty cycle instability from f = the switching frequency, typically 280 kHz carrying through to the next switching cycle. In the CS517x SW (CS5171/3) or 560 kHz (CS5172/4) (Hz); family, slope compensation is added during the entire switch D = the duty cycle; on−time, typically in the amount of 180 mA/�s. R = 0.063 �, the value of the internal emitter resistor; In some cases, SHM can rear its ugly head despite the E A = 5 V/V, the gain of the current sense amplifier. presence of the onboard slope compensation. The simple V cure to this problem is more slope compensation to avoid the In selecting appropriate values for the slope compensation unwanted oscillation. In that case, an external circuit, shown network, the designer is advised to choose a convenient capacitor, then select values for R2 and R3 such that the in Figure 39, can be added to increase the amount of slope amount of slope compensation added is 100 mA/�s. Then compensation used. This circuit requires only a few R2 may be increased or decreased as necessary. Of course, components and is “tacked on” to the compensation the series combination of R2 and R3 should be large enough network. to avoid drawing excessive current from V . Additionally, SW to ensure that the control loop stability is improved, the time V V SW SW constant formed by the additional components should be chosen such that V C 1� D R C � 3 3 f SW Finally, it is worth mentioning that the added slope compensation is a trade−off between duty cycle stability and R1 R2 transient response. The more slope compensation a designer C1 adds, the slower the transient response will be, due to the external circuitry interfering with the proper operation of the C2 error amplifier. Soft Start Through the addition of an external circuit, a soft−start function can be added to the CS5171/2/3/4 family of C3 R3 components. Soft−start circuitry prevents the V pin from C slamming high during start−up, thereby inhibiting the inductor current from rising at a high slope. Figure 39. Technique for Increasing Slope Compensation http://onsemi.com 15 CS5171, CS5172, CS5173, CS5174 This circuit, shown in Figure 40, requires a minimum found in the graph of operating current vs. temperature. This number of components and allows the soft−start circuitry to graph shows that IQ is strongly dependent on input voltage, activate any time the SS pin is used to restart the converter. V , and temperature. Then IN P � V I BIAS IN Q V IN Since the onboard switch is an NPN transistor, the base drive current must be factored in as well. This current is V CC drawn from the V pin, in addition to the control circuitry IN SS current. The base drive current is listed in the specifications SS as �I /�I , or switch transconductance. As before, the CC SW V C designer will find additional guidance in the graphs. With that information, the designer can calculate I CC P � V I � � D DRIVER IN SW D2 �I D1 SW R1 where: C1 I = the current through the switch; SW D = the duty cycle or percentage of switch on−time. C2 C3 I and D are dependent on the type of converter. In a SW boost converter, 1 I � I � D� SW(AVG) LOAD Efficiency V � V Figure 40. Soft Start OUT IN D� V OUT Resistor R1 and capacitors C1 and C2 form the In a flyback converter, compensation network. At turn on, the voltage at the V pin C starts to come up, charging capacitor C3 through Schottky V I OUT LOAD 1 I � � SW(AVG) diode D2, clamping the voltage at the V pin such that V Efficiency C IN switching begins when V reaches the V threshold, C C V OUT D� typically 1.05 V (refer to graphs for detail over temperature). N S V � V OUT IN N P V � V �V C F(D2) C3 The switch saturation voltage, V , is the last major (CE)SAT Therefore, C3 slows the start−up of the circuit by limiting source of on−chip power loss. V is the (CE)SAT the voltage on the V pin. The soft−start time increases with C collector−emitter voltage of the internal NPN transistor the size of C3. when it is driven into saturation by its base drive current. The Diode D1 discharges C3 when SS is low. If the shutdown value for V can be obtained from the specifications (CE)SAT function is not used with this part, the cathode of D1 should or from the graphs, as “Switch Saturation Voltage.” Thus, be connected to V . IN P � V I � D SAT (CE)SAT SW Calculating Junction Temperature To ensure safe operation of the CS5171/2/3/4, the Finally, the total on−chip power losses are designer must calculate the on−chip power dissipation and P � P �P �P D BIAS DRIVER SAT determine its expected junction temperature. Internal Power dissipation in a semiconductor device results in the thermal protection circuitry will turn the part off once the generation of heat in the junctions at the surface of the chip. junction temperature exceeds 180°C ± 30°. However, This heat is transferred to the surface of the IC package, but repeated operation at such high temperatures will ensure a a thermal gradient exists due to the resistive properties of the reduced operating life. package molding compound. The magnitude of the thermal Calculation of the junction temperature is an imprecise gradient is expressed in manufacturers’ data sheets as � , JA but simple task. First, the power losses must be quantified. or junction−to−ambient thermal resistance. The on−chip There are three major sources of power loss on the CS517x: junction temperature can be calculated if � , the air JA • biasing of internal control circuitry, P BIAS temperature near the surface of the IC, and the on−chip • switch driver, P DRIVER power dissipation are known. • switch saturation, P SAT T � T �(P � ) J A D JA The internal control circuitry, including the oscillator and where: linear regulator, requires a small amount of power even T = IC or FET junction temperature (°C); J when the switch is turned off. The specifications section of T = ambient temperature (°C); A this datasheet reveals that the typical operating current, I , Q P = power dissipated by part in question (W); D due to this circuitry is 5.5 mA. Additional guidance can be http://onsemi.com 16 CS5171, CS5172, CS5173, CS5174 Circuit Layout Guidelines � = junction−to−ambient thermal resistance (°C/W). JA In any switching power supply, circuit layout is very For the CS517x, � =165°C/W. JA important for proper operation. Rapidly switching currents Once the designer has calculated T , the question of J combined with trace inductance generates voltage whether the CS517x can be used in an application is settled. transitions that can cause problems. Therefore the following If T exceeds 150°C, the absolute maximum allowable J guidelines should be followed in the layout. junction temperature, the CS517x is not suitable for that application. 1. In boost circuits, high AC current circulates within the If T approaches 150°C, the designer should consider J loop composed of the diode, output capacitor, and possible means of reducing the junction temperature. on−chip power transistor. The length of associated Perhaps another converter topology could be selected to traces and leads should be kept as short as possible. In reduce the switch current. Increasing the airflow across the the flyback circuit, high AC current loops exist on both surface of the chip might be considered to reduce T . A sides of the transformer. On the primary side, the loop consists of the input capacitor, transformer, and on−chip power transistor, while the transformer, rectifier diodes, and output capacitors form another loop on the secondary side. Just as in the boost circuit, all traces and leads containing large AC currents should be kept short. 2. Separate the low current signal grounds from the power grounds. Use single point grounding or ground plane construction for the best results. 3. Locate the voltage feedback resistors as near the IC as possible to keep the sensitive feedback wiring short. Connect feedback resistors to the low current analog ground. http://onsemi.com 17 CS5171, CS5172, CS5173, CS5174 R2 4.87 k D1 C4 V OUT 1 8 V V −12 V C SW + 22 �F MBRS120T3 2 7 Test PGND C1 3 0.01 �F 6 NFB AGND + C3 L1 4 22 �F 5 SS SS V CC 22 �H V D2 CC MBRS120T3 5.0 V R3 + R1 C2 1.27 k 5.0 k 22 �F Figure 41. Additional Application Diagram, 5.0 V to −12 V/ 75 mA Inverting Converter 22 �H MBRS120T3 3.3 V 5.0 V IN O 10 �F 22 �F 3.6 k V (5) CC GND PGND (7) GND V (8) SW AGND (6) CS5171/3 V (1 ) FB (2) C 0.1 �F 1.3 k 200 pF 5.0 k Figure 42. Additional Application Diagram, 3.3 V Input, 5.0 V/ 400 mA Output Boost Converter http://onsemi.com 18 CS5172/4 CS5171, CS5172, CS5173, CS5174 MBRS140T3 V −12 V CC P6KE−15A T1 47 �F + + 1.0 �F 22 �F GND V (5) CC 47 �F 1N4148 + 1:2 GND PGND (7) V (8) +12 V SW AGND (6) MBRS140T3 CS5171/3 V (1 ) FB (2) C 10.72 k 47 nF 1.28 k 4.7 nF 2.0 k Figure 43. Additional Application Diagram, 2.7 to 13 V Input, �12 V/ 200 mA Output Flyback Converter GND V (1 ) V (5) GND CC C 1.1 k 5.0 k 22 �F 2.2 �F CS5171/3 200 pF Low 15 �H ESR −5.0 V (8) .01 �F SW V OUT V AGND (6) FB (2) IN PGND (7) 300 Figure 44. Additional Application Diagram, −9.0 V to −28 V Input, −5.0 V/700 mA Output Inverted Buck Converter 22 �H V CC 22 �F V (5) CC PGND (7) GND V (8) 5.0 V SW + AGND (6) 22 �F + 37.24 k CS5171/3 22 �F 22 �H V (1 ) C Low FB (2) ESR GND 200 pF .01 �F 5.0 k 12.76 k Figure 45. Additional Application Diagram, 2.7 V to 28 V Input, 5.0 V Output SEPIC Converter http://onsemi.com 19 + CS5171, CS5172, CS5173, CS5174 R1 R2 1.245 k/0.1 W, 1% 99.755 k/0.1 W, 1% GND C1 C2 C3 .1 � .1 � .1 � 50 V 50 V 50 V D1 D1 D1 D1 D1 D1 D1 1 8 V V 100 V C SW O C10 2 7 1N4148 1N4148 1N4148 1N4148 1N4148 1N4148 1N4148 .1 � PGND FB C11 3 6 R3 Test AGND C4 C5 C6 .01 � C9 C8 2.0 k .1 � .1 � .1 � C7 10 � .1 � 4 5 V SS CC 50 V 50 V 50 V .1 � GND 50 V 4.0 V Figure 46. Additional Application Diagram, 4.0 V Input, 100 V/ 10 mA Output Boost Converter with Output Voltage Multiplier 200 pF C6 D1 C1 R1 1 8 V V −12 V C SW 5.0 k 0.01 �F 22 �F 2 7 FB PGND L1 15 �H 3 6 Test AGND C3 45 D2 D3 SS SS V 22 �F CC + +5.0 V C4 0.1 �F GND GND C5 + 22 �F R2 R3 +12 V 1.28 k 10.72 k Figure 47. Additional Application Diagram, 5.0 V Input, ± 12 V Output Dual Boost Converter http://onsemi.com 20 CS5171/3 CS5171 CS5171, CS5172, CS5173, CS5174 ORDERING INFORMATION † Device Operating Temperature Range Package Shipping CS5171ED8 95 Units/Rail CS5171EDR8 2500 Tape & Reel CS5172ED8 95 Units/Rail CS5172EDR8 2500 Tape & Reel −40 40° °C