ON SEMICONDUCTOR CS4124YN16

CS4124 AWLYYWW CS4124 High Side PWM FET Controller The CS4124 is a monolithic integrated circuit designed primarily to control the rotor speed of permanent magnet, direct current (DC) brush motors. It drives the gate of an N channel power MOSFET or http://onsemi.com IGBT with a user–adjustable, fixed frequency, variable duty cycle, pulse width modulated (PWM) signal. The CS4124 can also be used to control other loads such as incandescent bulbs and solenoids. Inductive current from the motor or solenoid is recirculated through an external diode. 16 The CS4124 accepts a DC level input signal of 0 to 5.0 V to control the pulse width of the output signal. This signal can be generated by a 1 potentiometer referenced to the on–chip 5.0 V linear regulator, or a DIP–16 N SUFFIX filtered 0% to 100% PWM signal also referenced to the 5.0 V CASE 648 regulator. The IC is placed in a sleep state by pulling the CTL lead below 0.5 V. In this mode everything on the chip is shutdown except for the on–chip PIN CONNECTION AND regulator and the overall current draw is less than 275 μA. There are a MARKING DIAGRAM number of on–chip diagnostics that look for potential failure modes and can disable the external power MOSFET. 1 16 OUTPUT GND BOOST INH Features FLT I • 150 mA Peak PWM Gate Drive Output ADJ R I OSC SENSE+ • Patented Voltage Compensation Circuit C I OSC SENSE– • 100% Duty Cycle Capability CTL PMP • 5.0 V, ± 3.0% Linear Regulator PGND SNI • Low Current Sleep Mode V V CC REG • Overvoltage Protection A = Assembly Location • Boost Mode Power Supply WL, L = Wafer Lot • Output Inhibit YY, Y = Year WW, W = Work Week ORDERING INFORMATION* Device Package Shipping CS4124YN16 DIP–16 25 Units/Rail * Contact your local sales representative for 16-lead SOIC wide package.  Semiconductor Components Industries, LLC, 2000 1 Publication Order Number: November, 2000 – Rev. 6 CS4124/D CS4124 V BAT 42.5 μH 1000 μF 1000 μF R S 10 470 μH OUTPUT GND BOOST INH C .25 μF FLT 1.5 μF FLT I ADJ 10 k R OSC 93.1 k I + R SENSE CS1 R OSC I SENSE– C OSC C 51 Ω 10 nF 470 pF CS C PMP R OSC SENSE 0.022 μF R CTL SNI R CS2 4.0 mΩ SNI PGND 4 51 Ω V REG V CC 100 μF .01 μF 6 R GATE 1.0 μF 10 k 10 k PWM Input P1 100 k 10 k 1.0 M 10 k MOT+ 10 μF 10 k N1 10 k MOT– Figure 1. Applications Diagram ABSOLUTE MAXIMUM RATINGS* Rating Value Unit Storage Temperature Range –65 to 150 °C V –0.3 to 30 V CC V Peak Transient Voltage (load dump = 26 V w/ series 10 Ω resistor) 40 V CC Input Voltage Range (at any input) –0.3 to 10 V Maximum Junction Temperature 150 °C Lead Temperature Soldering Wave Solder (through hole styles only) Note 1. 260 peak °C ESD Susceptibility (Human Body Model) 2.0 kV 1. 10 seconds max. *The maximum package power dissipation must be observed. http://onsemi.com 2 CS4124 ELECTRICAL CHARACTERISTICS (4.0 V ≤ V ≤ 26 V; –40°C < T < 125°C; unless otherwise specified.) CC J Characteristic Test Conditions Min Typ Max Unit V Supply CC Operating Current Supply 7.0 V ≤ V ≤ 18 v – 5.0 10 mA CC 4.0 V ≤ V < 7.0 V, 18 V < V ≤ 26 V – – 15 mA CC CC Quiescent Current V = 12 V – 170 275 μA CC Overvoltage Shutdown – 26.5 – 29 V Control (CTL) Control Input Current CTL = 0 V to 5.0 V –2.0 0.1 2.0 μA Sleep Mode Threshold – 8.0% 10% 12% V REG Sleep Mode Hysteresis 7.0 V ≤ V ≤ 26 V 50 100 150 mV CC 4.0 V ≤ V < 7.0 V 10 – 150 mV CC Control Sense Differential Voltage Sense 7.0 V ≤ V ≤ 18 V: CC I = 1.0 V and R = 51 Ω 18 – 34 mV ADJ CS1 I = 4.0 V and R = 51 Ω 104 – 125 mV ADJ CS1 4.0 V ≤ V < 7.0 V: CC I = 1.0 V and R = 51 Ω 15 – 39 mV ADJ CS1 18 V < V ≤ 26 V: CC I = 1.0 V and R = 51 Ω 15 – 39 mV ADJ CS1 I = 4.0 V and R = 51 Ω 102 – 130 mV ADJ CS1 I Input Current 4.0 V ≤ V ≤ 26 V, I = 0 V to 5.0 V –2.0 0.3 2.0 μA ADJ CC ADJ Linear Regulator Output Voltage, V V = 4.0 V 2.0 – – V REG CC V = 13.2 V 4.85 – 5.15 V CC V = 26 V 4.85 – 5.20 V CC Inhibit Inhibit Threshold – 40% 50% 60% V REG Inhibit Hysteresis 4.0 V ≤ V ≤ 7.0 V 100 – 500 mV CC 7.0 V ≤ V ≤ 26 V 150 325 500 mV CC External Drive (OUTPUT) Output Frequency 4.0 V ≤ V < 7.0 V: CC R = 93.1 kΩ, C = 470 pF 10 – 25 kHz OSC OSC 7.0 V ≤ V ≤ 18 V: CC R = 93.1 kΩ, C = 470 pF 17 20 23 kHz OSC OSC 18 V < V ≤ 26 V: CC R = 93.1 kΩ, C = 470 pF 17 20 25 kHz OSC OSC Voltage to Duty Cycle Conversion 4.0 V ≤ V < 7.0 V: CC V = 13 V, CTL = 1.0 V 65 – 75 % CC V = 13 V, CTL = 2.0 V 100 – – % CC 7.0 V ≤ V ≤ 18 V: CC V = 13 V, CTL = 30% V 28.3 – 36.3 % CC REG V = 13 V, CTL = 55.8% V 56.0 – 64.0 % CC REG 18 V < V ≤ 26 V: CC V = 13 V, CTL = 1.5 V 11.8 – 21.8 % CC V = 13 V, CTL = 3.5 V 34.2 – 44.2 % CC Output Rise Time 4.0 V ≤ V ≤ 26 V: CC R = 6.0 Ω, C = 5.0 nF – .25 1.0 μs GATE GATE Output Fall Time 4.0 V ≤ V ≤ 26 V: CC R = 6.0 Ω, C = 5.0 nF – .30 1.0 μs GATE GATE http://onsemi.com 3 CS4124 ELECTRICAL CHARACTERISTICS (continued) (4.0 V ≤ V ≤ 26 V; –40°C < T < 125°C; unless otherwise specified.) CC J Characteristic Test Conditions Min Typ Max Unit External Drive (OUTPUT) (continued) Output Sink Current 4.0 V ≤ V < 7.0 V: CC R = 6.0 Ω, C = 5.0 nF – 150 – mA GATE GATE 7.0 V ≤ V ≤ 26 V: CC R = 6.0 Ω, C = 5.0 nF – 300 – mA GATE GATE Output Source Current 4.0 V ≤ V < 7.0 V: CC R = 6.0 Ω, C = 5.0 nF – 150 – mA GATE GATE 7.0 V ≤ V ≤ 26 V: CC R = 6.0 Ω, C = 5.0 nF – 300 – mA GATE GATE Output High Voltage I = 1.0 mA V = 1.7 – – V OUT BOOST Output Low Voltage I = –1.0 mA – – 1.3 V OUT Charge Pump (DRV) Boost Voltage – V + 6.4 – – V CC PIN FUNCTION DESCRIPTION PACKAGE PIN # 16 Lead PDIP PIN SYMBOL FUNCTION 1 OUTPUT MOSFET gate drive. 2 BOOST Boost voltage. 3 FLT Fault time out capacitor. 4 R Oscillator resistor. OSC 5 C Oscillator capacitor. OSC 6 CTL Pulse width control input. 7 PGND Power ground for on chip clamp. 8 V Positive power supply input. CC 9 V 5.0 V linear regulator. REG 10 SNI Sense inductor current. 11 PMP Collector of boost power transistor. 12 I Current sense minus. SENSE– 13 I Current sense plus. SENSE+ 14 I Current limit adjust. ADj 15 INH Output Inhibit. 16 GND Ground. http://onsemi.com 4 CS4124 GND S PMP Q R SNI + V CC V 5.0 V Regulator REG _ 450 mV Overvoltage OUTPUT + Clamp _ V CC PGND + + INH _ _ CTL + Q S 2.5 V _ R Reset Current I Triangle SENSE+ Sense Oscillator I SENSE– Timer + Out In _ I ADJ C FLT OSC R OSC Figure 2. Block Diagram http://onsemi.com 5 CS4124 TYPICAL PERFORMANCE CHARACTERISTICS 5.04 3.11 V = 26 V CC 5.02 3.01 V = 13.2 V CC 100 μA 2.91 5.00 2.81 2.71 4.98 2.0 mA 2.61 V = 7.0 V CC 5.0 mA 2.51 4.96 2.41 4.94 2.31 –50 050 100 150 –50 0 50 100 150 Temperature Temperature Figure 3. V vs. Temperature @ I = 5.0 mA Figure 4. V vs. Temperature @ V = 4.0 V REG LOAD REG CC 1.3 2.6 2.5 1.2 2.4 1.1 I = 300 mA 2.3 I = 150 mA 1.0 2.2 0.9 2.1 I = 150 mA 2.0 0.8 –50 0 50 100 150 –50 0 50 100 150 Temperature Temperature Figure 5. OUTPUT Voltage (Sinking Figure 6. OUTPUT Saturation Voltage Current) vs. Temperature (Sourcing Current) vs. Temperature http://onsemi.com 6 V REG V REG V REG V REG CS4124 APPLICATIONS INFORMATION THEORY OF OPERATION a 7.0 V average voltage across the load. If V then drops CC to 10 V, the IC would change the duty cycle to 70% and Oscillator hence keep the average load voltage at 7.0 V. The IC sets up a constant frequency triangle wave at the C lead whose frequency is related to the external OSC 120 components R and C , by the following equation: OSC OSC V = 8.0 V 0.83 100 CC Frequency� R � C OSC OSC The peak and valley of the triangle wave are proportional 80 to V by the following: CC V = 14 V CC V � 0.1� V VALLEY CC 60 V � 0.7� V PEAK CC V = 16 V CC 40 This is required to make the voltage compensation function properly. In order to keep the frequency of the 20 oscillator constant the current that charges C must also OSC vary with supply. R sets up the current which charges OSC 0 C . The voltage across R is 50% of V and OSC OSC CC 10 20 30 40 50 60 70 80 90 100 therefore: CTL Voltage (% of V ) REG V CC I � 0.5� Figure 7. Voltage Compensation ROSC R OSC 5.0 V Linear Regulator I is multiplied by (2) internally and transferred to the ROSC There is a 5.0 V, 5.0 mA linear regulator available at the C lead. Therefore: OSC V lead for external use. This voltage acts as a reference REG V CC I �� for many internal and external functions. It has a drop out of COSC R OSC approximately 1.5 V at room temperature. The period of the oscillator is: Current Sense and Timer V � V PEAK VALLEY T� 2C � OSC The IC differentially monitors the load current on a cycle I COSC by cycle basis at the I and I leads. The SENSE+ SENSE– The R and C components can be varied to create OSC OSC differential voltage across these two leads is amplified frequencies over the range of 15 Hz to 25 kHz. With the internally and compared to the voltage at the I lead. The ADJ suggested values of 93.1 kΩ and 470 pF for R and C , OSC OSC gain, A is set internally and externally by the following V the nominal frequency will be approximately 20 kHz. equation: I , at V = 14 V, will be 66.7 μA. I should not ROSC CC ROSC V I(ADJ) change over a more than 2:1 ratio and therefore C should 37000 OSC A � � V I � I 1000� R be changed to adjust the oscillator frequency. SENSE� SENSE� CS The current limit (I ) is set by the external current sense LIM Voltage Duty Cycle Conversion resistor (R ) placed across the I and I SENSE SENSE+ SENSE– The IC translates an input voltage at the CTL lead into a terminals and the voltage at the I lead. ADJ duty cycle at the OUTPUT lead. The transfer function incorporates ON Semiconductor’s patented Voltage 1000� R V CS I(ADJ) I � � LIM Compensation method to keep the average voltage and 37000 R SENSE current across the load constant regardless of fluctuations in The R resistors and C components form a differential CS CS the supply voltage. The duty cycle is varied based upon the low pass filter which filters out high frequency noise input voltage and supply voltage by the following equation: generated by the switching of the external MOSFET and the 2.8� V CTL associated lead noise. R also forms an error term in the Duty Cycle� 100%� CS V CC gain of the I equation because the I and I LIM SENSE+ SENSE– An internal DC voltage equal to: leads are low impedance inputs thereby creating a good V � (1.683� V )� V current sensing amplifier. Both leads source 50 μA while the DC CTL VALLEY chip is in run mode. I should be biased between 1.0 V and ADJ is compared to the oscillator voltage to produce the 4.0 V. When the current through the external MOSFET compensated duty cycle. The transfer is set up so that when exceeds I , an internal latch is set and the output pulls the LIM V = 14 V the duty cycle will equal V divided by V . CC CTL REG gate of the MOSFET low for the remainder of the oscillator For example at V = 14 V, V = 5.0 V and V = 2.5 V, CC REG CTL cycle (fault mode). At the start of the next cycle, the latch is the duty cycle would be 50% at the output. This would place http://onsemi.com 7 Duty Cycle (%) CS4124 reset and the IC reverts back to run mode until another fault inductor. The R resistor sets the peak current of the SNI occurs. If a number of faults occur in a given period of time, inductor by tripping a comparator when the voltage across the IC “times out” and disables the MOSFET for a long the resistor is 450 mV. The flip flop is reset and the inductor period of time to let it cool off. This is accomplished by delivers its stored energy to the load. The ripple voltage charging the C capacitor each time an over current (V ) at the Boost lead is controlled by C . A FLT RIPPLE BOOST condition occurs. If a cycle goes by with no overcurrent fault snubber circuit, made up of a series resistor and capacitor, is occurring, an even smaller amount of charge will be required to dampen the ringing of the inductor. A value of removed from C . If enough faults occur together, 4.0 Ω is recommended for R . FLT SNI eventually C will charge up to 2.4 V and the fault latch A zener diode is needed between the boost output voltage FLT will be set. The fault latch will not be reset until C and the battery. This will clamp the boost lead to a specified FLT discharges to 0.6 V. This action will continue indefinitely if value above the battery to prevent damage to the IC. A 9.0 the fault persists. volt zener diode is recommended. The off time and on time are set by the following: Sleep State 2.4V� 0.6V This device will enter into a low current mode (< 275 μA) Off Time� C � FLT 4.5 �A when CTL lead is brought to less than 0.5 V. All functions are disabled in this mode, except for the regulator. 2.4V� 0.6V On Time� C � FLT I AVG Inhibit When the inhibit is greater than 2.5 V the internal latch is where: set and the external MOSFET will be turned off for the I � (295.5 �A� DC)� [4.5 �A� (1� DC)] AVG remainder of the oscillator cycle. The latch is then reset at the start of the next cycle. I � (300 �A� DC)� 4.5 �A AVG Overvoltage Shutdown DC� PWM Duty Cycle The IC will disable the output during an overvoltage event. This is a real time fault event and does not set the Boost Switch Mode Power Supply internal latch and therefore is independent of the oscillator The CS4124 has an integrated boost mode power supply timing (i.e. asynchronous). There is 325 mV (typical) of which charges the gate of the external high–side MOSFET hysteresis on the overvoltage function. There is no to greater than 5.0 V above V . Three leads are used for undervoltage lockout. The device will shutdown gracefully CC voltage boost. They are Boost, PMP and SNI. The PMP lead once it runs out of headroom. is the collector of a darlington tied NPN power transistor. Reverse Battery This device charges the inductor during its on time. The The CS4124 will not survive a reverse battery condition. boost lead is the input to chip from the external reservoir A series diode is required between the battery and the V CC capacitor. The SNI lead is the emitter of the power NPN and lead for reverse battery. is connected externally to the R resistor. SNI The power supply is controlled by the oscillator. At the Load Dump start of a cycle an R–S flip flop is set the internal power NPN A 10 Ω resistor, (RS) is placed in series with V to limit CC transistor is turned on and energy begins to build up in the the current into the IC during 40 V peak transient conditions. http://onsemi.com 8 CS4124 PACKAGE DIMENSIONS DIP–16 N SUFFIX CASE 648–08 ISSUE R NOTES: –A– 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 16 9 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. B 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. 18 INCHES MILLIMETERS DIM MIN MAX MIN MAX F A 0.740 0.770 18.80 19.55 C L B 0.250 0.270 6.35 6.85 C 0.145 0.175 3.69 4.44 S D 0.015 0.021 0.39 0.53 F 0.040 0.70 1.02 1.77 SEATING –T– PLANE G 0.100 BSC 2.54 BSC H 0.050 BSC 1.27 BSC K M J 0.008 0.015 0.21 0.38 H J K 0.110 0.130 2.80 3.30 G L 0.295 0.305 7.50 7.74 D 16 PL M 0 10 0 10 � � � � S 0.020 0.040 0.51 1.01 M M 0.25 (0.010) T A PACKAGE THERMAL DATA Parameter DIP–16 Unit R Typical 42 °C/W ΘJC R Typical 80 °C/W ΘJA http://onsemi.com 9 CS4124 Notes http://onsemi.com 10 CS4124 Notes http://onsemi.com 11 CS4124 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. 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